miscregs.hh (13392:a292af6523cc) miscregs.hh (13531:e6f1bf55d038)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 659 unchanged lines hidden (view full) ---

668
669 // Introduced in ARMv8.1
670 MISCREG_TTBR1_EL2,
671 MISCREG_CNTHV_CTL_EL2,
672 MISCREG_CNTHV_CVAL_EL2,
673 MISCREG_CNTHV_TVAL_EL2,
674
675 MISCREG_ID_AA64MMFR2_EL1,
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 659 unchanged lines hidden (view full) ---

668
669 // Introduced in ARMv8.1
670 MISCREG_TTBR1_EL2,
671 MISCREG_CNTHV_CTL_EL2,
672 MISCREG_CNTHV_CVAL_EL2,
673 MISCREG_CNTHV_TVAL_EL2,
674
675 MISCREG_ID_AA64MMFR2_EL1,
676
677 // GICv3, CPU interface
678 MISCREG_ICC_PMR_EL1,
679 MISCREG_ICC_IAR0_EL1,
680 MISCREG_ICC_EOIR0_EL1,
681 MISCREG_ICC_HPPIR0_EL1,
682 MISCREG_ICC_BPR0_EL1,
683 MISCREG_ICC_AP0R0_EL1,
684 MISCREG_ICC_AP0R1_EL1,
685 MISCREG_ICC_AP0R2_EL1,
686 MISCREG_ICC_AP0R3_EL1,
687 MISCREG_ICC_AP1R0_EL1,
688 MISCREG_ICC_AP1R0_EL1_NS,
689 MISCREG_ICC_AP1R0_EL1_S,
690 MISCREG_ICC_AP1R1_EL1,
691 MISCREG_ICC_AP1R1_EL1_NS,
692 MISCREG_ICC_AP1R1_EL1_S,
693 MISCREG_ICC_AP1R2_EL1,
694 MISCREG_ICC_AP1R2_EL1_NS,
695 MISCREG_ICC_AP1R2_EL1_S,
696 MISCREG_ICC_AP1R3_EL1,
697 MISCREG_ICC_AP1R3_EL1_NS,
698 MISCREG_ICC_AP1R3_EL1_S,
699 MISCREG_ICC_DIR_EL1,
700 MISCREG_ICC_RPR_EL1,
701 MISCREG_ICC_SGI1R_EL1,
702 MISCREG_ICC_ASGI1R_EL1,
703 MISCREG_ICC_SGI0R_EL1,
704 MISCREG_ICC_IAR1_EL1,
705 MISCREG_ICC_EOIR1_EL1,
706 MISCREG_ICC_HPPIR1_EL1,
707 MISCREG_ICC_BPR1_EL1,
708 MISCREG_ICC_BPR1_EL1_NS,
709 MISCREG_ICC_BPR1_EL1_S,
710 MISCREG_ICC_CTLR_EL1,
711 MISCREG_ICC_CTLR_EL1_NS,
712 MISCREG_ICC_CTLR_EL1_S,
713 MISCREG_ICC_SRE_EL1,
714 MISCREG_ICC_SRE_EL1_NS,
715 MISCREG_ICC_SRE_EL1_S,
716 MISCREG_ICC_IGRPEN0_EL1,
717 MISCREG_ICC_IGRPEN1_EL1,
718 MISCREG_ICC_IGRPEN1_EL1_NS,
719 MISCREG_ICC_IGRPEN1_EL1_S,
720 MISCREG_ICC_SRE_EL2,
721 MISCREG_ICC_CTLR_EL3,
722 MISCREG_ICC_SRE_EL3,
723 MISCREG_ICC_IGRPEN1_EL3,
724
725 // GICv3, CPU interface, virtualization
726 MISCREG_ICH_AP0R0_EL2,
727 MISCREG_ICH_AP0R1_EL2,
728 MISCREG_ICH_AP0R2_EL2,
729 MISCREG_ICH_AP0R3_EL2,
730 MISCREG_ICH_AP1R0_EL2,
731 MISCREG_ICH_AP1R1_EL2,
732 MISCREG_ICH_AP1R2_EL2,
733 MISCREG_ICH_AP1R3_EL2,
734 MISCREG_ICH_HCR_EL2,
735 MISCREG_ICH_VTR_EL2,
736 MISCREG_ICH_MISR_EL2,
737 MISCREG_ICH_EISR_EL2,
738 MISCREG_ICH_ELRSR_EL2,
739 MISCREG_ICH_VMCR_EL2,
740 MISCREG_ICH_LR0_EL2,
741 MISCREG_ICH_LR1_EL2,
742 MISCREG_ICH_LR2_EL2,
743 MISCREG_ICH_LR3_EL2,
744 MISCREG_ICH_LR4_EL2,
745 MISCREG_ICH_LR5_EL2,
746 MISCREG_ICH_LR6_EL2,
747 MISCREG_ICH_LR7_EL2,
748 MISCREG_ICH_LR8_EL2,
749 MISCREG_ICH_LR9_EL2,
750 MISCREG_ICH_LR10_EL2,
751 MISCREG_ICH_LR11_EL2,
752 MISCREG_ICH_LR12_EL2,
753 MISCREG_ICH_LR13_EL2,
754 MISCREG_ICH_LR14_EL2,
755 MISCREG_ICH_LR15_EL2,
756
757 MISCREG_ICV_PMR_EL1,
758 MISCREG_ICV_IAR0_EL1,
759 MISCREG_ICV_EOIR0_EL1,
760 MISCREG_ICV_HPPIR0_EL1,
761 MISCREG_ICV_BPR0_EL1,
762 MISCREG_ICV_AP0R0_EL1,
763 MISCREG_ICV_AP0R1_EL1,
764 MISCREG_ICV_AP0R2_EL1,
765 MISCREG_ICV_AP0R3_EL1,
766 MISCREG_ICV_AP1R0_EL1,
767 MISCREG_ICV_AP1R0_EL1_NS,
768 MISCREG_ICV_AP1R0_EL1_S,
769 MISCREG_ICV_AP1R1_EL1,
770 MISCREG_ICV_AP1R1_EL1_NS,
771 MISCREG_ICV_AP1R1_EL1_S,
772 MISCREG_ICV_AP1R2_EL1,
773 MISCREG_ICV_AP1R2_EL1_NS,
774 MISCREG_ICV_AP1R2_EL1_S,
775 MISCREG_ICV_AP1R3_EL1,
776 MISCREG_ICV_AP1R3_EL1_NS,
777 MISCREG_ICV_AP1R3_EL1_S,
778 MISCREG_ICV_DIR_EL1,
779 MISCREG_ICV_RPR_EL1,
780 MISCREG_ICV_SGI1R_EL1,
781 MISCREG_ICV_ASGI1R_EL1,
782 MISCREG_ICV_SGI0R_EL1,
783 MISCREG_ICV_IAR1_EL1,
784 MISCREG_ICV_EOIR1_EL1,
785 MISCREG_ICV_HPPIR1_EL1,
786 MISCREG_ICV_BPR1_EL1,
787 MISCREG_ICV_BPR1_EL1_NS,
788 MISCREG_ICV_BPR1_EL1_S,
789 MISCREG_ICV_CTLR_EL1,
790 MISCREG_ICV_CTLR_EL1_NS,
791 MISCREG_ICV_CTLR_EL1_S,
792 MISCREG_ICV_SRE_EL1,
793 MISCREG_ICV_SRE_EL1_NS,
794 MISCREG_ICV_SRE_EL1_S,
795 MISCREG_ICV_IGRPEN0_EL1,
796 MISCREG_ICV_IGRPEN1_EL1,
797 MISCREG_ICV_IGRPEN1_EL1_NS,
798 MISCREG_ICV_IGRPEN1_EL1_S,
799
800 MISCREG_ICC_AP0R0,
801 MISCREG_ICC_AP0R1,
802 MISCREG_ICC_AP0R2,
803 MISCREG_ICC_AP0R3,
804 MISCREG_ICC_AP1R0,
805 MISCREG_ICC_AP1R0_NS,
806 MISCREG_ICC_AP1R0_S,
807 MISCREG_ICC_AP1R1,
808 MISCREG_ICC_AP1R1_NS,
809 MISCREG_ICC_AP1R1_S,
810 MISCREG_ICC_AP1R2,
811 MISCREG_ICC_AP1R2_NS,
812 MISCREG_ICC_AP1R2_S,
813 MISCREG_ICC_AP1R3,
814 MISCREG_ICC_AP1R3_NS,
815 MISCREG_ICC_AP1R3_S,
816 MISCREG_ICC_ASGI1R,
817 MISCREG_ICC_BPR0,
818 MISCREG_ICC_BPR1,
819 MISCREG_ICC_BPR1_NS,
820 MISCREG_ICC_BPR1_S,
821 MISCREG_ICC_CTLR,
822 MISCREG_ICC_CTLR_NS,
823 MISCREG_ICC_CTLR_S,
824 MISCREG_ICC_DIR,
825 MISCREG_ICC_EOIR0,
826 MISCREG_ICC_EOIR1,
827 MISCREG_ICC_HPPIR0,
828 MISCREG_ICC_HPPIR1,
829 MISCREG_ICC_HSRE,
830 MISCREG_ICC_IAR0,
831 MISCREG_ICC_IAR1,
832 MISCREG_ICC_IGRPEN0,
833 MISCREG_ICC_IGRPEN1,
834 MISCREG_ICC_IGRPEN1_NS,
835 MISCREG_ICC_IGRPEN1_S,
836 MISCREG_ICC_MCTLR,
837 MISCREG_ICC_MGRPEN1,
838 MISCREG_ICC_MSRE,
839 MISCREG_ICC_PMR,
840 MISCREG_ICC_RPR,
841 MISCREG_ICC_SGI0R,
842 MISCREG_ICC_SGI1R,
843 MISCREG_ICC_SRE,
844 MISCREG_ICC_SRE_NS,
845 MISCREG_ICC_SRE_S,
846
847 MISCREG_ICH_AP0R0,
848 MISCREG_ICH_AP0R1,
849 MISCREG_ICH_AP0R2,
850 MISCREG_ICH_AP0R3,
851 MISCREG_ICH_AP1R0,
852 MISCREG_ICH_AP1R1,
853 MISCREG_ICH_AP1R2,
854 MISCREG_ICH_AP1R3,
855 MISCREG_ICH_HCR,
856 MISCREG_ICH_VTR,
857 MISCREG_ICH_MISR,
858 MISCREG_ICH_EISR,
859 MISCREG_ICH_ELRSR,
860 MISCREG_ICH_VMCR,
861 MISCREG_ICH_LR0,
862 MISCREG_ICH_LR1,
863 MISCREG_ICH_LR2,
864 MISCREG_ICH_LR3,
865 MISCREG_ICH_LR4,
866 MISCREG_ICH_LR5,
867 MISCREG_ICH_LR6,
868 MISCREG_ICH_LR7,
869 MISCREG_ICH_LR8,
870 MISCREG_ICH_LR9,
871 MISCREG_ICH_LR10,
872 MISCREG_ICH_LR11,
873 MISCREG_ICH_LR12,
874 MISCREG_ICH_LR13,
875 MISCREG_ICH_LR14,
876 MISCREG_ICH_LR15,
877 MISCREG_ICH_LRC0,
878 MISCREG_ICH_LRC1,
879 MISCREG_ICH_LRC2,
880 MISCREG_ICH_LRC3,
881 MISCREG_ICH_LRC4,
882 MISCREG_ICH_LRC5,
883 MISCREG_ICH_LRC6,
884 MISCREG_ICH_LRC7,
885 MISCREG_ICH_LRC8,
886 MISCREG_ICH_LRC9,
887 MISCREG_ICH_LRC10,
888 MISCREG_ICH_LRC11,
889 MISCREG_ICH_LRC12,
890 MISCREG_ICH_LRC13,
891 MISCREG_ICH_LRC14,
892 MISCREG_ICH_LRC15,
893
676 // These MISCREG_FREESLOT are available Misc Register
677 // slots for future registers to be implemented.
678 MISCREG_FREESLOT_1,
679
680 // NUM_PHYS_MISCREGS specifies the number of actual physical
681 // registers, not considering the following pseudo-registers
682 // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
683 // Checkpointing should use this physical index when

--- 700 unchanged lines hidden (view full) ---

1384 "cbar_el1",
1385 "contextidr_el2",
1386
1387 "ttbr1_el2",
1388 "cnthv_ctl_el2",
1389 "cnthv_cval_el2",
1390 "cnthv_tval_el2",
1391 "id_aa64mmfr2_el1",
894 // These MISCREG_FREESLOT are available Misc Register
895 // slots for future registers to be implemented.
896 MISCREG_FREESLOT_1,
897
898 // NUM_PHYS_MISCREGS specifies the number of actual physical
899 // registers, not considering the following pseudo-registers
900 // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
901 // Checkpointing should use this physical index when

--- 700 unchanged lines hidden (view full) ---

1602 "cbar_el1",
1603 "contextidr_el2",
1604
1605 "ttbr1_el2",
1606 "cnthv_ctl_el2",
1607 "cnthv_cval_el2",
1608 "cnthv_tval_el2",
1609 "id_aa64mmfr2_el1",
1610
1611 // GICv3, CPU interface
1612 "icc_pmr_el1",
1613 "icc_iar0_el1",
1614 "icc_eoir0_el1",
1615 "icc_hppir0_el1",
1616 "icc_bpr0_el1",
1617 "icc_ap0r0_el1",
1618 "icc_ap0r1_el1",
1619 "icc_ap0r2_el1",
1620 "icc_ap0r3_el1",
1621 "icc_ap1r0_el1",
1622 "icc_ap1r0_el1_ns",
1623 "icc_ap1r0_el1_s",
1624 "icc_ap1r1_el1",
1625 "icc_ap1r1_el1_ns",
1626 "icc_ap1r1_el1_s",
1627 "icc_ap1r2_el1",
1628 "icc_ap1r2_el1_ns",
1629 "icc_ap1r2_el1_s",
1630 "icc_ap1r3_el1",
1631 "icc_ap1r3_el1_ns",
1632 "icc_ap1r3_el1_s",
1633 "icc_dir_el1",
1634 "icc_rpr_el1",
1635 "icc_sgi1r_el1",
1636 "icc_asgi1r_el1",
1637 "icc_sgi0r_el1",
1638 "icc_iar1_el1",
1639 "icc_eoir1_el1",
1640 "icc_hppir1_el1",
1641 "icc_bpr1_el1",
1642 "icc_bpr1_el1_ns",
1643 "icc_bpr1_el1_s",
1644 "icc_ctlr_el1",
1645 "icc_ctlr_el1_ns",
1646 "icc_ctlr_el1_s",
1647 "icc_sre_el1",
1648 "icc_sre_el1_ns",
1649 "icc_sre_el1_s",
1650 "icc_igrpen0_el1",
1651 "icc_igrpen1_el1",
1652 "icc_igrpen1_el1_ns",
1653 "icc_igrpen1_el1_s",
1654 "icc_sre_el2",
1655 "icc_ctlr_el3",
1656 "icc_sre_el3",
1657 "icc_igrpen1_el3",
1658
1659 // GICv3, CPU interface, virtualization
1660 "ich_ap0r0_el2",
1661 "ich_ap0r1_el2",
1662 "ich_ap0r2_el2",
1663 "ich_ap0r3_el2",
1664 "ich_ap1r0_el2",
1665 "ich_ap1r1_el2",
1666 "ich_ap1r2_el2",
1667 "ich_ap1r3_el2",
1668 "ich_hcr_el2",
1669 "ich_vtr_el2",
1670 "ich_misr_el2",
1671 "ich_eisr_el2",
1672 "ich_elrsr_el2",
1673 "ich_vmcr_el2",
1674 "ich_lr0_el2",
1675 "ich_lr1_el2",
1676 "ich_lr2_el2",
1677 "ich_lr3_el2",
1678 "ich_lr4_el2",
1679 "ich_lr5_el2",
1680 "ich_lr6_el2",
1681 "ich_lr7_el2",
1682 "ich_lr8_el2",
1683 "ich_lr9_el2",
1684 "ich_lr10_el2",
1685 "ich_lr11_el2",
1686 "ich_lr12_el2",
1687 "ich_lr13_el2",
1688 "ich_lr14_el2",
1689 "ich_lr15_el2",
1690
1691 "icv_pmr_el1",
1692 "icv_iar0_el1",
1693 "icv_eoir0_el1",
1694 "icv_hppir0_el1",
1695 "icv_bpr0_el1",
1696 "icv_ap0r0_el1",
1697 "icv_ap0r1_el1",
1698 "icv_ap0r2_el1",
1699 "icv_ap0r3_el1",
1700 "icv_ap1r0_el1",
1701 "icv_ap1r0_el1_ns",
1702 "icv_ap1r0_el1_s",
1703 "icv_ap1r1_el1",
1704 "icv_ap1r1_el1_ns",
1705 "icv_ap1r1_el1_s",
1706 "icv_ap1r2_el1",
1707 "icv_ap1r2_el1_ns",
1708 "icv_ap1r2_el1_s",
1709 "icv_ap1r3_el1",
1710 "icv_ap1r3_el1_ns",
1711 "icv_ap1r3_el1_s",
1712 "icv_dir_el1",
1713 "icv_rpr_el1",
1714 "icv_sgi1r_el1",
1715 "icv_asgi1r_el1",
1716 "icv_sgi0r_el1",
1717 "icv_iar1_el1",
1718 "icv_eoir1_el1",
1719 "icv_hppir1_el1",
1720 "icv_bpr1_el1",
1721 "icv_bpr1_el1_ns",
1722 "icv_bpr1_el1_s",
1723 "icv_ctlr_el1",
1724 "icv_ctlr_el1_ns",
1725 "icv_ctlr_el1_s",
1726 "icv_sre_el1",
1727 "icv_sre_el1_ns",
1728 "icv_sre_el1_s",
1729 "icv_igrpen0_el1",
1730 "icv_igrpen1_el1",
1731 "icv_igrpen1_el1_ns",
1732 "icv_igrpen1_el1_s",
1733
1734 "icc_ap0r0",
1735 "icc_ap0r1",
1736 "icc_ap0r2",
1737 "icc_ap0r3",
1738 "icc_ap1r0",
1739 "icc_ap1r0_ns",
1740 "icc_ap1r0_s",
1741 "icc_ap1r1",
1742 "icc_ap1r1_ns",
1743 "icc_ap1r1_s",
1744 "icc_ap1r2",
1745 "icc_ap1r2_ns",
1746 "icc_ap1r2_s",
1747 "icc_ap1r3",
1748 "icc_ap1r3_ns",
1749 "icc_ap1r3_s",
1750 "icc_asgi1r",
1751 "icc_bpr0",
1752 "icc_bpr1",
1753 "icc_bpr1_ns",
1754 "icc_bpr1_s",
1755 "icc_ctlr",
1756 "icc_ctlr_ns",
1757 "icc_ctlr_s",
1758 "icc_dir",
1759 "icc_eoir0",
1760 "icc_eoir1",
1761 "icc_hppir0",
1762 "icc_hppir1",
1763 "icc_hsre",
1764 "icc_iar0",
1765 "icc_iar1",
1766 "icc_igrpen0",
1767 "icc_igrpen1",
1768 "icc_igrpen1_ns",
1769 "icc_igrpen1_s",
1770 "icc_mctlr",
1771 "icc_mgrpen1",
1772 "icc_msre",
1773 "icc_pmr",
1774 "icc_rpr",
1775 "icc_sgi0r",
1776 "icc_sgi1r",
1777 "icc_sre",
1778 "icc_sre_ns",
1779 "icc_sre_s",
1780
1781 "ich_ap0r0",
1782 "ich_ap0r1",
1783 "ich_ap0r2",
1784 "ich_ap0r3",
1785 "ich_ap1r0",
1786 "ich_ap1r1",
1787 "ich_ap1r2",
1788 "ich_ap1r3",
1789 "ich_hcr",
1790 "ich_vtr",
1791 "ich_misr",
1792 "ich_eisr",
1793 "ich_elrsr",
1794 "ich_vmcr",
1795 "ich_lr0",
1796 "ich_lr1",
1797 "ich_lr2",
1798 "ich_lr3",
1799 "ich_lr4",
1800 "ich_lr5",
1801 "ich_lr6",
1802 "ich_lr7",
1803 "ich_lr8",
1804 "ich_lr9",
1805 "ich_lr10",
1806 "ich_lr11",
1807 "ich_lr12",
1808 "ich_lr13",
1809 "ich_lr14",
1810 "ich_lr15",
1811 "ich_lrc0",
1812 "ich_lrc1",
1813 "ich_lrc2",
1814 "ich_lrc3",
1815 "ich_lrc4",
1816 "ich_lrc5",
1817 "ich_lrc6",
1818 "ich_lrc7",
1819 "ich_lrc8",
1820 "ich_lrc9",
1821 "ich_lrc10",
1822 "ich_lrc11",
1823 "ich_lrc12",
1824 "ich_lrc13",
1825 "ich_lrc14",
1826 "ich_lrc15",
1827
1392 "freeslot2",
1393
1394 "num_phys_regs",
1395
1396 // Dummy registers
1397 "nop",
1398 "raz",
1399 "cp14_unimpl",

--- 106 unchanged lines hidden --- 		1828 "freeslot2",
1829
1830 "num_phys_regs",
1831
1832 // Dummy registers
1833 "nop",
1834 "raz",
1835 "cp14_unimpl",

--- 106 unchanged lines hidden ---