Cross Reference: /gem5/src/arch/arm/miscregs.hh

miscregs.hh (13116:d3c3e2533928)	miscregs.hh (13392:a292af6523cc)
1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 41 unchanged lines hidden (view full) --- 50#include "base/compiler.hh" 51 52class ThreadContext; 53 54 55namespace ArmISA 56{ 57 enum MiscRegIndex {	1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 41 unchanged lines hidden (view full) --- 50#include "base/compiler.hh" 51 52class ThreadContext; 53 54 55namespace ArmISA 56{ 57 enum MiscRegIndex {
58 MISCREG_CPSR = 0, // 0 59 MISCREG_SPSR, // 1 60 MISCREG_SPSR_FIQ, // 2 61 MISCREG_SPSR_IRQ, // 3 62 MISCREG_SPSR_SVC, // 4 63 MISCREG_SPSR_MON, // 5 64 MISCREG_SPSR_ABT, // 6 65 MISCREG_SPSR_HYP, // 7 66 MISCREG_SPSR_UND, // 8 67 MISCREG_ELR_HYP, // 9 68 MISCREG_FPSID, // 10 69 MISCREG_FPSCR, // 11 70 MISCREG_MVFR1, // 12 71 MISCREG_MVFR0, // 13 72 MISCREG_FPEXC, // 14	58 MISCREG_CPSR = 0, 59 MISCREG_SPSR, 60 MISCREG_SPSR_FIQ, 61 MISCREG_SPSR_IRQ, 62 MISCREG_SPSR_SVC, 63 MISCREG_SPSR_MON, 64 MISCREG_SPSR_ABT, 65 MISCREG_SPSR_HYP, 66 MISCREG_SPSR_UND, 67 MISCREG_ELR_HYP, 68 MISCREG_FPSID, 69 MISCREG_FPSCR, 70 MISCREG_MVFR1, 71 MISCREG_MVFR0, 72 MISCREG_FPEXC,
73 74 // Helper registers	73 74 // Helper registers
75 MISCREG_CPSR_MODE, // 15 76 MISCREG_CPSR_Q, // 16 77 MISCREG_FPSCR_EXC, // 17 78 MISCREG_FPSCR_QC, // 18 79 MISCREG_LOCKADDR, // 19 80 MISCREG_LOCKFLAG, // 20 81 MISCREG_PRRR_MAIR0, // 21 82 MISCREG_PRRR_MAIR0_NS, // 22 83 MISCREG_PRRR_MAIR0_S, // 23 84 MISCREG_NMRR_MAIR1, // 24 85 MISCREG_NMRR_MAIR1_NS, // 25 86 MISCREG_NMRR_MAIR1_S, // 26 87 MISCREG_PMXEVTYPER_PMCCFILTR, // 27 88 MISCREG_SCTLR_RST, // 28 89 MISCREG_SEV_MAILBOX, // 29	75 MISCREG_CPSR_MODE, 76 MISCREG_CPSR_Q, 77 MISCREG_FPSCR_EXC, 78 MISCREG_FPSCR_QC, 79 MISCREG_LOCKADDR, 80 MISCREG_LOCKFLAG, 81 MISCREG_PRRR_MAIR0, 82 MISCREG_PRRR_MAIR0_NS, 83 MISCREG_PRRR_MAIR0_S, 84 MISCREG_NMRR_MAIR1, 85 MISCREG_NMRR_MAIR1_NS, 86 MISCREG_NMRR_MAIR1_S, 87 MISCREG_PMXEVTYPER_PMCCFILTR, 88 MISCREG_SCTLR_RST, 89 MISCREG_SEV_MAILBOX,
90 91 // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)	90 91 // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
92 MISCREG_DBGDIDR, // 30 93 MISCREG_DBGDSCRint, // 31 94 MISCREG_DBGDCCINT, // 32 95 MISCREG_DBGDTRTXint, // 33 96 MISCREG_DBGDTRRXint, // 34 97 MISCREG_DBGWFAR, // 35 98 MISCREG_DBGVCR, // 36 99 MISCREG_DBGDTRRXext, // 37 100 MISCREG_DBGDSCRext, // 38 101 MISCREG_DBGDTRTXext, // 39 102 MISCREG_DBGOSECCR, // 40 103 MISCREG_DBGBVR0, // 41 104 MISCREG_DBGBVR1, // 42 105 MISCREG_DBGBVR2, // 43 106 MISCREG_DBGBVR3, // 44 107 MISCREG_DBGBVR4, // 45 108 MISCREG_DBGBVR5, // 46 109 MISCREG_DBGBCR0, // 47 110 MISCREG_DBGBCR1, // 48 111 MISCREG_DBGBCR2, // 49 112 MISCREG_DBGBCR3, // 50 113 MISCREG_DBGBCR4, // 51 114 MISCREG_DBGBCR5, // 52 115 MISCREG_DBGWVR0, // 53 116 MISCREG_DBGWVR1, // 54 117 MISCREG_DBGWVR2, // 55 118 MISCREG_DBGWVR3, // 56 119 MISCREG_DBGWCR0, // 57 120 MISCREG_DBGWCR1, // 58 121 MISCREG_DBGWCR2, // 59 122 MISCREG_DBGWCR3, // 60 123 MISCREG_DBGDRAR, // 61 124 MISCREG_DBGBXVR4, // 62 125 MISCREG_DBGBXVR5, // 63 126 MISCREG_DBGOSLAR, // 64 127 MISCREG_DBGOSLSR, // 65 128 MISCREG_DBGOSDLR, // 66 129 MISCREG_DBGPRCR, // 67 130 MISCREG_DBGDSAR, // 68 131 MISCREG_DBGCLAIMSET, // 69 132 MISCREG_DBGCLAIMCLR, // 70 133 MISCREG_DBGAUTHSTATUS, // 71 134 MISCREG_DBGDEVID2, // 72 135 MISCREG_DBGDEVID1, // 73 136 MISCREG_DBGDEVID0, // 74 137 MISCREG_TEECR, // 75, not in ARM DDI 0487A.b+ 138 MISCREG_JIDR, // 76 139 MISCREG_TEEHBR, // 77, not in ARM DDI 0487A.b+ 140 MISCREG_JOSCR, // 78 141 MISCREG_JMCR, // 79	92 MISCREG_DBGDIDR, 93 MISCREG_DBGDSCRint, 94 MISCREG_DBGDCCINT, 95 MISCREG_DBGDTRTXint, 96 MISCREG_DBGDTRRXint, 97 MISCREG_DBGWFAR, 98 MISCREG_DBGVCR, 99 MISCREG_DBGDTRRXext, 100 MISCREG_DBGDSCRext, 101 MISCREG_DBGDTRTXext, 102 MISCREG_DBGOSECCR, 103 MISCREG_DBGBVR0, 104 MISCREG_DBGBVR1, 105 MISCREG_DBGBVR2, 106 MISCREG_DBGBVR3, 107 MISCREG_DBGBVR4, 108 MISCREG_DBGBVR5, 109 MISCREG_DBGBCR0, 110 MISCREG_DBGBCR1, 111 MISCREG_DBGBCR2, 112 MISCREG_DBGBCR3, 113 MISCREG_DBGBCR4, 114 MISCREG_DBGBCR5, 115 MISCREG_DBGWVR0, 116 MISCREG_DBGWVR1, 117 MISCREG_DBGWVR2, 118 MISCREG_DBGWVR3, 119 MISCREG_DBGWCR0, 120 MISCREG_DBGWCR1, 121 MISCREG_DBGWCR2, 122 MISCREG_DBGWCR3, 123 MISCREG_DBGDRAR, 124 MISCREG_DBGBXVR4, 125 MISCREG_DBGBXVR5, 126 MISCREG_DBGOSLAR, 127 MISCREG_DBGOSLSR, 128 MISCREG_DBGOSDLR, 129 MISCREG_DBGPRCR, 130 MISCREG_DBGDSAR, 131 MISCREG_DBGCLAIMSET, 132 MISCREG_DBGCLAIMCLR, 133 MISCREG_DBGAUTHSTATUS, 134 MISCREG_DBGDEVID2, 135 MISCREG_DBGDEVID1, 136 MISCREG_DBGDEVID0, 137 MISCREG_TEECR, // not in ARM DDI 0487A.b+ 138 MISCREG_JIDR, 139 MISCREG_TEEHBR, // not in ARM DDI 0487A.b+ 140 MISCREG_JOSCR, 141 MISCREG_JMCR,
142 143 // AArch32 CP15 registers (system control)	142 143 // AArch32 CP15 registers (system control)
144 MISCREG_MIDR, // 80 145 MISCREG_CTR, // 81 146 MISCREG_TCMTR, // 82 147 MISCREG_TLBTR, // 83 148 MISCREG_MPIDR, // 84 149 MISCREG_REVIDR, // 85 150 MISCREG_ID_PFR0, // 86 151 MISCREG_ID_PFR1, // 87 152 MISCREG_ID_DFR0, // 88 153 MISCREG_ID_AFR0, // 89 154 MISCREG_ID_MMFR0, // 90 155 MISCREG_ID_MMFR1, // 91 156 MISCREG_ID_MMFR2, // 92 157 MISCREG_ID_MMFR3, // 93 158 MISCREG_ID_ISAR0, // 94 159 MISCREG_ID_ISAR1, // 95 160 MISCREG_ID_ISAR2, // 96 161 MISCREG_ID_ISAR3, // 97 162 MISCREG_ID_ISAR4, // 98 163 MISCREG_ID_ISAR5, // 99 164 MISCREG_CCSIDR, // 100 165 MISCREG_CLIDR, // 101 166 MISCREG_AIDR, // 102 167 MISCREG_CSSELR, // 103 168 MISCREG_CSSELR_NS, // 104 169 MISCREG_CSSELR_S, // 105 170 MISCREG_VPIDR, // 106 171 MISCREG_VMPIDR, // 107 172 MISCREG_SCTLR, // 108 173 MISCREG_SCTLR_NS, // 109 174 MISCREG_SCTLR_S, // 110 175 MISCREG_ACTLR, // 111 176 MISCREG_ACTLR_NS, // 112 177 MISCREG_ACTLR_S, // 113 178 MISCREG_CPACR, // 114 179 MISCREG_SCR, // 115 180 MISCREG_SDER, // 116 181 MISCREG_NSACR, // 117 182 MISCREG_HSCTLR, // 118 183 MISCREG_HACTLR, // 119 184 MISCREG_HCR, // 120 185 MISCREG_HDCR, // 121 186 MISCREG_HCPTR, // 122 187 MISCREG_HSTR, // 123 188 MISCREG_HACR, // 124 189 MISCREG_TTBR0, // 125 190 MISCREG_TTBR0_NS, // 126 191 MISCREG_TTBR0_S, // 127 192 MISCREG_TTBR1, // 128 193 MISCREG_TTBR1_NS, // 129 194 MISCREG_TTBR1_S, // 130 195 MISCREG_TTBCR, // 131 196 MISCREG_TTBCR_NS, // 132 197 MISCREG_TTBCR_S, // 133 198 MISCREG_HTCR, // 134 199 MISCREG_VTCR, // 135 200 MISCREG_DACR, // 136 201 MISCREG_DACR_NS, // 137 202 MISCREG_DACR_S, // 138 203 MISCREG_DFSR, // 139 204 MISCREG_DFSR_NS, // 140 205 MISCREG_DFSR_S, // 141 206 MISCREG_IFSR, // 142 207 MISCREG_IFSR_NS, // 143 208 MISCREG_IFSR_S, // 144 209 MISCREG_ADFSR, // 145 210 MISCREG_ADFSR_NS, // 146 211 MISCREG_ADFSR_S, // 147 212 MISCREG_AIFSR, // 148 213 MISCREG_AIFSR_NS, // 149 214 MISCREG_AIFSR_S, // 150 215 MISCREG_HADFSR, // 151 216 MISCREG_HAIFSR, // 152 217 MISCREG_HSR, // 153 218 MISCREG_DFAR, // 154 219 MISCREG_DFAR_NS, // 155 220 MISCREG_DFAR_S, // 156 221 MISCREG_IFAR, // 157 222 MISCREG_IFAR_NS, // 158 223 MISCREG_IFAR_S, // 159 224 MISCREG_HDFAR, // 160 225 MISCREG_HIFAR, // 161 226 MISCREG_HPFAR, // 162 227 MISCREG_ICIALLUIS, // 163 228 MISCREG_BPIALLIS, // 164 229 MISCREG_PAR, // 165 230 MISCREG_PAR_NS, // 166 231 MISCREG_PAR_S, // 167 232 MISCREG_ICIALLU, // 168 233 MISCREG_ICIMVAU, // 169 234 MISCREG_CP15ISB, // 170 235 MISCREG_BPIALL, // 171 236 MISCREG_BPIMVA, // 172 237 MISCREG_DCIMVAC, // 173 238 MISCREG_DCISW, // 174 239 MISCREG_ATS1CPR, // 175 240 MISCREG_ATS1CPW, // 176 241 MISCREG_ATS1CUR, // 177 242 MISCREG_ATS1CUW, // 178 243 MISCREG_ATS12NSOPR, // 179 244 MISCREG_ATS12NSOPW, // 180 245 MISCREG_ATS12NSOUR, // 181 246 MISCREG_ATS12NSOUW, // 182 247 MISCREG_DCCMVAC, // 183 248 MISCREG_DCCSW, // 184 249 MISCREG_CP15DSB, // 185 250 MISCREG_CP15DMB, // 186 251 MISCREG_DCCMVAU, // 187 252 MISCREG_DCCIMVAC, // 188 253 MISCREG_DCCISW, // 189 254 MISCREG_ATS1HR, // 190 255 MISCREG_ATS1HW, // 191 256 MISCREG_TLBIALLIS, // 192 257 MISCREG_TLBIMVAIS, // 193 258 MISCREG_TLBIASIDIS, // 194 259 MISCREG_TLBIMVAAIS, // 195 260 MISCREG_TLBIMVALIS, // 196 261 MISCREG_TLBIMVAALIS, // 197 262 MISCREG_ITLBIALL, // 198 263 MISCREG_ITLBIMVA, // 199 264 MISCREG_ITLBIASID, // 200 265 MISCREG_DTLBIALL, // 201 266 MISCREG_DTLBIMVA, // 202 267 MISCREG_DTLBIASID, // 203 268 MISCREG_TLBIALL, // 204 269 MISCREG_TLBIMVA, // 205 270 MISCREG_TLBIASID, // 206 271 MISCREG_TLBIMVAA, // 207 272 MISCREG_TLBIMVAL, // 208 273 MISCREG_TLBIMVAAL, // 209 274 MISCREG_TLBIIPAS2IS, // 210 275 MISCREG_TLBIIPAS2LIS, // 211 276 MISCREG_TLBIALLHIS, // 212 277 MISCREG_TLBIMVAHIS, // 213 278 MISCREG_TLBIALLNSNHIS, // 214 279 MISCREG_TLBIMVALHIS, // 215 280 MISCREG_TLBIIPAS2, // 216 281 MISCREG_TLBIIPAS2L, // 217 282 MISCREG_TLBIALLH, // 218 283 MISCREG_TLBIMVAH, // 219 284 MISCREG_TLBIALLNSNH, // 220 285 MISCREG_TLBIMVALH, // 221 286 MISCREG_PMCR, // 222 287 MISCREG_PMCNTENSET, // 223 288 MISCREG_PMCNTENCLR, // 224 289 MISCREG_PMOVSR, // 225 290 MISCREG_PMSWINC, // 226 291 MISCREG_PMSELR, // 227 292 MISCREG_PMCEID0, // 228 293 MISCREG_PMCEID1, // 229 294 MISCREG_PMCCNTR, // 230 295 MISCREG_PMXEVTYPER, // 231 296 MISCREG_PMCCFILTR, // 232 297 MISCREG_PMXEVCNTR, // 233 298 MISCREG_PMUSERENR, // 234 299 MISCREG_PMINTENSET, // 235 300 MISCREG_PMINTENCLR, // 236 301 MISCREG_PMOVSSET, // 237 302 MISCREG_L2CTLR, // 238 303 MISCREG_L2ECTLR, // 239 304 MISCREG_PRRR, // 240 305 MISCREG_PRRR_NS, // 241 306 MISCREG_PRRR_S, // 242 307 MISCREG_MAIR0, // 243 308 MISCREG_MAIR0_NS, // 244 309 MISCREG_MAIR0_S, // 245 310 MISCREG_NMRR, // 246 311 MISCREG_NMRR_NS, // 247 312 MISCREG_NMRR_S, // 248 313 MISCREG_MAIR1, // 249 314 MISCREG_MAIR1_NS, // 250 315 MISCREG_MAIR1_S, // 251 316 MISCREG_AMAIR0, // 252 317 MISCREG_AMAIR0_NS, // 253 318 MISCREG_AMAIR0_S, // 254 319 MISCREG_AMAIR1, // 255 320 MISCREG_AMAIR1_NS, // 256 321 MISCREG_AMAIR1_S, // 257 322 MISCREG_HMAIR0, // 258 323 MISCREG_HMAIR1, // 259 324 MISCREG_HAMAIR0, // 260 325 MISCREG_HAMAIR1, // 261 326 MISCREG_VBAR, // 262 327 MISCREG_VBAR_NS, // 263 328 MISCREG_VBAR_S, // 264 329 MISCREG_MVBAR, // 265 330 MISCREG_RMR, // 266 331 MISCREG_ISR, // 267 332 MISCREG_HVBAR, // 268 333 MISCREG_FCSEIDR, // 269 334 MISCREG_CONTEXTIDR, // 270 335 MISCREG_CONTEXTIDR_NS, // 271 336 MISCREG_CONTEXTIDR_S, // 272 337 MISCREG_TPIDRURW, // 273 338 MISCREG_TPIDRURW_NS, // 274 339 MISCREG_TPIDRURW_S, // 275 340 MISCREG_TPIDRURO, // 276 341 MISCREG_TPIDRURO_NS, // 277 342 MISCREG_TPIDRURO_S, // 278 343 MISCREG_TPIDRPRW, // 279 344 MISCREG_TPIDRPRW_NS, // 280 345 MISCREG_TPIDRPRW_S, // 281 346 MISCREG_HTPIDR, // 282 347 MISCREG_CNTFRQ, // 283 348 MISCREG_CNTKCTL, // 284 349 MISCREG_CNTP_TVAL, // 285 350 MISCREG_CNTP_TVAL_NS, // 286 351 MISCREG_CNTP_TVAL_S, // 287 352 MISCREG_CNTP_CTL, // 288 353 MISCREG_CNTP_CTL_NS, // 289 354 MISCREG_CNTP_CTL_S, // 290 355 MISCREG_CNTV_TVAL, // 291 356 MISCREG_CNTV_CTL, // 292 357 MISCREG_CNTHCTL, // 293 358 MISCREG_CNTHP_TVAL, // 294 359 MISCREG_CNTHP_CTL, // 295 360 MISCREG_IL1DATA0, // 296 361 MISCREG_IL1DATA1, // 297 362 MISCREG_IL1DATA2, // 298 363 MISCREG_IL1DATA3, // 299 364 MISCREG_DL1DATA0, // 300 365 MISCREG_DL1DATA1, // 301 366 MISCREG_DL1DATA2, // 302 367 MISCREG_DL1DATA3, // 303 368 MISCREG_DL1DATA4, // 304 369 MISCREG_RAMINDEX, // 305 370 MISCREG_L2ACTLR, // 306 371 MISCREG_CBAR, // 307 372 MISCREG_HTTBR, // 308 373 MISCREG_VTTBR, // 309 374 MISCREG_CNTPCT, // 310 375 MISCREG_CNTVCT, // 311 376 MISCREG_CNTP_CVAL, // 312 377 MISCREG_CNTP_CVAL_NS, // 313 378 MISCREG_CNTP_CVAL_S, // 314 379 MISCREG_CNTV_CVAL, // 315 380 MISCREG_CNTVOFF, // 316 381 MISCREG_CNTHP_CVAL, // 317 382 MISCREG_CPUMERRSR, // 318 383 MISCREG_L2MERRSR, // 319	144 MISCREG_MIDR, 145 MISCREG_CTR, 146 MISCREG_TCMTR, 147 MISCREG_TLBTR, 148 MISCREG_MPIDR, 149 MISCREG_REVIDR, 150 MISCREG_ID_PFR0, 151 MISCREG_ID_PFR1, 152 MISCREG_ID_DFR0, 153 MISCREG_ID_AFR0, 154 MISCREG_ID_MMFR0, 155 MISCREG_ID_MMFR1, 156 MISCREG_ID_MMFR2, 157 MISCREG_ID_MMFR3, 158 MISCREG_ID_ISAR0, 159 MISCREG_ID_ISAR1, 160 MISCREG_ID_ISAR2, 161 MISCREG_ID_ISAR3, 162 MISCREG_ID_ISAR4, 163 MISCREG_ID_ISAR5, 164 MISCREG_CCSIDR, 165 MISCREG_CLIDR, 166 MISCREG_AIDR, 167 MISCREG_CSSELR, 168 MISCREG_CSSELR_NS, 169 MISCREG_CSSELR_S, 170 MISCREG_VPIDR, 171 MISCREG_VMPIDR, 172 MISCREG_SCTLR, 173 MISCREG_SCTLR_NS, 174 MISCREG_SCTLR_S, 175 MISCREG_ACTLR, 176 MISCREG_ACTLR_NS, 177 MISCREG_ACTLR_S, 178 MISCREG_CPACR, 179 MISCREG_SCR, 180 MISCREG_SDER, 181 MISCREG_NSACR, 182 MISCREG_HSCTLR, 183 MISCREG_HACTLR, 184 MISCREG_HCR, 185 MISCREG_HDCR, 186 MISCREG_HCPTR, 187 MISCREG_HSTR, 188 MISCREG_HACR, 189 MISCREG_TTBR0, 190 MISCREG_TTBR0_NS, 191 MISCREG_TTBR0_S, 192 MISCREG_TTBR1, 193 MISCREG_TTBR1_NS, 194 MISCREG_TTBR1_S, 195 MISCREG_TTBCR, 196 MISCREG_TTBCR_NS, 197 MISCREG_TTBCR_S, 198 MISCREG_HTCR, 199 MISCREG_VTCR, 200 MISCREG_DACR, 201 MISCREG_DACR_NS, 202 MISCREG_DACR_S, 203 MISCREG_DFSR, 204 MISCREG_DFSR_NS, 205 MISCREG_DFSR_S, 206 MISCREG_IFSR, 207 MISCREG_IFSR_NS, 208 MISCREG_IFSR_S, 209 MISCREG_ADFSR, 210 MISCREG_ADFSR_NS, 211 MISCREG_ADFSR_S, 212 MISCREG_AIFSR, 213 MISCREG_AIFSR_NS, 214 MISCREG_AIFSR_S, 215 MISCREG_HADFSR, 216 MISCREG_HAIFSR, 217 MISCREG_HSR, 218 MISCREG_DFAR, 219 MISCREG_DFAR_NS, 220 MISCREG_DFAR_S, 221 MISCREG_IFAR, 222 MISCREG_IFAR_NS, 223 MISCREG_IFAR_S, 224 MISCREG_HDFAR, 225 MISCREG_HIFAR, 226 MISCREG_HPFAR, 227 MISCREG_ICIALLUIS, 228 MISCREG_BPIALLIS, 229 MISCREG_PAR, 230 MISCREG_PAR_NS, 231 MISCREG_PAR_S, 232 MISCREG_ICIALLU, 233 MISCREG_ICIMVAU, 234 MISCREG_CP15ISB, 235 MISCREG_BPIALL, 236 MISCREG_BPIMVA, 237 MISCREG_DCIMVAC, 238 MISCREG_DCISW, 239 MISCREG_ATS1CPR, 240 MISCREG_ATS1CPW, 241 MISCREG_ATS1CUR, 242 MISCREG_ATS1CUW, 243 MISCREG_ATS12NSOPR, 244 MISCREG_ATS12NSOPW, 245 MISCREG_ATS12NSOUR, 246 MISCREG_ATS12NSOUW, 247 MISCREG_DCCMVAC, 248 MISCREG_DCCSW, 249 MISCREG_CP15DSB, 250 MISCREG_CP15DMB, 251 MISCREG_DCCMVAU, 252 MISCREG_DCCIMVAC, 253 MISCREG_DCCISW, 254 MISCREG_ATS1HR, 255 MISCREG_ATS1HW, 256 MISCREG_TLBIALLIS, 257 MISCREG_TLBIMVAIS, 258 MISCREG_TLBIASIDIS, 259 MISCREG_TLBIMVAAIS, 260 MISCREG_TLBIMVALIS, 261 MISCREG_TLBIMVAALIS, 262 MISCREG_ITLBIALL, 263 MISCREG_ITLBIMVA, 264 MISCREG_ITLBIASID, 265 MISCREG_DTLBIALL, 266 MISCREG_DTLBIMVA, 267 MISCREG_DTLBIASID, 268 MISCREG_TLBIALL, 269 MISCREG_TLBIMVA, 270 MISCREG_TLBIASID, 271 MISCREG_TLBIMVAA, 272 MISCREG_TLBIMVAL, 273 MISCREG_TLBIMVAAL, 274 MISCREG_TLBIIPAS2IS, 275 MISCREG_TLBIIPAS2LIS, 276 MISCREG_TLBIALLHIS, 277 MISCREG_TLBIMVAHIS, 278 MISCREG_TLBIALLNSNHIS, 279 MISCREG_TLBIMVALHIS, 280 MISCREG_TLBIIPAS2, 281 MISCREG_TLBIIPAS2L, 282 MISCREG_TLBIALLH, 283 MISCREG_TLBIMVAH, 284 MISCREG_TLBIALLNSNH, 285 MISCREG_TLBIMVALH, 286 MISCREG_PMCR, 287 MISCREG_PMCNTENSET, 288 MISCREG_PMCNTENCLR, 289 MISCREG_PMOVSR, 290 MISCREG_PMSWINC, 291 MISCREG_PMSELR, 292 MISCREG_PMCEID0, 293 MISCREG_PMCEID1, 294 MISCREG_PMCCNTR, 295 MISCREG_PMXEVTYPER, 296 MISCREG_PMCCFILTR, 297 MISCREG_PMXEVCNTR, 298 MISCREG_PMUSERENR, 299 MISCREG_PMINTENSET, 300 MISCREG_PMINTENCLR, 301 MISCREG_PMOVSSET, 302 MISCREG_L2CTLR, 303 MISCREG_L2ECTLR, 304 MISCREG_PRRR, 305 MISCREG_PRRR_NS, 306 MISCREG_PRRR_S, 307 MISCREG_MAIR0, 308 MISCREG_MAIR0_NS, 309 MISCREG_MAIR0_S, 310 MISCREG_NMRR, 311 MISCREG_NMRR_NS, 312 MISCREG_NMRR_S, 313 MISCREG_MAIR1, 314 MISCREG_MAIR1_NS, 315 MISCREG_MAIR1_S, 316 MISCREG_AMAIR0, 317 MISCREG_AMAIR0_NS, 318 MISCREG_AMAIR0_S, 319 MISCREG_AMAIR1, 320 MISCREG_AMAIR1_NS, 321 MISCREG_AMAIR1_S, 322 MISCREG_HMAIR0, 323 MISCREG_HMAIR1, 324 MISCREG_HAMAIR0, 325 MISCREG_HAMAIR1, 326 MISCREG_VBAR, 327 MISCREG_VBAR_NS, 328 MISCREG_VBAR_S, 329 MISCREG_MVBAR, 330 MISCREG_RMR, 331 MISCREG_ISR, 332 MISCREG_HVBAR, 333 MISCREG_FCSEIDR, 334 MISCREG_CONTEXTIDR, 335 MISCREG_CONTEXTIDR_NS, 336 MISCREG_CONTEXTIDR_S, 337 MISCREG_TPIDRURW, 338 MISCREG_TPIDRURW_NS, 339 MISCREG_TPIDRURW_S, 340 MISCREG_TPIDRURO, 341 MISCREG_TPIDRURO_NS, 342 MISCREG_TPIDRURO_S, 343 MISCREG_TPIDRPRW, 344 MISCREG_TPIDRPRW_NS, 345 MISCREG_TPIDRPRW_S, 346 MISCREG_HTPIDR, 347 MISCREG_CNTFRQ, 348 MISCREG_CNTKCTL, 349 MISCREG_CNTP_TVAL, 350 MISCREG_CNTP_TVAL_NS, 351 MISCREG_CNTP_TVAL_S, 352 MISCREG_CNTP_CTL, 353 MISCREG_CNTP_CTL_NS, 354 MISCREG_CNTP_CTL_S, 355 MISCREG_CNTV_TVAL, 356 MISCREG_CNTV_CTL, 357 MISCREG_CNTHCTL, 358 MISCREG_CNTHP_TVAL, 359 MISCREG_CNTHP_CTL, 360 MISCREG_IL1DATA0, 361 MISCREG_IL1DATA1, 362 MISCREG_IL1DATA2, 363 MISCREG_IL1DATA3, 364 MISCREG_DL1DATA0, 365 MISCREG_DL1DATA1, 366 MISCREG_DL1DATA2, 367 MISCREG_DL1DATA3, 368 MISCREG_DL1DATA4, 369 MISCREG_RAMINDEX, 370 MISCREG_L2ACTLR, 371 MISCREG_CBAR, 372 MISCREG_HTTBR, 373 MISCREG_VTTBR, 374 MISCREG_CNTPCT, 375 MISCREG_CNTVCT, 376 MISCREG_CNTP_CVAL, 377 MISCREG_CNTP_CVAL_NS, 378 MISCREG_CNTP_CVAL_S, 379 MISCREG_CNTV_CVAL, 380 MISCREG_CNTVOFF, 381 MISCREG_CNTHP_CVAL, 382 MISCREG_CPUMERRSR, 383 MISCREG_L2MERRSR,
384 385 // AArch64 registers (Op0=2)	384 385 // AArch64 registers (Op0=2)
386 MISCREG_MDCCINT_EL1, // 320 387 MISCREG_OSDTRRX_EL1, // 321 388 MISCREG_MDSCR_EL1, // 322 389 MISCREG_OSDTRTX_EL1, // 323 390 MISCREG_OSECCR_EL1, // 324 391 MISCREG_DBGBVR0_EL1, // 325 392 MISCREG_DBGBVR1_EL1, // 326 393 MISCREG_DBGBVR2_EL1, // 327 394 MISCREG_DBGBVR3_EL1, // 328 395 MISCREG_DBGBVR4_EL1, // 329 396 MISCREG_DBGBVR5_EL1, // 330 397 MISCREG_DBGBCR0_EL1, // 331 398 MISCREG_DBGBCR1_EL1, // 332 399 MISCREG_DBGBCR2_EL1, // 333 400 MISCREG_DBGBCR3_EL1, // 334 401 MISCREG_DBGBCR4_EL1, // 335 402 MISCREG_DBGBCR5_EL1, // 336 403 MISCREG_DBGWVR0_EL1, // 337 404 MISCREG_DBGWVR1_EL1, // 338 405 MISCREG_DBGWVR2_EL1, // 339 406 MISCREG_DBGWVR3_EL1, // 340 407 MISCREG_DBGWCR0_EL1, // 341 408 MISCREG_DBGWCR1_EL1, // 342 409 MISCREG_DBGWCR2_EL1, // 343 410 MISCREG_DBGWCR3_EL1, // 344 411 MISCREG_MDCCSR_EL0, // 345 412 MISCREG_MDDTR_EL0, // 346 413 MISCREG_MDDTRTX_EL0, // 347 414 MISCREG_MDDTRRX_EL0, // 348 415 MISCREG_DBGVCR32_EL2, // 349 416 MISCREG_MDRAR_EL1, // 350 417 MISCREG_OSLAR_EL1, // 351 418 MISCREG_OSLSR_EL1, // 352 419 MISCREG_OSDLR_EL1, // 353 420 MISCREG_DBGPRCR_EL1, // 354 421 MISCREG_DBGCLAIMSET_EL1, // 355 422 MISCREG_DBGCLAIMCLR_EL1, // 356 423 MISCREG_DBGAUTHSTATUS_EL1, // 357 424 MISCREG_TEECR32_EL1, // 358, not in ARM DDI 0487A.b+ 425 MISCREG_TEEHBR32_EL1, // 359, not in ARM DDI 0487A.b+	386 MISCREG_MDCCINT_EL1, 387 MISCREG_OSDTRRX_EL1, 388 MISCREG_MDSCR_EL1, 389 MISCREG_OSDTRTX_EL1, 390 MISCREG_OSECCR_EL1, 391 MISCREG_DBGBVR0_EL1, 392 MISCREG_DBGBVR1_EL1, 393 MISCREG_DBGBVR2_EL1, 394 MISCREG_DBGBVR3_EL1, 395 MISCREG_DBGBVR4_EL1, 396 MISCREG_DBGBVR5_EL1, 397 MISCREG_DBGBCR0_EL1, 398 MISCREG_DBGBCR1_EL1, 399 MISCREG_DBGBCR2_EL1, 400 MISCREG_DBGBCR3_EL1, 401 MISCREG_DBGBCR4_EL1, 402 MISCREG_DBGBCR5_EL1, 403 MISCREG_DBGWVR0_EL1, 404 MISCREG_DBGWVR1_EL1, 405 MISCREG_DBGWVR2_EL1, 406 MISCREG_DBGWVR3_EL1, 407 MISCREG_DBGWCR0_EL1, 408 MISCREG_DBGWCR1_EL1, 409 MISCREG_DBGWCR2_EL1, 410 MISCREG_DBGWCR3_EL1, 411 MISCREG_MDCCSR_EL0, 412 MISCREG_MDDTR_EL0, 413 MISCREG_MDDTRTX_EL0, 414 MISCREG_MDDTRRX_EL0, 415 MISCREG_DBGVCR32_EL2, 416 MISCREG_MDRAR_EL1, 417 MISCREG_OSLAR_EL1, 418 MISCREG_OSLSR_EL1, 419 MISCREG_OSDLR_EL1, 420 MISCREG_DBGPRCR_EL1, 421 MISCREG_DBGCLAIMSET_EL1, 422 MISCREG_DBGCLAIMCLR_EL1, 423 MISCREG_DBGAUTHSTATUS_EL1, 424 MISCREG_TEECR32_EL1, // not in ARM DDI 0487A.b+ 425 MISCREG_TEEHBR32_EL1, // not in ARM DDI 0487A.b+
426 427 // AArch64 registers (Op0=1,3)	426 427 // AArch64 registers (Op0=1,3)
428 MISCREG_MIDR_EL1, // 360 429 MISCREG_MPIDR_EL1, // 361 430 MISCREG_REVIDR_EL1, // 362 431 MISCREG_ID_PFR0_EL1, // 363 432 MISCREG_ID_PFR1_EL1, // 364 433 MISCREG_ID_DFR0_EL1, // 365 434 MISCREG_ID_AFR0_EL1, // 366 435 MISCREG_ID_MMFR0_EL1, // 367 436 MISCREG_ID_MMFR1_EL1, // 368 437 MISCREG_ID_MMFR2_EL1, // 369 438 MISCREG_ID_MMFR3_EL1, // 370 439 MISCREG_ID_ISAR0_EL1, // 371 440 MISCREG_ID_ISAR1_EL1, // 372 441 MISCREG_ID_ISAR2_EL1, // 373 442 MISCREG_ID_ISAR3_EL1, // 374 443 MISCREG_ID_ISAR4_EL1, // 375 444 MISCREG_ID_ISAR5_EL1, // 376 445 MISCREG_MVFR0_EL1, // 377 446 MISCREG_MVFR1_EL1, // 378 447 MISCREG_MVFR2_EL1, // 379 448 MISCREG_ID_AA64PFR0_EL1, // 380 449 MISCREG_ID_AA64PFR1_EL1, // 381 450 MISCREG_ID_AA64DFR0_EL1, // 382 451 MISCREG_ID_AA64DFR1_EL1, // 383 452 MISCREG_ID_AA64AFR0_EL1, // 384 453 MISCREG_ID_AA64AFR1_EL1, // 385 454 MISCREG_ID_AA64ISAR0_EL1, // 386 455 MISCREG_ID_AA64ISAR1_EL1, // 387 456 MISCREG_ID_AA64MMFR0_EL1, // 388 457 MISCREG_ID_AA64MMFR1_EL1, // 389 458 MISCREG_CCSIDR_EL1, // 390 459 MISCREG_CLIDR_EL1, // 391 460 MISCREG_AIDR_EL1, // 392 461 MISCREG_CSSELR_EL1, // 393 462 MISCREG_CTR_EL0, // 394 463 MISCREG_DCZID_EL0, // 395 464 MISCREG_VPIDR_EL2, // 396 465 MISCREG_VMPIDR_EL2, // 397 466 MISCREG_SCTLR_EL1, // 398 467 MISCREG_ACTLR_EL1, // 399 468 MISCREG_CPACR_EL1, // 400 469 MISCREG_SCTLR_EL2, // 401 470 MISCREG_ACTLR_EL2, // 402 471 MISCREG_HCR_EL2, // 403 472 MISCREG_MDCR_EL2, // 404 473 MISCREG_CPTR_EL2, // 405 474 MISCREG_HSTR_EL2, // 406 475 MISCREG_HACR_EL2, // 407 476 MISCREG_SCTLR_EL3, // 408 477 MISCREG_ACTLR_EL3, // 409 478 MISCREG_SCR_EL3, // 410 479 MISCREG_SDER32_EL3, // 411 480 MISCREG_CPTR_EL3, // 412 481 MISCREG_MDCR_EL3, // 413 482 MISCREG_TTBR0_EL1, // 414 483 MISCREG_TTBR1_EL1, // 415 484 MISCREG_TCR_EL1, // 416 485 MISCREG_TTBR0_EL2, // 417 486 MISCREG_TCR_EL2, // 418 487 MISCREG_VTTBR_EL2, // 419 488 MISCREG_VTCR_EL2, // 420 489 MISCREG_TTBR0_EL3, // 421 490 MISCREG_TCR_EL3, // 422 491 MISCREG_DACR32_EL2, // 423 492 MISCREG_SPSR_EL1, // 424 493 MISCREG_ELR_EL1, // 425 494 MISCREG_SP_EL0, // 426 495 MISCREG_SPSEL, // 427 496 MISCREG_CURRENTEL, // 428 497 MISCREG_NZCV, // 429 498 MISCREG_DAIF, // 430 499 MISCREG_FPCR, // 431 500 MISCREG_FPSR, // 432 501 MISCREG_DSPSR_EL0, // 433 502 MISCREG_DLR_EL0, // 434 503 MISCREG_SPSR_EL2, // 435 504 MISCREG_ELR_EL2, // 436 505 MISCREG_SP_EL1, // 437 506 MISCREG_SPSR_IRQ_AA64, // 438 507 MISCREG_SPSR_ABT_AA64, // 439 508 MISCREG_SPSR_UND_AA64, // 440 509 MISCREG_SPSR_FIQ_AA64, // 441 510 MISCREG_SPSR_EL3, // 442 511 MISCREG_ELR_EL3, // 443 512 MISCREG_SP_EL2, // 444 513 MISCREG_AFSR0_EL1, // 445 514 MISCREG_AFSR1_EL1, // 446 515 MISCREG_ESR_EL1, // 447 516 MISCREG_IFSR32_EL2, // 448 517 MISCREG_AFSR0_EL2, // 449 518 MISCREG_AFSR1_EL2, // 450 519 MISCREG_ESR_EL2, // 451 520 MISCREG_FPEXC32_EL2, // 452 521 MISCREG_AFSR0_EL3, // 453 522 MISCREG_AFSR1_EL3, // 454 523 MISCREG_ESR_EL3, // 455 524 MISCREG_FAR_EL1, // 456 525 MISCREG_FAR_EL2, // 457 526 MISCREG_HPFAR_EL2, // 458 527 MISCREG_FAR_EL3, // 459 528 MISCREG_IC_IALLUIS, // 460 529 MISCREG_PAR_EL1, // 461 530 MISCREG_IC_IALLU, // 462 531 MISCREG_DC_IVAC_Xt, // 463 532 MISCREG_DC_ISW_Xt, // 464 533 MISCREG_AT_S1E1R_Xt, // 465 534 MISCREG_AT_S1E1W_Xt, // 466 535 MISCREG_AT_S1E0R_Xt, // 467 536 MISCREG_AT_S1E0W_Xt, // 468 537 MISCREG_DC_CSW_Xt, // 469 538 MISCREG_DC_CISW_Xt, // 470 539 MISCREG_DC_ZVA_Xt, // 471 540 MISCREG_IC_IVAU_Xt, // 472 541 MISCREG_DC_CVAC_Xt, // 473 542 MISCREG_DC_CVAU_Xt, // 474 543 MISCREG_DC_CIVAC_Xt, // 475 544 MISCREG_AT_S1E2R_Xt, // 476 545 MISCREG_AT_S1E2W_Xt, // 477 546 MISCREG_AT_S12E1R_Xt, // 478 547 MISCREG_AT_S12E1W_Xt, // 479 548 MISCREG_AT_S12E0R_Xt, // 480 549 MISCREG_AT_S12E0W_Xt, // 481 550 MISCREG_AT_S1E3R_Xt, // 482 551 MISCREG_AT_S1E3W_Xt, // 483 552 MISCREG_TLBI_VMALLE1IS, // 484 553 MISCREG_TLBI_VAE1IS_Xt, // 485 554 MISCREG_TLBI_ASIDE1IS_Xt, // 486 555 MISCREG_TLBI_VAAE1IS_Xt, // 487 556 MISCREG_TLBI_VALE1IS_Xt, // 488 557 MISCREG_TLBI_VAALE1IS_Xt, // 489 558 MISCREG_TLBI_VMALLE1, // 490 559 MISCREG_TLBI_VAE1_Xt, // 491 560 MISCREG_TLBI_ASIDE1_Xt, // 492 561 MISCREG_TLBI_VAAE1_Xt, // 493 562 MISCREG_TLBI_VALE1_Xt, // 494 563 MISCREG_TLBI_VAALE1_Xt, // 495 564 MISCREG_TLBI_IPAS2E1IS_Xt, // 496 565 MISCREG_TLBI_IPAS2LE1IS_Xt, // 497 566 MISCREG_TLBI_ALLE2IS, // 498 567 MISCREG_TLBI_VAE2IS_Xt, // 499 568 MISCREG_TLBI_ALLE1IS, // 500 569 MISCREG_TLBI_VALE2IS_Xt, // 501 570 MISCREG_TLBI_VMALLS12E1IS, // 502 571 MISCREG_TLBI_IPAS2E1_Xt, // 503 572 MISCREG_TLBI_IPAS2LE1_Xt, // 504 573 MISCREG_TLBI_ALLE2, // 505 574 MISCREG_TLBI_VAE2_Xt, // 506 575 MISCREG_TLBI_ALLE1, // 507 576 MISCREG_TLBI_VALE2_Xt, // 508 577 MISCREG_TLBI_VMALLS12E1, // 509 578 MISCREG_TLBI_ALLE3IS, // 510 579 MISCREG_TLBI_VAE3IS_Xt, // 511 580 MISCREG_TLBI_VALE3IS_Xt, // 512 581 MISCREG_TLBI_ALLE3, // 513 582 MISCREG_TLBI_VAE3_Xt, // 514 583 MISCREG_TLBI_VALE3_Xt, // 515 584 MISCREG_PMINTENSET_EL1, // 516 585 MISCREG_PMINTENCLR_EL1, // 517 586 MISCREG_PMCR_EL0, // 518 587 MISCREG_PMCNTENSET_EL0, // 519 588 MISCREG_PMCNTENCLR_EL0, // 520 589 MISCREG_PMOVSCLR_EL0, // 521 590 MISCREG_PMSWINC_EL0, // 522 591 MISCREG_PMSELR_EL0, // 523 592 MISCREG_PMCEID0_EL0, // 524 593 MISCREG_PMCEID1_EL0, // 525 594 MISCREG_PMCCNTR_EL0, // 526 595 MISCREG_PMXEVTYPER_EL0, // 527 596 MISCREG_PMCCFILTR_EL0, // 528 597 MISCREG_PMXEVCNTR_EL0, // 529 598 MISCREG_PMUSERENR_EL0, // 530 599 MISCREG_PMOVSSET_EL0, // 531 600 MISCREG_MAIR_EL1, // 532 601 MISCREG_AMAIR_EL1, // 533 602 MISCREG_MAIR_EL2, // 534 603 MISCREG_AMAIR_EL2, // 535 604 MISCREG_MAIR_EL3, // 536 605 MISCREG_AMAIR_EL3, // 537 606 MISCREG_L2CTLR_EL1, // 538 607 MISCREG_L2ECTLR_EL1, // 539 608 MISCREG_VBAR_EL1, // 540 609 MISCREG_RVBAR_EL1, // 541 610 MISCREG_ISR_EL1, // 542 611 MISCREG_VBAR_EL2, // 543 612 MISCREG_RVBAR_EL2, // 544 613 MISCREG_VBAR_EL3, // 545 614 MISCREG_RVBAR_EL3, // 546 615 MISCREG_RMR_EL3, // 547 616 MISCREG_CONTEXTIDR_EL1, // 548 617 MISCREG_TPIDR_EL1, // 549 618 MISCREG_TPIDR_EL0, // 550 619 MISCREG_TPIDRRO_EL0, // 551 620 MISCREG_TPIDR_EL2, // 552 621 MISCREG_TPIDR_EL3, // 553 622 MISCREG_CNTKCTL_EL1, // 554 623 MISCREG_CNTFRQ_EL0, // 555 624 MISCREG_CNTPCT_EL0, // 556 625 MISCREG_CNTVCT_EL0, // 557 626 MISCREG_CNTP_TVAL_EL0, // 558 627 MISCREG_CNTP_CTL_EL0, // 559 628 MISCREG_CNTP_CVAL_EL0, // 560 629 MISCREG_CNTV_TVAL_EL0, // 561 630 MISCREG_CNTV_CTL_EL0, // 562 631 MISCREG_CNTV_CVAL_EL0, // 563 632 MISCREG_PMEVCNTR0_EL0, // 564 633 MISCREG_PMEVCNTR1_EL0, // 565 634 MISCREG_PMEVCNTR2_EL0, // 566 635 MISCREG_PMEVCNTR3_EL0, // 567 636 MISCREG_PMEVCNTR4_EL0, // 568 637 MISCREG_PMEVCNTR5_EL0, // 569 638 MISCREG_PMEVTYPER0_EL0, // 570 639 MISCREG_PMEVTYPER1_EL0, // 571 640 MISCREG_PMEVTYPER2_EL0, // 572 641 MISCREG_PMEVTYPER3_EL0, // 573 642 MISCREG_PMEVTYPER4_EL0, // 574 643 MISCREG_PMEVTYPER5_EL0, // 575 644 MISCREG_CNTVOFF_EL2, // 576 645 MISCREG_CNTHCTL_EL2, // 577 646 MISCREG_CNTHP_TVAL_EL2, // 578 647 MISCREG_CNTHP_CTL_EL2, // 579 648 MISCREG_CNTHP_CVAL_EL2, // 580 649 MISCREG_CNTPS_TVAL_EL1, // 581 650 MISCREG_CNTPS_CTL_EL1, // 582 651 MISCREG_CNTPS_CVAL_EL1, // 583 652 MISCREG_IL1DATA0_EL1, // 584 653 MISCREG_IL1DATA1_EL1, // 585 654 MISCREG_IL1DATA2_EL1, // 586 655 MISCREG_IL1DATA3_EL1, // 587 656 MISCREG_DL1DATA0_EL1, // 588 657 MISCREG_DL1DATA1_EL1, // 589 658 MISCREG_DL1DATA2_EL1, // 590 659 MISCREG_DL1DATA3_EL1, // 591 660 MISCREG_DL1DATA4_EL1, // 592 661 MISCREG_L2ACTLR_EL1, // 593 662 MISCREG_CPUACTLR_EL1, // 594 663 MISCREG_CPUECTLR_EL1, // 595 664 MISCREG_CPUMERRSR_EL1, // 596 665 MISCREG_L2MERRSR_EL1, // 597 666 MISCREG_CBAR_EL1, // 598 667 MISCREG_CONTEXTIDR_EL2, // 599	428 MISCREG_MIDR_EL1, 429 MISCREG_MPIDR_EL1, 430 MISCREG_REVIDR_EL1, 431 MISCREG_ID_PFR0_EL1, 432 MISCREG_ID_PFR1_EL1, 433 MISCREG_ID_DFR0_EL1, 434 MISCREG_ID_AFR0_EL1, 435 MISCREG_ID_MMFR0_EL1, 436 MISCREG_ID_MMFR1_EL1, 437 MISCREG_ID_MMFR2_EL1, 438 MISCREG_ID_MMFR3_EL1, 439 MISCREG_ID_ISAR0_EL1, 440 MISCREG_ID_ISAR1_EL1, 441 MISCREG_ID_ISAR2_EL1, 442 MISCREG_ID_ISAR3_EL1, 443 MISCREG_ID_ISAR4_EL1, 444 MISCREG_ID_ISAR5_EL1, 445 MISCREG_MVFR0_EL1, 446 MISCREG_MVFR1_EL1, 447 MISCREG_MVFR2_EL1, 448 MISCREG_ID_AA64PFR0_EL1, 449 MISCREG_ID_AA64PFR1_EL1, 450 MISCREG_ID_AA64DFR0_EL1, 451 MISCREG_ID_AA64DFR1_EL1, 452 MISCREG_ID_AA64AFR0_EL1, 453 MISCREG_ID_AA64AFR1_EL1, 454 MISCREG_ID_AA64ISAR0_EL1, 455 MISCREG_ID_AA64ISAR1_EL1, 456 MISCREG_ID_AA64MMFR0_EL1, 457 MISCREG_ID_AA64MMFR1_EL1, 458 MISCREG_CCSIDR_EL1, 459 MISCREG_CLIDR_EL1, 460 MISCREG_AIDR_EL1, 461 MISCREG_CSSELR_EL1, 462 MISCREG_CTR_EL0, 463 MISCREG_DCZID_EL0, 464 MISCREG_VPIDR_EL2, 465 MISCREG_VMPIDR_EL2, 466 MISCREG_SCTLR_EL1, 467 MISCREG_ACTLR_EL1, 468 MISCREG_CPACR_EL1, 469 MISCREG_SCTLR_EL2, 470 MISCREG_ACTLR_EL2, 471 MISCREG_HCR_EL2, 472 MISCREG_MDCR_EL2, 473 MISCREG_CPTR_EL2, 474 MISCREG_HSTR_EL2, 475 MISCREG_HACR_EL2, 476 MISCREG_SCTLR_EL3, 477 MISCREG_ACTLR_EL3, 478 MISCREG_SCR_EL3, 479 MISCREG_SDER32_EL3, 480 MISCREG_CPTR_EL3, 481 MISCREG_MDCR_EL3, 482 MISCREG_TTBR0_EL1, 483 MISCREG_TTBR1_EL1, 484 MISCREG_TCR_EL1, 485 MISCREG_TTBR0_EL2, 486 MISCREG_TCR_EL2, 487 MISCREG_VTTBR_EL2, 488 MISCREG_VTCR_EL2, 489 MISCREG_TTBR0_EL3, 490 MISCREG_TCR_EL3, 491 MISCREG_DACR32_EL2, 492 MISCREG_SPSR_EL1, 493 MISCREG_ELR_EL1, 494 MISCREG_SP_EL0, 495 MISCREG_SPSEL, 496 MISCREG_CURRENTEL, 497 MISCREG_NZCV, 498 MISCREG_DAIF, 499 MISCREG_FPCR, 500 MISCREG_FPSR, 501 MISCREG_DSPSR_EL0, 502 MISCREG_DLR_EL0, 503 MISCREG_SPSR_EL2, 504 MISCREG_ELR_EL2, 505 MISCREG_SP_EL1, 506 MISCREG_SPSR_IRQ_AA64, 507 MISCREG_SPSR_ABT_AA64, 508 MISCREG_SPSR_UND_AA64, 509 MISCREG_SPSR_FIQ_AA64, 510 MISCREG_SPSR_EL3, 511 MISCREG_ELR_EL3, 512 MISCREG_SP_EL2, 513 MISCREG_AFSR0_EL1, 514 MISCREG_AFSR1_EL1, 515 MISCREG_ESR_EL1, 516 MISCREG_IFSR32_EL2, 517 MISCREG_AFSR0_EL2, 518 MISCREG_AFSR1_EL2, 519 MISCREG_ESR_EL2, 520 MISCREG_FPEXC32_EL2, 521 MISCREG_AFSR0_EL3, 522 MISCREG_AFSR1_EL3, 523 MISCREG_ESR_EL3, 524 MISCREG_FAR_EL1, 525 MISCREG_FAR_EL2, 526 MISCREG_HPFAR_EL2, 527 MISCREG_FAR_EL3, 528 MISCREG_IC_IALLUIS, 529 MISCREG_PAR_EL1, 530 MISCREG_IC_IALLU, 531 MISCREG_DC_IVAC_Xt, 532 MISCREG_DC_ISW_Xt, 533 MISCREG_AT_S1E1R_Xt, 534 MISCREG_AT_S1E1W_Xt, 535 MISCREG_AT_S1E0R_Xt, 536 MISCREG_AT_S1E0W_Xt, 537 MISCREG_DC_CSW_Xt, 538 MISCREG_DC_CISW_Xt, 539 MISCREG_DC_ZVA_Xt, 540 MISCREG_IC_IVAU_Xt, 541 MISCREG_DC_CVAC_Xt, 542 MISCREG_DC_CVAU_Xt, 543 MISCREG_DC_CIVAC_Xt, 544 MISCREG_AT_S1E2R_Xt, 545 MISCREG_AT_S1E2W_Xt, 546 MISCREG_AT_S12E1R_Xt, 547 MISCREG_AT_S12E1W_Xt, 548 MISCREG_AT_S12E0R_Xt, 549 MISCREG_AT_S12E0W_Xt, 550 MISCREG_AT_S1E3R_Xt, 551 MISCREG_AT_S1E3W_Xt, 552 MISCREG_TLBI_VMALLE1IS, 553 MISCREG_TLBI_VAE1IS_Xt, 554 MISCREG_TLBI_ASIDE1IS_Xt, 555 MISCREG_TLBI_VAAE1IS_Xt, 556 MISCREG_TLBI_VALE1IS_Xt, 557 MISCREG_TLBI_VAALE1IS_Xt, 558 MISCREG_TLBI_VMALLE1, 559 MISCREG_TLBI_VAE1_Xt, 560 MISCREG_TLBI_ASIDE1_Xt, 561 MISCREG_TLBI_VAAE1_Xt, 562 MISCREG_TLBI_VALE1_Xt, 563 MISCREG_TLBI_VAALE1_Xt, 564 MISCREG_TLBI_IPAS2E1IS_Xt, 565 MISCREG_TLBI_IPAS2LE1IS_Xt, 566 MISCREG_TLBI_ALLE2IS, 567 MISCREG_TLBI_VAE2IS_Xt, 568 MISCREG_TLBI_ALLE1IS, 569 MISCREG_TLBI_VALE2IS_Xt, 570 MISCREG_TLBI_VMALLS12E1IS, 571 MISCREG_TLBI_IPAS2E1_Xt, 572 MISCREG_TLBI_IPAS2LE1_Xt, 573 MISCREG_TLBI_ALLE2, 574 MISCREG_TLBI_VAE2_Xt, 575 MISCREG_TLBI_ALLE1, 576 MISCREG_TLBI_VALE2_Xt, 577 MISCREG_TLBI_VMALLS12E1, 578 MISCREG_TLBI_ALLE3IS, 579 MISCREG_TLBI_VAE3IS_Xt, 580 MISCREG_TLBI_VALE3IS_Xt, 581 MISCREG_TLBI_ALLE3, 582 MISCREG_TLBI_VAE3_Xt, 583 MISCREG_TLBI_VALE3_Xt, 584 MISCREG_PMINTENSET_EL1, 585 MISCREG_PMINTENCLR_EL1, 586 MISCREG_PMCR_EL0, 587 MISCREG_PMCNTENSET_EL0, 588 MISCREG_PMCNTENCLR_EL0, 589 MISCREG_PMOVSCLR_EL0, 590 MISCREG_PMSWINC_EL0, 591 MISCREG_PMSELR_EL0, 592 MISCREG_PMCEID0_EL0, 593 MISCREG_PMCEID1_EL0, 594 MISCREG_PMCCNTR_EL0, 595 MISCREG_PMXEVTYPER_EL0, 596 MISCREG_PMCCFILTR_EL0, 597 MISCREG_PMXEVCNTR_EL0, 598 MISCREG_PMUSERENR_EL0, 599 MISCREG_PMOVSSET_EL0, 600 MISCREG_MAIR_EL1, 601 MISCREG_AMAIR_EL1, 602 MISCREG_MAIR_EL2, 603 MISCREG_AMAIR_EL2, 604 MISCREG_MAIR_EL3, 605 MISCREG_AMAIR_EL3, 606 MISCREG_L2CTLR_EL1, 607 MISCREG_L2ECTLR_EL1, 608 MISCREG_VBAR_EL1, 609 MISCREG_RVBAR_EL1, 610 MISCREG_ISR_EL1, 611 MISCREG_VBAR_EL2, 612 MISCREG_RVBAR_EL2, 613 MISCREG_VBAR_EL3, 614 MISCREG_RVBAR_EL3, 615 MISCREG_RMR_EL3, 616 MISCREG_CONTEXTIDR_EL1, 617 MISCREG_TPIDR_EL1, 618 MISCREG_TPIDR_EL0, 619 MISCREG_TPIDRRO_EL0, 620 MISCREG_TPIDR_EL2, 621 MISCREG_TPIDR_EL3, 622 MISCREG_CNTKCTL_EL1, 623 MISCREG_CNTFRQ_EL0, 624 MISCREG_CNTPCT_EL0, 625 MISCREG_CNTVCT_EL0, 626 MISCREG_CNTP_TVAL_EL0, 627 MISCREG_CNTP_CTL_EL0, 628 MISCREG_CNTP_CVAL_EL0, 629 MISCREG_CNTV_TVAL_EL0, 630 MISCREG_CNTV_CTL_EL0, 631 MISCREG_CNTV_CVAL_EL0, 632 MISCREG_PMEVCNTR0_EL0, 633 MISCREG_PMEVCNTR1_EL0, 634 MISCREG_PMEVCNTR2_EL0, 635 MISCREG_PMEVCNTR3_EL0, 636 MISCREG_PMEVCNTR4_EL0, 637 MISCREG_PMEVCNTR5_EL0, 638 MISCREG_PMEVTYPER0_EL0, 639 MISCREG_PMEVTYPER1_EL0, 640 MISCREG_PMEVTYPER2_EL0, 641 MISCREG_PMEVTYPER3_EL0, 642 MISCREG_PMEVTYPER4_EL0, 643 MISCREG_PMEVTYPER5_EL0, 644 MISCREG_CNTVOFF_EL2, 645 MISCREG_CNTHCTL_EL2, 646 MISCREG_CNTHP_TVAL_EL2, 647 MISCREG_CNTHP_CTL_EL2, 648 MISCREG_CNTHP_CVAL_EL2, 649 MISCREG_CNTPS_TVAL_EL1, 650 MISCREG_CNTPS_CTL_EL1, 651 MISCREG_CNTPS_CVAL_EL1, 652 MISCREG_IL1DATA0_EL1, 653 MISCREG_IL1DATA1_EL1, 654 MISCREG_IL1DATA2_EL1, 655 MISCREG_IL1DATA3_EL1, 656 MISCREG_DL1DATA0_EL1, 657 MISCREG_DL1DATA1_EL1, 658 MISCREG_DL1DATA2_EL1, 659 MISCREG_DL1DATA3_EL1, 660 MISCREG_DL1DATA4_EL1, 661 MISCREG_L2ACTLR_EL1, 662 MISCREG_CPUACTLR_EL1, 663 MISCREG_CPUECTLR_EL1, 664 MISCREG_CPUMERRSR_EL1, 665 MISCREG_L2MERRSR_EL1, 666 MISCREG_CBAR_EL1, 667 MISCREG_CONTEXTIDR_EL2,
668 669 // Introduced in ARMv8.1	668 669 // Introduced in ARMv8.1
670 MISCREG_TTBR1_EL2, // 600 671 MISCREG_CNTHV_CTL_EL2, // 601 672 MISCREG_CNTHV_CVAL_EL2, // 602 673 MISCREG_CNTHV_TVAL_EL2, // 603	670 MISCREG_TTBR1_EL2, 671 MISCREG_CNTHV_CTL_EL2, 672 MISCREG_CNTHV_CVAL_EL2, 673 MISCREG_CNTHV_TVAL_EL2,
674	674
675 MISCREG_ID_AA64MMFR2_EL1, // 604	675 MISCREG_ID_AA64MMFR2_EL1,
676 // These MISCREG_FREESLOT are available Misc Register 677 // slots for future registers to be implemented.	676 // These MISCREG_FREESLOT are available Misc Register 677 // slots for future registers to be implemented.
678 MISCREG_FREESLOT_1, // 605	678 MISCREG_FREESLOT_1,
679 680 // NUM_PHYS_MISCREGS specifies the number of actual physical 681 // registers, not considering the following pseudo-registers 682 // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL. 683 // Checkpointing should use this physical index when 684 // saving/restoring register values.	679 680 // NUM_PHYS_MISCREGS specifies the number of actual physical 681 // registers, not considering the following pseudo-registers 682 // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL. 683 // Checkpointing should use this physical index when 684 // saving/restoring register values.
685 NUM_PHYS_MISCREGS = 606, // 606	685 NUM_PHYS_MISCREGS,
686 687 // Dummy registers 688 MISCREG_NOP, 689 MISCREG_RAZ, 690 MISCREG_CP14_UNIMPL, 691 MISCREG_CP15_UNIMPL, 692 MISCREG_UNKNOWN, 693 --- 812 unchanged lines hidden ---	686 687 // Dummy registers 688 MISCREG_NOP, 689 MISCREG_RAZ, 690 MISCREG_CP14_UNIMPL, 691 MISCREG_CP15_UNIMPL, 692 MISCREG_UNKNOWN, 693 --- 812 unchanged lines hidden ---

1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 41 unchanged lines hidden (view full) ---

50#include "base/compiler.hh"
51
52class ThreadContext;
53
54
55namespace ArmISA
56{
57 enum MiscRegIndex {

58 MISCREG_CPSR = 0, // 0
59 MISCREG_SPSR, // 1
60 MISCREG_SPSR_FIQ, // 2
61 MISCREG_SPSR_IRQ, // 3
62 MISCREG_SPSR_SVC, // 4
63 MISCREG_SPSR_MON, // 5
64 MISCREG_SPSR_ABT, // 6
65 MISCREG_SPSR_HYP, // 7
66 MISCREG_SPSR_UND, // 8
67 MISCREG_ELR_HYP, // 9
68 MISCREG_FPSID, // 10
69 MISCREG_FPSCR, // 11
70 MISCREG_MVFR1, // 12
71 MISCREG_MVFR0, // 13
72 MISCREG_FPEXC, // 14

58 MISCREG_CPSR = 0,
59 MISCREG_SPSR,
60 MISCREG_SPSR_FIQ,
61 MISCREG_SPSR_IRQ,
62 MISCREG_SPSR_SVC,
63 MISCREG_SPSR_MON,
64 MISCREG_SPSR_ABT,
65 MISCREG_SPSR_HYP,
66 MISCREG_SPSR_UND,
67 MISCREG_ELR_HYP,
68 MISCREG_FPSID,
69 MISCREG_FPSCR,
70 MISCREG_MVFR1,
71 MISCREG_MVFR0,
72 MISCREG_FPEXC,

73
74 // Helper registers

75 MISCREG_CPSR_MODE, // 15
76 MISCREG_CPSR_Q, // 16
77 MISCREG_FPSCR_EXC, // 17
78 MISCREG_FPSCR_QC, // 18
79 MISCREG_LOCKADDR, // 19
80 MISCREG_LOCKFLAG, // 20
81 MISCREG_PRRR_MAIR0, // 21
82 MISCREG_PRRR_MAIR0_NS, // 22
83 MISCREG_PRRR_MAIR0_S, // 23
84 MISCREG_NMRR_MAIR1, // 24
85 MISCREG_NMRR_MAIR1_NS, // 25
86 MISCREG_NMRR_MAIR1_S, // 26
87 MISCREG_PMXEVTYPER_PMCCFILTR, // 27
88 MISCREG_SCTLR_RST, // 28
89 MISCREG_SEV_MAILBOX, // 29

75 MISCREG_CPSR_MODE,
76 MISCREG_CPSR_Q,
77 MISCREG_FPSCR_EXC,
78 MISCREG_FPSCR_QC,
79 MISCREG_LOCKADDR,
80 MISCREG_LOCKFLAG,
81 MISCREG_PRRR_MAIR0,
82 MISCREG_PRRR_MAIR0_NS,
83 MISCREG_PRRR_MAIR0_S,
84 MISCREG_NMRR_MAIR1,
85 MISCREG_NMRR_MAIR1_NS,
86 MISCREG_NMRR_MAIR1_S,
87 MISCREG_PMXEVTYPER_PMCCFILTR,
88 MISCREG_SCTLR_RST,
89 MISCREG_SEV_MAILBOX,

90
91 // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)

92 MISCREG_DBGDIDR, // 30
93 MISCREG_DBGDSCRint, // 31
94 MISCREG_DBGDCCINT, // 32
95 MISCREG_DBGDTRTXint, // 33
96 MISCREG_DBGDTRRXint, // 34
97 MISCREG_DBGWFAR, // 35
98 MISCREG_DBGVCR, // 36
99 MISCREG_DBGDTRRXext, // 37
100 MISCREG_DBGDSCRext, // 38
101 MISCREG_DBGDTRTXext, // 39
102 MISCREG_DBGOSECCR, // 40
103 MISCREG_DBGBVR0, // 41
104 MISCREG_DBGBVR1, // 42
105 MISCREG_DBGBVR2, // 43
106 MISCREG_DBGBVR3, // 44
107 MISCREG_DBGBVR4, // 45
108 MISCREG_DBGBVR5, // 46
109 MISCREG_DBGBCR0, // 47
110 MISCREG_DBGBCR1, // 48
111 MISCREG_DBGBCR2, // 49
112 MISCREG_DBGBCR3, // 50
113 MISCREG_DBGBCR4, // 51
114 MISCREG_DBGBCR5, // 52
115 MISCREG_DBGWVR0, // 53
116 MISCREG_DBGWVR1, // 54
117 MISCREG_DBGWVR2, // 55
118 MISCREG_DBGWVR3, // 56
119 MISCREG_DBGWCR0, // 57
120 MISCREG_DBGWCR1, // 58
121 MISCREG_DBGWCR2, // 59
122 MISCREG_DBGWCR3, // 60
123 MISCREG_DBGDRAR, // 61
124 MISCREG_DBGBXVR4, // 62
125 MISCREG_DBGBXVR5, // 63
126 MISCREG_DBGOSLAR, // 64
127 MISCREG_DBGOSLSR, // 65
128 MISCREG_DBGOSDLR, // 66
129 MISCREG_DBGPRCR, // 67
130 MISCREG_DBGDSAR, // 68
131 MISCREG_DBGCLAIMSET, // 69
132 MISCREG_DBGCLAIMCLR, // 70
133 MISCREG_DBGAUTHSTATUS, // 71
134 MISCREG_DBGDEVID2, // 72
135 MISCREG_DBGDEVID1, // 73
136 MISCREG_DBGDEVID0, // 74
137 MISCREG_TEECR, // 75, not in ARM DDI 0487A.b+
138 MISCREG_JIDR, // 76
139 MISCREG_TEEHBR, // 77, not in ARM DDI 0487A.b+
140 MISCREG_JOSCR, // 78
141 MISCREG_JMCR, // 79

92 MISCREG_DBGDIDR,
93 MISCREG_DBGDSCRint,
94 MISCREG_DBGDCCINT,
95 MISCREG_DBGDTRTXint,
96 MISCREG_DBGDTRRXint,
97 MISCREG_DBGWFAR,
98 MISCREG_DBGVCR,
99 MISCREG_DBGDTRRXext,
100 MISCREG_DBGDSCRext,
101 MISCREG_DBGDTRTXext,
102 MISCREG_DBGOSECCR,
103 MISCREG_DBGBVR0,
104 MISCREG_DBGBVR1,
105 MISCREG_DBGBVR2,
106 MISCREG_DBGBVR3,
107 MISCREG_DBGBVR4,
108 MISCREG_DBGBVR5,
109 MISCREG_DBGBCR0,
110 MISCREG_DBGBCR1,
111 MISCREG_DBGBCR2,
112 MISCREG_DBGBCR3,
113 MISCREG_DBGBCR4,
114 MISCREG_DBGBCR5,
115 MISCREG_DBGWVR0,
116 MISCREG_DBGWVR1,
117 MISCREG_DBGWVR2,
118 MISCREG_DBGWVR3,
119 MISCREG_DBGWCR0,
120 MISCREG_DBGWCR1,
121 MISCREG_DBGWCR2,
122 MISCREG_DBGWCR3,
123 MISCREG_DBGDRAR,
124 MISCREG_DBGBXVR4,
125 MISCREG_DBGBXVR5,
126 MISCREG_DBGOSLAR,
127 MISCREG_DBGOSLSR,
128 MISCREG_DBGOSDLR,
129 MISCREG_DBGPRCR,
130 MISCREG_DBGDSAR,
131 MISCREG_DBGCLAIMSET,
132 MISCREG_DBGCLAIMCLR,
133 MISCREG_DBGAUTHSTATUS,
134 MISCREG_DBGDEVID2,
135 MISCREG_DBGDEVID1,
136 MISCREG_DBGDEVID0,
137 MISCREG_TEECR, // not in ARM DDI 0487A.b+
138 MISCREG_JIDR,
139 MISCREG_TEEHBR, // not in ARM DDI 0487A.b+
140 MISCREG_JOSCR,
141 MISCREG_JMCR,

142
143 // AArch32 CP15 registers (system control)

144 MISCREG_MIDR, // 80
145 MISCREG_CTR, // 81
146 MISCREG_TCMTR, // 82
147 MISCREG_TLBTR, // 83
148 MISCREG_MPIDR, // 84
149 MISCREG_REVIDR, // 85
150 MISCREG_ID_PFR0, // 86
151 MISCREG_ID_PFR1, // 87
152 MISCREG_ID_DFR0, // 88
153 MISCREG_ID_AFR0, // 89
154 MISCREG_ID_MMFR0, // 90
155 MISCREG_ID_MMFR1, // 91
156 MISCREG_ID_MMFR2, // 92
157 MISCREG_ID_MMFR3, // 93
158 MISCREG_ID_ISAR0, // 94
159 MISCREG_ID_ISAR1, // 95
160 MISCREG_ID_ISAR2, // 96
161 MISCREG_ID_ISAR3, // 97
162 MISCREG_ID_ISAR4, // 98
163 MISCREG_ID_ISAR5, // 99
164 MISCREG_CCSIDR, // 100
165 MISCREG_CLIDR, // 101
166 MISCREG_AIDR, // 102
167 MISCREG_CSSELR, // 103
168 MISCREG_CSSELR_NS, // 104
169 MISCREG_CSSELR_S, // 105
170 MISCREG_VPIDR, // 106
171 MISCREG_VMPIDR, // 107
172 MISCREG_SCTLR, // 108
173 MISCREG_SCTLR_NS, // 109
174 MISCREG_SCTLR_S, // 110
175 MISCREG_ACTLR, // 111
176 MISCREG_ACTLR_NS, // 112
177 MISCREG_ACTLR_S, // 113
178 MISCREG_CPACR, // 114
179 MISCREG_SCR, // 115
180 MISCREG_SDER, // 116
181 MISCREG_NSACR, // 117
182 MISCREG_HSCTLR, // 118
183 MISCREG_HACTLR, // 119
184 MISCREG_HCR, // 120
185 MISCREG_HDCR, // 121
186 MISCREG_HCPTR, // 122
187 MISCREG_HSTR, // 123
188 MISCREG_HACR, // 124
189 MISCREG_TTBR0, // 125
190 MISCREG_TTBR0_NS, // 126
191 MISCREG_TTBR0_S, // 127
192 MISCREG_TTBR1, // 128
193 MISCREG_TTBR1_NS, // 129
194 MISCREG_TTBR1_S, // 130
195 MISCREG_TTBCR, // 131
196 MISCREG_TTBCR_NS, // 132
197 MISCREG_TTBCR_S, // 133
198 MISCREG_HTCR, // 134
199 MISCREG_VTCR, // 135
200 MISCREG_DACR, // 136
201 MISCREG_DACR_NS, // 137
202 MISCREG_DACR_S, // 138
203 MISCREG_DFSR, // 139
204 MISCREG_DFSR_NS, // 140
205 MISCREG_DFSR_S, // 141
206 MISCREG_IFSR, // 142
207 MISCREG_IFSR_NS, // 143
208 MISCREG_IFSR_S, // 144
209 MISCREG_ADFSR, // 145
210 MISCREG_ADFSR_NS, // 146
211 MISCREG_ADFSR_S, // 147
212 MISCREG_AIFSR, // 148
213 MISCREG_AIFSR_NS, // 149
214 MISCREG_AIFSR_S, // 150
215 MISCREG_HADFSR, // 151
216 MISCREG_HAIFSR, // 152
217 MISCREG_HSR, // 153
218 MISCREG_DFAR, // 154
219 MISCREG_DFAR_NS, // 155
220 MISCREG_DFAR_S, // 156
221 MISCREG_IFAR, // 157
222 MISCREG_IFAR_NS, // 158
223 MISCREG_IFAR_S, // 159
224 MISCREG_HDFAR, // 160
225 MISCREG_HIFAR, // 161
226 MISCREG_HPFAR, // 162
227 MISCREG_ICIALLUIS, // 163
228 MISCREG_BPIALLIS, // 164
229 MISCREG_PAR, // 165
230 MISCREG_PAR_NS, // 166
231 MISCREG_PAR_S, // 167
232 MISCREG_ICIALLU, // 168
233 MISCREG_ICIMVAU, // 169
234 MISCREG_CP15ISB, // 170
235 MISCREG_BPIALL, // 171
236 MISCREG_BPIMVA, // 172
237 MISCREG_DCIMVAC, // 173
238 MISCREG_DCISW, // 174
239 MISCREG_ATS1CPR, // 175
240 MISCREG_ATS1CPW, // 176
241 MISCREG_ATS1CUR, // 177
242 MISCREG_ATS1CUW, // 178
243 MISCREG_ATS12NSOPR, // 179
244 MISCREG_ATS12NSOPW, // 180
245 MISCREG_ATS12NSOUR, // 181
246 MISCREG_ATS12NSOUW, // 182
247 MISCREG_DCCMVAC, // 183
248 MISCREG_DCCSW, // 184
249 MISCREG_CP15DSB, // 185
250 MISCREG_CP15DMB, // 186
251 MISCREG_DCCMVAU, // 187
252 MISCREG_DCCIMVAC, // 188
253 MISCREG_DCCISW, // 189
254 MISCREG_ATS1HR, // 190
255 MISCREG_ATS1HW, // 191
256 MISCREG_TLBIALLIS, // 192
257 MISCREG_TLBIMVAIS, // 193
258 MISCREG_TLBIASIDIS, // 194
259 MISCREG_TLBIMVAAIS, // 195
260 MISCREG_TLBIMVALIS, // 196
261 MISCREG_TLBIMVAALIS, // 197
262 MISCREG_ITLBIALL, // 198
263 MISCREG_ITLBIMVA, // 199
264 MISCREG_ITLBIASID, // 200
265 MISCREG_DTLBIALL, // 201
266 MISCREG_DTLBIMVA, // 202
267 MISCREG_DTLBIASID, // 203
268 MISCREG_TLBIALL, // 204
269 MISCREG_TLBIMVA, // 205
270 MISCREG_TLBIASID, // 206
271 MISCREG_TLBIMVAA, // 207
272 MISCREG_TLBIMVAL, // 208
273 MISCREG_TLBIMVAAL, // 209
274 MISCREG_TLBIIPAS2IS, // 210
275 MISCREG_TLBIIPAS2LIS, // 211
276 MISCREG_TLBIALLHIS, // 212
277 MISCREG_TLBIMVAHIS, // 213
278 MISCREG_TLBIALLNSNHIS, // 214
279 MISCREG_TLBIMVALHIS, // 215
280 MISCREG_TLBIIPAS2, // 216
281 MISCREG_TLBIIPAS2L, // 217
282 MISCREG_TLBIALLH, // 218
283 MISCREG_TLBIMVAH, // 219
284 MISCREG_TLBIALLNSNH, // 220
285 MISCREG_TLBIMVALH, // 221
286 MISCREG_PMCR, // 222
287 MISCREG_PMCNTENSET, // 223
288 MISCREG_PMCNTENCLR, // 224
289 MISCREG_PMOVSR, // 225
290 MISCREG_PMSWINC, // 226
291 MISCREG_PMSELR, // 227
292 MISCREG_PMCEID0, // 228
293 MISCREG_PMCEID1, // 229
294 MISCREG_PMCCNTR, // 230
295 MISCREG_PMXEVTYPER, // 231
296 MISCREG_PMCCFILTR, // 232
297 MISCREG_PMXEVCNTR, // 233
298 MISCREG_PMUSERENR, // 234
299 MISCREG_PMINTENSET, // 235
300 MISCREG_PMINTENCLR, // 236
301 MISCREG_PMOVSSET, // 237
302 MISCREG_L2CTLR, // 238
303 MISCREG_L2ECTLR, // 239
304 MISCREG_PRRR, // 240
305 MISCREG_PRRR_NS, // 241
306 MISCREG_PRRR_S, // 242
307 MISCREG_MAIR0, // 243
308 MISCREG_MAIR0_NS, // 244
309 MISCREG_MAIR0_S, // 245
310 MISCREG_NMRR, // 246
311 MISCREG_NMRR_NS, // 247
312 MISCREG_NMRR_S, // 248
313 MISCREG_MAIR1, // 249
314 MISCREG_MAIR1_NS, // 250
315 MISCREG_MAIR1_S, // 251
316 MISCREG_AMAIR0, // 252
317 MISCREG_AMAIR0_NS, // 253
318 MISCREG_AMAIR0_S, // 254
319 MISCREG_AMAIR1, // 255
320 MISCREG_AMAIR1_NS, // 256
321 MISCREG_AMAIR1_S, // 257
322 MISCREG_HMAIR0, // 258
323 MISCREG_HMAIR1, // 259
324 MISCREG_HAMAIR0, // 260
325 MISCREG_HAMAIR1, // 261
326 MISCREG_VBAR, // 262
327 MISCREG_VBAR_NS, // 263
328 MISCREG_VBAR_S, // 264
329 MISCREG_MVBAR, // 265
330 MISCREG_RMR, // 266
331 MISCREG_ISR, // 267
332 MISCREG_HVBAR, // 268
333 MISCREG_FCSEIDR, // 269
334 MISCREG_CONTEXTIDR, // 270
335 MISCREG_CONTEXTIDR_NS, // 271
336 MISCREG_CONTEXTIDR_S, // 272
337 MISCREG_TPIDRURW, // 273
338 MISCREG_TPIDRURW_NS, // 274
339 MISCREG_TPIDRURW_S, // 275
340 MISCREG_TPIDRURO, // 276
341 MISCREG_TPIDRURO_NS, // 277
342 MISCREG_TPIDRURO_S, // 278
343 MISCREG_TPIDRPRW, // 279
344 MISCREG_TPIDRPRW_NS, // 280
345 MISCREG_TPIDRPRW_S, // 281
346 MISCREG_HTPIDR, // 282
347 MISCREG_CNTFRQ, // 283
348 MISCREG_CNTKCTL, // 284
349 MISCREG_CNTP_TVAL, // 285
350 MISCREG_CNTP_TVAL_NS, // 286
351 MISCREG_CNTP_TVAL_S, // 287
352 MISCREG_CNTP_CTL, // 288
353 MISCREG_CNTP_CTL_NS, // 289
354 MISCREG_CNTP_CTL_S, // 290
355 MISCREG_CNTV_TVAL, // 291
356 MISCREG_CNTV_CTL, // 292
357 MISCREG_CNTHCTL, // 293
358 MISCREG_CNTHP_TVAL, // 294
359 MISCREG_CNTHP_CTL, // 295
360 MISCREG_IL1DATA0, // 296
361 MISCREG_IL1DATA1, // 297
362 MISCREG_IL1DATA2, // 298
363 MISCREG_IL1DATA3, // 299
364 MISCREG_DL1DATA0, // 300
365 MISCREG_DL1DATA1, // 301
366 MISCREG_DL1DATA2, // 302
367 MISCREG_DL1DATA3, // 303
368 MISCREG_DL1DATA4, // 304
369 MISCREG_RAMINDEX, // 305
370 MISCREG_L2ACTLR, // 306
371 MISCREG_CBAR, // 307
372 MISCREG_HTTBR, // 308
373 MISCREG_VTTBR, // 309
374 MISCREG_CNTPCT, // 310
375 MISCREG_CNTVCT, // 311
376 MISCREG_CNTP_CVAL, // 312
377 MISCREG_CNTP_CVAL_NS, // 313
378 MISCREG_CNTP_CVAL_S, // 314
379 MISCREG_CNTV_CVAL, // 315
380 MISCREG_CNTVOFF, // 316
381 MISCREG_CNTHP_CVAL, // 317
382 MISCREG_CPUMERRSR, // 318
383 MISCREG_L2MERRSR, // 319

144 MISCREG_MIDR,
145 MISCREG_CTR,
146 MISCREG_TCMTR,
147 MISCREG_TLBTR,
148 MISCREG_MPIDR,
149 MISCREG_REVIDR,
150 MISCREG_ID_PFR0,
151 MISCREG_ID_PFR1,
152 MISCREG_ID_DFR0,
153 MISCREG_ID_AFR0,
154 MISCREG_ID_MMFR0,
155 MISCREG_ID_MMFR1,
156 MISCREG_ID_MMFR2,
157 MISCREG_ID_MMFR3,
158 MISCREG_ID_ISAR0,
159 MISCREG_ID_ISAR1,
160 MISCREG_ID_ISAR2,
161 MISCREG_ID_ISAR3,
162 MISCREG_ID_ISAR4,
163 MISCREG_ID_ISAR5,
164 MISCREG_CCSIDR,
165 MISCREG_CLIDR,
166 MISCREG_AIDR,
167 MISCREG_CSSELR,
168 MISCREG_CSSELR_NS,
169 MISCREG_CSSELR_S,
170 MISCREG_VPIDR,
171 MISCREG_VMPIDR,
172 MISCREG_SCTLR,
173 MISCREG_SCTLR_NS,
174 MISCREG_SCTLR_S,
175 MISCREG_ACTLR,
176 MISCREG_ACTLR_NS,
177 MISCREG_ACTLR_S,
178 MISCREG_CPACR,
179 MISCREG_SCR,
180 MISCREG_SDER,
181 MISCREG_NSACR,
182 MISCREG_HSCTLR,
183 MISCREG_HACTLR,
184 MISCREG_HCR,
185 MISCREG_HDCR,
186 MISCREG_HCPTR,
187 MISCREG_HSTR,
188 MISCREG_HACR,
189 MISCREG_TTBR0,
190 MISCREG_TTBR0_NS,
191 MISCREG_TTBR0_S,
192 MISCREG_TTBR1,
193 MISCREG_TTBR1_NS,
194 MISCREG_TTBR1_S,
195 MISCREG_TTBCR,
196 MISCREG_TTBCR_NS,
197 MISCREG_TTBCR_S,
198 MISCREG_HTCR,
199 MISCREG_VTCR,
200 MISCREG_DACR,
201 MISCREG_DACR_NS,
202 MISCREG_DACR_S,
203 MISCREG_DFSR,
204 MISCREG_DFSR_NS,
205 MISCREG_DFSR_S,
206 MISCREG_IFSR,
207 MISCREG_IFSR_NS,
208 MISCREG_IFSR_S,
209 MISCREG_ADFSR,
210 MISCREG_ADFSR_NS,
211 MISCREG_ADFSR_S,
212 MISCREG_AIFSR,
213 MISCREG_AIFSR_NS,
214 MISCREG_AIFSR_S,
215 MISCREG_HADFSR,
216 MISCREG_HAIFSR,
217 MISCREG_HSR,
218 MISCREG_DFAR,
219 MISCREG_DFAR_NS,
220 MISCREG_DFAR_S,
221 MISCREG_IFAR,
222 MISCREG_IFAR_NS,
223 MISCREG_IFAR_S,
224 MISCREG_HDFAR,
225 MISCREG_HIFAR,
226 MISCREG_HPFAR,
227 MISCREG_ICIALLUIS,
228 MISCREG_BPIALLIS,
229 MISCREG_PAR,
230 MISCREG_PAR_NS,
231 MISCREG_PAR_S,
232 MISCREG_ICIALLU,
233 MISCREG_ICIMVAU,
234 MISCREG_CP15ISB,
235 MISCREG_BPIALL,
236 MISCREG_BPIMVA,
237 MISCREG_DCIMVAC,
238 MISCREG_DCISW,
239 MISCREG_ATS1CPR,
240 MISCREG_ATS1CPW,
241 MISCREG_ATS1CUR,
242 MISCREG_ATS1CUW,
243 MISCREG_ATS12NSOPR,
244 MISCREG_ATS12NSOPW,
245 MISCREG_ATS12NSOUR,
246 MISCREG_ATS12NSOUW,
247 MISCREG_DCCMVAC,
248 MISCREG_DCCSW,
249 MISCREG_CP15DSB,
250 MISCREG_CP15DMB,
251 MISCREG_DCCMVAU,
252 MISCREG_DCCIMVAC,
253 MISCREG_DCCISW,
254 MISCREG_ATS1HR,
255 MISCREG_ATS1HW,
256 MISCREG_TLBIALLIS,
257 MISCREG_TLBIMVAIS,
258 MISCREG_TLBIASIDIS,
259 MISCREG_TLBIMVAAIS,
260 MISCREG_TLBIMVALIS,
261 MISCREG_TLBIMVAALIS,
262 MISCREG_ITLBIALL,
263 MISCREG_ITLBIMVA,
264 MISCREG_ITLBIASID,
265 MISCREG_DTLBIALL,
266 MISCREG_DTLBIMVA,
267 MISCREG_DTLBIASID,
268 MISCREG_TLBIALL,
269 MISCREG_TLBIMVA,
270 MISCREG_TLBIASID,
271 MISCREG_TLBIMVAA,
272 MISCREG_TLBIMVAL,
273 MISCREG_TLBIMVAAL,
274 MISCREG_TLBIIPAS2IS,
275 MISCREG_TLBIIPAS2LIS,
276 MISCREG_TLBIALLHIS,
277 MISCREG_TLBIMVAHIS,
278 MISCREG_TLBIALLNSNHIS,
279 MISCREG_TLBIMVALHIS,
280 MISCREG_TLBIIPAS2,
281 MISCREG_TLBIIPAS2L,
282 MISCREG_TLBIALLH,
283 MISCREG_TLBIMVAH,
284 MISCREG_TLBIALLNSNH,
285 MISCREG_TLBIMVALH,
286 MISCREG_PMCR,
287 MISCREG_PMCNTENSET,
288 MISCREG_PMCNTENCLR,
289 MISCREG_PMOVSR,
290 MISCREG_PMSWINC,
291 MISCREG_PMSELR,
292 MISCREG_PMCEID0,
293 MISCREG_PMCEID1,
294 MISCREG_PMCCNTR,
295 MISCREG_PMXEVTYPER,
296 MISCREG_PMCCFILTR,
297 MISCREG_PMXEVCNTR,
298 MISCREG_PMUSERENR,
299 MISCREG_PMINTENSET,
300 MISCREG_PMINTENCLR,
301 MISCREG_PMOVSSET,
302 MISCREG_L2CTLR,
303 MISCREG_L2ECTLR,
304 MISCREG_PRRR,
305 MISCREG_PRRR_NS,
306 MISCREG_PRRR_S,
307 MISCREG_MAIR0,
308 MISCREG_MAIR0_NS,
309 MISCREG_MAIR0_S,
310 MISCREG_NMRR,
311 MISCREG_NMRR_NS,
312 MISCREG_NMRR_S,
313 MISCREG_MAIR1,
314 MISCREG_MAIR1_NS,
315 MISCREG_MAIR1_S,
316 MISCREG_AMAIR0,
317 MISCREG_AMAIR0_NS,
318 MISCREG_AMAIR0_S,
319 MISCREG_AMAIR1,
320 MISCREG_AMAIR1_NS,
321 MISCREG_AMAIR1_S,
322 MISCREG_HMAIR0,
323 MISCREG_HMAIR1,
324 MISCREG_HAMAIR0,
325 MISCREG_HAMAIR1,
326 MISCREG_VBAR,
327 MISCREG_VBAR_NS,
328 MISCREG_VBAR_S,
329 MISCREG_MVBAR,
330 MISCREG_RMR,
331 MISCREG_ISR,
332 MISCREG_HVBAR,
333 MISCREG_FCSEIDR,
334 MISCREG_CONTEXTIDR,
335 MISCREG_CONTEXTIDR_NS,
336 MISCREG_CONTEXTIDR_S,
337 MISCREG_TPIDRURW,
338 MISCREG_TPIDRURW_NS,
339 MISCREG_TPIDRURW_S,
340 MISCREG_TPIDRURO,
341 MISCREG_TPIDRURO_NS,
342 MISCREG_TPIDRURO_S,
343 MISCREG_TPIDRPRW,
344 MISCREG_TPIDRPRW_NS,
345 MISCREG_TPIDRPRW_S,
346 MISCREG_HTPIDR,
347 MISCREG_CNTFRQ,
348 MISCREG_CNTKCTL,
349 MISCREG_CNTP_TVAL,
350 MISCREG_CNTP_TVAL_NS,
351 MISCREG_CNTP_TVAL_S,
352 MISCREG_CNTP_CTL,
353 MISCREG_CNTP_CTL_NS,
354 MISCREG_CNTP_CTL_S,
355 MISCREG_CNTV_TVAL,
356 MISCREG_CNTV_CTL,
357 MISCREG_CNTHCTL,
358 MISCREG_CNTHP_TVAL,
359 MISCREG_CNTHP_CTL,
360 MISCREG_IL1DATA0,
361 MISCREG_IL1DATA1,
362 MISCREG_IL1DATA2,
363 MISCREG_IL1DATA3,
364 MISCREG_DL1DATA0,
365 MISCREG_DL1DATA1,
366 MISCREG_DL1DATA2,
367 MISCREG_DL1DATA3,
368 MISCREG_DL1DATA4,
369 MISCREG_RAMINDEX,
370 MISCREG_L2ACTLR,
371 MISCREG_CBAR,
372 MISCREG_HTTBR,
373 MISCREG_VTTBR,
374 MISCREG_CNTPCT,
375 MISCREG_CNTVCT,
376 MISCREG_CNTP_CVAL,
377 MISCREG_CNTP_CVAL_NS,
378 MISCREG_CNTP_CVAL_S,
379 MISCREG_CNTV_CVAL,
380 MISCREG_CNTVOFF,
381 MISCREG_CNTHP_CVAL,
382 MISCREG_CPUMERRSR,
383 MISCREG_L2MERRSR,

384
385 // AArch64 registers (Op0=2)

386 MISCREG_MDCCINT_EL1, // 320
387 MISCREG_OSDTRRX_EL1, // 321
388 MISCREG_MDSCR_EL1, // 322
389 MISCREG_OSDTRTX_EL1, // 323
390 MISCREG_OSECCR_EL1, // 324
391 MISCREG_DBGBVR0_EL1, // 325
392 MISCREG_DBGBVR1_EL1, // 326
393 MISCREG_DBGBVR2_EL1, // 327
394 MISCREG_DBGBVR3_EL1, // 328
395 MISCREG_DBGBVR4_EL1, // 329
396 MISCREG_DBGBVR5_EL1, // 330
397 MISCREG_DBGBCR0_EL1, // 331
398 MISCREG_DBGBCR1_EL1, // 332
399 MISCREG_DBGBCR2_EL1, // 333
400 MISCREG_DBGBCR3_EL1, // 334
401 MISCREG_DBGBCR4_EL1, // 335
402 MISCREG_DBGBCR5_EL1, // 336
403 MISCREG_DBGWVR0_EL1, // 337
404 MISCREG_DBGWVR1_EL1, // 338
405 MISCREG_DBGWVR2_EL1, // 339
406 MISCREG_DBGWVR3_EL1, // 340
407 MISCREG_DBGWCR0_EL1, // 341
408 MISCREG_DBGWCR1_EL1, // 342
409 MISCREG_DBGWCR2_EL1, // 343
410 MISCREG_DBGWCR3_EL1, // 344
411 MISCREG_MDCCSR_EL0, // 345
412 MISCREG_MDDTR_EL0, // 346
413 MISCREG_MDDTRTX_EL0, // 347
414 MISCREG_MDDTRRX_EL0, // 348
415 MISCREG_DBGVCR32_EL2, // 349
416 MISCREG_MDRAR_EL1, // 350
417 MISCREG_OSLAR_EL1, // 351
418 MISCREG_OSLSR_EL1, // 352
419 MISCREG_OSDLR_EL1, // 353
420 MISCREG_DBGPRCR_EL1, // 354
421 MISCREG_DBGCLAIMSET_EL1, // 355
422 MISCREG_DBGCLAIMCLR_EL1, // 356
423 MISCREG_DBGAUTHSTATUS_EL1, // 357
424 MISCREG_TEECR32_EL1, // 358, not in ARM DDI 0487A.b+
425 MISCREG_TEEHBR32_EL1, // 359, not in ARM DDI 0487A.b+

386 MISCREG_MDCCINT_EL1,
387 MISCREG_OSDTRRX_EL1,
388 MISCREG_MDSCR_EL1,
389 MISCREG_OSDTRTX_EL1,
390 MISCREG_OSECCR_EL1,
391 MISCREG_DBGBVR0_EL1,
392 MISCREG_DBGBVR1_EL1,
393 MISCREG_DBGBVR2_EL1,
394 MISCREG_DBGBVR3_EL1,
395 MISCREG_DBGBVR4_EL1,
396 MISCREG_DBGBVR5_EL1,
397 MISCREG_DBGBCR0_EL1,
398 MISCREG_DBGBCR1_EL1,
399 MISCREG_DBGBCR2_EL1,
400 MISCREG_DBGBCR3_EL1,
401 MISCREG_DBGBCR4_EL1,
402 MISCREG_DBGBCR5_EL1,
403 MISCREG_DBGWVR0_EL1,
404 MISCREG_DBGWVR1_EL1,
405 MISCREG_DBGWVR2_EL1,
406 MISCREG_DBGWVR3_EL1,
407 MISCREG_DBGWCR0_EL1,
408 MISCREG_DBGWCR1_EL1,
409 MISCREG_DBGWCR2_EL1,
410 MISCREG_DBGWCR3_EL1,
411 MISCREG_MDCCSR_EL0,
412 MISCREG_MDDTR_EL0,
413 MISCREG_MDDTRTX_EL0,
414 MISCREG_MDDTRRX_EL0,
415 MISCREG_DBGVCR32_EL2,
416 MISCREG_MDRAR_EL1,
417 MISCREG_OSLAR_EL1,
418 MISCREG_OSLSR_EL1,
419 MISCREG_OSDLR_EL1,
420 MISCREG_DBGPRCR_EL1,
421 MISCREG_DBGCLAIMSET_EL1,
422 MISCREG_DBGCLAIMCLR_EL1,
423 MISCREG_DBGAUTHSTATUS_EL1,
424 MISCREG_TEECR32_EL1, // not in ARM DDI 0487A.b+
425 MISCREG_TEEHBR32_EL1, // not in ARM DDI 0487A.b+

426
427 // AArch64 registers (Op0=1,3)

428 MISCREG_MIDR_EL1, // 360
429 MISCREG_MPIDR_EL1, // 361
430 MISCREG_REVIDR_EL1, // 362
431 MISCREG_ID_PFR0_EL1, // 363
432 MISCREG_ID_PFR1_EL1, // 364
433 MISCREG_ID_DFR0_EL1, // 365
434 MISCREG_ID_AFR0_EL1, // 366
435 MISCREG_ID_MMFR0_EL1, // 367
436 MISCREG_ID_MMFR1_EL1, // 368
437 MISCREG_ID_MMFR2_EL1, // 369
438 MISCREG_ID_MMFR3_EL1, // 370
439 MISCREG_ID_ISAR0_EL1, // 371
440 MISCREG_ID_ISAR1_EL1, // 372
441 MISCREG_ID_ISAR2_EL1, // 373
442 MISCREG_ID_ISAR3_EL1, // 374
443 MISCREG_ID_ISAR4_EL1, // 375
444 MISCREG_ID_ISAR5_EL1, // 376
445 MISCREG_MVFR0_EL1, // 377
446 MISCREG_MVFR1_EL1, // 378
447 MISCREG_MVFR2_EL1, // 379
448 MISCREG_ID_AA64PFR0_EL1, // 380
449 MISCREG_ID_AA64PFR1_EL1, // 381
450 MISCREG_ID_AA64DFR0_EL1, // 382
451 MISCREG_ID_AA64DFR1_EL1, // 383
452 MISCREG_ID_AA64AFR0_EL1, // 384
453 MISCREG_ID_AA64AFR1_EL1, // 385
454 MISCREG_ID_AA64ISAR0_EL1, // 386
455 MISCREG_ID_AA64ISAR1_EL1, // 387
456 MISCREG_ID_AA64MMFR0_EL1, // 388
457 MISCREG_ID_AA64MMFR1_EL1, // 389
458 MISCREG_CCSIDR_EL1, // 390
459 MISCREG_CLIDR_EL1, // 391
460 MISCREG_AIDR_EL1, // 392
461 MISCREG_CSSELR_EL1, // 393
462 MISCREG_CTR_EL0, // 394
463 MISCREG_DCZID_EL0, // 395
464 MISCREG_VPIDR_EL2, // 396
465 MISCREG_VMPIDR_EL2, // 397
466 MISCREG_SCTLR_EL1, // 398
467 MISCREG_ACTLR_EL1, // 399
468 MISCREG_CPACR_EL1, // 400
469 MISCREG_SCTLR_EL2, // 401
470 MISCREG_ACTLR_EL2, // 402
471 MISCREG_HCR_EL2, // 403
472 MISCREG_MDCR_EL2, // 404
473 MISCREG_CPTR_EL2, // 405
474 MISCREG_HSTR_EL2, // 406
475 MISCREG_HACR_EL2, // 407
476 MISCREG_SCTLR_EL3, // 408
477 MISCREG_ACTLR_EL3, // 409
478 MISCREG_SCR_EL3, // 410
479 MISCREG_SDER32_EL3, // 411
480 MISCREG_CPTR_EL3, // 412
481 MISCREG_MDCR_EL3, // 413
482 MISCREG_TTBR0_EL1, // 414
483 MISCREG_TTBR1_EL1, // 415
484 MISCREG_TCR_EL1, // 416
485 MISCREG_TTBR0_EL2, // 417
486 MISCREG_TCR_EL2, // 418
487 MISCREG_VTTBR_EL2, // 419
488 MISCREG_VTCR_EL2, // 420
489 MISCREG_TTBR0_EL3, // 421
490 MISCREG_TCR_EL3, // 422
491 MISCREG_DACR32_EL2, // 423
492 MISCREG_SPSR_EL1, // 424
493 MISCREG_ELR_EL1, // 425
494 MISCREG_SP_EL0, // 426
495 MISCREG_SPSEL, // 427
496 MISCREG_CURRENTEL, // 428
497 MISCREG_NZCV, // 429
498 MISCREG_DAIF, // 430
499 MISCREG_FPCR, // 431
500 MISCREG_FPSR, // 432
501 MISCREG_DSPSR_EL0, // 433
502 MISCREG_DLR_EL0, // 434
503 MISCREG_SPSR_EL2, // 435
504 MISCREG_ELR_EL2, // 436
505 MISCREG_SP_EL1, // 437
506 MISCREG_SPSR_IRQ_AA64, // 438
507 MISCREG_SPSR_ABT_AA64, // 439
508 MISCREG_SPSR_UND_AA64, // 440
509 MISCREG_SPSR_FIQ_AA64, // 441
510 MISCREG_SPSR_EL3, // 442
511 MISCREG_ELR_EL3, // 443
512 MISCREG_SP_EL2, // 444
513 MISCREG_AFSR0_EL1, // 445
514 MISCREG_AFSR1_EL1, // 446
515 MISCREG_ESR_EL1, // 447
516 MISCREG_IFSR32_EL2, // 448
517 MISCREG_AFSR0_EL2, // 449
518 MISCREG_AFSR1_EL2, // 450
519 MISCREG_ESR_EL2, // 451
520 MISCREG_FPEXC32_EL2, // 452
521 MISCREG_AFSR0_EL3, // 453
522 MISCREG_AFSR1_EL3, // 454
523 MISCREG_ESR_EL3, // 455
524 MISCREG_FAR_EL1, // 456
525 MISCREG_FAR_EL2, // 457
526 MISCREG_HPFAR_EL2, // 458
527 MISCREG_FAR_EL3, // 459
528 MISCREG_IC_IALLUIS, // 460
529 MISCREG_PAR_EL1, // 461
530 MISCREG_IC_IALLU, // 462
531 MISCREG_DC_IVAC_Xt, // 463
532 MISCREG_DC_ISW_Xt, // 464
533 MISCREG_AT_S1E1R_Xt, // 465
534 MISCREG_AT_S1E1W_Xt, // 466
535 MISCREG_AT_S1E0R_Xt, // 467
536 MISCREG_AT_S1E0W_Xt, // 468
537 MISCREG_DC_CSW_Xt, // 469
538 MISCREG_DC_CISW_Xt, // 470
539 MISCREG_DC_ZVA_Xt, // 471
540 MISCREG_IC_IVAU_Xt, // 472
541 MISCREG_DC_CVAC_Xt, // 473
542 MISCREG_DC_CVAU_Xt, // 474
543 MISCREG_DC_CIVAC_Xt, // 475
544 MISCREG_AT_S1E2R_Xt, // 476
545 MISCREG_AT_S1E2W_Xt, // 477
546 MISCREG_AT_S12E1R_Xt, // 478
547 MISCREG_AT_S12E1W_Xt, // 479
548 MISCREG_AT_S12E0R_Xt, // 480
549 MISCREG_AT_S12E0W_Xt, // 481
550 MISCREG_AT_S1E3R_Xt, // 482
551 MISCREG_AT_S1E3W_Xt, // 483
552 MISCREG_TLBI_VMALLE1IS, // 484
553 MISCREG_TLBI_VAE1IS_Xt, // 485
554 MISCREG_TLBI_ASIDE1IS_Xt, // 486
555 MISCREG_TLBI_VAAE1IS_Xt, // 487
556 MISCREG_TLBI_VALE1IS_Xt, // 488
557 MISCREG_TLBI_VAALE1IS_Xt, // 489
558 MISCREG_TLBI_VMALLE1, // 490
559 MISCREG_TLBI_VAE1_Xt, // 491
560 MISCREG_TLBI_ASIDE1_Xt, // 492
561 MISCREG_TLBI_VAAE1_Xt, // 493
562 MISCREG_TLBI_VALE1_Xt, // 494
563 MISCREG_TLBI_VAALE1_Xt, // 495
564 MISCREG_TLBI_IPAS2E1IS_Xt, // 496
565 MISCREG_TLBI_IPAS2LE1IS_Xt, // 497
566 MISCREG_TLBI_ALLE2IS, // 498
567 MISCREG_TLBI_VAE2IS_Xt, // 499
568 MISCREG_TLBI_ALLE1IS, // 500
569 MISCREG_TLBI_VALE2IS_Xt, // 501
570 MISCREG_TLBI_VMALLS12E1IS, // 502
571 MISCREG_TLBI_IPAS2E1_Xt, // 503
572 MISCREG_TLBI_IPAS2LE1_Xt, // 504
573 MISCREG_TLBI_ALLE2, // 505
574 MISCREG_TLBI_VAE2_Xt, // 506
575 MISCREG_TLBI_ALLE1, // 507
576 MISCREG_TLBI_VALE2_Xt, // 508
577 MISCREG_TLBI_VMALLS12E1, // 509
578 MISCREG_TLBI_ALLE3IS, // 510
579 MISCREG_TLBI_VAE3IS_Xt, // 511
580 MISCREG_TLBI_VALE3IS_Xt, // 512
581 MISCREG_TLBI_ALLE3, // 513
582 MISCREG_TLBI_VAE3_Xt, // 514
583 MISCREG_TLBI_VALE3_Xt, // 515
584 MISCREG_PMINTENSET_EL1, // 516
585 MISCREG_PMINTENCLR_EL1, // 517
586 MISCREG_PMCR_EL0, // 518
587 MISCREG_PMCNTENSET_EL0, // 519
588 MISCREG_PMCNTENCLR_EL0, // 520
589 MISCREG_PMOVSCLR_EL0, // 521
590 MISCREG_PMSWINC_EL0, // 522
591 MISCREG_PMSELR_EL0, // 523
592 MISCREG_PMCEID0_EL0, // 524
593 MISCREG_PMCEID1_EL0, // 525
594 MISCREG_PMCCNTR_EL0, // 526
595 MISCREG_PMXEVTYPER_EL0, // 527
596 MISCREG_PMCCFILTR_EL0, // 528
597 MISCREG_PMXEVCNTR_EL0, // 529
598 MISCREG_PMUSERENR_EL0, // 530
599 MISCREG_PMOVSSET_EL0, // 531
600 MISCREG_MAIR_EL1, // 532
601 MISCREG_AMAIR_EL1, // 533
602 MISCREG_MAIR_EL2, // 534
603 MISCREG_AMAIR_EL2, // 535
604 MISCREG_MAIR_EL3, // 536
605 MISCREG_AMAIR_EL3, // 537
606 MISCREG_L2CTLR_EL1, // 538
607 MISCREG_L2ECTLR_EL1, // 539
608 MISCREG_VBAR_EL1, // 540
609 MISCREG_RVBAR_EL1, // 541
610 MISCREG_ISR_EL1, // 542
611 MISCREG_VBAR_EL2, // 543
612 MISCREG_RVBAR_EL2, // 544
613 MISCREG_VBAR_EL3, // 545
614 MISCREG_RVBAR_EL3, // 546
615 MISCREG_RMR_EL3, // 547
616 MISCREG_CONTEXTIDR_EL1, // 548
617 MISCREG_TPIDR_EL1, // 549
618 MISCREG_TPIDR_EL0, // 550
619 MISCREG_TPIDRRO_EL0, // 551
620 MISCREG_TPIDR_EL2, // 552
621 MISCREG_TPIDR_EL3, // 553
622 MISCREG_CNTKCTL_EL1, // 554
623 MISCREG_CNTFRQ_EL0, // 555
624 MISCREG_CNTPCT_EL0, // 556
625 MISCREG_CNTVCT_EL0, // 557
626 MISCREG_CNTP_TVAL_EL0, // 558
627 MISCREG_CNTP_CTL_EL0, // 559
628 MISCREG_CNTP_CVAL_EL0, // 560
629 MISCREG_CNTV_TVAL_EL0, // 561
630 MISCREG_CNTV_CTL_EL0, // 562
631 MISCREG_CNTV_CVAL_EL0, // 563
632 MISCREG_PMEVCNTR0_EL0, // 564
633 MISCREG_PMEVCNTR1_EL0, // 565
634 MISCREG_PMEVCNTR2_EL0, // 566
635 MISCREG_PMEVCNTR3_EL0, // 567
636 MISCREG_PMEVCNTR4_EL0, // 568
637 MISCREG_PMEVCNTR5_EL0, // 569
638 MISCREG_PMEVTYPER0_EL0, // 570
639 MISCREG_PMEVTYPER1_EL0, // 571
640 MISCREG_PMEVTYPER2_EL0, // 572
641 MISCREG_PMEVTYPER3_EL0, // 573
642 MISCREG_PMEVTYPER4_EL0, // 574
643 MISCREG_PMEVTYPER5_EL0, // 575
644 MISCREG_CNTVOFF_EL2, // 576
645 MISCREG_CNTHCTL_EL2, // 577
646 MISCREG_CNTHP_TVAL_EL2, // 578
647 MISCREG_CNTHP_CTL_EL2, // 579
648 MISCREG_CNTHP_CVAL_EL2, // 580
649 MISCREG_CNTPS_TVAL_EL1, // 581
650 MISCREG_CNTPS_CTL_EL1, // 582
651 MISCREG_CNTPS_CVAL_EL1, // 583
652 MISCREG_IL1DATA0_EL1, // 584
653 MISCREG_IL1DATA1_EL1, // 585
654 MISCREG_IL1DATA2_EL1, // 586
655 MISCREG_IL1DATA3_EL1, // 587
656 MISCREG_DL1DATA0_EL1, // 588
657 MISCREG_DL1DATA1_EL1, // 589
658 MISCREG_DL1DATA2_EL1, // 590
659 MISCREG_DL1DATA3_EL1, // 591
660 MISCREG_DL1DATA4_EL1, // 592
661 MISCREG_L2ACTLR_EL1, // 593
662 MISCREG_CPUACTLR_EL1, // 594
663 MISCREG_CPUECTLR_EL1, // 595
664 MISCREG_CPUMERRSR_EL1, // 596
665 MISCREG_L2MERRSR_EL1, // 597
666 MISCREG_CBAR_EL1, // 598
667 MISCREG_CONTEXTIDR_EL2, // 599

428 MISCREG_MIDR_EL1,
429 MISCREG_MPIDR_EL1,
430 MISCREG_REVIDR_EL1,
431 MISCREG_ID_PFR0_EL1,
432 MISCREG_ID_PFR1_EL1,
433 MISCREG_ID_DFR0_EL1,
434 MISCREG_ID_AFR0_EL1,
435 MISCREG_ID_MMFR0_EL1,
436 MISCREG_ID_MMFR1_EL1,
437 MISCREG_ID_MMFR2_EL1,
438 MISCREG_ID_MMFR3_EL1,
439 MISCREG_ID_ISAR0_EL1,
440 MISCREG_ID_ISAR1_EL1,
441 MISCREG_ID_ISAR2_EL1,
442 MISCREG_ID_ISAR3_EL1,
443 MISCREG_ID_ISAR4_EL1,
444 MISCREG_ID_ISAR5_EL1,
445 MISCREG_MVFR0_EL1,
446 MISCREG_MVFR1_EL1,
447 MISCREG_MVFR2_EL1,
448 MISCREG_ID_AA64PFR0_EL1,
449 MISCREG_ID_AA64PFR1_EL1,
450 MISCREG_ID_AA64DFR0_EL1,
451 MISCREG_ID_AA64DFR1_EL1,
452 MISCREG_ID_AA64AFR0_EL1,
453 MISCREG_ID_AA64AFR1_EL1,
454 MISCREG_ID_AA64ISAR0_EL1,
455 MISCREG_ID_AA64ISAR1_EL1,
456 MISCREG_ID_AA64MMFR0_EL1,
457 MISCREG_ID_AA64MMFR1_EL1,
458 MISCREG_CCSIDR_EL1,
459 MISCREG_CLIDR_EL1,
460 MISCREG_AIDR_EL1,
461 MISCREG_CSSELR_EL1,
462 MISCREG_CTR_EL0,
463 MISCREG_DCZID_EL0,
464 MISCREG_VPIDR_EL2,
465 MISCREG_VMPIDR_EL2,
466 MISCREG_SCTLR_EL1,
467 MISCREG_ACTLR_EL1,
468 MISCREG_CPACR_EL1,
469 MISCREG_SCTLR_EL2,
470 MISCREG_ACTLR_EL2,
471 MISCREG_HCR_EL2,
472 MISCREG_MDCR_EL2,
473 MISCREG_CPTR_EL2,
474 MISCREG_HSTR_EL2,
475 MISCREG_HACR_EL2,
476 MISCREG_SCTLR_EL3,
477 MISCREG_ACTLR_EL3,
478 MISCREG_SCR_EL3,
479 MISCREG_SDER32_EL3,
480 MISCREG_CPTR_EL3,
481 MISCREG_MDCR_EL3,
482 MISCREG_TTBR0_EL1,
483 MISCREG_TTBR1_EL1,
484 MISCREG_TCR_EL1,
485 MISCREG_TTBR0_EL2,
486 MISCREG_TCR_EL2,
487 MISCREG_VTTBR_EL2,
488 MISCREG_VTCR_EL2,
489 MISCREG_TTBR0_EL3,
490 MISCREG_TCR_EL3,
491 MISCREG_DACR32_EL2,
492 MISCREG_SPSR_EL1,
493 MISCREG_ELR_EL1,
494 MISCREG_SP_EL0,
495 MISCREG_SPSEL,
496 MISCREG_CURRENTEL,
497 MISCREG_NZCV,
498 MISCREG_DAIF,
499 MISCREG_FPCR,
500 MISCREG_FPSR,
501 MISCREG_DSPSR_EL0,
502 MISCREG_DLR_EL0,
503 MISCREG_SPSR_EL2,
504 MISCREG_ELR_EL2,
505 MISCREG_SP_EL1,
506 MISCREG_SPSR_IRQ_AA64,
507 MISCREG_SPSR_ABT_AA64,
508 MISCREG_SPSR_UND_AA64,
509 MISCREG_SPSR_FIQ_AA64,
510 MISCREG_SPSR_EL3,
511 MISCREG_ELR_EL3,
512 MISCREG_SP_EL2,
513 MISCREG_AFSR0_EL1,
514 MISCREG_AFSR1_EL1,
515 MISCREG_ESR_EL1,
516 MISCREG_IFSR32_EL2,
517 MISCREG_AFSR0_EL2,
518 MISCREG_AFSR1_EL2,
519 MISCREG_ESR_EL2,
520 MISCREG_FPEXC32_EL2,
521 MISCREG_AFSR0_EL3,
522 MISCREG_AFSR1_EL3,
523 MISCREG_ESR_EL3,
524 MISCREG_FAR_EL1,
525 MISCREG_FAR_EL2,
526 MISCREG_HPFAR_EL2,
527 MISCREG_FAR_EL3,
528 MISCREG_IC_IALLUIS,
529 MISCREG_PAR_EL1,
530 MISCREG_IC_IALLU,
531 MISCREG_DC_IVAC_Xt,
532 MISCREG_DC_ISW_Xt,
533 MISCREG_AT_S1E1R_Xt,
534 MISCREG_AT_S1E1W_Xt,
535 MISCREG_AT_S1E0R_Xt,
536 MISCREG_AT_S1E0W_Xt,
537 MISCREG_DC_CSW_Xt,
538 MISCREG_DC_CISW_Xt,
539 MISCREG_DC_ZVA_Xt,
540 MISCREG_IC_IVAU_Xt,
541 MISCREG_DC_CVAC_Xt,
542 MISCREG_DC_CVAU_Xt,
543 MISCREG_DC_CIVAC_Xt,
544 MISCREG_AT_S1E2R_Xt,
545 MISCREG_AT_S1E2W_Xt,
546 MISCREG_AT_S12E1R_Xt,
547 MISCREG_AT_S12E1W_Xt,
548 MISCREG_AT_S12E0R_Xt,
549 MISCREG_AT_S12E0W_Xt,
550 MISCREG_AT_S1E3R_Xt,
551 MISCREG_AT_S1E3W_Xt,
552 MISCREG_TLBI_VMALLE1IS,
553 MISCREG_TLBI_VAE1IS_Xt,
554 MISCREG_TLBI_ASIDE1IS_Xt,
555 MISCREG_TLBI_VAAE1IS_Xt,
556 MISCREG_TLBI_VALE1IS_Xt,
557 MISCREG_TLBI_VAALE1IS_Xt,
558 MISCREG_TLBI_VMALLE1,
559 MISCREG_TLBI_VAE1_Xt,
560 MISCREG_TLBI_ASIDE1_Xt,
561 MISCREG_TLBI_VAAE1_Xt,
562 MISCREG_TLBI_VALE1_Xt,
563 MISCREG_TLBI_VAALE1_Xt,
564 MISCREG_TLBI_IPAS2E1IS_Xt,
565 MISCREG_TLBI_IPAS2LE1IS_Xt,
566 MISCREG_TLBI_ALLE2IS,
567 MISCREG_TLBI_VAE2IS_Xt,
568 MISCREG_TLBI_ALLE1IS,
569 MISCREG_TLBI_VALE2IS_Xt,
570 MISCREG_TLBI_VMALLS12E1IS,
571 MISCREG_TLBI_IPAS2E1_Xt,
572 MISCREG_TLBI_IPAS2LE1_Xt,
573 MISCREG_TLBI_ALLE2,
574 MISCREG_TLBI_VAE2_Xt,
575 MISCREG_TLBI_ALLE1,
576 MISCREG_TLBI_VALE2_Xt,
577 MISCREG_TLBI_VMALLS12E1,
578 MISCREG_TLBI_ALLE3IS,
579 MISCREG_TLBI_VAE3IS_Xt,
580 MISCREG_TLBI_VALE3IS_Xt,
581 MISCREG_TLBI_ALLE3,
582 MISCREG_TLBI_VAE3_Xt,
583 MISCREG_TLBI_VALE3_Xt,
584 MISCREG_PMINTENSET_EL1,
585 MISCREG_PMINTENCLR_EL1,
586 MISCREG_PMCR_EL0,
587 MISCREG_PMCNTENSET_EL0,
588 MISCREG_PMCNTENCLR_EL0,
589 MISCREG_PMOVSCLR_EL0,
590 MISCREG_PMSWINC_EL0,
591 MISCREG_PMSELR_EL0,
592 MISCREG_PMCEID0_EL0,
593 MISCREG_PMCEID1_EL0,
594 MISCREG_PMCCNTR_EL0,
595 MISCREG_PMXEVTYPER_EL0,
596 MISCREG_PMCCFILTR_EL0,
597 MISCREG_PMXEVCNTR_EL0,
598 MISCREG_PMUSERENR_EL0,
599 MISCREG_PMOVSSET_EL0,
600 MISCREG_MAIR_EL1,
601 MISCREG_AMAIR_EL1,
602 MISCREG_MAIR_EL2,
603 MISCREG_AMAIR_EL2,
604 MISCREG_MAIR_EL3,
605 MISCREG_AMAIR_EL3,
606 MISCREG_L2CTLR_EL1,
607 MISCREG_L2ECTLR_EL1,
608 MISCREG_VBAR_EL1,
609 MISCREG_RVBAR_EL1,
610 MISCREG_ISR_EL1,
611 MISCREG_VBAR_EL2,
612 MISCREG_RVBAR_EL2,
613 MISCREG_VBAR_EL3,
614 MISCREG_RVBAR_EL3,
615 MISCREG_RMR_EL3,
616 MISCREG_CONTEXTIDR_EL1,
617 MISCREG_TPIDR_EL1,
618 MISCREG_TPIDR_EL0,
619 MISCREG_TPIDRRO_EL0,
620 MISCREG_TPIDR_EL2,
621 MISCREG_TPIDR_EL3,
622 MISCREG_CNTKCTL_EL1,
623 MISCREG_CNTFRQ_EL0,
624 MISCREG_CNTPCT_EL0,
625 MISCREG_CNTVCT_EL0,
626 MISCREG_CNTP_TVAL_EL0,
627 MISCREG_CNTP_CTL_EL0,
628 MISCREG_CNTP_CVAL_EL0,
629 MISCREG_CNTV_TVAL_EL0,
630 MISCREG_CNTV_CTL_EL0,
631 MISCREG_CNTV_CVAL_EL0,
632 MISCREG_PMEVCNTR0_EL0,
633 MISCREG_PMEVCNTR1_EL0,
634 MISCREG_PMEVCNTR2_EL0,
635 MISCREG_PMEVCNTR3_EL0,
636 MISCREG_PMEVCNTR4_EL0,
637 MISCREG_PMEVCNTR5_EL0,
638 MISCREG_PMEVTYPER0_EL0,
639 MISCREG_PMEVTYPER1_EL0,
640 MISCREG_PMEVTYPER2_EL0,
641 MISCREG_PMEVTYPER3_EL0,
642 MISCREG_PMEVTYPER4_EL0,
643 MISCREG_PMEVTYPER5_EL0,
644 MISCREG_CNTVOFF_EL2,
645 MISCREG_CNTHCTL_EL2,
646 MISCREG_CNTHP_TVAL_EL2,
647 MISCREG_CNTHP_CTL_EL2,
648 MISCREG_CNTHP_CVAL_EL2,
649 MISCREG_CNTPS_TVAL_EL1,
650 MISCREG_CNTPS_CTL_EL1,
651 MISCREG_CNTPS_CVAL_EL1,
652 MISCREG_IL1DATA0_EL1,
653 MISCREG_IL1DATA1_EL1,
654 MISCREG_IL1DATA2_EL1,
655 MISCREG_IL1DATA3_EL1,
656 MISCREG_DL1DATA0_EL1,
657 MISCREG_DL1DATA1_EL1,
658 MISCREG_DL1DATA2_EL1,
659 MISCREG_DL1DATA3_EL1,
660 MISCREG_DL1DATA4_EL1,
661 MISCREG_L2ACTLR_EL1,
662 MISCREG_CPUACTLR_EL1,
663 MISCREG_CPUECTLR_EL1,
664 MISCREG_CPUMERRSR_EL1,
665 MISCREG_L2MERRSR_EL1,
666 MISCREG_CBAR_EL1,
667 MISCREG_CONTEXTIDR_EL2,

668
669 // Introduced in ARMv8.1

670 MISCREG_TTBR1_EL2, // 600
671 MISCREG_CNTHV_CTL_EL2, // 601
672 MISCREG_CNTHV_CVAL_EL2, // 602
673 MISCREG_CNTHV_TVAL_EL2, // 603

670 MISCREG_TTBR1_EL2,
671 MISCREG_CNTHV_CTL_EL2,
672 MISCREG_CNTHV_CVAL_EL2,
673 MISCREG_CNTHV_TVAL_EL2,

674

675 MISCREG_ID_AA64MMFR2_EL1, // 604

675 MISCREG_ID_AA64MMFR2_EL1,

676 // These MISCREG_FREESLOT are available Misc Register
677 // slots for future registers to be implemented.

678 MISCREG_FREESLOT_1, // 605

678 MISCREG_FREESLOT_1,

679
680 // NUM_PHYS_MISCREGS specifies the number of actual physical
681 // registers, not considering the following pseudo-registers
682 // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
683 // Checkpointing should use this physical index when
684 // saving/restoring register values.

685 NUM_PHYS_MISCREGS = 606, // 606

685 NUM_PHYS_MISCREGS,