miscregs.hh (13019:3fa5ab820fa8) miscregs.hh (13115:e056f29e1994)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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41 * Giacomo Gabrielli
42 */
43#ifndef __ARCH_ARM_MISCREGS_HH__
44#define __ARCH_ARM_MISCREGS_HH__
45
46#include <bitset>
47#include <tuple>
48
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 32 unchanged lines hidden (view full) ---

41 * Giacomo Gabrielli
42 */
43#ifndef __ARCH_ARM_MISCREGS_HH__
44#define __ARCH_ARM_MISCREGS_HH__
45
46#include <bitset>
47#include <tuple>
48
49#include "base/bitunion.hh"
49#include "arch/arm/miscregs_types.hh"
50#include "base/compiler.hh"
51
52class ThreadContext;
53
54
55namespace ArmISA
56{
57 enum MiscRegIndex {

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1411 "disr_el1",
1412 "vsesr_el2",
1413 "vdisr_el2",
1414 };
1415
1416 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1417 "The miscRegName array and NUM_MISCREGS are inconsistent.");
1418
50#include "base/compiler.hh"
51
52class ThreadContext;
53
54
55namespace ArmISA
56{
57 enum MiscRegIndex {

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1411 "disr_el1",
1412 "vsesr_el2",
1413 "vdisr_el2",
1414 };
1415
1416 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1417 "The miscRegName array and NUM_MISCREGS are inconsistent.");
1418
1419 BitUnion32(CPSR)
1420 Bitfield<31, 30> nz;
1421 Bitfield<29> c;
1422 Bitfield<28> v;
1423 Bitfield<27> q;
1424 Bitfield<26, 25> it1;
1425 Bitfield<24> j;
1426 Bitfield<23, 22> res0_23_22;
1427 Bitfield<21> ss; // AArch64
1428 Bitfield<20> il; // AArch64
1429 Bitfield<19, 16> ge;
1430 Bitfield<15, 10> it2;
1431 Bitfield<9> d; // AArch64
1432 Bitfield<9> e;
1433 Bitfield<8> a;
1434 Bitfield<7> i;
1435 Bitfield<6> f;
1436 Bitfield<8, 6> aif;
1437 Bitfield<9, 6> daif; // AArch64
1438 Bitfield<5> t;
1439 Bitfield<4> width; // AArch64
1440 Bitfield<3, 2> el; // AArch64
1441 Bitfield<4, 0> mode;
1442 Bitfield<0> sp; // AArch64
1443 EndBitUnion(CPSR)
1444
1445 // This mask selects bits of the CPSR that actually go in the CondCodes
1446 // integer register to allow renaming.
1447 static const uint32_t CondCodesMask = 0xF00F0000;
1448 static const uint32_t CpsrMaskQ = 0x08000000;
1449
1450 // APSR (Application Program Status Register Mask). It is the user level
1451 // alias for the CPSR. The APSR is a subset of the CPSR. Although
1452 // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
1453 // APSR:
1454 // Bit[9] returns the value of CPSR.E.
1455 // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
1456 static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0;
1457
1458 // CPSR (Current Program Status Register Mask).
1459 static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
1460
1419 // This mask selects bits of the CPSR that actually go in the CondCodes
1420 // integer register to allow renaming.
1421 static const uint32_t CondCodesMask = 0xF00F0000;
1422 static const uint32_t CpsrMaskQ = 0x08000000;
1423
1424 // APSR (Application Program Status Register Mask). It is the user level
1425 // alias for the CPSR. The APSR is a subset of the CPSR. Although
1426 // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
1427 // APSR:
1428 // Bit[9] returns the value of CPSR.E.
1429 // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
1430 static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0;
1431
1432 // CPSR (Current Program Status Register Mask).
1433 static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
1434
1461 BitUnion32(HDCR)
1462 Bitfield<11> tdra;
1463 Bitfield<10> tdosa;
1464 Bitfield<9> tda;
1465 Bitfield<8> tde;
1466 Bitfield<7> hpme;
1467 Bitfield<6> tpm;
1468 Bitfield<5> tpmcr;
1469 Bitfield<4, 0> hpmn;
1470 EndBitUnion(HDCR)
1471
1472 BitUnion32(HCPTR)
1473 Bitfield<31> tcpac;
1474 Bitfield<20> tta;
1475 Bitfield<15> tase;
1476 Bitfield<13> tcp13;
1477 Bitfield<12> tcp12;
1478 Bitfield<11> tcp11;
1479 Bitfield<10> tcp10;
1480 Bitfield<10> tfp; // AArch64
1481 Bitfield<9> tcp9;
1482 Bitfield<8> tcp8;
1483 Bitfield<7> tcp7;
1484 Bitfield<6> tcp6;
1485 Bitfield<5> tcp5;
1486 Bitfield<4> tcp4;
1487 Bitfield<3> tcp3;
1488 Bitfield<2> tcp2;
1489 Bitfield<1> tcp1;
1490 Bitfield<0> tcp0;
1491 EndBitUnion(HCPTR)
1492
1493 BitUnion32(HSTR)
1494 Bitfield<17> tjdbx;
1495 Bitfield<16> ttee;
1496 Bitfield<15> t15;
1497 Bitfield<13> t13;
1498 Bitfield<12> t12;
1499 Bitfield<11> t11;
1500 Bitfield<10> t10;
1501 Bitfield<9> t9;
1502 Bitfield<8> t8;
1503 Bitfield<7> t7;
1504 Bitfield<6> t6;
1505 Bitfield<5> t5;
1506 Bitfield<4> t4;
1507 Bitfield<3> t3;
1508 Bitfield<2> t2;
1509 Bitfield<1> t1;
1510 Bitfield<0> t0;
1511 EndBitUnion(HSTR)
1512
1513 BitUnion64(HCR)
1514 Bitfield<34> e2h; // AArch64
1515 Bitfield<33> id; // AArch64
1516 Bitfield<32> cd; // AArch64
1517 Bitfield<31> rw; // AArch64
1518 Bitfield<30> trvm; // AArch64
1519 Bitfield<29> hcd; // AArch64
1520 Bitfield<28> tdz; // AArch64
1521
1522 Bitfield<27> tge;
1523 Bitfield<26> tvm;
1524 Bitfield<25> ttlb;
1525 Bitfield<24> tpu;
1526 Bitfield<23> tpc;
1527 Bitfield<22> tsw;
1528 Bitfield<21> tac;
1529 Bitfield<21> tacr; // AArch64
1530 Bitfield<20> tidcp;
1531 Bitfield<19> tsc;
1532 Bitfield<18> tid3;
1533 Bitfield<17> tid2;
1534 Bitfield<16> tid1;
1535 Bitfield<15> tid0;
1536 Bitfield<14> twe;
1537 Bitfield<13> twi;
1538 Bitfield<12> dc;
1539 Bitfield<11, 10> bsu;
1540 Bitfield<9> fb;
1541 Bitfield<8> va;
1542 Bitfield<8> vse; // AArch64
1543 Bitfield<7> vi;
1544 Bitfield<6> vf;
1545 Bitfield<5> amo;
1546 Bitfield<4> imo;
1547 Bitfield<3> fmo;
1548 Bitfield<2> ptw;
1549 Bitfield<1> swio;
1550 Bitfield<0> vm;
1551 EndBitUnion(HCR)
1552
1553 BitUnion32(NSACR)
1554 Bitfield<20> nstrcdis;
1555 Bitfield<19> rfr;
1556 Bitfield<15> nsasedis;
1557 Bitfield<14> nsd32dis;
1558 Bitfield<13> cp13;
1559 Bitfield<12> cp12;
1560 Bitfield<11> cp11;
1561 Bitfield<10> cp10;
1562 Bitfield<9> cp9;
1563 Bitfield<8> cp8;
1564 Bitfield<7> cp7;
1565 Bitfield<6> cp6;
1566 Bitfield<5> cp5;
1567 Bitfield<4> cp4;
1568 Bitfield<3> cp3;
1569 Bitfield<2> cp2;
1570 Bitfield<1> cp1;
1571 Bitfield<0> cp0;
1572 EndBitUnion(NSACR)
1573
1574 BitUnion32(SCR)
1575 Bitfield<13> twe;
1576 Bitfield<12> twi;
1577 Bitfield<11> st; // AArch64
1578 Bitfield<10> rw; // AArch64
1579 Bitfield<9> sif;
1580 Bitfield<8> hce;
1581 Bitfield<7> scd;
1582 Bitfield<7> smd; // AArch64
1583 Bitfield<6> nEt;
1584 Bitfield<5> aw;
1585 Bitfield<4> fw;
1586 Bitfield<3> ea;
1587 Bitfield<2> fiq;
1588 Bitfield<1> irq;
1589 Bitfield<0> ns;
1590 EndBitUnion(SCR)
1591
1592 BitUnion32(SCTLR)
1593 Bitfield<30> te; // Thumb Exception Enable (AArch32 only)
1594 Bitfield<29> afe; // Access flag enable (AArch32 only)
1595 Bitfield<28> tre; // TEX remap enable (AArch32 only)
1596 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only)
1597 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC,
1598 // DC CVAC and IC IVAU instructions
1599 // (AArch64 SCTLR_EL1 only)
1600 Bitfield<25> ee; // Exception Endianness
1601 Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only)
1602 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
1603 // (AArch64 SCTLR_EL1 only)
1604 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)
1605 Bitfield<22> u; // Alignment (dropped in ARMv7)
1606 Bitfield<21> fi; // Fast interrupts configuration enable
1607 // (ARMv7 only)
1608 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN
1609 // (AArch32 only)
1610 Bitfield<19> dz; // Divide by Zero fault enable
1611 // (dropped in ARMv7)
1612 Bitfield<19> wxn; // Write permission implies XN
1613 Bitfield<18> ntwe; // Not trap WFE
1614 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1615 Bitfield<18> rao2; // Read as one
1616 Bitfield<16> ntwi; // Not trap WFI
1617 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1618 Bitfield<16> rao3; // Read as one
1619 Bitfield<15> uct; // Enable EL0 access to CTR_EL0
1620 // (AArch64 SCTLR_EL1 only)
1621 Bitfield<14> rr; // Round Robin select (ARMv7 only)
1622 Bitfield<14> dze; // Enable EL0 access to DC ZVA
1623 // (AArch64 SCTLR_EL1 only)
1624 Bitfield<13> v; // Vectors bit (AArch32 only)
1625 Bitfield<12> i; // Instruction cache enable
1626 Bitfield<11> z; // Branch prediction enable (ARMv7 only)
1627 Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only)
1628 Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7)
1629 Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only)
1630 Bitfield<8> sed; // SETEND disable
1631 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1632 Bitfield<7> b; // Endianness support (dropped in ARMv7)
1633 Bitfield<7> itd; // IT disable
1634 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1635 Bitfield<6, 3> rao4; // Read as one
1636 Bitfield<6> thee; // ThumbEE enable
1637 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1638 Bitfield<5> cp15ben; // CP15 barrier enable
1639 // (AArch32 and AArch64 SCTLR_EL1 only)
1640 Bitfield<4> sa0; // Stack Alignment Check Enable for EL0
1641 // (AArch64 SCTLR_EL1 only)
1642 Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only)
1643 Bitfield<2> c; // Cache enable
1644 Bitfield<1> a; // Alignment check enable
1645 Bitfield<0> m; // MMU enable
1646 EndBitUnion(SCTLR)
1647
1648 BitUnion32(CPACR)
1649 Bitfield<1, 0> cp0;
1650 Bitfield<3, 2> cp1;
1651 Bitfield<5, 4> cp2;
1652 Bitfield<7, 6> cp3;
1653 Bitfield<9, 8> cp4;
1654 Bitfield<11, 10> cp5;
1655 Bitfield<13, 12> cp6;
1656 Bitfield<15, 14> cp7;
1657 Bitfield<17, 16> cp8;
1658 Bitfield<19, 18> cp9;
1659 Bitfield<21, 20> cp10;
1660 Bitfield<21, 20> fpen; // AArch64
1661 Bitfield<23, 22> cp11;
1662 Bitfield<25, 24> cp12;
1663 Bitfield<27, 26> cp13;
1664 Bitfield<29, 28> rsvd;
1665 Bitfield<28> tta; // AArch64
1666 Bitfield<30> d32dis;
1667 Bitfield<31> asedis;
1668 EndBitUnion(CPACR)
1669
1670 BitUnion32(FSR)
1671 Bitfield<3, 0> fsLow;
1672 Bitfield<5, 0> status; // LPAE
1673 Bitfield<7, 4> domain;
1674 Bitfield<9> lpae;
1675 Bitfield<10> fsHigh;
1676 Bitfield<11> wnr;
1677 Bitfield<12> ext;
1678 Bitfield<13> cm; // LPAE
1679 EndBitUnion(FSR)
1680
1681 BitUnion32(FPSCR)
1682 Bitfield<0> ioc;
1683 Bitfield<1> dzc;
1684 Bitfield<2> ofc;
1685 Bitfield<3> ufc;
1686 Bitfield<4> ixc;
1687 Bitfield<7> idc;
1688 Bitfield<8> ioe;
1689 Bitfield<9> dze;
1690 Bitfield<10> ofe;
1691 Bitfield<11> ufe;
1692 Bitfield<12> ixe;
1693 Bitfield<15> ide;
1694 Bitfield<18, 16> len;
1695 Bitfield<21, 20> stride;
1696 Bitfield<23, 22> rMode;
1697 Bitfield<24> fz;
1698 Bitfield<25> dn;
1699 Bitfield<26> ahp;
1700 Bitfield<27> qc;
1701 Bitfield<28> v;
1702 Bitfield<29> c;
1703 Bitfield<30> z;
1704 Bitfield<31> n;
1705 EndBitUnion(FPSCR)
1706
1707 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1708 // integer register to allow renaming.
1709 static const uint32_t FpCondCodesMask = 0xF0000000;
1710 // This mask selects the cumulative FP exception flags of the FPSCR.
1711 static const uint32_t FpscrExcMask = 0x0000009F;
1712 // This mask selects the cumulative saturation flag of the FPSCR.
1713 static const uint32_t FpscrQcMask = 0x08000000;
1714
1435 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1436 // integer register to allow renaming.
1437 static const uint32_t FpCondCodesMask = 0xF0000000;
1438 // This mask selects the cumulative FP exception flags of the FPSCR.
1439 static const uint32_t FpscrExcMask = 0x0000009F;
1440 // This mask selects the cumulative saturation flag of the FPSCR.
1441 static const uint32_t FpscrQcMask = 0x08000000;
1442
1715 BitUnion32(FPEXC)
1716 Bitfield<31> ex;
1717 Bitfield<30> en;
1718 Bitfield<29, 0> subArchDefined;
1719 EndBitUnion(FPEXC)
1720
1721 BitUnion32(MVFR0)
1722 Bitfield<3, 0> advSimdRegisters;
1723 Bitfield<7, 4> singlePrecision;
1724 Bitfield<11, 8> doublePrecision;
1725 Bitfield<15, 12> vfpExceptionTrapping;
1726 Bitfield<19, 16> divide;
1727 Bitfield<23, 20> squareRoot;
1728 Bitfield<27, 24> shortVectors;
1729 Bitfield<31, 28> roundingModes;
1730 EndBitUnion(MVFR0)
1731
1732 BitUnion32(MVFR1)
1733 Bitfield<3, 0> flushToZero;
1734 Bitfield<7, 4> defaultNaN;
1735 Bitfield<11, 8> advSimdLoadStore;
1736 Bitfield<15, 12> advSimdInteger;
1737 Bitfield<19, 16> advSimdSinglePrecision;
1738 Bitfield<23, 20> advSimdHalfPrecision;
1739 Bitfield<27, 24> vfpHalfPrecision;
1740 Bitfield<31, 28> raz;
1741 EndBitUnion(MVFR1)
1742
1743 BitUnion64(TTBCR)
1744 // Short-descriptor translation table format
1745 Bitfield<2, 0> n;
1746 Bitfield<4> pd0;
1747 Bitfield<5> pd1;
1748 // Long-descriptor translation table format
1749 Bitfield<2, 0> t0sz;
1750 Bitfield<7> epd0;
1751 Bitfield<9, 8> irgn0;
1752 Bitfield<11, 10> orgn0;
1753 Bitfield<13, 12> sh0;
1754 Bitfield<14> tg0;
1755 Bitfield<18, 16> t1sz;
1756 Bitfield<22> a1;
1757 Bitfield<23> epd1;
1758 Bitfield<25, 24> irgn1;
1759 Bitfield<27, 26> orgn1;
1760 Bitfield<29, 28> sh1;
1761 Bitfield<30> tg1;
1762 Bitfield<34, 32> ips;
1763 Bitfield<36> as;
1764 Bitfield<37> tbi0;
1765 Bitfield<38> tbi1;
1766 // Common
1767 Bitfield<31> eae;
1768 // TCR_EL2/3 (AArch64)
1769 Bitfield<18, 16> ps;
1770 Bitfield<20> tbi;
1771 EndBitUnion(TTBCR)
1772
1773 // Fields of TCR_EL{1,2,3} (mostly overlapping)
1774 // TCR_EL1 is natively 64 bits, the others are 32 bits
1775 BitUnion64(TCR)
1776 Bitfield<5, 0> t0sz;
1777 Bitfield<7> epd0; // EL1
1778 Bitfield<9, 8> irgn0;
1779 Bitfield<11, 10> orgn0;
1780 Bitfield<13, 12> sh0;
1781 Bitfield<15, 14> tg0;
1782 Bitfield<18, 16> ps;
1783 Bitfield<20> tbi; // EL2/EL3
1784 Bitfield<21, 16> t1sz; // EL1
1785 Bitfield<22> a1; // EL1
1786 Bitfield<23> epd1; // EL1
1787 Bitfield<25, 24> irgn1; // EL1
1788 Bitfield<27, 26> orgn1; // EL1
1789 Bitfield<29, 28> sh1; // EL1
1790 Bitfield<31, 30> tg1; // EL1
1791 Bitfield<34, 32> ips; // EL1
1792 Bitfield<36> as; // EL1
1793 Bitfield<37> tbi0; // EL1
1794 Bitfield<38> tbi1; // EL1
1795 EndBitUnion(TCR)
1796
1797 BitUnion32(HTCR)
1798 Bitfield<2, 0> t0sz;
1799 Bitfield<9, 8> irgn0;
1800 Bitfield<11, 10> orgn0;
1801 Bitfield<13, 12> sh0;
1802 EndBitUnion(HTCR)
1803
1804 BitUnion32(VTCR_t)
1805 Bitfield<3, 0> t0sz;
1806 Bitfield<4> s;
1807 Bitfield<5, 0> t0sz64;
1808 Bitfield<7, 6> sl0;
1809 Bitfield<9, 8> irgn0;
1810 Bitfield<11, 10> orgn0;
1811 Bitfield<13, 12> sh0;
1812 Bitfield<15, 14> tg0;
1813 Bitfield<18, 16> ps; // Only defined for VTCR_EL2
1814 EndBitUnion(VTCR_t)
1815
1816 BitUnion32(PRRR)
1817 Bitfield<1,0> tr0;
1818 Bitfield<3,2> tr1;
1819 Bitfield<5,4> tr2;
1820 Bitfield<7,6> tr3;
1821 Bitfield<9,8> tr4;
1822 Bitfield<11,10> tr5;
1823 Bitfield<13,12> tr6;
1824 Bitfield<15,14> tr7;
1825 Bitfield<16> ds0;
1826 Bitfield<17> ds1;
1827 Bitfield<18> ns0;
1828 Bitfield<19> ns1;
1829 Bitfield<24> nos0;
1830 Bitfield<25> nos1;
1831 Bitfield<26> nos2;
1832 Bitfield<27> nos3;
1833 Bitfield<28> nos4;
1834 Bitfield<29> nos5;
1835 Bitfield<30> nos6;
1836 Bitfield<31> nos7;
1837 EndBitUnion(PRRR)
1838
1839 BitUnion32(NMRR)
1840 Bitfield<1,0> ir0;
1841 Bitfield<3,2> ir1;
1842 Bitfield<5,4> ir2;
1843 Bitfield<7,6> ir3;
1844 Bitfield<9,8> ir4;
1845 Bitfield<11,10> ir5;
1846 Bitfield<13,12> ir6;
1847 Bitfield<15,14> ir7;
1848 Bitfield<17,16> or0;
1849 Bitfield<19,18> or1;
1850 Bitfield<21,20> or2;
1851 Bitfield<23,22> or3;
1852 Bitfield<25,24> or4;
1853 Bitfield<27,26> or5;
1854 Bitfield<29,28> or6;
1855 Bitfield<31,30> or7;
1856 EndBitUnion(NMRR)
1857
1858 BitUnion32(CONTEXTIDR)
1859 Bitfield<7,0> asid;
1860 Bitfield<31,8> procid;
1861 EndBitUnion(CONTEXTIDR)
1862
1863 BitUnion32(L2CTLR)
1864 Bitfield<2,0> sataRAMLatency;
1865 Bitfield<4,3> reserved_4_3;
1866 Bitfield<5> dataRAMSetup;
1867 Bitfield<8,6> tagRAMLatency;
1868 Bitfield<9> tagRAMSetup;
1869 Bitfield<11,10> dataRAMSlice;
1870 Bitfield<12> tagRAMSlice;
1871 Bitfield<20,13> reserved_20_13;
1872 Bitfield<21> eccandParityEnable;
1873 Bitfield<22> reserved_22;
1874 Bitfield<23> interptCtrlPresent;
1875 Bitfield<25,24> numCPUs;
1876 Bitfield<30,26> reserved_30_26;
1877 Bitfield<31> l2rstDISABLE_monitor;
1878 EndBitUnion(L2CTLR)
1879
1880 BitUnion32(CTR)
1881 Bitfield<3,0> iCacheLineSize;
1882 Bitfield<13,4> raz_13_4;
1883 Bitfield<15,14> l1IndexPolicy;
1884 Bitfield<19,16> dCacheLineSize;
1885 Bitfield<23,20> erg;
1886 Bitfield<27,24> cwg;
1887 Bitfield<28> raz_28;
1888 Bitfield<31,29> format;
1889 EndBitUnion(CTR)
1890
1891 BitUnion32(PMSELR)
1892 Bitfield<4, 0> sel;
1893 EndBitUnion(PMSELR)
1894
1895 BitUnion64(PAR)
1896 // 64-bit format
1897 Bitfield<63, 56> attr;
1898 Bitfield<39, 12> pa;
1899 Bitfield<11> lpae;
1900 Bitfield<9> ns;
1901 Bitfield<8, 7> sh;
1902 Bitfield<0> f;
1903 EndBitUnion(PAR)
1904
1905 BitUnion32(ESR)
1906 Bitfield<31, 26> ec;
1907 Bitfield<25> il;
1908 Bitfield<15, 0> imm16;
1909 EndBitUnion(ESR)
1910
1911 BitUnion32(CPTR)
1912 Bitfield<31> tcpac;
1913 Bitfield<20> tta;
1914 Bitfield<13, 12> res1_13_12_el2;
1915 Bitfield<10> tfp;
1916 Bitfield<9, 0> res1_9_0_el2;
1917 EndBitUnion(CPTR)
1918
1919
1920 /**
1921 * Check for permission to read coprocessor registers.
1922 *
1923 * Checks whether an instruction at the current program mode has
1924 * permissions to read the coprocessor registers. This function
1925 * returns whether the check is undefined and if not whether the
1926 * read access is permitted.
1927 *

--- 55 unchanged lines hidden --- 		1443 /**
1444 * Check for permission to read coprocessor registers.
1445 *
1446 * Checks whether an instruction at the current program mode has
1447 * permissions to read the coprocessor registers. This function
1448 * returns whether the check is undefined and if not whether the
1449 * read access is permitted.
1450 *

--- 55 unchanged lines hidden ---