miscregs.hh (12801:51f4f0331c9d) miscregs.hh (12815:bf1db9797e73)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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691 MISCREG_CP15_UNIMPL,
692 MISCREG_UNKNOWN,
693
694 // Implementation defined register: this represent
695 // a pool of unimplemented registers whose access can throw
696 // either UNDEFINED or hypervisor trap exception.
697 MISCREG_IMPDEF_UNIMPL,
698
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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691 MISCREG_CP15_UNIMPL,
692 MISCREG_UNKNOWN,
693
694 // Implementation defined register: this represent
695 // a pool of unimplemented registers whose access can throw
696 // either UNDEFINED or hypervisor trap exception.
697 MISCREG_IMPDEF_UNIMPL,
698
699 // RAS extension (unimplemented)
700 MISCREG_ERRIDR_EL1,
701 MISCREG_ERRSELR_EL1,
702 MISCREG_ERXFR_EL1,
703 MISCREG_ERXCTLR_EL1,
704 MISCREG_ERXSTATUS_EL1,
705 MISCREG_ERXADDR_EL1,
706 MISCREG_ERXMISC0_EL1,
707 MISCREG_ERXMISC1_EL1,
708 MISCREG_DISR_EL1,
709 MISCREG_VSESR_EL2,
710 MISCREG_VDISR_EL2,
711
699 // Total number of Misc Registers: Physical + Dummy
700 NUM_MISCREGS
701 };
702
703 enum MiscRegInfo {
704 MISCREG_IMPLEMENTED,
705 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
706 // arch generic counter)

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1381 "num_phys_regs",
1382
1383 // Dummy registers
1384 "nop",
1385 "raz",
1386 "cp14_unimpl",
1387 "cp15_unimpl",
1388 "unknown",
712 // Total number of Misc Registers: Physical + Dummy
713 NUM_MISCREGS
714 };
715
716 enum MiscRegInfo {
717 MISCREG_IMPLEMENTED,
718 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
719 // arch generic counter)

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1394 "num_phys_regs",
1395
1396 // Dummy registers
1397 "nop",
1398 "raz",
1399 "cp14_unimpl",
1400 "cp15_unimpl",
1401 "unknown",
1389 "impl_defined"
1402 "impl_defined",
1403 "erridr_el1",
1404 "errselr_el1",
1405 "erxfr_el1",
1406 "erxctlr_el1",
1407 "erxstatus_el1",
1408 "erxaddr_el1",
1409 "erxmisc0_el1",
1410 "erxmisc1_el1",
1411 "disr_el1",
1412 "vsesr_el2",
1413 "vdisr_el2",
1390 };
1391
1392 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1393 "The miscRegName array and NUM_MISCREGS are inconsistent.");
1394
1395 BitUnion32(CPSR)
1396 Bitfield<31, 30> nz;
1397 Bitfield<29> c;

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1415
1416 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1417 "The miscRegName array and NUM_MISCREGS are inconsistent.");
1418
1419 BitUnion32(CPSR)
1420 Bitfield<31, 30> nz;
1421 Bitfield<29> c;

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