| miscregs.hh (12530:ab63172c4fbe) | miscregs.hh (12675:f3439303feb4) |
|---|---|
| 1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 652 unchanged lines hidden (view full) --- 661 MISCREG_L2ACTLR_EL1, // 593 662 MISCREG_CPUACTLR_EL1, // 594 663 MISCREG_CPUECTLR_EL1, // 595 664 MISCREG_CPUMERRSR_EL1, // 596 665 MISCREG_L2MERRSR_EL1, // 597 666 MISCREG_CBAR_EL1, // 598 667 MISCREG_CONTEXTIDR_EL2, // 599 668 | 1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 652 unchanged lines hidden (view full) --- 661 MISCREG_L2ACTLR_EL1, // 593 662 MISCREG_CPUACTLR_EL1, // 594 663 MISCREG_CPUECTLR_EL1, // 595 664 MISCREG_CPUMERRSR_EL1, // 596 665 MISCREG_L2MERRSR_EL1, // 597 666 MISCREG_CBAR_EL1, // 598 667 MISCREG_CONTEXTIDR_EL2, // 599 668 |
| 669 // Introduced in ARMv8.1 670 MISCREG_TTBR1_EL2, // 600 671 |
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| 669 // These MISCREG_FREESLOT are available Misc Register 670 // slots for future registers to be implemented. | 672 // These MISCREG_FREESLOT are available Misc Register 673 // slots for future registers to be implemented. |
| 671 MISCREG_FREESLOT_1, // 600 672 MISCREG_FREESLOT_2, // 601 673 MISCREG_FREESLOT_3, // 602 674 MISCREG_FREESLOT_4, // 603 675 MISCREG_FREESLOT_5, // 604 676 MISCREG_FREESLOT_6, // 605 | 674 MISCREG_FREESLOT_1, // 601 675 MISCREG_FREESLOT_2, // 602 676 MISCREG_FREESLOT_3, // 603 677 MISCREG_FREESLOT_4, // 604 678 MISCREG_FREESLOT_5, // 605 |
| 677 678 // NUM_PHYS_MISCREGS specifies the number of actual physical 679 // registers, not considering the following pseudo-registers 680 // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL. 681 // Checkpointing should use this physical index when 682 // saving/restoring register values. 683 NUM_PHYS_MISCREGS = 606, // 606 684 --- 680 unchanged lines hidden (view full) --- 1365 "l2actlr_el1", 1366 "cpuactlr_el1", 1367 "cpuectlr_el1", 1368 "cpumerrsr_el1", 1369 "l2merrsr_el1", 1370 "cbar_el1", 1371 "contextidr_el2", 1372 | 679 680 // NUM_PHYS_MISCREGS specifies the number of actual physical 681 // registers, not considering the following pseudo-registers 682 // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL. 683 // Checkpointing should use this physical index when 684 // saving/restoring register values. 685 NUM_PHYS_MISCREGS = 606, // 606 686 --- 680 unchanged lines hidden (view full) --- 1367 "l2actlr_el1", 1368 "cpuactlr_el1", 1369 "cpuectlr_el1", 1370 "cpumerrsr_el1", 1371 "l2merrsr_el1", 1372 "cbar_el1", 1373 "contextidr_el2", 1374 |
| 1375 "ttbr1_el2", |
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| 1373 "freeslot1", 1374 "freeslot2", 1375 "freeslot3", 1376 "freeslot4", 1377 "freeslot5", | 1376 "freeslot1", 1377 "freeslot2", 1378 "freeslot3", 1379 "freeslot4", 1380 "freeslot5", |
| 1378 "freeslot6", | |
| 1379 1380 "num_phys_regs", 1381 1382 // Dummy registers 1383 "nop", 1384 "raz", 1385 "cp14_unimpl", 1386 "cp15_unimpl", --- 559 unchanged lines hidden --- | 1381 1382 "num_phys_regs", 1383 1384 // Dummy registers 1385 "nop", 1386 "raz", 1387 "cp14_unimpl", 1388 "cp15_unimpl", --- 559 unchanged lines hidden --- |