| miscregs.hh (12529:d110a01d2689) | miscregs.hh (12530:ab63172c4fbe) |
|---|---|
| 1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 663 unchanged lines hidden (view full) --- 672 MISCREG_FREESLOT_2, // 601 673 MISCREG_FREESLOT_3, // 602 674 MISCREG_FREESLOT_4, // 603 675 MISCREG_FREESLOT_5, // 604 676 MISCREG_FREESLOT_6, // 605 677 678 // NUM_PHYS_MISCREGS specifies the number of actual physical 679 // registers, not considering the following pseudo-registers | 1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 663 unchanged lines hidden (view full) --- 672 MISCREG_FREESLOT_2, // 601 673 MISCREG_FREESLOT_3, // 602 674 MISCREG_FREESLOT_4, // 603 675 MISCREG_FREESLOT_5, // 604 676 MISCREG_FREESLOT_6, // 605 677 678 // NUM_PHYS_MISCREGS specifies the number of actual physical 679 // registers, not considering the following pseudo-registers |
| 680 // (dummy registers), like UNKNOWN, CP15_UNIMPL... | 680 // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL. |
| 681 // Checkpointing should use this physical index when 682 // saving/restoring register values. 683 NUM_PHYS_MISCREGS = 606, // 606 684 685 // Dummy registers 686 MISCREG_NOP, 687 MISCREG_RAZ, 688 MISCREG_CP14_UNIMPL, 689 MISCREG_CP15_UNIMPL, 690 MISCREG_A64_UNIMPL, 691 MISCREG_UNKNOWN, 692 | 681 // Checkpointing should use this physical index when 682 // saving/restoring register values. 683 NUM_PHYS_MISCREGS = 606, // 606 684 685 // Dummy registers 686 MISCREG_NOP, 687 MISCREG_RAZ, 688 MISCREG_CP14_UNIMPL, 689 MISCREG_CP15_UNIMPL, 690 MISCREG_A64_UNIMPL, 691 MISCREG_UNKNOWN, 692 |
| 693 // Implementation defined register: this represent 694 // a pool of unimplemented registers whose access can throw 695 // either UNDEFINED or hypervisor trap exception. 696 MISCREG_IMPDEF_UNIMPL, 697 |
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| 693 // Total number of Misc Registers: Physical + Dummy 694 NUM_MISCREGS 695 }; 696 697 enum MiscRegInfo { 698 MISCREG_IMPLEMENTED, 699 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a 700 // arch generic counter) --- 674 unchanged lines hidden (view full) --- 1375 "num_phys_regs", 1376 1377 // Dummy registers 1378 "nop", 1379 "raz", 1380 "cp14_unimpl", 1381 "cp15_unimpl", 1382 "a64_unimpl", | 698 // Total number of Misc Registers: Physical + Dummy 699 NUM_MISCREGS 700 }; 701 702 enum MiscRegInfo { 703 MISCREG_IMPLEMENTED, 704 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a 705 // arch generic counter) --- 674 unchanged lines hidden (view full) --- 1380 "num_phys_regs", 1381 1382 // Dummy registers 1383 "nop", 1384 "raz", 1385 "cp14_unimpl", 1386 "cp15_unimpl", 1387 "a64_unimpl", |
| 1383 "unknown" | 1388 "unknown", 1389 "impl_defined" |
| 1384 }; 1385 1386 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS, 1387 "The miscRegName array and NUM_MISCREGS are inconsistent."); 1388 1389 BitUnion32(CPSR) 1390 Bitfield<31, 30> nz; 1391 Bitfield<29> c; --- 548 unchanged lines hidden --- | 1390 }; 1391 1392 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS, 1393 "The miscRegName array and NUM_MISCREGS are inconsistent."); 1394 1395 BitUnion32(CPSR) 1396 Bitfield<31, 30> nz; 1397 Bitfield<29> c; --- 548 unchanged lines hidden --- |