miscregs.hh (12499:b81688796004) miscregs.hh (12529:d110a01d2689)
1/*
1/*
2 * Copyright (c) 2010-2017 ARM Limited
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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661 MISCREG_L2ACTLR_EL1, // 593
662 MISCREG_CPUACTLR_EL1, // 594
663 MISCREG_CPUECTLR_EL1, // 595
664 MISCREG_CPUMERRSR_EL1, // 596
665 MISCREG_L2MERRSR_EL1, // 597
666 MISCREG_CBAR_EL1, // 598
667 MISCREG_CONTEXTIDR_EL2, // 599
668
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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661 MISCREG_L2ACTLR_EL1, // 593
662 MISCREG_CPUACTLR_EL1, // 594
663 MISCREG_CPUECTLR_EL1, // 595
664 MISCREG_CPUMERRSR_EL1, // 596
665 MISCREG_L2MERRSR_EL1, // 597
666 MISCREG_CBAR_EL1, // 598
667 MISCREG_CONTEXTIDR_EL2, // 599
668
669 // These MISCREG_FREESLOT are available Misc Register
670 // slots for future registers to be implemented.
671 MISCREG_FREESLOT_1, // 600
672 MISCREG_FREESLOT_2, // 601
673 MISCREG_FREESLOT_3, // 602
674 MISCREG_FREESLOT_4, // 603
675 MISCREG_FREESLOT_5, // 604
676 MISCREG_FREESLOT_6, // 605
677
678 // NUM_PHYS_MISCREGS specifies the number of actual physical
679 // registers, not considering the following pseudo-registers
680 // (dummy registers), like UNKNOWN, CP15_UNIMPL...
681 // Checkpointing should use this physical index when
682 // saving/restoring register values.
683 NUM_PHYS_MISCREGS = 606, // 606
684
669 // Dummy registers
685 // Dummy registers
670 MISCREG_NOP, // 600
671 MISCREG_RAZ, // 601
672 MISCREG_CP14_UNIMPL, // 602
673 MISCREG_CP15_UNIMPL, // 603
674 MISCREG_A64_UNIMPL, // 604
675 MISCREG_UNKNOWN, // 605
686 MISCREG_NOP,
687 MISCREG_RAZ,
688 MISCREG_CP14_UNIMPL,
689 MISCREG_CP15_UNIMPL,
690 MISCREG_A64_UNIMPL,
691 MISCREG_UNKNOWN,
676
692
677 NUM_MISCREGS // 606
693 // Total number of Misc Registers: Physical + Dummy
694 NUM_MISCREGS
678 };
679
680 enum MiscRegInfo {
681 MISCREG_IMPLEMENTED,
682 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
683 // arch generic counter)
684 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
685 // tells whether the instruction should raise a

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1343 "l2actlr_el1",
1344 "cpuactlr_el1",
1345 "cpuectlr_el1",
1346 "cpumerrsr_el1",
1347 "l2merrsr_el1",
1348 "cbar_el1",
1349 "contextidr_el2",
1350
695 };
696
697 enum MiscRegInfo {
698 MISCREG_IMPLEMENTED,
699 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
700 // arch generic counter)
701 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
702 // tells whether the instruction should raise a

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1360 "l2actlr_el1",
1361 "cpuactlr_el1",
1362 "cpuectlr_el1",
1363 "cpumerrsr_el1",
1364 "l2merrsr_el1",
1365 "cbar_el1",
1366 "contextidr_el2",
1367
1368 "freeslot1",
1369 "freeslot2",
1370 "freeslot3",
1371 "freeslot4",
1372 "freeslot5",
1373 "freeslot6",
1374
1375 "num_phys_regs",
1376
1351 // Dummy registers
1352 "nop",
1353 "raz",
1354 "cp14_unimpl",
1355 "cp15_unimpl",
1356 "a64_unimpl",
1357 "unknown"
1358 };

--- 555 unchanged lines hidden --- 		1377 // Dummy registers
1378 "nop",
1379 "raz",
1380 "cp14_unimpl",
1381 "cp15_unimpl",
1382 "a64_unimpl",
1383 "unknown"
1384 };

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