| miscregs.hh (11575:0005b28685f0) | miscregs.hh (11768:5b80960dcf08) |
|---|---|
| 1/* 2 * Copyright (c) 2010-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 119 unchanged lines hidden (view full) --- 128 MISCREG_DBGPRCR, // 67 129 MISCREG_DBGDSAR, // 68 130 MISCREG_DBGCLAIMSET, // 69 131 MISCREG_DBGCLAIMCLR, // 70 132 MISCREG_DBGAUTHSTATUS, // 71 133 MISCREG_DBGDEVID2, // 72 134 MISCREG_DBGDEVID1, // 73 135 MISCREG_DBGDEVID0, // 74 | 1/* 2 * Copyright (c) 2010-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 119 unchanged lines hidden (view full) --- 128 MISCREG_DBGPRCR, // 67 129 MISCREG_DBGDSAR, // 68 130 MISCREG_DBGCLAIMSET, // 69 131 MISCREG_DBGCLAIMCLR, // 70 132 MISCREG_DBGAUTHSTATUS, // 71 133 MISCREG_DBGDEVID2, // 72 134 MISCREG_DBGDEVID1, // 73 135 MISCREG_DBGDEVID0, // 74 |
| 136 MISCREG_TEECR, // 75 | 136 MISCREG_TEECR, // 75, not in ARM DDI 0487A.b+ |
| 137 MISCREG_JIDR, // 76 | 137 MISCREG_JIDR, // 76 |
| 138 MISCREG_TEEHBR, // 77 | 138 MISCREG_TEEHBR, // 77, not in ARM DDI 0487A.b+ |
| 139 MISCREG_JOSCR, // 78 140 MISCREG_JMCR, // 79 141 142 // AArch32 CP15 registers (system control) 143 MISCREG_MIDR, // 80 144 MISCREG_CTR, // 81 145 MISCREG_TCMTR, // 82 146 MISCREG_TLBTR, // 83 --- 268 unchanged lines hidden (view full) --- 415 MISCREG_MDRAR_EL1, // 350 416 MISCREG_OSLAR_EL1, // 351 417 MISCREG_OSLSR_EL1, // 352 418 MISCREG_OSDLR_EL1, // 353 419 MISCREG_DBGPRCR_EL1, // 354 420 MISCREG_DBGCLAIMSET_EL1, // 355 421 MISCREG_DBGCLAIMCLR_EL1, // 356 422 MISCREG_DBGAUTHSTATUS_EL1, // 357 | 139 MISCREG_JOSCR, // 78 140 MISCREG_JMCR, // 79 141 142 // AArch32 CP15 registers (system control) 143 MISCREG_MIDR, // 80 144 MISCREG_CTR, // 81 145 MISCREG_TCMTR, // 82 146 MISCREG_TLBTR, // 83 --- 268 unchanged lines hidden (view full) --- 415 MISCREG_MDRAR_EL1, // 350 416 MISCREG_OSLAR_EL1, // 351 417 MISCREG_OSLSR_EL1, // 352 418 MISCREG_OSDLR_EL1, // 353 419 MISCREG_DBGPRCR_EL1, // 354 420 MISCREG_DBGCLAIMSET_EL1, // 355 421 MISCREG_DBGCLAIMCLR_EL1, // 356 422 MISCREG_DBGAUTHSTATUS_EL1, // 357 |
| 423 MISCREG_TEECR32_EL1, // 358 424 MISCREG_TEEHBR32_EL1, // 359 | 423 MISCREG_TEECR32_EL1, // 358, not in ARM DDI 0487A.b+ 424 MISCREG_TEEHBR32_EL1, // 359, not in ARM DDI 0487A.b+ |
| 425 426 // AArch64 registers (Op0=1,3) 427 MISCREG_MIDR_EL1, // 360 428 MISCREG_MPIDR_EL1, // 361 429 MISCREG_REVIDR_EL1, // 362 430 MISCREG_ID_PFR0_EL1, // 363 431 MISCREG_ID_PFR1_EL1, // 364 432 MISCREG_ID_DFR0_EL1, // 365 --- 1456 unchanged lines hidden --- | 425 426 // AArch64 registers (Op0=1,3) 427 MISCREG_MIDR_EL1, // 360 428 MISCREG_MPIDR_EL1, // 361 429 MISCREG_REVIDR_EL1, // 362 430 MISCREG_ID_PFR0_EL1, // 363 431 MISCREG_ID_PFR1_EL1, // 364 432 MISCREG_ID_DFR0_EL1, // 365 --- 1456 unchanged lines hidden --- |