miscregs.hh (10506:aa23216161fa) miscregs.hh (10856:d02b45a554b5)
1/*
1/*
2 * Copyright (c) 2010-2014 ARM Limited
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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658 MISCREG_DL1DATA3_EL1, // 591
659 MISCREG_DL1DATA4_EL1, // 592
660 MISCREG_L2ACTLR_EL1, // 593
661 MISCREG_CPUACTLR_EL1, // 594
662 MISCREG_CPUECTLR_EL1, // 595
663 MISCREG_CPUMERRSR_EL1, // 596
664 MISCREG_L2MERRSR_EL1, // 597
665 MISCREG_CBAR_EL1, // 598
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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658 MISCREG_DL1DATA3_EL1, // 591
659 MISCREG_DL1DATA4_EL1, // 592
660 MISCREG_L2ACTLR_EL1, // 593
661 MISCREG_CPUACTLR_EL1, // 594
662 MISCREG_CPUECTLR_EL1, // 595
663 MISCREG_CPUMERRSR_EL1, // 596
664 MISCREG_L2MERRSR_EL1, // 597
665 MISCREG_CBAR_EL1, // 598
666 MISCREG_CONTEXTIDR_EL2, // 599
666
667 // Dummy registers
667
668 // Dummy registers
668 MISCREG_NOP, // 599
669 MISCREG_RAZ, // 600
670 MISCREG_CP14_UNIMPL, // 601
671 MISCREG_CP15_UNIMPL, // 602
672 MISCREG_A64_UNIMPL, // 603
673 MISCREG_UNKNOWN, // 604
669 MISCREG_NOP, // 600
670 MISCREG_RAZ, // 601
671 MISCREG_CP14_UNIMPL, // 602
672 MISCREG_CP15_UNIMPL, // 603
673 MISCREG_A64_UNIMPL, // 604
674 MISCREG_UNKNOWN, // 605
674
675
675 NUM_MISCREGS // 605
676 NUM_MISCREGS // 606
676 };
677
678 enum MiscRegInfo {
679 MISCREG_IMPLEMENTED,
680 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
681 // arch generic counter)
682 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
683 // tells whether the instruction should raise a

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1339 "dl1data3_el1",
1340 "dl1data4_el1",
1341 "l2actlr_el1",
1342 "cpuactlr_el1",
1343 "cpuectlr_el1",
1344 "cpumerrsr_el1",
1345 "l2merrsr_el1",
1346 "cbar_el1",
677 };
678
679 enum MiscRegInfo {
680 MISCREG_IMPLEMENTED,
681 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
682 // arch generic counter)
683 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
684 // tells whether the instruction should raise a

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1340 "dl1data3_el1",
1341 "dl1data4_el1",
1342 "l2actlr_el1",
1343 "cpuactlr_el1",
1344 "cpuectlr_el1",
1345 "cpumerrsr_el1",
1346 "l2merrsr_el1",
1347 "cbar_el1",
1348 "contextidr_el2",
1347
1348 // Dummy registers
1349 "nop",
1350 "raz",
1351 "cp14_unimpl",
1352 "cp15_unimpl",
1353 "a64_unimpl",
1354 "unknown"

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1350 // Dummy registers
1351 "nop",
1352 "raz",
1353 "cp14_unimpl",
1354 "cp15_unimpl",
1355 "a64_unimpl",
1356 "unknown"

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