| miscregs.hh (10338:8bee5f4edb92) | miscregs.hh (10421:d469fdcd937e) |
|---|---|
| 1/* 2 * Copyright (c) 2010-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1845 unchanged lines hidden (view full) --- 1854 1855 // Checks write access permissions to AArch64 system registers 1856 bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 1857 ThreadContext *tc); 1858 1859 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful 1860 // for MCR/MRC instructions 1861 int | 1/* 2 * Copyright (c) 2010-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1845 unchanged lines hidden (view full) --- 1854 1855 // Checks write access permissions to AArch64 system registers 1856 bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 1857 ThreadContext *tc); 1858 1859 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful 1860 // for MCR/MRC instructions 1861 int |
| 1862 flattenMiscRegNsBanked(int reg, ThreadContext *tc); | 1862 flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc); |
| 1863 1864 // Flattens a misc reg index using the specified security state. This is 1865 // used for opperations (eg address translations) where the security 1866 // state of the register access may differ from the current state of the 1867 // processor 1868 int | 1863 1864 // Flattens a misc reg index using the specified security state. This is 1865 // used for opperations (eg address translations) where the security 1866 // state of the register access may differ from the current state of the 1867 // processor 1868 int |
| 1869 flattenMiscRegNsBanked(int reg, ThreadContext *tc, bool ns); | 1869 flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns); |
| 1870 1871 // Takes a misc reg index and returns the root reg if its one of a set of 1872 // banked registers 1873 void 1874 preUnflattenMiscReg(); 1875 1876 int 1877 unflattenMiscReg(int reg); 1878 1879} 1880 1881#endif // __ARCH_ARM_MISCREGS_HH__ | 1870 1871 // Takes a misc reg index and returns the root reg if its one of a set of 1872 // banked registers 1873 void 1874 preUnflattenMiscReg(); 1875 1876 int 1877 unflattenMiscReg(int reg); 1878 1879} 1880 1881#endif // __ARCH_ARM_MISCREGS_HH__ |