miscregs.hh (10324:f40134eb3f85) miscregs.hh (10338:8bee5f4edb92)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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48#include "base/bitunion.hh"
49#include "base/compiler.hh"
50
51class ThreadContext;
52
53
54namespace ArmISA
55{
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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48#include "base/bitunion.hh"
49#include "base/compiler.hh"
50
51class ThreadContext;
52
53
54namespace ArmISA
55{
56 enum ConditionCode {
57 COND_EQ = 0,
58 COND_NE, // 1
59 COND_CS, // 2
60 COND_CC, // 3
61 COND_MI, // 4
62 COND_PL, // 5
63 COND_VS, // 6
64 COND_VC, // 7
65 COND_HI, // 8
66 COND_LS, // 9
67 COND_GE, // 10
68 COND_LT, // 11
69 COND_GT, // 12
70 COND_LE, // 13
71 COND_AL, // 14
72 COND_UC // 15
73 };
74
75 enum MiscRegIndex {
76 MISCREG_CPSR = 0, // 0
77 MISCREG_SPSR, // 1
78 MISCREG_SPSR_FIQ, // 2
79 MISCREG_SPSR_IRQ, // 3
80 MISCREG_SPSR_SVC, // 4
81 MISCREG_SPSR_MON, // 5
82 MISCREG_SPSR_ABT, // 6

--- 1818 unchanged lines hidden --- 		56 enum MiscRegIndex {
57 MISCREG_CPSR = 0, // 0
58 MISCREG_SPSR, // 1
59 MISCREG_SPSR_FIQ, // 2
60 MISCREG_SPSR_IRQ, // 3
61 MISCREG_SPSR_SVC, // 4
62 MISCREG_SPSR_MON, // 5
63 MISCREG_SPSR_ABT, // 6

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