1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 248 unchanged lines hidden (view full) --- 257 Bitfield<8> a; 258 Bitfield<7> i; 259 Bitfield<6> f; 260 Bitfield<5> t; 261 Bitfield<4, 0> mode; 262 EndBitUnion(CPSR) 263 264 BitUnion8(ITSTATE) |
265 /* Note that the split (cond, mask) below is not as in ARM ARM. 266 * But it is more convenient for simulation. The condition 267 * is always the concatenation of the top 3 bits and the next bit, 268 * which applies when one of the bottom 4 bits is set. 269 * Refer to predecoder.cc for the use case. 270 */ |
271 Bitfield<7, 4> cond; 272 Bitfield<3, 0> mask; 273 // Bitfields for moving to/from CPSR 274 Bitfield<7, 2> top6; 275 Bitfield<1, 0> bottom2; 276 EndBitUnion(ITSTATE) 277 278 // This mask selects bits of the CPSR that actually go in the CondCodes --- 161 unchanged lines hidden --- |