70d69
< MISCREG_ITSTATE,
210c209
< "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
---
> "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
267,280d265
< BitUnion8(ITSTATE)
< /* Note that the split (cond, mask) below is not as in ARM ARM.
< * But it is more convenient for simulation. The condition
< * is always the concatenation of the top 3 bits and the next bit,
< * which applies when one of the bottom 4 bits is set.
< * Refer to predecoder.cc for the use case.
< */
< Bitfield<7, 4> cond;
< Bitfield<3, 0> mask;
< // Bitfields for moving to/from CPSR
< Bitfield<7, 2> top6;
< Bitfield<1, 0> bottom2;
< EndBitUnion(ITSTATE)
<