1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
46
47namespace ArmISA
48{
49 enum ConditionCode {
50 COND_EQ = 0,
51 COND_NE, // 1
52 COND_CS, // 2
53 COND_CC, // 3
54 COND_MI, // 4
55 COND_PL, // 5
56 COND_VS, // 6
57 COND_VC, // 7
58 COND_HI, // 8
59 COND_LS, // 9
60 COND_GE, // 10
61 COND_LT, // 11
62 COND_GT, // 12
63 COND_LE, // 13
64 COND_AL, // 14
65 COND_UC // 15
66 };
67
68 enum MiscRegIndex {
69 MISCREG_CPSR = 0,
70 MISCREG_SPSR,
71 MISCREG_SPSR_FIQ,
72 MISCREG_SPSR_IRQ,
73 MISCREG_SPSR_SVC,
74 MISCREG_SPSR_MON,
75 MISCREG_SPSR_UND,
76 MISCREG_SPSR_ABT,
77 MISCREG_FPSR,
78 MISCREG_FPSID,
79 MISCREG_FPSCR,
80 MISCREG_FPEXC,
81 MISCREG_MVFR0,
82 MISCREG_MVFR1,
83 MISCREG_SEV_MAILBOX,
84
85 // CP15 registers
86 MISCREG_CP15_START,
87 MISCREG_SCTLR = MISCREG_CP15_START,
88 MISCREG_DCCISW,
89 MISCREG_DCCIMVAC,
90 MISCREG_DCCMVAC,
91 MISCREG_CONTEXTIDR,
92 MISCREG_TPIDRURW,
93 MISCREG_TPIDRURO,
94 MISCREG_TPIDRPRW,
95 MISCREG_CP15ISB,
96 MISCREG_CP15DSB,
97 MISCREG_CP15DMB,
98 MISCREG_CPACR,
99 MISCREG_CLIDR,
100 MISCREG_CCSIDR,
101 MISCREG_CSSELR,
102 MISCREG_ICIALLUIS,
103 MISCREG_ICIALLU,
104 MISCREG_ICIMVAU,
105 MISCREG_BPIMVA,
106 MISCREG_BPIALLIS,
107 MISCREG_BPIALL,
108 MISCREG_MIDR,
109 MISCREG_TTBR0,
110 MISCREG_TTBR1,
111 MISCREG_TLBTR,
112 MISCREG_DACR,
113 MISCREG_TLBIALLIS,
114 MISCREG_TLBIMVAIS,
115 MISCREG_TLBIASIDIS,
116 MISCREG_TLBIMVAAIS,
117 MISCREG_ITLBIALL,
118 MISCREG_ITLBIMVA,
119 MISCREG_ITLBIASID,
120 MISCREG_DTLBIALL,
121 MISCREG_DTLBIMVA,
122 MISCREG_DTLBIASID,
123 MISCREG_TLBIALL,
124 MISCREG_TLBIMVA,
125 MISCREG_TLBIASID,
126 MISCREG_TLBIMVAA,
127 MISCREG_DFSR,
128 MISCREG_IFSR,
129 MISCREG_DFAR,
130 MISCREG_IFAR,
131 MISCREG_CP15_UNIMP_START,
132 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
133 MISCREG_TCMTR,
134 MISCREG_MPIDR,
135 MISCREG_ID_PFR0,
136 MISCREG_ID_PFR1,
137 MISCREG_ID_DFR0,
138 MISCREG_ID_AFR0,
139 MISCREG_ID_MMFR0,
140 MISCREG_ID_MMFR1,
141 MISCREG_ID_MMFR2,
142 MISCREG_ID_MMFR3,
143 MISCREG_ID_ISAR0,
144 MISCREG_ID_ISAR1,
145 MISCREG_ID_ISAR2,
146 MISCREG_ID_ISAR3,
147 MISCREG_ID_ISAR4,
148 MISCREG_ID_ISAR5,
149 MISCREG_PAR,
150 MISCREG_AIDR,
151 MISCREG_ACTLR,
152 MISCREG_ADFSR,
153 MISCREG_AIFSR,
154 MISCREG_DCIMVAC,
155 MISCREG_DCISW,
156 MISCREG_MCCSW,
157 MISCREG_DCCMVAU,
158 MISCREG_SCR,
159 MISCREG_SDER,
160 MISCREG_NSACR,
161 MISCREG_TTBCR,
162 MISCREG_V2PCWPR,
163 MISCREG_V2PCWPW,
164 MISCREG_V2PCWUR,
165 MISCREG_V2PCWUW,
166 MISCREG_V2POWPR,
167 MISCREG_V2POWPW,
168 MISCREG_V2POWUR,
169 MISCREG_V2POWUW,
170 MISCREG_PRRR,
171 MISCREG_NMRR,
172 MISCREG_VBAR,
173 MISCREG_MVBAR,
174 MISCREG_ISR,
175 MISCREG_FCEIDR,
176
177
178 MISCREG_CP15_END,
179
180 // Dummy indices
181 MISCREG_NOP = MISCREG_CP15_END,
182 MISCREG_RAZ,
183
184 NUM_MISCREGS
185 };
186
187 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
188 unsigned crm, unsigned opc2);
189
190 const char * const miscRegName[NUM_MISCREGS] = {
191 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
192 "spsr_mon", "spsr_und", "spsr_abt",
193 "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
194 "sev_mailbox",
195 "sctlr", "dccisw", "dccimvac", "dccmvac",
196 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
197 "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
198 "clidr", "ccsidr", "csselr",
199 "icialluis", "iciallu", "icimvau",
200 "bpimva", "bpiallis", "bpiall",
201 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
202 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
203 "itlbiall", "itlbimva", "itlbiasid",
204 "dtlbiall", "dtlbimva", "dtlbiasid",
205 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
206 "dfsr", "ifsr", "dfar", "ifar",
207 "ctr", "tcmtr", "mpidr",
208 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
209 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
210 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
211 "par", "aidr", "actlr",
212 "adfsr", "aifsr",
213 "dcimvac", "dcisw", "mccsw",
214 "dccmvau",
215 "scr", "sder", "nsacr", "ttbcr",
216 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
217 "v2powpr", "v2powpw", "v2powur", "v2powuw",
218 "prrr", "nmrr", "vbar", "mvbar", "isr", "fceidr",
219 "nop", "raz"
220 };
221
222 BitUnion32(CPSR)
223 Bitfield<31> n;
224 Bitfield<30> z;
225 Bitfield<29> c;
226 Bitfield<28> v;
227 Bitfield<27> q;
228 Bitfield<26,25> it1;
229 Bitfield<24> j;
230 Bitfield<19, 16> ge;
231 Bitfield<15,10> it2;
232 Bitfield<9> e;
233 Bitfield<8> a;
234 Bitfield<7> i;
235 Bitfield<6> f;
236 Bitfield<5> t;
237 Bitfield<4, 0> mode;
238 EndBitUnion(CPSR)
239
240 // This mask selects bits of the CPSR that actually go in the CondCodes
241 // integer register to allow renaming.
242 static const uint32_t CondCodesMask = 0xF80F0000;
243
244 BitUnion32(SCTLR)
245 Bitfield<31> ie; // Instruction endianness
246 Bitfield<30> te; // Thumb Exception Enable
247 Bitfield<29> afe; // Access flag enable
248 Bitfield<28> tre; // TEX Remap bit
249 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
250 Bitfield<25> ee; // Exception Endianness bit
251 Bitfield<24> ve; // Interrupt vectors enable
252 Bitfield<23> rao1;// Read as one
253 Bitfield<22> u; // Alignment (now unused)
254 Bitfield<21> fi; // Fast interrupts configuration enable
255 Bitfield<19> dz; // Divide by Zero fault enable bit
256 Bitfield<18> rao2;// Read as one
257 Bitfield<17> br; // Background region bit
258 Bitfield<16> rao3;// Read as one
259 Bitfield<14> rr; // Round robin cache replacement
260 Bitfield<13> v; // Base address for exception vectors
261 Bitfield<12> i; // instruction cache enable
262 Bitfield<11> z; // branch prediction enable bit
263 Bitfield<10> sw; // Enable swp/swpb
264 Bitfield<6,3> rao4;// Read as one
265 Bitfield<7> b; // Endianness support (unused)
266 Bitfield<2> c; // Cache enable bit
267 Bitfield<1> a; // Alignment fault checking
268 Bitfield<0> m; // MMU enable bit
269 EndBitUnion(SCTLR)
270
271 BitUnion32(CPACR)
272 Bitfield<1, 0> cp0;
273 Bitfield<3, 2> cp1;
274 Bitfield<5, 4> cp2;
275 Bitfield<7, 6> cp3;
276 Bitfield<9, 8> cp4;
277 Bitfield<11, 10> cp5;
278 Bitfield<13, 12> cp6;
279 Bitfield<15, 14> cp7;
280 Bitfield<17, 16> cp8;
281 Bitfield<19, 18> cp9;
282 Bitfield<21, 20> cp10;
283 Bitfield<23, 22> cp11;
284 Bitfield<25, 24> cp12;
285 Bitfield<27, 26> cp13;
286 Bitfield<30> d32dis;
287 Bitfield<31> asedis;
288 EndBitUnion(CPACR)
289
290 BitUnion32(FSR)
291 Bitfield<3, 0> fsLow;
292 Bitfield<7, 4> domain;
293 Bitfield<10> fsHigh;
294 Bitfield<11> wnr;
295 Bitfield<12> ext;
296 EndBitUnion(FSR)
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
46
47namespace ArmISA
48{
49 enum ConditionCode {
50 COND_EQ = 0,
51 COND_NE, // 1
52 COND_CS, // 2
53 COND_CC, // 3
54 COND_MI, // 4
55 COND_PL, // 5
56 COND_VS, // 6
57 COND_VC, // 7
58 COND_HI, // 8
59 COND_LS, // 9
60 COND_GE, // 10
61 COND_LT, // 11
62 COND_GT, // 12
63 COND_LE, // 13
64 COND_AL, // 14
65 COND_UC // 15
66 };
67
68 enum MiscRegIndex {
69 MISCREG_CPSR = 0,
70 MISCREG_SPSR,
71 MISCREG_SPSR_FIQ,
72 MISCREG_SPSR_IRQ,
73 MISCREG_SPSR_SVC,
74 MISCREG_SPSR_MON,
75 MISCREG_SPSR_UND,
76 MISCREG_SPSR_ABT,
77 MISCREG_FPSR,
78 MISCREG_FPSID,
79 MISCREG_FPSCR,
80 MISCREG_FPEXC,
81 MISCREG_MVFR0,
82 MISCREG_MVFR1,
83 MISCREG_SEV_MAILBOX,
84
85 // CP15 registers
86 MISCREG_CP15_START,
87 MISCREG_SCTLR = MISCREG_CP15_START,
88 MISCREG_DCCISW,
89 MISCREG_DCCIMVAC,
90 MISCREG_DCCMVAC,
91 MISCREG_CONTEXTIDR,
92 MISCREG_TPIDRURW,
93 MISCREG_TPIDRURO,
94 MISCREG_TPIDRPRW,
95 MISCREG_CP15ISB,
96 MISCREG_CP15DSB,
97 MISCREG_CP15DMB,
98 MISCREG_CPACR,
99 MISCREG_CLIDR,
100 MISCREG_CCSIDR,
101 MISCREG_CSSELR,
102 MISCREG_ICIALLUIS,
103 MISCREG_ICIALLU,
104 MISCREG_ICIMVAU,
105 MISCREG_BPIMVA,
106 MISCREG_BPIALLIS,
107 MISCREG_BPIALL,
108 MISCREG_MIDR,
109 MISCREG_TTBR0,
110 MISCREG_TTBR1,
111 MISCREG_TLBTR,
112 MISCREG_DACR,
113 MISCREG_TLBIALLIS,
114 MISCREG_TLBIMVAIS,
115 MISCREG_TLBIASIDIS,
116 MISCREG_TLBIMVAAIS,
117 MISCREG_ITLBIALL,
118 MISCREG_ITLBIMVA,
119 MISCREG_ITLBIASID,
120 MISCREG_DTLBIALL,
121 MISCREG_DTLBIMVA,
122 MISCREG_DTLBIASID,
123 MISCREG_TLBIALL,
124 MISCREG_TLBIMVA,
125 MISCREG_TLBIASID,
126 MISCREG_TLBIMVAA,
127 MISCREG_DFSR,
128 MISCREG_IFSR,
129 MISCREG_DFAR,
130 MISCREG_IFAR,
131 MISCREG_CP15_UNIMP_START,
132 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
133 MISCREG_TCMTR,
134 MISCREG_MPIDR,
135 MISCREG_ID_PFR0,
136 MISCREG_ID_PFR1,
137 MISCREG_ID_DFR0,
138 MISCREG_ID_AFR0,
139 MISCREG_ID_MMFR0,
140 MISCREG_ID_MMFR1,
141 MISCREG_ID_MMFR2,
142 MISCREG_ID_MMFR3,
143 MISCREG_ID_ISAR0,
144 MISCREG_ID_ISAR1,
145 MISCREG_ID_ISAR2,
146 MISCREG_ID_ISAR3,
147 MISCREG_ID_ISAR4,
148 MISCREG_ID_ISAR5,
149 MISCREG_PAR,
150 MISCREG_AIDR,
151 MISCREG_ACTLR,
152 MISCREG_ADFSR,
153 MISCREG_AIFSR,
154 MISCREG_DCIMVAC,
155 MISCREG_DCISW,
156 MISCREG_MCCSW,
157 MISCREG_DCCMVAU,
158 MISCREG_SCR,
159 MISCREG_SDER,
160 MISCREG_NSACR,
161 MISCREG_TTBCR,
162 MISCREG_V2PCWPR,
163 MISCREG_V2PCWPW,
164 MISCREG_V2PCWUR,
165 MISCREG_V2PCWUW,
166 MISCREG_V2POWPR,
167 MISCREG_V2POWPW,
168 MISCREG_V2POWUR,
169 MISCREG_V2POWUW,
170 MISCREG_PRRR,
171 MISCREG_NMRR,
172 MISCREG_VBAR,
173 MISCREG_MVBAR,
174 MISCREG_ISR,
175 MISCREG_FCEIDR,
176
177
178 MISCREG_CP15_END,
179
180 // Dummy indices
181 MISCREG_NOP = MISCREG_CP15_END,
182 MISCREG_RAZ,
183
184 NUM_MISCREGS
185 };
186
187 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
188 unsigned crm, unsigned opc2);
189
190 const char * const miscRegName[NUM_MISCREGS] = {
191 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
192 "spsr_mon", "spsr_und", "spsr_abt",
193 "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
194 "sev_mailbox",
195 "sctlr", "dccisw", "dccimvac", "dccmvac",
196 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
197 "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
198 "clidr", "ccsidr", "csselr",
199 "icialluis", "iciallu", "icimvau",
200 "bpimva", "bpiallis", "bpiall",
201 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
202 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
203 "itlbiall", "itlbimva", "itlbiasid",
204 "dtlbiall", "dtlbimva", "dtlbiasid",
205 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
206 "dfsr", "ifsr", "dfar", "ifar",
207 "ctr", "tcmtr", "mpidr",
208 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
209 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
210 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
211 "par", "aidr", "actlr",
212 "adfsr", "aifsr",
213 "dcimvac", "dcisw", "mccsw",
214 "dccmvau",
215 "scr", "sder", "nsacr", "ttbcr",
216 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
217 "v2powpr", "v2powpw", "v2powur", "v2powuw",
218 "prrr", "nmrr", "vbar", "mvbar", "isr", "fceidr",
219 "nop", "raz"
220 };
221
222 BitUnion32(CPSR)
223 Bitfield<31> n;
224 Bitfield<30> z;
225 Bitfield<29> c;
226 Bitfield<28> v;
227 Bitfield<27> q;
228 Bitfield<26,25> it1;
229 Bitfield<24> j;
230 Bitfield<19, 16> ge;
231 Bitfield<15,10> it2;
232 Bitfield<9> e;
233 Bitfield<8> a;
234 Bitfield<7> i;
235 Bitfield<6> f;
236 Bitfield<5> t;
237 Bitfield<4, 0> mode;
238 EndBitUnion(CPSR)
239
240 // This mask selects bits of the CPSR that actually go in the CondCodes
241 // integer register to allow renaming.
242 static const uint32_t CondCodesMask = 0xF80F0000;
243
244 BitUnion32(SCTLR)
245 Bitfield<31> ie; // Instruction endianness
246 Bitfield<30> te; // Thumb Exception Enable
247 Bitfield<29> afe; // Access flag enable
248 Bitfield<28> tre; // TEX Remap bit
249 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
250 Bitfield<25> ee; // Exception Endianness bit
251 Bitfield<24> ve; // Interrupt vectors enable
252 Bitfield<23> rao1;// Read as one
253 Bitfield<22> u; // Alignment (now unused)
254 Bitfield<21> fi; // Fast interrupts configuration enable
255 Bitfield<19> dz; // Divide by Zero fault enable bit
256 Bitfield<18> rao2;// Read as one
257 Bitfield<17> br; // Background region bit
258 Bitfield<16> rao3;// Read as one
259 Bitfield<14> rr; // Round robin cache replacement
260 Bitfield<13> v; // Base address for exception vectors
261 Bitfield<12> i; // instruction cache enable
262 Bitfield<11> z; // branch prediction enable bit
263 Bitfield<10> sw; // Enable swp/swpb
264 Bitfield<6,3> rao4;// Read as one
265 Bitfield<7> b; // Endianness support (unused)
266 Bitfield<2> c; // Cache enable bit
267 Bitfield<1> a; // Alignment fault checking
268 Bitfield<0> m; // MMU enable bit
269 EndBitUnion(SCTLR)
270
271 BitUnion32(CPACR)
272 Bitfield<1, 0> cp0;
273 Bitfield<3, 2> cp1;
274 Bitfield<5, 4> cp2;
275 Bitfield<7, 6> cp3;
276 Bitfield<9, 8> cp4;
277 Bitfield<11, 10> cp5;
278 Bitfield<13, 12> cp6;
279 Bitfield<15, 14> cp7;
280 Bitfield<17, 16> cp8;
281 Bitfield<19, 18> cp9;
282 Bitfield<21, 20> cp10;
283 Bitfield<23, 22> cp11;
284 Bitfield<25, 24> cp12;
285 Bitfield<27, 26> cp13;
286 Bitfield<30> d32dis;
287 Bitfield<31> asedis;
288 EndBitUnion(CPACR)
289
290 BitUnion32(FSR)
291 Bitfield<3, 0> fsLow;
292 Bitfield<7, 4> domain;
293 Bitfield<10> fsHigh;
294 Bitfield<11> wnr;
295 Bitfield<12> ext;
296 EndBitUnion(FSR)
|