1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
46
47namespace ArmISA
48{
49 enum ConditionCode {
50 COND_EQ = 0,
51 COND_NE, // 1
52 COND_CS, // 2
53 COND_CC, // 3
54 COND_MI, // 4
55 COND_PL, // 5
56 COND_VS, // 6
57 COND_VC, // 7
58 COND_HI, // 8
59 COND_LS, // 9
60 COND_GE, // 10
61 COND_LT, // 11
62 COND_GT, // 12
63 COND_LE, // 13
64 COND_AL, // 14
65 COND_UC // 15
66 };
67
68 enum MiscRegIndex {
69 MISCREG_CPSR = 0,
70 MISCREG_SPSR,
71 MISCREG_SPSR_FIQ,
72 MISCREG_SPSR_IRQ,
73 MISCREG_SPSR_SVC,
74 MISCREG_SPSR_MON,
75 MISCREG_SPSR_UND,
76 MISCREG_SPSR_ABT,
77 MISCREG_FPSR,
78 MISCREG_FPSID,
79 MISCREG_FPSCR,
80 MISCREG_FPEXC,
81
82 // CP15 registers
83 MISCREG_CP15_START,
84 MISCREG_SCTLR = MISCREG_CP15_START,
85 MISCREG_DCCISW,
86 MISCREG_DCCIMVAC,
87 MISCREG_CONTEXTIDR,
88 MISCREG_TPIDRURW,
89 MISCREG_TPIDRURO,
90 MISCREG_TPIDRPRW,
91 MISCREG_CP15ISB,
92 MISCREG_CP15DSB,
93 MISCREG_CP15DMB,
94 MISCREG_CPACR,
95 MISCREG_CLIDR,
96 MISCREG_ICIALLUIS,
97 MISCREG_ICIALLU,
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
46
47namespace ArmISA
48{
49 enum ConditionCode {
50 COND_EQ = 0,
51 COND_NE, // 1
52 COND_CS, // 2
53 COND_CC, // 3
54 COND_MI, // 4
55 COND_PL, // 5
56 COND_VS, // 6
57 COND_VC, // 7
58 COND_HI, // 8
59 COND_LS, // 9
60 COND_GE, // 10
61 COND_LT, // 11
62 COND_GT, // 12
63 COND_LE, // 13
64 COND_AL, // 14
65 COND_UC // 15
66 };
67
68 enum MiscRegIndex {
69 MISCREG_CPSR = 0,
70 MISCREG_SPSR,
71 MISCREG_SPSR_FIQ,
72 MISCREG_SPSR_IRQ,
73 MISCREG_SPSR_SVC,
74 MISCREG_SPSR_MON,
75 MISCREG_SPSR_UND,
76 MISCREG_SPSR_ABT,
77 MISCREG_FPSR,
78 MISCREG_FPSID,
79 MISCREG_FPSCR,
80 MISCREG_FPEXC,
81
82 // CP15 registers
83 MISCREG_CP15_START,
84 MISCREG_SCTLR = MISCREG_CP15_START,
85 MISCREG_DCCISW,
86 MISCREG_DCCIMVAC,
87 MISCREG_CONTEXTIDR,
88 MISCREG_TPIDRURW,
89 MISCREG_TPIDRURO,
90 MISCREG_TPIDRPRW,
91 MISCREG_CP15ISB,
92 MISCREG_CP15DSB,
93 MISCREG_CP15DMB,
94 MISCREG_CPACR,
95 MISCREG_CLIDR,
96 MISCREG_ICIALLUIS,
97 MISCREG_ICIALLU,
|
| 98 MISCREG_ICIMVAU,
|
98 MISCREG_CP15_UNIMP_START,
99 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
100 MISCREG_TCMTR,
101 MISCREG_MPUIR,
102 MISCREG_MPIDR,
103 MISCREG_MIDR,
104 MISCREG_ID_PFR0,
105 MISCREG_ID_PFR1,
106 MISCREG_ID_DFR0,
107 MISCREG_ID_AFR0,
108 MISCREG_ID_MMFR0,
109 MISCREG_ID_MMFR1,
110 MISCREG_ID_MMFR2,
111 MISCREG_ID_MMFR3,
112 MISCREG_ID_ISAR0,
113 MISCREG_ID_ISAR1,
114 MISCREG_ID_ISAR2,
115 MISCREG_ID_ISAR3,
116 MISCREG_ID_ISAR4,
117 MISCREG_ID_ISAR5,
118 MISCREG_CCSIDR,
119 MISCREG_AIDR,
120 MISCREG_CSSELR,
121 MISCREG_ACTLR,
122 MISCREG_DFSR,
123 MISCREG_IFSR,
124 MISCREG_ADFSR,
125 MISCREG_AIFSR,
126 MISCREG_DFAR,
127 MISCREG_IFAR,
128 MISCREG_DRBAR,
129 MISCREG_IRBAR,
130 MISCREG_DRSR,
131 MISCREG_IRSR,
132 MISCREG_DRACR,
133 MISCREG_IRACR,
134 MISCREG_RGNR,
135 MISCREG_BPIALLIS,
| 99 MISCREG_CP15_UNIMP_START,
100 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
101 MISCREG_TCMTR,
102 MISCREG_MPUIR,
103 MISCREG_MPIDR,
104 MISCREG_MIDR,
105 MISCREG_ID_PFR0,
106 MISCREG_ID_PFR1,
107 MISCREG_ID_DFR0,
108 MISCREG_ID_AFR0,
109 MISCREG_ID_MMFR0,
110 MISCREG_ID_MMFR1,
111 MISCREG_ID_MMFR2,
112 MISCREG_ID_MMFR3,
113 MISCREG_ID_ISAR0,
114 MISCREG_ID_ISAR1,
115 MISCREG_ID_ISAR2,
116 MISCREG_ID_ISAR3,
117 MISCREG_ID_ISAR4,
118 MISCREG_ID_ISAR5,
119 MISCREG_CCSIDR,
120 MISCREG_AIDR,
121 MISCREG_CSSELR,
122 MISCREG_ACTLR,
123 MISCREG_DFSR,
124 MISCREG_IFSR,
125 MISCREG_ADFSR,
126 MISCREG_AIFSR,
127 MISCREG_DFAR,
128 MISCREG_IFAR,
129 MISCREG_DRBAR,
130 MISCREG_IRBAR,
131 MISCREG_DRSR,
132 MISCREG_IRSR,
133 MISCREG_DRACR,
134 MISCREG_IRACR,
135 MISCREG_RGNR,
136 MISCREG_BPIALLIS,
|
136 MISCREG_ICIMVAU,
| |
137 MISCREG_BPIALL,
138 MISCREG_BPIMVA,
139 MISCREG_DCIMVAC,
140 MISCREG_DCISW,
141 MISCREG_DCCMVAC,
142 MISCREG_MCCSW,
143 MISCREG_DCCMVAU,
144
145 MISCREG_CP15_END,
146
147 // Dummy indices
148 MISCREG_NOP = MISCREG_CP15_END,
149 MISCREG_RAZ,
150
151 NUM_MISCREGS
152 };
153
154 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
155 unsigned crm, unsigned opc2);
156
157 const char * const miscRegName[NUM_MISCREGS] = {
158 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
159 "spsr_mon", "spsr_und", "spsr_abt",
160 "fpsr", "fpsid", "fpscr", "fpexc",
161 "sctlr", "dccisw", "dccimvac",
162 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
163 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr",
| 137 MISCREG_BPIALL,
138 MISCREG_BPIMVA,
139 MISCREG_DCIMVAC,
140 MISCREG_DCISW,
141 MISCREG_DCCMVAC,
142 MISCREG_MCCSW,
143 MISCREG_DCCMVAU,
144
145 MISCREG_CP15_END,
146
147 // Dummy indices
148 MISCREG_NOP = MISCREG_CP15_END,
149 MISCREG_RAZ,
150
151 NUM_MISCREGS
152 };
153
154 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
155 unsigned crm, unsigned opc2);
156
157 const char * const miscRegName[NUM_MISCREGS] = {
158 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
159 "spsr_mon", "spsr_und", "spsr_abt",
160 "fpsr", "fpsid", "fpscr", "fpexc",
161 "sctlr", "dccisw", "dccimvac",
162 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
163 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr",
|
164 "icialluis", "iciallu",
| 164 "icialluis", "iciallu", "icimvau",
|
165 "ctr", "tcmtr", "mpuir", "mpidr", "midr",
166 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
167 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
168 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
169 "ccsidr", "aidr", "csselr", "actlr",
170 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
171 "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
| 165 "ctr", "tcmtr", "mpuir", "mpidr", "midr",
166 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
167 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
168 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
169 "ccsidr", "aidr", "csselr", "actlr",
170 "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
171 "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
|
172 "rgnr", "bpiallis", "icimvau",
| 172 "rgnr", "bpiallis",
|
173 "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
174 "dccmvau",
175 "nop", "raz"
176 };
177
178 BitUnion32(CPSR)
179 Bitfield<31> n;
180 Bitfield<30> z;
181 Bitfield<29> c;
182 Bitfield<28> v;
183 Bitfield<27> q;
184 Bitfield<26,25> it1;
185 Bitfield<24> j;
186 Bitfield<19, 16> ge;
187 Bitfield<15,10> it2;
188 Bitfield<9> e;
189 Bitfield<8> a;
190 Bitfield<7> i;
191 Bitfield<6> f;
192 Bitfield<5> t;
193 Bitfield<4, 0> mode;
194 EndBitUnion(CPSR)
195
196 // This mask selects bits of the CPSR that actually go in the CondCodes
197 // integer register to allow renaming.
198 static const uint32_t CondCodesMask = 0xF80F0000;
199
200 // These otherwise unused bits of the PC are used to select a mode
201 // like the J and T bits of the CPSR.
202 static const Addr PcJBitShift = 33;
203 static const Addr PcTBitShift = 34;
204 static const Addr PcModeMask = (ULL(1) << PcJBitShift) |
205 (ULL(1) << PcTBitShift);
206
207 BitUnion32(SCTLR)
208 Bitfield<30> te; // Thumb Exception Enable
209 Bitfield<29> afe; // Access flag enable
210 Bitfield<28> tre; // TEX Remap bit
211 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
212 Bitfield<25> ee; // Exception Endianness bit
213 Bitfield<24> ve; // Interrupt vectors enable
214 Bitfield<23> rao1;// Read as one
215 Bitfield<22> u; // Alignment (now unused)
216 Bitfield<21> fi; // Fast interrupts configuration enable
217 Bitfield<18> rao2;// Read as one
218 Bitfield<17> ha; // Hardware access flag enable
219 Bitfield<16> rao3;// Read as one
220 Bitfield<14> rr; // Round robin cache replacement
221 Bitfield<13> v; // Base address for exception vectors
222 Bitfield<12> i; // instruction cache enable
223 Bitfield<11> z; // branch prediction enable bit
224 Bitfield<10> sw; // Enable swp/swpb
225 Bitfield<6,3> rao4;// Read as one
226 Bitfield<7> b; // Endianness support (unused)
227 Bitfield<2> c; // Cache enable bit
228 Bitfield<1> a; // Alignment fault checking
229 Bitfield<0> m; // MMU enable bit
230 EndBitUnion(SCTLR)
231};
232
233#endif // __ARCH_ARM_MISCREGS_HH__
| 173 "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
174 "dccmvau",
175 "nop", "raz"
176 };
177
178 BitUnion32(CPSR)
179 Bitfield<31> n;
180 Bitfield<30> z;
181 Bitfield<29> c;
182 Bitfield<28> v;
183 Bitfield<27> q;
184 Bitfield<26,25> it1;
185 Bitfield<24> j;
186 Bitfield<19, 16> ge;
187 Bitfield<15,10> it2;
188 Bitfield<9> e;
189 Bitfield<8> a;
190 Bitfield<7> i;
191 Bitfield<6> f;
192 Bitfield<5> t;
193 Bitfield<4, 0> mode;
194 EndBitUnion(CPSR)
195
196 // This mask selects bits of the CPSR that actually go in the CondCodes
197 // integer register to allow renaming.
198 static const uint32_t CondCodesMask = 0xF80F0000;
199
200 // These otherwise unused bits of the PC are used to select a mode
201 // like the J and T bits of the CPSR.
202 static const Addr PcJBitShift = 33;
203 static const Addr PcTBitShift = 34;
204 static const Addr PcModeMask = (ULL(1) << PcJBitShift) |
205 (ULL(1) << PcTBitShift);
206
207 BitUnion32(SCTLR)
208 Bitfield<30> te; // Thumb Exception Enable
209 Bitfield<29> afe; // Access flag enable
210 Bitfield<28> tre; // TEX Remap bit
211 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
212 Bitfield<25> ee; // Exception Endianness bit
213 Bitfield<24> ve; // Interrupt vectors enable
214 Bitfield<23> rao1;// Read as one
215 Bitfield<22> u; // Alignment (now unused)
216 Bitfield<21> fi; // Fast interrupts configuration enable
217 Bitfield<18> rao2;// Read as one
218 Bitfield<17> ha; // Hardware access flag enable
219 Bitfield<16> rao3;// Read as one
220 Bitfield<14> rr; // Round robin cache replacement
221 Bitfield<13> v; // Base address for exception vectors
222 Bitfield<12> i; // instruction cache enable
223 Bitfield<11> z; // branch prediction enable bit
224 Bitfield<10> sw; // Enable swp/swpb
225 Bitfield<6,3> rao4;// Read as one
226 Bitfield<7> b; // Endianness support (unused)
227 Bitfield<2> c; // Cache enable bit
228 Bitfield<1> a; // Alignment fault checking
229 Bitfield<0> m; // MMU enable bit
230 EndBitUnion(SCTLR)
231};
232
233#endif // __ARCH_ARM_MISCREGS_HH__
|