miscregs.hh (6750:33ac9df63f3e) miscregs.hh (7093:9832d4b070fc)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30#ifndef __ARCH_ARM_MISCREGS_HH__
31#define __ARCH_ARM_MISCREGS_HH__
32
33#include "base/bitunion.hh"
34
35namespace ArmISA
36{
37 enum ConditionCode {
38 COND_EQ = 0,
39 COND_NE, // 1
40 COND_CS, // 2
41 COND_CC, // 3
42 COND_MI, // 4
43 COND_PL, // 5
44 COND_VS, // 6
45 COND_VC, // 7
46 COND_HI, // 8
47 COND_LS, // 9
48 COND_GE, // 10
49 COND_LT, // 11
50 COND_GT, // 12
51 COND_LE, // 13
52 COND_AL, // 14
53 COND_NV // 15
54 };
55
56 enum MiscRegIndex {
57 MISCREG_CPSR = 0,
58 MISCREG_SPSR,
59 MISCREG_SPSR_FIQ,
60 MISCREG_SPSR_IRQ,
61 MISCREG_SPSR_SVC,
62 MISCREG_SPSR_MON,
63 MISCREG_SPSR_UND,
64 MISCREG_SPSR_ABT,
65 MISCREG_FPSR,
66 MISCREG_FPSID,
67 MISCREG_FPSCR,
68 MISCREG_FPEXC,
69 MISCREG_SCTLR,
70 NUM_MISCREGS
71 };
72
73 const char * const miscRegName[NUM_MISCREGS] = {
74 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und",
75 "spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "sctlr"
76 };
77
78 BitUnion32(CPSR)
79 Bitfield<31> n;
80 Bitfield<30> z;
81 Bitfield<29> c;
82 Bitfield<28> v;
83 Bitfield<27> q;
84 Bitfield<26,25> it1;
85 Bitfield<24> j;
86 Bitfield<19, 16> ge;
87 Bitfield<15,10> it2;
88 Bitfield<9> e;
89 Bitfield<8> a;
90 Bitfield<7> i;
91 Bitfield<6> f;
92 Bitfield<5> t;
93 Bitfield<4, 0> mode;
94 EndBitUnion(CPSR)
95
96 // This mask selects bits of the CPSR that actually go in the CondCodes
97 // integer register to allow renaming.
98 static const uint32_t CondCodesMask = 0xF80F0000;
99
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
46
47namespace ArmISA
48{
49 enum ConditionCode {
50 COND_EQ = 0,
51 COND_NE, // 1
52 COND_CS, // 2
53 COND_CC, // 3
54 COND_MI, // 4
55 COND_PL, // 5
56 COND_VS, // 6
57 COND_VC, // 7
58 COND_HI, // 8
59 COND_LS, // 9
60 COND_GE, // 10
61 COND_LT, // 11
62 COND_GT, // 12
63 COND_LE, // 13
64 COND_AL, // 14
65 COND_NV // 15
66 };
67
68 enum MiscRegIndex {
69 MISCREG_CPSR = 0,
70 MISCREG_SPSR,
71 MISCREG_SPSR_FIQ,
72 MISCREG_SPSR_IRQ,
73 MISCREG_SPSR_SVC,
74 MISCREG_SPSR_MON,
75 MISCREG_SPSR_UND,
76 MISCREG_SPSR_ABT,
77 MISCREG_FPSR,
78 MISCREG_FPSID,
79 MISCREG_FPSCR,
80 MISCREG_FPEXC,
81 MISCREG_SCTLR,
82 NUM_MISCREGS
83 };
84
85 const char * const miscRegName[NUM_MISCREGS] = {
86 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und",
87 "spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "sctlr"
88 };
89
90 BitUnion32(CPSR)
91 Bitfield<31> n;
92 Bitfield<30> z;
93 Bitfield<29> c;
94 Bitfield<28> v;
95 Bitfield<27> q;
96 Bitfield<26,25> it1;
97 Bitfield<24> j;
98 Bitfield<19, 16> ge;
99 Bitfield<15,10> it2;
100 Bitfield<9> e;
101 Bitfield<8> a;
102 Bitfield<7> i;
103 Bitfield<6> f;
104 Bitfield<5> t;
105 Bitfield<4, 0> mode;
106 EndBitUnion(CPSR)
107
108 // This mask selects bits of the CPSR that actually go in the CondCodes
109 // integer register to allow renaming.
110 static const uint32_t CondCodesMask = 0xF80F0000;
111
112 // These otherwise unused bits of the PC are used to select a mode
113 // like the J and T bits of the CPSR.
114 static const Addr PcJBitShift = 33;
115 static const Addr PcTBitShift = 34;
116 static const Addr PcModeMask = (ULL(1) << PcJBitShift) |
117 (ULL(1) << PcTBitShift);
118
100 BitUnion32(SCTLR)
101 Bitfield<30> te; // Thumb Exception Enable
102 Bitfield<29> afe; // Access flag enable
103 Bitfield<28> tre; // TEX Remap bit
104 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
105 Bitfield<25> ee; // Exception Endianness bit
106 Bitfield<24> ve; // Interrupt vectors enable
107 Bitfield<23> rao1;// Read as one
108 Bitfield<22> u; // Alignment (now unused)
109 Bitfield<21> fi; // Fast interrupts configuration enable
110 Bitfield<18> rao2;// Read as one
111 Bitfield<17> ha; // Hardware access flag enable
112 Bitfield<16> rao3;// Read as one
113 Bitfield<14> rr; // Round robin cache replacement
114 Bitfield<13> v; // Base address for exception vectors
115 Bitfield<12> i; // instruction cache enable
116 Bitfield<11> z; // branch prediction enable bit
117 Bitfield<10> sw; // Enable swp/swpb
118 Bitfield<6,3> rao4;// Read as one
119 Bitfield<7> b; // Endianness support (unused)
120 Bitfield<2> c; // Cache enable bit
121 Bitfield<1> a; // Alignment fault checking
122 Bitfield<0> m; // MMU enable bit
123 EndBitUnion(SCTLR)
124};
125
126#endif // __ARCH_ARM_MISCREGS_HH__
119 BitUnion32(SCTLR)
120 Bitfield<30> te; // Thumb Exception Enable
121 Bitfield<29> afe; // Access flag enable
122 Bitfield<28> tre; // TEX Remap bit
123 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
124 Bitfield<25> ee; // Exception Endianness bit
125 Bitfield<24> ve; // Interrupt vectors enable
126 Bitfield<23> rao1;// Read as one
127 Bitfield<22> u; // Alignment (now unused)
128 Bitfield<21> fi; // Fast interrupts configuration enable
129 Bitfield<18> rao2;// Read as one
130 Bitfield<17> ha; // Hardware access flag enable
131 Bitfield<16> rao3;// Read as one
132 Bitfield<14> rr; // Round robin cache replacement
133 Bitfield<13> v; // Base address for exception vectors
134 Bitfield<12> i; // instruction cache enable
135 Bitfield<11> z; // branch prediction enable bit
136 Bitfield<10> sw; // Enable swp/swpb
137 Bitfield<6,3> rao4;// Read as one
138 Bitfield<7> b; // Endianness support (unused)
139 Bitfield<2> c; // Cache enable bit
140 Bitfield<1> a; // Alignment fault checking
141 Bitfield<0> m; // MMU enable bit
142 EndBitUnion(SCTLR)
143};
144
145#endif // __ARCH_ARM_MISCREGS_HH__