miscregs.hh (8179:bbab80b639cb) | miscregs.hh (8205:7ecbffb674aa) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 53 unchanged lines hidden (view full) --- 62 COND_GT, // 12 63 COND_LE, // 13 64 COND_AL, // 14 65 COND_UC // 15 66 }; 67 68 enum MiscRegIndex { 69 MISCREG_CPSR = 0, | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 53 unchanged lines hidden (view full) --- 62 COND_GT, // 12 63 COND_LE, // 13 64 COND_AL, // 14 65 COND_UC // 15 66 }; 67 68 enum MiscRegIndex { 69 MISCREG_CPSR = 0, |
70 MISCREG_ITSTATE, | |
71 MISCREG_SPSR, 72 MISCREG_SPSR_FIQ, 73 MISCREG_SPSR_IRQ, 74 MISCREG_SPSR_SVC, 75 MISCREG_SPSR_MON, 76 MISCREG_SPSR_UND, 77 MISCREG_SPSR_ABT, 78 MISCREG_FPSR, --- 123 unchanged lines hidden (view full) --- 202 203 NUM_MISCREGS 204 }; 205 206 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 207 unsigned crm, unsigned opc2); 208 209 const char * const miscRegName[NUM_MISCREGS] = { | 70 MISCREG_SPSR, 71 MISCREG_SPSR_FIQ, 72 MISCREG_SPSR_IRQ, 73 MISCREG_SPSR_SVC, 74 MISCREG_SPSR_MON, 75 MISCREG_SPSR_UND, 76 MISCREG_SPSR_ABT, 77 MISCREG_FPSR, --- 123 unchanged lines hidden (view full) --- 201 202 NUM_MISCREGS 203 }; 204 205 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 206 unsigned crm, unsigned opc2); 207 208 const char * const miscRegName[NUM_MISCREGS] = { |
210 "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", | 209 "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", |
211 "spsr_mon", "spsr_und", "spsr_abt", 212 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", 213 "mvfr0", "mvfr1", 214 "sctlr_rst", "sev_mailbox", 215 "sctlr", "dccisw", "dccimvac", "dccmvac", 216 "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 217 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 218 "clidr", "ccsidr", "csselr", --- 40 unchanged lines hidden (view full) --- 259 Bitfield<9> e; 260 Bitfield<8> a; 261 Bitfield<7> i; 262 Bitfield<6> f; 263 Bitfield<5> t; 264 Bitfield<4, 0> mode; 265 EndBitUnion(CPSR) 266 | 210 "spsr_mon", "spsr_und", "spsr_abt", 211 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", 212 "mvfr0", "mvfr1", 213 "sctlr_rst", "sev_mailbox", 214 "sctlr", "dccisw", "dccimvac", "dccmvac", 215 "contextidr", "tpidrurw", "tpidruro", "tpidrprw", 216 "cp15isb", "cp15dsb", "cp15dmb", "cpacr", 217 "clidr", "ccsidr", "csselr", --- 40 unchanged lines hidden (view full) --- 258 Bitfield<9> e; 259 Bitfield<8> a; 260 Bitfield<7> i; 261 Bitfield<6> f; 262 Bitfield<5> t; 263 Bitfield<4, 0> mode; 264 EndBitUnion(CPSR) 265 |
267 BitUnion8(ITSTATE) 268 /* Note that the split (cond, mask) below is not as in ARM ARM. 269 * But it is more convenient for simulation. The condition 270 * is always the concatenation of the top 3 bits and the next bit, 271 * which applies when one of the bottom 4 bits is set. 272 * Refer to predecoder.cc for the use case. 273 */ 274 Bitfield<7, 4> cond; 275 Bitfield<3, 0> mask; 276 // Bitfields for moving to/from CPSR 277 Bitfield<7, 2> top6; 278 Bitfield<1, 0> bottom2; 279 EndBitUnion(ITSTATE) 280 | |
281 // This mask selects bits of the CPSR that actually go in the CondCodes 282 // integer register to allow renaming. 283 static const uint32_t CondCodesMask = 0xF80F0000; 284 285 BitUnion32(SCTLR) 286 Bitfield<31> ie; // Instruction endianness 287 Bitfield<30> te; // Thumb Exception Enable 288 Bitfield<29> afe; // Access flag enable --- 158 unchanged lines hidden --- | 266 // This mask selects bits of the CPSR that actually go in the CondCodes 267 // integer register to allow renaming. 268 static const uint32_t CondCodesMask = 0xF80F0000; 269 270 BitUnion32(SCTLR) 271 Bitfield<31> ie; // Instruction endianness 272 Bitfield<30> te; // Thumb Exception Enable 273 Bitfield<29> afe; // Access flag enable --- 158 unchanged lines hidden --- |