miscregs.hh (6750:33ac9df63f3e) | miscregs.hh (7093:9832d4b070fc) |
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1/* | 1/* |
2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
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2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright --- 82 unchanged lines hidden (view full) --- 92 Bitfield<5> t; 93 Bitfield<4, 0> mode; 94 EndBitUnion(CPSR) 95 96 // This mask selects bits of the CPSR that actually go in the CondCodes 97 // integer register to allow renaming. 98 static const uint32_t CondCodesMask = 0xF80F0000; 99 | 14 * Copyright (c) 2009 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 82 unchanged lines hidden (view full) --- 104 Bitfield<5> t; 105 Bitfield<4, 0> mode; 106 EndBitUnion(CPSR) 107 108 // This mask selects bits of the CPSR that actually go in the CondCodes 109 // integer register to allow renaming. 110 static const uint32_t CondCodesMask = 0xF80F0000; 111 |
112 // These otherwise unused bits of the PC are used to select a mode 113 // like the J and T bits of the CPSR. 114 static const Addr PcJBitShift = 33; 115 static const Addr PcTBitShift = 34; 116 static const Addr PcModeMask = (ULL(1) << PcJBitShift) | 117 (ULL(1) << PcTBitShift); 118 |
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100 BitUnion32(SCTLR) 101 Bitfield<30> te; // Thumb Exception Enable 102 Bitfield<29> afe; // Access flag enable 103 Bitfield<28> tre; // TEX Remap bit 104 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 105 Bitfield<25> ee; // Exception Endianness bit 106 Bitfield<24> ve; // Interrupt vectors enable 107 Bitfield<23> rao1;// Read as one --- 19 unchanged lines hidden --- | 119 BitUnion32(SCTLR) 120 Bitfield<30> te; // Thumb Exception Enable 121 Bitfield<29> afe; // Access flag enable 122 Bitfield<28> tre; // TEX Remap bit 123 Bitfield<27> nmfi;// Non-maskable fast interrupts enable 124 Bitfield<25> ee; // Exception Endianness bit 125 Bitfield<24> ve; // Interrupt vectors enable 126 Bitfield<23> rao1;// Read as one --- 19 unchanged lines hidden --- |