1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
--- 22 unchanged lines hidden (view full) ---
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
46#include "base/compiler.hh"
47
48namespace ArmISA
49{
50 enum ConditionCode {
51 COND_EQ = 0,
52 COND_NE, // 1
53 COND_CS, // 2
54 COND_CC, // 3
55 COND_MI, // 4
--- 6 unchanged lines hidden (view full) ---
62 COND_LT, // 11
63 COND_GT, // 12
64 COND_LE, // 13
65 COND_AL, // 14
66 COND_UC // 15
67 };
68
69 enum MiscRegIndex {
70 MISCREG_CPSR = 0,
71 MISCREG_CPSR_Q,
72 MISCREG_SPSR,
73 MISCREG_SPSR_FIQ,
74 MISCREG_SPSR_IRQ,
75 MISCREG_SPSR_SVC,
76 MISCREG_SPSR_MON,
77 MISCREG_SPSR_UND,
78 MISCREG_SPSR_ABT,
79 MISCREG_FPSR,
80 MISCREG_FPSID,
81 MISCREG_FPSCR,
82 MISCREG_FPSCR_QC, // Cumulative saturation flag
83 MISCREG_FPSCR_EXC, // Cumulative FP exception flags
84 MISCREG_FPEXC,
85 MISCREG_MVFR0,
86 MISCREG_MVFR1,
87 MISCREG_SCTLR_RST,
88 MISCREG_SEV_MAILBOX,
89
90 // CP14 registers
91 MISCREG_CP14_START,
92 MISCREG_DBGDIDR = MISCREG_CP14_START,
93 MISCREG_DBGDSCR_INT,
94 MISCREG_DBGDTRRX_INT,
95 MISCREG_DBGTRTX_INT,
96 MISCREG_DBGWFAR,
97 MISCREG_DBGVCR,
98 MISCREG_DBGECR,
99 MISCREG_DBGDSCCR,
100 MISCREG_DBGSMCR,
101 MISCREG_DBGDTRRX_EXT,
102 MISCREG_DBGDSCR_EXT,
103 MISCREG_DBGDTRTX_EXT,
104 MISCREG_DBGDRCR,
105 MISCREG_DBGBVR,
106 MISCREG_DBGBCR,
107 MISCREG_DBGBVR_M,
108 MISCREG_DBGBCR_M,
109 MISCREG_DBGDRAR,
110 MISCREG_DBGBXVR_M,
111 MISCREG_DBGOSLAR,
112 MISCREG_DBGOSSRR,
113 MISCREG_DBGOSDLR,
114 MISCREG_DBGPRCR,
115 MISCREG_DBGPRSR,
116 MISCREG_DBGDSAR,
117 MISCREG_DBGITCTRL,
118 MISCREG_DBGCLAIMSET,
119 MISCREG_DBGCLAIMCLR,
120 MISCREG_DBGAUTHSTATUS,
121 MISCREG_DBGDEVID2,
122 MISCREG_DBGDEVID1,
123 MISCREG_DBGDEVID,
124 MISCREG_TEEHBR,
125
126 // CP15 registers
127 MISCREG_CP15_START,
128 MISCREG_SCTLR = MISCREG_CP15_START,
129 MISCREG_DCCISW,
130 MISCREG_DCCIMVAC,
131 MISCREG_DCCMVAC,
132 MISCREG_CONTEXTIDR,
133 MISCREG_TPIDRURW,
134 MISCREG_TPIDRURO,
135 MISCREG_TPIDRPRW,
136 MISCREG_CP15ISB,
137 MISCREG_CP15DSB,
138 MISCREG_CP15DMB,
139 MISCREG_CPACR,
140 MISCREG_CLIDR,
141 MISCREG_CCSIDR,
142 MISCREG_CSSELR,
143 MISCREG_ICIALLUIS,
144 MISCREG_ICIALLU,
145 MISCREG_ICIMVAU,
146 MISCREG_BPIMVA,
147 MISCREG_BPIALLIS,
148 MISCREG_BPIALL,
149 MISCREG_MIDR,
150 MISCREG_TTBR0,
151 MISCREG_TTBR1,
152 MISCREG_TLBTR,
153 MISCREG_DACR,
154 MISCREG_TLBIALLIS,
155 MISCREG_TLBIMVAIS,
156 MISCREG_TLBIASIDIS,
157 MISCREG_TLBIMVAAIS,
158 MISCREG_ITLBIALL,
159 MISCREG_ITLBIMVA,
160 MISCREG_ITLBIASID,
161 MISCREG_DTLBIALL,
162 MISCREG_DTLBIMVA,
163 MISCREG_DTLBIASID,
164 MISCREG_TLBIALL,
165 MISCREG_TLBIMVA,
166 MISCREG_TLBIASID,
167 MISCREG_TLBIMVAA,
168 MISCREG_DFSR,
169 MISCREG_IFSR,
170 MISCREG_DFAR,
171 MISCREG_IFAR,
172 MISCREG_MPIDR,
173 MISCREG_PRRR,
174 MISCREG_NMRR,
175 MISCREG_TTBCR,
176 MISCREG_ID_PFR0,
177 MISCREG_CTR,
178 MISCREG_SCR,
179 MISCREG_SDER,
180 MISCREG_PAR,
181 MISCREG_V2PCWPR,
182 MISCREG_V2PCWPW,
183 MISCREG_V2PCWUR,
184 MISCREG_V2PCWUW,
185 MISCREG_V2POWPR,
186 MISCREG_V2POWPW,
187 MISCREG_V2POWUR,
188 MISCREG_V2POWUW,
189 MISCREG_ID_MMFR0,
190 MISCREG_ID_MMFR2,
191 MISCREG_ID_MMFR3,
192 MISCREG_ACTLR,
193 MISCREG_PMCR,
194 MISCREG_PMCCNTR,
195 MISCREG_PMCNTENSET,
196 MISCREG_PMCNTENCLR,
197 MISCREG_PMOVSR,
198 MISCREG_PMSWINC,
199 MISCREG_PMSELR,
200 MISCREG_PMCEID0,
201 MISCREG_PMCEID1,
202 MISCREG_PMC_OTHER,
203 MISCREG_PMXEVCNTR,
204 MISCREG_PMUSERENR,
205 MISCREG_PMINTENSET,
206 MISCREG_PMINTENCLR,
207 MISCREG_ID_ISAR0,
208 MISCREG_ID_ISAR1,
209 MISCREG_ID_ISAR2,
210 MISCREG_ID_ISAR3,
211 MISCREG_ID_ISAR4,
212 MISCREG_ID_ISAR5,
213 MISCREG_LOCKFLAG,
214 MISCREG_LOCKADDR,
215 MISCREG_ID_PFR1,
216 MISCREG_L2CTLR,
217 MISCREG_CP15_UNIMP_START,
218 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
219 MISCREG_ID_DFR0,
220 MISCREG_ID_AFR0,
221 MISCREG_ID_MMFR1,
222 MISCREG_AIDR,
223 MISCREG_ADFSR,
224 MISCREG_AIFSR,
225 MISCREG_DCIMVAC,
226 MISCREG_DCISW,
227 MISCREG_MCCSW,
228 MISCREG_DCCMVAU,
229 MISCREG_NSACR,
230 MISCREG_VBAR,
231 MISCREG_MVBAR,
232 MISCREG_ISR,
233 MISCREG_FCEIDR,
234 MISCREG_L2LATENCY,
235 MISCREG_CRN15,
236
237
238 MISCREG_CP15_END,
239
240 // Dummy indices
241 MISCREG_NOP = MISCREG_CP15_END,
242 MISCREG_RAZ,
243
244 NUM_MISCREGS
245 };
246
247 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
248 unsigned crm, unsigned opc2);
249
250 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
251 unsigned crm, unsigned opc2);
252
253
254 const char * const miscRegName[] = {
255 "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
256 "spsr_mon", "spsr_und", "spsr_abt",
257 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc",
258 "mvfr0", "mvfr1",
259 "sctlr_rst", "sev_mailbox",
260 "DBGDIDR",
261 "DBGDSCR_INT",
262 "DBGDTRRX_INT",
263 "DBGTRTX_INT",
264 "DBGWFAR",
265 "DBGVCR",
266 "DBGECR",
267 "DBGDSCCR",
268 "DBGSMCR",
269 "DBGDTRRX_EXT",
270 "DBGDSCR_EXT",
271 "DBGDTRTX_EXT",
272 "DBGDRCR",
273 "DBGBVR",
274 "DBGBCR",
275 "DBGBVR_M",
276 "DBGBCR_M",
277 "DBGDRAR",
278 "DBGBXVR_M",
279 "DBGOSLAR",
280 "DBGOSSRR",
281 "DBGOSDLR",
282 "DBGPRCR",
283 "DBGPRSR",
284 "DBGDSAR",
285 "DBGITCTRL",
286 "DBGCLAIMSET",
287 "DBGCLAIMCLR",
288 "DBGAUTHSTATUS",
289 "DBGDEVID2",
290 "DBGDEVID1",
291 "DBGDEVID",
292 "TEEHBR",
293 "sctlr", "dccisw", "dccimvac", "dccmvac",
294 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
295 "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
296 "clidr", "ccsidr", "csselr",
297 "icialluis", "iciallu", "icimvau",
298 "bpimva", "bpiallis", "bpiall",
299 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
300 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
301 "itlbiall", "itlbimva", "itlbiasid",
302 "dtlbiall", "dtlbimva", "dtlbiasid",
303 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
304 "dfsr", "ifsr", "dfar", "ifar", "mpidr",
305 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr",
306 "scr", "sder", "par",
307 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
308 "v2powpr", "v2powpw", "v2powur", "v2powuw",
309 "id_mmfr0", "id_mmfr2", "id_mmfr3", "actlr", "pmcr", "pmccntr",
310 "pmcntenset", "pmcntenclr", "pmovsr",
311 "pmswinc", "pmselr", "pmceid0",
312 "pmceid1", "pmc_other", "pmxevcntr",
313 "pmuserenr", "pmintenset", "pmintenclr",
314 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
315 "lockflag", "lockaddr", "id_pfr1",
316 "l2ctlr",
317 // Unimplemented below
318 "tcmtr",
319 "id_dfr0", "id_afr0",
320 "id_mmfr1",
321 "aidr", "adfsr", "aifsr",
322 "dcimvac", "dcisw", "mccsw",
323 "dccmvau",
324 "nsacr",
325 "vbar", "mvbar", "isr", "fceidr", "l2latency",
326 "crn15",
327 "nop", "raz"
328 };
329
330 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
331 "The miscRegName array and NUM_MISCREGS are inconsistent.");
332
333 BitUnion32(CPSR)
334 Bitfield<31,30> nz;
335 Bitfield<29> c;
336 Bitfield<28> v;
337 Bitfield<27> q;
338 Bitfield<26,25> it1;
339 Bitfield<24> j;
340 Bitfield<19, 16> ge;
341 Bitfield<15,10> it2;
342 Bitfield<9> e;
343 Bitfield<8> a;
344 Bitfield<7> i;
345 Bitfield<6> f;
346 Bitfield<5> t;
347 Bitfield<4, 0> mode;
348 EndBitUnion(CPSR)
349
350 // This mask selects bits of the CPSR that actually go in the CondCodes
351 // integer register to allow renaming.
352 static const uint32_t CondCodesMask = 0xF00F0000;
353 static const uint32_t CpsrMaskQ = 0x08000000;
354
355 BitUnion32(SCTLR)
356 Bitfield<31> ie; // Instruction endianness
357 Bitfield<30> te; // Thumb Exception Enable
358 Bitfield<29> afe; // Access flag enable
359 Bitfield<28> tre; // TEX Remap bit
360 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
361 Bitfield<25> ee; // Exception Endianness bit
362 Bitfield<24> ve; // Interrupt vectors enable
363 Bitfield<23> xp; // Extended page table enable bit
364 Bitfield<22> u; // Alignment (now unused)
365 Bitfield<21> fi; // Fast interrupts configuration enable
366 Bitfield<19> dz; // Divide by Zero fault enable bit
367 Bitfield<18> rao2;// Read as one
368 Bitfield<17> br; // Background region bit
369 Bitfield<16> rao3;// Read as one
370 Bitfield<14> rr; // Round robin cache replacement
371 Bitfield<13> v; // Base address for exception vectors
372 Bitfield<12> i; // instruction cache enable
373 Bitfield<11> z; // branch prediction enable bit
374 Bitfield<10> sw; // Enable swp/swpb
375 Bitfield<9,8> rs; // deprecated protection bits
376 Bitfield<6,3> rao4;// Read as one
377 Bitfield<7> b; // Endianness support (unused)
378 Bitfield<2> c; // Cache enable bit
379 Bitfield<1> a; // Alignment fault checking
380 Bitfield<0> m; // MMU enable bit
381 EndBitUnion(SCTLR)
382
383 BitUnion32(CPACR)
384 Bitfield<1, 0> cp0;
385 Bitfield<3, 2> cp1;
386 Bitfield<5, 4> cp2;
387 Bitfield<7, 6> cp3;
388 Bitfield<9, 8> cp4;
389 Bitfield<11, 10> cp5;
390 Bitfield<13, 12> cp6;
391 Bitfield<15, 14> cp7;
392 Bitfield<17, 16> cp8;
393 Bitfield<19, 18> cp9;
394 Bitfield<21, 20> cp10;
395 Bitfield<23, 22> cp11;
396 Bitfield<25, 24> cp12;
397 Bitfield<27, 26> cp13;
398 Bitfield<29, 28> rsvd;
399 Bitfield<30> d32dis;
400 Bitfield<31> asedis;
401 EndBitUnion(CPACR)
402
403 BitUnion32(FSR)
404 Bitfield<3, 0> fsLow;
405 Bitfield<7, 4> domain;
406 Bitfield<10> fsHigh;
407 Bitfield<11> wnr;
408 Bitfield<12> ext;
409 EndBitUnion(FSR)
410
411 BitUnion32(FPSCR)
412 Bitfield<0> ioc;
413 Bitfield<1> dzc;
414 Bitfield<2> ofc;
415 Bitfield<3> ufc;
416 Bitfield<4> ixc;
--- 48 unchanged lines hidden (view full) ---
465 Bitfield<11, 8> advSimdLoadStore;
466 Bitfield<15, 12> advSimdInteger;
467 Bitfield<19, 16> advSimdSinglePrecision;
468 Bitfield<23, 20> advSimdHalfPrecision;
469 Bitfield<27, 24> vfpHalfPrecision;
470 Bitfield<31, 28> raz;
471 EndBitUnion(MVFR1)
472
473 BitUnion32(PRRR)
474 Bitfield<1,0> tr0;
475 Bitfield<3,2> tr1;
476 Bitfield<5,4> tr2;
477 Bitfield<7,6> tr3;
478 Bitfield<9,8> tr4;
479 Bitfield<11,10> tr5;
480 Bitfield<13,12> tr6;
--- 58 unchanged lines hidden (view full) ---
539 Bitfield<13,4> raz_13_4;
540 Bitfield<15,14> l1IndexPolicy;
541 Bitfield<19,16> dCacheLineSize;
542 Bitfield<23,20> erg;
543 Bitfield<27,24> cwg;
544 Bitfield<28> raz_28;
545 Bitfield<31,29> format;
546 EndBitUnion(CTR)
547}
548
549#endif // __ARCH_ARM_MISCREGS_HH__
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
--- 22 unchanged lines hidden (view full) ---
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42#ifndef __ARCH_ARM_MISCREGS_HH__
43#define __ARCH_ARM_MISCREGS_HH__
44
45#include "base/bitunion.hh"
46#include "base/compiler.hh"
47
48namespace ArmISA
49{
50 enum ConditionCode {
51 COND_EQ = 0,
52 COND_NE, // 1
53 COND_CS, // 2
54 COND_CC, // 3
55 COND_MI, // 4
--- 6 unchanged lines hidden (view full) ---
62 COND_LT, // 11
63 COND_GT, // 12
64 COND_LE, // 13
65 COND_AL, // 14
66 COND_UC // 15
67 };
68
69 enum MiscRegIndex {
70 MISCREG_CPSR = 0,
71 MISCREG_CPSR_Q,
72 MISCREG_SPSR,
73 MISCREG_SPSR_FIQ,
74 MISCREG_SPSR_IRQ,
75 MISCREG_SPSR_SVC,
76 MISCREG_SPSR_MON,
77 MISCREG_SPSR_UND,
78 MISCREG_SPSR_ABT,
79 MISCREG_FPSR,
80 MISCREG_FPSID,
81 MISCREG_FPSCR,
82 MISCREG_FPSCR_QC, // Cumulative saturation flag
83 MISCREG_FPSCR_EXC, // Cumulative FP exception flags
84 MISCREG_FPEXC,
85 MISCREG_MVFR0,
86 MISCREG_MVFR1,
87 MISCREG_SCTLR_RST,
88 MISCREG_SEV_MAILBOX,
89
90 // CP14 registers
91 MISCREG_CP14_START,
92 MISCREG_DBGDIDR = MISCREG_CP14_START,
93 MISCREG_DBGDSCR_INT,
94 MISCREG_DBGDTRRX_INT,
95 MISCREG_DBGTRTX_INT,
96 MISCREG_DBGWFAR,
97 MISCREG_DBGVCR,
98 MISCREG_DBGECR,
99 MISCREG_DBGDSCCR,
100 MISCREG_DBGSMCR,
101 MISCREG_DBGDTRRX_EXT,
102 MISCREG_DBGDSCR_EXT,
103 MISCREG_DBGDTRTX_EXT,
104 MISCREG_DBGDRCR,
105 MISCREG_DBGBVR,
106 MISCREG_DBGBCR,
107 MISCREG_DBGBVR_M,
108 MISCREG_DBGBCR_M,
109 MISCREG_DBGDRAR,
110 MISCREG_DBGBXVR_M,
111 MISCREG_DBGOSLAR,
112 MISCREG_DBGOSSRR,
113 MISCREG_DBGOSDLR,
114 MISCREG_DBGPRCR,
115 MISCREG_DBGPRSR,
116 MISCREG_DBGDSAR,
117 MISCREG_DBGITCTRL,
118 MISCREG_DBGCLAIMSET,
119 MISCREG_DBGCLAIMCLR,
120 MISCREG_DBGAUTHSTATUS,
121 MISCREG_DBGDEVID2,
122 MISCREG_DBGDEVID1,
123 MISCREG_DBGDEVID,
124 MISCREG_TEEHBR,
125
126 // CP15 registers
127 MISCREG_CP15_START,
128 MISCREG_SCTLR = MISCREG_CP15_START,
129 MISCREG_DCCISW,
130 MISCREG_DCCIMVAC,
131 MISCREG_DCCMVAC,
132 MISCREG_CONTEXTIDR,
133 MISCREG_TPIDRURW,
134 MISCREG_TPIDRURO,
135 MISCREG_TPIDRPRW,
136 MISCREG_CP15ISB,
137 MISCREG_CP15DSB,
138 MISCREG_CP15DMB,
139 MISCREG_CPACR,
140 MISCREG_CLIDR,
141 MISCREG_CCSIDR,
142 MISCREG_CSSELR,
143 MISCREG_ICIALLUIS,
144 MISCREG_ICIALLU,
145 MISCREG_ICIMVAU,
146 MISCREG_BPIMVA,
147 MISCREG_BPIALLIS,
148 MISCREG_BPIALL,
149 MISCREG_MIDR,
150 MISCREG_TTBR0,
151 MISCREG_TTBR1,
152 MISCREG_TLBTR,
153 MISCREG_DACR,
154 MISCREG_TLBIALLIS,
155 MISCREG_TLBIMVAIS,
156 MISCREG_TLBIASIDIS,
157 MISCREG_TLBIMVAAIS,
158 MISCREG_ITLBIALL,
159 MISCREG_ITLBIMVA,
160 MISCREG_ITLBIASID,
161 MISCREG_DTLBIALL,
162 MISCREG_DTLBIMVA,
163 MISCREG_DTLBIASID,
164 MISCREG_TLBIALL,
165 MISCREG_TLBIMVA,
166 MISCREG_TLBIASID,
167 MISCREG_TLBIMVAA,
168 MISCREG_DFSR,
169 MISCREG_IFSR,
170 MISCREG_DFAR,
171 MISCREG_IFAR,
172 MISCREG_MPIDR,
173 MISCREG_PRRR,
174 MISCREG_NMRR,
175 MISCREG_TTBCR,
176 MISCREG_ID_PFR0,
177 MISCREG_CTR,
178 MISCREG_SCR,
179 MISCREG_SDER,
180 MISCREG_PAR,
181 MISCREG_V2PCWPR,
182 MISCREG_V2PCWPW,
183 MISCREG_V2PCWUR,
184 MISCREG_V2PCWUW,
185 MISCREG_V2POWPR,
186 MISCREG_V2POWPW,
187 MISCREG_V2POWUR,
188 MISCREG_V2POWUW,
189 MISCREG_ID_MMFR0,
190 MISCREG_ID_MMFR2,
191 MISCREG_ID_MMFR3,
192 MISCREG_ACTLR,
193 MISCREG_PMCR,
194 MISCREG_PMCCNTR,
195 MISCREG_PMCNTENSET,
196 MISCREG_PMCNTENCLR,
197 MISCREG_PMOVSR,
198 MISCREG_PMSWINC,
199 MISCREG_PMSELR,
200 MISCREG_PMCEID0,
201 MISCREG_PMCEID1,
202 MISCREG_PMC_OTHER,
203 MISCREG_PMXEVCNTR,
204 MISCREG_PMUSERENR,
205 MISCREG_PMINTENSET,
206 MISCREG_PMINTENCLR,
207 MISCREG_ID_ISAR0,
208 MISCREG_ID_ISAR1,
209 MISCREG_ID_ISAR2,
210 MISCREG_ID_ISAR3,
211 MISCREG_ID_ISAR4,
212 MISCREG_ID_ISAR5,
213 MISCREG_LOCKFLAG,
214 MISCREG_LOCKADDR,
215 MISCREG_ID_PFR1,
216 MISCREG_L2CTLR,
217 MISCREG_CP15_UNIMP_START,
218 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
219 MISCREG_ID_DFR0,
220 MISCREG_ID_AFR0,
221 MISCREG_ID_MMFR1,
222 MISCREG_AIDR,
223 MISCREG_ADFSR,
224 MISCREG_AIFSR,
225 MISCREG_DCIMVAC,
226 MISCREG_DCISW,
227 MISCREG_MCCSW,
228 MISCREG_DCCMVAU,
229 MISCREG_NSACR,
230 MISCREG_VBAR,
231 MISCREG_MVBAR,
232 MISCREG_ISR,
233 MISCREG_FCEIDR,
234 MISCREG_L2LATENCY,
235 MISCREG_CRN15,
236
237
238 MISCREG_CP15_END,
239
240 // Dummy indices
241 MISCREG_NOP = MISCREG_CP15_END,
242 MISCREG_RAZ,
243
244 NUM_MISCREGS
245 };
246
247 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
248 unsigned crm, unsigned opc2);
249
250 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
251 unsigned crm, unsigned opc2);
252
253
254 const char * const miscRegName[] = {
255 "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
256 "spsr_mon", "spsr_und", "spsr_abt",
257 "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc",
258 "mvfr0", "mvfr1",
259 "sctlr_rst", "sev_mailbox",
260 "DBGDIDR",
261 "DBGDSCR_INT",
262 "DBGDTRRX_INT",
263 "DBGTRTX_INT",
264 "DBGWFAR",
265 "DBGVCR",
266 "DBGECR",
267 "DBGDSCCR",
268 "DBGSMCR",
269 "DBGDTRRX_EXT",
270 "DBGDSCR_EXT",
271 "DBGDTRTX_EXT",
272 "DBGDRCR",
273 "DBGBVR",
274 "DBGBCR",
275 "DBGBVR_M",
276 "DBGBCR_M",
277 "DBGDRAR",
278 "DBGBXVR_M",
279 "DBGOSLAR",
280 "DBGOSSRR",
281 "DBGOSDLR",
282 "DBGPRCR",
283 "DBGPRSR",
284 "DBGDSAR",
285 "DBGITCTRL",
286 "DBGCLAIMSET",
287 "DBGCLAIMCLR",
288 "DBGAUTHSTATUS",
289 "DBGDEVID2",
290 "DBGDEVID1",
291 "DBGDEVID",
292 "TEEHBR",
293 "sctlr", "dccisw", "dccimvac", "dccmvac",
294 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
295 "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
296 "clidr", "ccsidr", "csselr",
297 "icialluis", "iciallu", "icimvau",
298 "bpimva", "bpiallis", "bpiall",
299 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
300 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
301 "itlbiall", "itlbimva", "itlbiasid",
302 "dtlbiall", "dtlbimva", "dtlbiasid",
303 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
304 "dfsr", "ifsr", "dfar", "ifar", "mpidr",
305 "prrr", "nmrr", "ttbcr", "id_pfr0", "ctr",
306 "scr", "sder", "par",
307 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
308 "v2powpr", "v2powpw", "v2powur", "v2powuw",
309 "id_mmfr0", "id_mmfr2", "id_mmfr3", "actlr", "pmcr", "pmccntr",
310 "pmcntenset", "pmcntenclr", "pmovsr",
311 "pmswinc", "pmselr", "pmceid0",
312 "pmceid1", "pmc_other", "pmxevcntr",
313 "pmuserenr", "pmintenset", "pmintenclr",
314 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
315 "lockflag", "lockaddr", "id_pfr1",
316 "l2ctlr",
317 // Unimplemented below
318 "tcmtr",
319 "id_dfr0", "id_afr0",
320 "id_mmfr1",
321 "aidr", "adfsr", "aifsr",
322 "dcimvac", "dcisw", "mccsw",
323 "dccmvau",
324 "nsacr",
325 "vbar", "mvbar", "isr", "fceidr", "l2latency",
326 "crn15",
327 "nop", "raz"
328 };
329
330 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
331 "The miscRegName array and NUM_MISCREGS are inconsistent.");
332
333 BitUnion32(CPSR)
334 Bitfield<31,30> nz;
335 Bitfield<29> c;
336 Bitfield<28> v;
337 Bitfield<27> q;
338 Bitfield<26,25> it1;
339 Bitfield<24> j;
340 Bitfield<19, 16> ge;
341 Bitfield<15,10> it2;
342 Bitfield<9> e;
343 Bitfield<8> a;
344 Bitfield<7> i;
345 Bitfield<6> f;
346 Bitfield<5> t;
347 Bitfield<4, 0> mode;
348 EndBitUnion(CPSR)
349
350 // This mask selects bits of the CPSR that actually go in the CondCodes
351 // integer register to allow renaming.
352 static const uint32_t CondCodesMask = 0xF00F0000;
353 static const uint32_t CpsrMaskQ = 0x08000000;
354
355 BitUnion32(SCTLR)
356 Bitfield<31> ie; // Instruction endianness
357 Bitfield<30> te; // Thumb Exception Enable
358 Bitfield<29> afe; // Access flag enable
359 Bitfield<28> tre; // TEX Remap bit
360 Bitfield<27> nmfi;// Non-maskable fast interrupts enable
361 Bitfield<25> ee; // Exception Endianness bit
362 Bitfield<24> ve; // Interrupt vectors enable
363 Bitfield<23> xp; // Extended page table enable bit
364 Bitfield<22> u; // Alignment (now unused)
365 Bitfield<21> fi; // Fast interrupts configuration enable
366 Bitfield<19> dz; // Divide by Zero fault enable bit
367 Bitfield<18> rao2;// Read as one
368 Bitfield<17> br; // Background region bit
369 Bitfield<16> rao3;// Read as one
370 Bitfield<14> rr; // Round robin cache replacement
371 Bitfield<13> v; // Base address for exception vectors
372 Bitfield<12> i; // instruction cache enable
373 Bitfield<11> z; // branch prediction enable bit
374 Bitfield<10> sw; // Enable swp/swpb
375 Bitfield<9,8> rs; // deprecated protection bits
376 Bitfield<6,3> rao4;// Read as one
377 Bitfield<7> b; // Endianness support (unused)
378 Bitfield<2> c; // Cache enable bit
379 Bitfield<1> a; // Alignment fault checking
380 Bitfield<0> m; // MMU enable bit
381 EndBitUnion(SCTLR)
382
383 BitUnion32(CPACR)
384 Bitfield<1, 0> cp0;
385 Bitfield<3, 2> cp1;
386 Bitfield<5, 4> cp2;
387 Bitfield<7, 6> cp3;
388 Bitfield<9, 8> cp4;
389 Bitfield<11, 10> cp5;
390 Bitfield<13, 12> cp6;
391 Bitfield<15, 14> cp7;
392 Bitfield<17, 16> cp8;
393 Bitfield<19, 18> cp9;
394 Bitfield<21, 20> cp10;
395 Bitfield<23, 22> cp11;
396 Bitfield<25, 24> cp12;
397 Bitfield<27, 26> cp13;
398 Bitfield<29, 28> rsvd;
399 Bitfield<30> d32dis;
400 Bitfield<31> asedis;
401 EndBitUnion(CPACR)
402
403 BitUnion32(FSR)
404 Bitfield<3, 0> fsLow;
405 Bitfield<7, 4> domain;
406 Bitfield<10> fsHigh;
407 Bitfield<11> wnr;
408 Bitfield<12> ext;
409 EndBitUnion(FSR)
410
411 BitUnion32(FPSCR)
412 Bitfield<0> ioc;
413 Bitfield<1> dzc;
414 Bitfield<2> ofc;
415 Bitfield<3> ufc;
416 Bitfield<4> ixc;
--- 48 unchanged lines hidden (view full) ---
465 Bitfield<11, 8> advSimdLoadStore;
466 Bitfield<15, 12> advSimdInteger;
467 Bitfield<19, 16> advSimdSinglePrecision;
468 Bitfield<23, 20> advSimdHalfPrecision;
469 Bitfield<27, 24> vfpHalfPrecision;
470 Bitfield<31, 28> raz;
471 EndBitUnion(MVFR1)
472
473 BitUnion32(PRRR)
474 Bitfield<1,0> tr0;
475 Bitfield<3,2> tr1;
476 Bitfield<5,4> tr2;
477 Bitfield<7,6> tr3;
478 Bitfield<9,8> tr4;
479 Bitfield<11,10> tr5;
480 Bitfield<13,12> tr6;
--- 58 unchanged lines hidden (view full) ---
539 Bitfield<13,4> raz_13_4;
540 Bitfield<15,14> l1IndexPolicy;
541 Bitfield<19,16> dCacheLineSize;
542 Bitfield<23,20> erg;
543 Bitfield<27,24> cwg;
544 Bitfield<28> raz_28;
545 Bitfield<31,29> format;
546 EndBitUnion(CTR)
547}
548
549#endif // __ARCH_ARM_MISCREGS_HH__