1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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73 MISCREG_SPSR_IRQ,
74 MISCREG_SPSR_SVC,
75 MISCREG_SPSR_MON,
76 MISCREG_SPSR_UND,
77 MISCREG_SPSR_ABT,
78 MISCREG_FPSR,
79 MISCREG_FPSID,
80 MISCREG_FPSCR,
81 MISCREG_FPEXC,
82 MISCREG_MVFR0,
83 MISCREG_MVFR1,
84 MISCREG_SCTLR_RST,
85 MISCREG_SEV_MAILBOX,
86
87 // CP15 registers
88 MISCREG_CP15_START,

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201 };
202
203 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
204 unsigned crm, unsigned opc2);
205
206 const char * const miscRegName[NUM_MISCREGS] = {
207 "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
208 "spsr_mon", "spsr_und", "spsr_abt",
209 "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
210 "sctlr_rst", "sev_mailbox",
211 "sctlr", "dccisw", "dccimvac", "dccmvac",
212 "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
213 "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
214 "clidr", "ccsidr", "csselr",
215 "icialluis", "iciallu", "icimvau",
216 "bpimva", "bpiallis", "bpiall",
217 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",

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357 Bitfield<28> v;
358 Bitfield<29> c;
359 Bitfield<30> z;
360 Bitfield<31> n;
361 EndBitUnion(FPSCR)
362
363 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
364 // integer register to allow renaming.
365 static const uint32_t FpCondCodesMask = 0xF800009F;
366
367 BitUnion32(FPEXC)
368 Bitfield<31> ex;
369 Bitfield<30> en;
370 Bitfield<29, 0> subArchDefined;
371 EndBitUnion(FPEXC)
372
373 BitUnion32(MVFR0)

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