1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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125 MISCREG_TLBIMVA,
126 MISCREG_TLBIASID,
127 MISCREG_TLBIMVAA,
128 MISCREG_DFSR,
129 MISCREG_IFSR,
130 MISCREG_DFAR,
131 MISCREG_IFAR,
132 MISCREG_MPIDR,
133 MISCREG_CP15_UNIMP_START,
134 MISCREG_CTR = MISCREG_CP15_UNIMP_START,
135 MISCREG_TCMTR,
136 MISCREG_ID_PFR0,
137 MISCREG_ID_PFR1,
138 MISCREG_ID_DFR0,
139 MISCREG_ID_AFR0,
140 MISCREG_ID_MMFR0,
141 MISCREG_ID_MMFR1,
142 MISCREG_ID_MMFR2,
143 MISCREG_ID_MMFR3,
144 MISCREG_ID_ISAR0,

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154 MISCREG_AIFSR,
155 MISCREG_DCIMVAC,
156 MISCREG_DCISW,
157 MISCREG_MCCSW,
158 MISCREG_DCCMVAU,
159 MISCREG_SCR,
160 MISCREG_SDER,
161 MISCREG_NSACR,
162 MISCREG_TTBCR,
163 MISCREG_V2PCWPR,
164 MISCREG_V2PCWPW,
165 MISCREG_V2PCWUR,
166 MISCREG_V2PCWUW,
167 MISCREG_V2POWPR,
168 MISCREG_V2POWPW,
169 MISCREG_V2POWUR,
170 MISCREG_V2POWUW,
171 MISCREG_PRRR,
172 MISCREG_NMRR,
173 MISCREG_VBAR,
174 MISCREG_MVBAR,
175 MISCREG_ISR,
176 MISCREG_FCEIDR,
177
178
179 MISCREG_CP15_END,
180

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200 "icialluis", "iciallu", "icimvau",
201 "bpimva", "bpiallis", "bpiall",
202 "midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
203 "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
204 "itlbiall", "itlbimva", "itlbiasid",
205 "dtlbiall", "dtlbimva", "dtlbiasid",
206 "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
207 "dfsr", "ifsr", "dfar", "ifar", "mpidr",
208 "ctr", "tcmtr",
209 "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
210 "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
211 "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
212 "par", "aidr", "actlr",
213 "adfsr", "aifsr",
214 "dcimvac", "dcisw", "mccsw",
215 "dccmvau",
216 "scr", "sder", "nsacr", "ttbcr",
217 "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
218 "v2powpr", "v2powpw", "v2powur", "v2powuw",
219 "prrr", "nmrr", "vbar", "mvbar", "isr", "fceidr",
220 "nop", "raz"
221 };
222
223 BitUnion32(CPSR)
224 Bitfield<31> n;
225 Bitfield<30> z;
226 Bitfield<29> c;
227 Bitfield<28> v;

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338 Bitfield<7, 4> defaultNaN;
339 Bitfield<11, 8> advSimdLoadStore;
340 Bitfield<15, 12> advSimdInteger;
341 Bitfield<19, 16> advSimdSinglePrecision;
342 Bitfield<23, 20> advSimdHalfPrecision;
343 Bitfield<27, 24> vfpHalfPrecision;
344 Bitfield<31, 28> raz;
345 EndBitUnion(MVFR1)
346};
347
348#endif // __ARCH_ARM_MISCREGS_HH__