1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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668
669 // Introduced in ARMv8.1
670 MISCREG_TTBR1_EL2,
671 MISCREG_CNTHV_CTL_EL2,
672 MISCREG_CNTHV_CVAL_EL2,
673 MISCREG_CNTHV_TVAL_EL2,
674
675 MISCREG_ID_AA64MMFR2_EL1,
676 // These MISCREG_FREESLOT are available Misc Register
677 // slots for future registers to be implemented.
678 MISCREG_FREESLOT_1,
679
680 // NUM_PHYS_MISCREGS specifies the number of actual physical
681 // registers, not considering the following pseudo-registers
682 // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
683 // Checkpointing should use this physical index when

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1384 "cbar_el1",
1385 "contextidr_el2",
1386
1387 "ttbr1_el2",
1388 "cnthv_ctl_el2",
1389 "cnthv_cval_el2",
1390 "cnthv_tval_el2",
1391 "id_aa64mmfr2_el1",
1392 "freeslot2",
1393
1394 "num_phys_regs",
1395
1396 // Dummy registers
1397 "nop",
1398 "raz",
1399 "cp14_unimpl",

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