miscregs.cc (7853:69aae4379062) miscregs.cc (8058:a259ab86cabf)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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376 case 0:
377 return MISCREG_PMUSERENR;
378 case 1:
379 return MISCREG_PMINTENSET;
380 case 2:
381 return MISCREG_PMINTENCLR;
382 }
383 }
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 367 unchanged lines hidden (view full) ---

376 case 0:
377 return MISCREG_PMUSERENR;
378 case 1:
379 return MISCREG_PMINTENSET;
380 case 2:
381 return MISCREG_PMINTENCLR;
382 }
383 }
384 } else if (opc1 == 1) {
385 return MISCREG_L2LATENCY;
384 }
385 //Reserved for Branch Predictor, Cache and TCM operations
386 break;
387 case 10:
388 if (opc1 == 0) {
389 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
390 if (crm == 2) { // TEX Remap Registers
391 if (opc2 == 0) {

--- 67 unchanged lines hidden --- 		386 }
387 //Reserved for Branch Predictor, Cache and TCM operations
388 break;
389 case 10:
390 if (opc1 == 0) {
391 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
392 if (crm == 2) { // TEX Remap Registers
393 if (opc2 == 0) {

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