miscregs.cc (7406:ddc26bd4ea7d) miscregs.cc (7583:665d71561298)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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336 case 3:
337 return MISCREG_TLBIMVAA;
338 }
339 break;
340 }
341 }
342 break;
343 case 9:
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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336 case 3:
337 return MISCREG_TLBIMVAA;
338 }
339 break;
340 }
341 }
342 break;
343 case 9:
344 if (opc1 >= 0 && opc1 <= 7) {
344 if (opc1 == 0) {
345 switch (crm) {
345 switch (crm) {
346 case 0:
347 case 1:
348 case 2:
349 case 5:
350 case 6:
351 case 7:
352 case 8:
353 //Reserved for Branch Predictor, Cache and TCM operations
354 case 12:
346 case 12:
347 switch (opc2) {
348 case 0:
349 return MISCREG_PMCR;
350 case 1:
351 return MISCREG_PMCNTENSET;
352 case 2:
353 return MISCREG_PMCNTENCLR;
354 case 3:
355 return MISCREG_PMOVSR;
356 case 4:
357 return MISCREG_PMSWINC;
358 case 5:
359 return MISCREG_PMSELR;
360 case 6:
361 return MISCREG_PMCEID0;
362 case 7:
363 return MISCREG_PMCEID1;
364 }
355 case 13:
365 case 13:
366 switch (opc2) {
367 case 0:
368 return MISCREG_PMCCNTR;
369 case 1:
370 return MISCREG_PMC_OTHER;
371 case 2:
372 return MISCREG_PMXEVCNTR;
373 }
356 case 14:
374 case 14:
357 case 15:
358 // Reserved for Performance monitors
359 break;
375 switch (opc2) {
376 case 0:
377 return MISCREG_PMUSERENR;
378 case 1:
379 return MISCREG_PMINTENSET;
380 case 2:
381 return MISCREG_PMINTENCLR;
382 }
360 }
361 }
383 }
384 }
385 //Reserved for Branch Predictor, Cache and TCM operations
362 break;
363 case 10:
364 if (opc1 == 0) {
365 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
366 if (crm == 2) { // TEX Remap Registers
367 if (opc2 == 0) {
368 return MISCREG_PRRR;
369 } else if (opc2 == 1) {

--- 67 unchanged lines hidden --- 		386 break;
387 case 10:
388 if (opc1 == 0) {
389 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
390 if (crm == 2) { // TEX Remap Registers
391 if (opc2 == 0) {
392 return MISCREG_PRRR;
393 } else if (opc2 == 1) {

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