miscregs.cc (7351:d90afcb8724e) | miscregs.cc (7404:bfc74724914e) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 24 unchanged lines hidden (view full) --- 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#include "arch/arm/miscregs.hh" | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 24 unchanged lines hidden (view full) --- 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#include "arch/arm/miscregs.hh" |
41#include "base/misc.hh" |
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41 42namespace ArmISA 43{ 44 45MiscRegIndex 46decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 47{ 48 switch (crn) { --- 370 unchanged lines hidden (view full) --- 419 } 420 } 421 } 422 break; 423 case 15: 424 // Implementation defined 425 break; 426 } | 42 43namespace ArmISA 44{ 45 46MiscRegIndex 47decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 48{ 49 switch (crn) { --- 370 unchanged lines hidden (view full) --- 420 } 421 } 422 } 423 break; 424 case 15: 425 // Implementation defined 426 break; 427 } |
428 warn("Unknown miscreg: CRn: %d Opc1: %d CRm: %d opc2: %d\n", 429 crn, opc1, crm, opc2); |
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427 // Unrecognized register 428 return NUM_MISCREGS; 429} 430 431}; | 430 // Unrecognized register 431 return NUM_MISCREGS; 432} 433 434}; |