miscregs.cc (14172:bba55ff08279) miscregs.cc (14229:eb52acecf179)
1/*
2 * Copyright (c) 2010-2013, 2015-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 948 unchanged lines hidden (view full) ---

957 case 3:
958 return MISCREG_CNTV_CVAL;
959 case 4:
960 return MISCREG_CNTVOFF;
961 case 6:
962 return MISCREG_CNTHP_CVAL;
963 }
964 break;
1/*
2 * Copyright (c) 2010-2013, 2015-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 948 unchanged lines hidden (view full) ---

957 case 3:
958 return MISCREG_CNTV_CVAL;
959 case 4:
960 return MISCREG_CNTVOFF;
961 case 6:
962 return MISCREG_CNTHP_CVAL;
963 }
964 break;
965 case 12:
966 switch (opc1) {
967 case 0:
968 return MISCREG_ICC_SGI1R;
969 case 1:
970 return MISCREG_ICC_ASGI1R;
971 case 2:
972 return MISCREG_ICC_SGI0R;
973 default:
974 break;
975 }
976 break;
965 case 15:
966 if (opc1 == 0)
967 return MISCREG_CPUMERRSR;
968 else if (opc1 == 1)
969 return MISCREG_L2MERRSR;
970 break;
971 }
972 // Unrecognized register

--- 4066 unchanged lines hidden --- 		977 case 15:
978 if (opc1 == 0)
979 return MISCREG_CPUMERRSR;
980 else if (opc1 == 1)
981 return MISCREG_L2MERRSR;
982 break;
983 }
984 // Unrecognized register

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