miscregs.cc (14128:6ed23d07d0d1) miscregs.cc (14172:bba55ff08279)
1/*
2 * Copyright (c) 2010-2013, 2015-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1112 if (reg == MISCREG_RVBAR_EL2) {
1113 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1114 if (highest_el == EL3)
1115 return false;
1116 }
1117
1118 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1119
1/*
2 * Copyright (c) 2010-2013, 2015-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1103 unchanged lines hidden (view full) ---

1112 if (reg == MISCREG_RVBAR_EL2) {
1113 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1114 if (highest_el == EL3)
1115 return false;
1116 }
1117
1118 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1119
1120 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
1120 switch (currEL(cpsr)) {
1121 case EL0:
1122 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1123 miscRegInfo[reg][MISCREG_USR_NS_RD];
1124 case EL1:
1125 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1126 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1127 case EL2:
1128 return miscRegInfo[reg][MISCREG_HYP_RD];

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1135}
1136
1137bool
1138canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1139{
1140 // Check for SP_EL0 access while SPSEL == 0
1141 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1142 return false;
1121 case EL0:
1122 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1123 miscRegInfo[reg][MISCREG_USR_NS_RD];
1124 case EL1:
1125 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1126 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1127 case EL2:
1128 return miscRegInfo[reg][MISCREG_HYP_RD];

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1135}
1136
1137bool
1138canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1139{
1140 // Check for SP_EL0 access while SPSEL == 0
1141 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1142 return false;
1143 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
1143 ExceptionLevel el = currEL(cpsr);
1144 if (reg == MISCREG_DAIF) {
1145 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1146 if (el == EL0 && !sctlr.uma)
1147 return false;
1148 }
1149 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
1150 // In syscall-emulation mode, this test is skipped and DCZVA is always
1151 // allowed at EL0

--- 3887 unchanged lines hidden --- 		1144 if (reg == MISCREG_DAIF) {
1145 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1146 if (el == EL0 && !sctlr.uma)
1147 return false;
1148 }
1149 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
1150 // In syscall-emulation mode, this test is skipped and DCZVA is always
1151 // allowed at EL0

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