miscregs.cc (13395:0f064dae9f6b) miscregs.cc (13502:7803bd430e0e)
1/*
2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 2439 unchanged lines hidden (view full) ---

2448 if (completed)
2449 return;
2450
2451 // This boolean variable specifies if the system is running in aarch32 at
2452 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2453 // is running in aarch64 (aarch32EL3 = false)
2454 bool aarch32EL3 = haveSecurity && !highestELIs64;
2455
1/*
2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 2439 unchanged lines hidden (view full) ---

2448 if (completed)
2449 return;
2450
2451 // This boolean variable specifies if the system is running in aarch32 at
2452 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2453 // is running in aarch64 (aarch32EL3 = false)
2454 bool aarch32EL3 = haveSecurity && !highestELIs64;
2455
2456 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2457 // unsupported
2458 bool SPAN = false;
2459
2460 // Implicit error synchronization event enable (Arm 8.2+), unsupported
2461 bool IESB = false;
2462
2463 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2464 // unsupported
2465 bool LSMAOE = false;
2466
2467 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2468 bool nTLSMD = false;
2469
2470 // Pointer authentication (Arm 8.3+), unsupported
2471 bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2472 bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2473 bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2474 bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2475
2456 /**
2457 * Some registers alias with others, and therefore need to be translated.
2458 * When two mapping registers are given, they are the 32b lower and
2459 * upper halves, respectively, of the 64b register being mapped.
2460 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2461 *
2462 * NAM = "not architecturally mandated",
2463 * from ARM DDI 0487A.i, template text

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2742 InitReg(MISCREG_CSSELR_S)
2743 .bankedChild()
2744 .secure().exceptUserMode();
2745 InitReg(MISCREG_VPIDR)
2746 .hyp().monNonSecure();
2747 InitReg(MISCREG_VMPIDR)
2748 .hyp().monNonSecure();
2749 InitReg(MISCREG_SCTLR)
2476 /**
2477 * Some registers alias with others, and therefore need to be translated.
2478 * When two mapping registers are given, they are the 32b lower and
2479 * upper halves, respectively, of the 64b register being mapped.
2480 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2481 *
2482 * NAM = "not architecturally mandated",
2483 * from ARM DDI 0487A.i, template text

--- 278 unchanged lines hidden (view full) ---

2762 InitReg(MISCREG_CSSELR_S)
2763 .bankedChild()
2764 .secure().exceptUserMode();
2765 InitReg(MISCREG_VPIDR)
2766 .hyp().monNonSecure();
2767 InitReg(MISCREG_VMPIDR)
2768 .hyp().monNonSecure();
2769 InitReg(MISCREG_SCTLR)
2750 .banked();
2770 .banked()
2771 // readMiscRegNoEffect() uses this metadata
2772 // despite using children (below) as backing store
2773 .res0(0x8d22c600)
2774 .res1(0x00400800 | (SPAN ? 0 : 0x800000)
2775 | (LSMAOE ? 0 : 0x10)
2776 | (nTLSMD ? 0 : 0x8));
2751 InitReg(MISCREG_SCTLR_NS)
2752 .bankedChild()
2753 .privSecure(!aarch32EL3)
2754 .nonSecure().exceptUserMode();
2755 InitReg(MISCREG_SCTLR_S)
2756 .bankedChild()
2757 .secure().exceptUserMode();
2758 InitReg(MISCREG_ACTLR)

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2770 .mon().secure().exceptUserMode()
2771 .res0(0xff40) // [31:16], [6]
2772 .res1(0x0030); // [5:4]
2773 InitReg(MISCREG_SDER)
2774 .mon();
2775 InitReg(MISCREG_NSACR)
2776 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2777 InitReg(MISCREG_HSCTLR)
2777 InitReg(MISCREG_SCTLR_NS)
2778 .bankedChild()
2779 .privSecure(!aarch32EL3)
2780 .nonSecure().exceptUserMode();
2781 InitReg(MISCREG_SCTLR_S)
2782 .bankedChild()
2783 .secure().exceptUserMode();
2784 InitReg(MISCREG_ACTLR)

--- 11 unchanged lines hidden (view full) ---

2796 .mon().secure().exceptUserMode()
2797 .res0(0xff40) // [31:16], [6]
2798 .res1(0x0030); // [5:4]
2799 InitReg(MISCREG_SDER)
2800 .mon();
2801 InitReg(MISCREG_NSACR)
2802 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2803 InitReg(MISCREG_HSCTLR)
2778 .hyp().monNonSecure();
2804 .hyp().monNonSecure()
2805 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
2806 | (IESB ? 0 : 0x200000)
2807 | (EnDA ? 0 : 0x8000000)
2808 | (EnIB ? 0 : 0x40000000)
2809 | (EnIA ? 0 : 0x80000000))
2810 .res1(0x30c50830);
2779 InitReg(MISCREG_HACTLR)
2780 .hyp().monNonSecure();
2781 InitReg(MISCREG_HCR)
2782 .hyp().monNonSecure();
2783 InitReg(MISCREG_HDCR)
2784 .hyp().monNonSecure();
2785 InitReg(MISCREG_HCPTR)
2786 .hyp().monNonSecure();

--- 383 unchanged lines hidden (view full) ---

3170 .privRead(FullSystem && system->highestEL() == EL1)
3171 .exceptUserMode();
3172 InitReg(MISCREG_RMR)
3173 .unimplemented()
3174 .mon().secure().exceptUserMode();
3175 InitReg(MISCREG_ISR)
3176 .allPrivileges().exceptUserMode().writes(0);
3177 InitReg(MISCREG_HVBAR)
2811 InitReg(MISCREG_HACTLR)
2812 .hyp().monNonSecure();
2813 InitReg(MISCREG_HCR)
2814 .hyp().monNonSecure();
2815 InitReg(MISCREG_HDCR)
2816 .hyp().monNonSecure();
2817 InitReg(MISCREG_HCPTR)
2818 .hyp().monNonSecure();

--- 383 unchanged lines hidden (view full) ---

3202 .privRead(FullSystem && system->highestEL() == EL1)
3203 .exceptUserMode();
3204 InitReg(MISCREG_RMR)
3205 .unimplemented()
3206 .mon().secure().exceptUserMode();
3207 InitReg(MISCREG_ISR)
3208 .allPrivileges().exceptUserMode().writes(0);
3209 InitReg(MISCREG_HVBAR)
3178 .hyp().monNonSecure();
3210 .hyp().monNonSecure()
3211 .res0(0x1f);
3179 InitReg(MISCREG_FCSEIDR)
3180 .unimplemented()
3181 .warnNotFail()
3182 .allPrivileges().exceptUserMode();
3183 InitReg(MISCREG_CONTEXTIDR)
3184 .banked();
3185 InitReg(MISCREG_CONTEXTIDR_NS)
3186 .bankedChild()

--- 345 unchanged lines hidden (view full) ---

3532 InitReg(MISCREG_VPIDR_EL2)
3533 .hyp().mon()
3534 .mapsTo(MISCREG_VPIDR);
3535 InitReg(MISCREG_VMPIDR_EL2)
3536 .hyp().mon()
3537 .mapsTo(MISCREG_VMPIDR);
3538 InitReg(MISCREG_SCTLR_EL1)
3539 .allPrivileges().exceptUserMode()
3212 InitReg(MISCREG_FCSEIDR)
3213 .unimplemented()
3214 .warnNotFail()
3215 .allPrivileges().exceptUserMode();
3216 InitReg(MISCREG_CONTEXTIDR)
3217 .banked();
3218 InitReg(MISCREG_CONTEXTIDR_NS)
3219 .bankedChild()

--- 345 unchanged lines hidden (view full) ---

3565 InitReg(MISCREG_VPIDR_EL2)
3566 .hyp().mon()
3567 .mapsTo(MISCREG_VPIDR);
3568 InitReg(MISCREG_VMPIDR_EL2)
3569 .hyp().mon()
3570 .mapsTo(MISCREG_VMPIDR);
3571 InitReg(MISCREG_SCTLR_EL1)
3572 .allPrivileges().exceptUserMode()
3573 .res0( 0x20440 | (EnDB ? 0 : 0x2000)
3574 | (IESB ? 0 : 0x200000)
3575 | (EnDA ? 0 : 0x8000000)
3576 | (EnIB ? 0 : 0x40000000)
3577 | (EnIA ? 0 : 0x80000000))
3578 .res1(0x500800 | (SPAN ? 0 : 0x800000)
3579 | (nTLSMD ? 0 : 0x8000000)
3580 | (LSMAOE ? 0 : 0x10000000))
3540 .mapsTo(MISCREG_SCTLR_NS);
3541 InitReg(MISCREG_ACTLR_EL1)
3542 .allPrivileges().exceptUserMode()
3543 .mapsTo(MISCREG_ACTLR_NS);
3544 InitReg(MISCREG_CPACR_EL1)
3545 .allPrivileges().exceptUserMode()
3546 .mapsTo(MISCREG_CPACR);
3547 InitReg(MISCREG_SCTLR_EL2)
3548 .hyp().mon()
3581 .mapsTo(MISCREG_SCTLR_NS);
3582 InitReg(MISCREG_ACTLR_EL1)
3583 .allPrivileges().exceptUserMode()
3584 .mapsTo(MISCREG_ACTLR_NS);
3585 InitReg(MISCREG_CPACR_EL1)
3586 .allPrivileges().exceptUserMode()
3587 .mapsTo(MISCREG_CPACR);
3588 InitReg(MISCREG_SCTLR_EL2)
3589 .hyp().mon()
3590 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3591 | (IESB ? 0 : 0x200000)
3592 | (EnDA ? 0 : 0x8000000)
3593 | (EnIB ? 0 : 0x40000000)
3594 | (EnIA ? 0 : 0x80000000))
3595 .res1(0x30c50830)
3549 .mapsTo(MISCREG_HSCTLR);
3550 InitReg(MISCREG_ACTLR_EL2)
3551 .hyp().mon()
3552 .mapsTo(MISCREG_HACTLR);
3553 InitReg(MISCREG_HCR_EL2)
3554 .hyp().mon()
3555 .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
3556 InitReg(MISCREG_MDCR_EL2)

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3561 .mapsTo(MISCREG_HCPTR);
3562 InitReg(MISCREG_HSTR_EL2)
3563 .hyp().mon()
3564 .mapsTo(MISCREG_HSTR);
3565 InitReg(MISCREG_HACR_EL2)
3566 .hyp().mon()
3567 .mapsTo(MISCREG_HACR);
3568 InitReg(MISCREG_SCTLR_EL3)
3596 .mapsTo(MISCREG_HSCTLR);
3597 InitReg(MISCREG_ACTLR_EL2)
3598 .hyp().mon()
3599 .mapsTo(MISCREG_HACTLR);
3600 InitReg(MISCREG_HCR_EL2)
3601 .hyp().mon()
3602 .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
3603 InitReg(MISCREG_MDCR_EL2)

--- 4 unchanged lines hidden (view full) ---

3608 .mapsTo(MISCREG_HCPTR);
3609 InitReg(MISCREG_HSTR_EL2)
3610 .hyp().mon()
3611 .mapsTo(MISCREG_HSTR);
3612 InitReg(MISCREG_HACR_EL2)
3613 .hyp().mon()
3614 .mapsTo(MISCREG_HACR);
3615 InitReg(MISCREG_SCTLR_EL3)
3569 .mon();
3616 .mon()
3617 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3618 | (IESB ? 0 : 0x200000)
3619 | (EnDA ? 0 : 0x8000000)
3620 | (EnIB ? 0 : 0x40000000)
3621 | (EnIA ? 0 : 0x80000000))
3622 .res1(0x30c50830);
3570 InitReg(MISCREG_ACTLR_EL3)
3571 .mon();
3572 InitReg(MISCREG_SCR_EL3)
3573 .mon()
3574 .mapsTo(MISCREG_SCR); // NAM D7-2005
3575 InitReg(MISCREG_SDER32_EL3)
3576 .mon()
3577 .mapsTo(MISCREG_SDER);

--- 309 unchanged lines hidden (view full) ---

3887 .allPrivileges().exceptUserMode()
3888 .mapsTo(MISCREG_VBAR_NS);
3889 InitReg(MISCREG_RVBAR_EL1)
3890 .allPrivileges().exceptUserMode().writes(0);
3891 InitReg(MISCREG_ISR_EL1)
3892 .allPrivileges().exceptUserMode().writes(0);
3893 InitReg(MISCREG_VBAR_EL2)
3894 .hyp().mon()
3623 InitReg(MISCREG_ACTLR_EL3)
3624 .mon();
3625 InitReg(MISCREG_SCR_EL3)
3626 .mon()
3627 .mapsTo(MISCREG_SCR); // NAM D7-2005
3628 InitReg(MISCREG_SDER32_EL3)
3629 .mon()
3630 .mapsTo(MISCREG_SDER);

--- 309 unchanged lines hidden (view full) ---

3940 .allPrivileges().exceptUserMode()
3941 .mapsTo(MISCREG_VBAR_NS);
3942 InitReg(MISCREG_RVBAR_EL1)
3943 .allPrivileges().exceptUserMode().writes(0);
3944 InitReg(MISCREG_ISR_EL1)
3945 .allPrivileges().exceptUserMode().writes(0);
3946 InitReg(MISCREG_VBAR_EL2)
3947 .hyp().mon()
3948 .res0(0x7ff)
3895 .mapsTo(MISCREG_HVBAR);
3896 InitReg(MISCREG_RVBAR_EL2)
3897 .mon().hyp().writes(0);
3898 InitReg(MISCREG_VBAR_EL3)
3899 .mon();
3900 InitReg(MISCREG_RVBAR_EL3)
3901 .mon().writes(0);
3902 InitReg(MISCREG_RMR_EL3)

--- 211 unchanged lines hidden --- 		3949 .mapsTo(MISCREG_HVBAR);
3950 InitReg(MISCREG_RVBAR_EL2)
3951 .mon().hyp().writes(0);
3952 InitReg(MISCREG_VBAR_EL3)
3953 .mon();
3954 InitReg(MISCREG_RVBAR_EL3)
3955 .mon().writes(0);
3956 InitReg(MISCREG_RMR_EL3)

--- 211 unchanged lines hidden ---