miscregs.cc (13366:c135fac88a78) miscregs.cc (13395:0f064dae9f6b)
1/*
2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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3160 InitReg(MISCREG_VBAR_NS)
3161 .bankedChild()
3162 .privSecure(!aarch32EL3)
3163 .nonSecure().exceptUserMode();
3164 InitReg(MISCREG_VBAR_S)
3165 .bankedChild()
3166 .secure().exceptUserMode();
3167 InitReg(MISCREG_MVBAR)
1/*
2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 3151 unchanged lines hidden (view full) ---

3160 InitReg(MISCREG_VBAR_NS)
3161 .bankedChild()
3162 .privSecure(!aarch32EL3)
3163 .nonSecure().exceptUserMode();
3164 InitReg(MISCREG_VBAR_S)
3165 .bankedChild()
3166 .secure().exceptUserMode();
3167 InitReg(MISCREG_MVBAR)
3168 .mon().secure().exceptUserMode();
3168 .mon().secure()
3169 .hypRead(FullSystem && system->highestEL() == EL2)
3170 .privRead(FullSystem && system->highestEL() == EL1)
3171 .exceptUserMode();
3169 InitReg(MISCREG_RMR)
3170 .unimplemented()
3171 .mon().secure().exceptUserMode();
3172 InitReg(MISCREG_ISR)
3173 .allPrivileges().exceptUserMode().writes(0);
3174 InitReg(MISCREG_HVBAR)
3175 .hyp().monNonSecure();
3176 InitReg(MISCREG_FCSEIDR)

--- 934 unchanged lines hidden --- 		3172 InitReg(MISCREG_RMR)
3173 .unimplemented()
3174 .mon().secure().exceptUserMode();
3175 InitReg(MISCREG_ISR)
3176 .allPrivileges().exceptUserMode().writes(0);
3177 InitReg(MISCREG_HVBAR)
3178 .hyp().monNonSecure();
3179 InitReg(MISCREG_FCSEIDR)

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