miscregs.cc (12713:8bd811411ed7) | miscregs.cc (12714:6870e0c151b1) |
---|---|
1/* 2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 3994 unchanged lines hidden (view full) --- 4003 .allPrivileges().exceptUserMode().writes(0); 4004 InitReg(MISCREG_CP14_UNIMPL) 4005 .unimplemented() 4006 .warnNotFail(); 4007 InitReg(MISCREG_CP15_UNIMPL) 4008 .unimplemented() 4009 .warnNotFail(); 4010 InitReg(MISCREG_UNKNOWN); | 1/* 2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 3994 unchanged lines hidden (view full) --- 4003 .allPrivileges().exceptUserMode().writes(0); 4004 InitReg(MISCREG_CP14_UNIMPL) 4005 .unimplemented() 4006 .warnNotFail(); 4007 InitReg(MISCREG_CP15_UNIMPL) 4008 .unimplemented() 4009 .warnNotFail(); 4010 InitReg(MISCREG_UNKNOWN); |
4011 InitReg(MISCREG_IMPDEF_UNIMPL) 4012 .unimplemented() 4013 .warnNotFail(impdefAsNop); |
|
4011 4012 // Register mappings for some unimplemented registers: 4013 // ESR_EL1 -> DFSR 4014 // RMR_EL1 -> RMR 4015 // RMR_EL2 -> HRMR 4016 // DBGDTR_EL0 -> DBGDTR{R or T}Xint 4017 // DBGDTRRX_EL0 -> DBGDTRRXint 4018 // DBGDTRTX_EL0 -> DBGDTRRXint 4019 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5) 4020 4021 completed = true; 4022} 4023 4024} // namespace ArmISA | 4014 4015 // Register mappings for some unimplemented registers: 4016 // ESR_EL1 -> DFSR 4017 // RMR_EL1 -> RMR 4018 // RMR_EL2 -> HRMR 4019 // DBGDTR_EL0 -> DBGDTR{R or T}Xint 4020 // DBGDTRRX_EL0 -> DBGDTRRXint 4021 // DBGDTRTX_EL0 -> DBGDTRRXint 4022 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5) 4023 4024 completed = true; 4025} 4026 4027} // namespace ArmISA |