miscregs.cc (12577:5cafe57f87e5) miscregs.cc (12661:2ae7948a5572)
1/*
2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 2373 unchanged lines hidden (view full) ---

2382ISA::initializeMiscRegMetadata()
2383{
2384 // the MiscReg metadata tables are shared across all instances of the
2385 // ISA object, so there's no need to initialize them multiple times.
2386 static bool completed = false;
2387 if (completed)
2388 return;
2389
1/*
2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 2373 unchanged lines hidden (view full) ---

2382ISA::initializeMiscRegMetadata()
2383{
2384 // the MiscReg metadata tables are shared across all instances of the
2385 // ISA object, so there's no need to initialize them multiple times.
2386 static bool completed = false;
2387 if (completed)
2388 return;
2389
2390 // This boolean variable specifies if the system is running in aarch32 at
2391 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2392 // is running in aarch64 (aarch32EL3 = false)
2393 bool aarch32EL3 = haveSecurity && !highestELIs64;
2394
2390 /**
2391 * Some registers alias with others, and therefore need to be translated.
2392 * When two mapping registers are given, they are the 32b lower and
2393 * upper halves, respectively, of the 64b register being mapped.
2394 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2395 *
2396 * NAM = "not architecturally mandated",
2397 * from ARM DDI 0487A.i, template text

--- 46 unchanged lines hidden (view full) ---

2444 .allPrivileges();
2445 InitReg(MISCREG_LOCKFLAG)
2446 .allPrivileges();
2447 InitReg(MISCREG_PRRR_MAIR0)
2448 .mutex()
2449 .banked();
2450 InitReg(MISCREG_PRRR_MAIR0_NS)
2451 .mutex()
2395 /**
2396 * Some registers alias with others, and therefore need to be translated.
2397 * When two mapping registers are given, they are the 32b lower and
2398 * upper halves, respectively, of the 64b register being mapped.
2399 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2400 *
2401 * NAM = "not architecturally mandated",
2402 * from ARM DDI 0487A.i, template text

--- 46 unchanged lines hidden (view full) ---

2449 .allPrivileges();
2450 InitReg(MISCREG_LOCKFLAG)
2451 .allPrivileges();
2452 InitReg(MISCREG_PRRR_MAIR0)
2453 .mutex()
2454 .banked();
2455 InitReg(MISCREG_PRRR_MAIR0_NS)
2456 .mutex()
2457 .privSecure(!aarch32EL3)
2452 .bankedChild();
2453 InitReg(MISCREG_PRRR_MAIR0_S)
2454 .mutex()
2455 .bankedChild();
2456 InitReg(MISCREG_NMRR_MAIR1)
2457 .mutex()
2458 .banked();
2459 InitReg(MISCREG_NMRR_MAIR1_NS)
2460 .mutex()
2458 .bankedChild();
2459 InitReg(MISCREG_PRRR_MAIR0_S)
2460 .mutex()
2461 .bankedChild();
2462 InitReg(MISCREG_NMRR_MAIR1)
2463 .mutex()
2464 .banked();
2465 InitReg(MISCREG_NMRR_MAIR1_NS)
2466 .mutex()
2467 .privSecure(!aarch32EL3)
2461 .bankedChild();
2462 InitReg(MISCREG_NMRR_MAIR1_S)
2463 .mutex()
2464 .bankedChild();
2465 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2466 .mutex();
2467 InitReg(MISCREG_SCTLR_RST)
2468 .allPrivileges();

--- 195 unchanged lines hidden (view full) ---

2664 InitReg(MISCREG_CLIDR)
2665 .allPrivileges().exceptUserMode().writes(0);
2666 InitReg(MISCREG_AIDR)
2667 .allPrivileges().exceptUserMode().writes(0);
2668 InitReg(MISCREG_CSSELR)
2669 .banked();
2670 InitReg(MISCREG_CSSELR_NS)
2671 .bankedChild()
2468 .bankedChild();
2469 InitReg(MISCREG_NMRR_MAIR1_S)
2470 .mutex()
2471 .bankedChild();
2472 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2473 .mutex();
2474 InitReg(MISCREG_SCTLR_RST)
2475 .allPrivileges();

--- 195 unchanged lines hidden (view full) ---

2671 InitReg(MISCREG_CLIDR)
2672 .allPrivileges().exceptUserMode().writes(0);
2673 InitReg(MISCREG_AIDR)
2674 .allPrivileges().exceptUserMode().writes(0);
2675 InitReg(MISCREG_CSSELR)
2676 .banked();
2677 InitReg(MISCREG_CSSELR_NS)
2678 .bankedChild()
2679 .privSecure(!aarch32EL3)
2672 .nonSecure().exceptUserMode();
2673 InitReg(MISCREG_CSSELR_S)
2674 .bankedChild()
2675 .secure().exceptUserMode();
2676 InitReg(MISCREG_VPIDR)
2677 .hyp().monNonSecure();
2678 InitReg(MISCREG_VMPIDR)
2679 .hyp().monNonSecure();
2680 InitReg(MISCREG_SCTLR)
2681 .banked();
2682 InitReg(MISCREG_SCTLR_NS)
2683 .bankedChild()
2680 .nonSecure().exceptUserMode();
2681 InitReg(MISCREG_CSSELR_S)
2682 .bankedChild()
2683 .secure().exceptUserMode();
2684 InitReg(MISCREG_VPIDR)
2685 .hyp().monNonSecure();
2686 InitReg(MISCREG_VMPIDR)
2687 .hyp().monNonSecure();
2688 InitReg(MISCREG_SCTLR)
2689 .banked();
2690 InitReg(MISCREG_SCTLR_NS)
2691 .bankedChild()
2692 .privSecure(!aarch32EL3)
2684 .nonSecure().exceptUserMode();
2685 InitReg(MISCREG_SCTLR_S)
2686 .bankedChild()
2687 .secure().exceptUserMode();
2688 InitReg(MISCREG_ACTLR)
2689 .banked();
2690 InitReg(MISCREG_ACTLR_NS)
2691 .bankedChild()
2693 .nonSecure().exceptUserMode();
2694 InitReg(MISCREG_SCTLR_S)
2695 .bankedChild()
2696 .secure().exceptUserMode();
2697 InitReg(MISCREG_ACTLR)
2698 .banked();
2699 InitReg(MISCREG_ACTLR_NS)
2700 .bankedChild()
2701 .privSecure(!aarch32EL3)
2692 .nonSecure().exceptUserMode();
2693 InitReg(MISCREG_ACTLR_S)
2694 .bankedChild()
2695 .secure().exceptUserMode();
2696 InitReg(MISCREG_CPACR)
2697 .allPrivileges().exceptUserMode();
2698 InitReg(MISCREG_SCR)
2699 .mon().secure().exceptUserMode()

--- 18 unchanged lines hidden (view full) ---

2718 InitReg(MISCREG_HACR)
2719 .unimplemented()
2720 .warnNotFail()
2721 .hyp().monNonSecure();
2722 InitReg(MISCREG_TTBR0)
2723 .banked();
2724 InitReg(MISCREG_TTBR0_NS)
2725 .bankedChild()
2702 .nonSecure().exceptUserMode();
2703 InitReg(MISCREG_ACTLR_S)
2704 .bankedChild()
2705 .secure().exceptUserMode();
2706 InitReg(MISCREG_CPACR)
2707 .allPrivileges().exceptUserMode();
2708 InitReg(MISCREG_SCR)
2709 .mon().secure().exceptUserMode()

--- 18 unchanged lines hidden (view full) ---

2728 InitReg(MISCREG_HACR)
2729 .unimplemented()
2730 .warnNotFail()
2731 .hyp().monNonSecure();
2732 InitReg(MISCREG_TTBR0)
2733 .banked();
2734 InitReg(MISCREG_TTBR0_NS)
2735 .bankedChild()
2736 .privSecure(!aarch32EL3)
2726 .nonSecure().exceptUserMode();
2727 InitReg(MISCREG_TTBR0_S)
2728 .bankedChild()
2729 .secure().exceptUserMode();
2730 InitReg(MISCREG_TTBR1)
2731 .banked();
2732 InitReg(MISCREG_TTBR1_NS)
2733 .bankedChild()
2737 .nonSecure().exceptUserMode();
2738 InitReg(MISCREG_TTBR0_S)
2739 .bankedChild()
2740 .secure().exceptUserMode();
2741 InitReg(MISCREG_TTBR1)
2742 .banked();
2743 InitReg(MISCREG_TTBR1_NS)
2744 .bankedChild()
2745 .privSecure(!aarch32EL3)
2734 .nonSecure().exceptUserMode();
2735 InitReg(MISCREG_TTBR1_S)
2736 .bankedChild()
2737 .secure().exceptUserMode();
2738 InitReg(MISCREG_TTBCR)
2739 .banked();
2740 InitReg(MISCREG_TTBCR_NS)
2741 .bankedChild()
2746 .nonSecure().exceptUserMode();
2747 InitReg(MISCREG_TTBR1_S)
2748 .bankedChild()
2749 .secure().exceptUserMode();
2750 InitReg(MISCREG_TTBCR)
2751 .banked();
2752 InitReg(MISCREG_TTBCR_NS)
2753 .bankedChild()
2754 .privSecure(!aarch32EL3)
2742 .nonSecure().exceptUserMode();
2743 InitReg(MISCREG_TTBCR_S)
2744 .bankedChild()
2745 .secure().exceptUserMode();
2746 InitReg(MISCREG_HTCR)
2747 .hyp().monNonSecure();
2748 InitReg(MISCREG_VTCR)
2749 .hyp().monNonSecure();
2750 InitReg(MISCREG_DACR)
2751 .banked();
2752 InitReg(MISCREG_DACR_NS)
2753 .bankedChild()
2755 .nonSecure().exceptUserMode();
2756 InitReg(MISCREG_TTBCR_S)
2757 .bankedChild()
2758 .secure().exceptUserMode();
2759 InitReg(MISCREG_HTCR)
2760 .hyp().monNonSecure();
2761 InitReg(MISCREG_VTCR)
2762 .hyp().monNonSecure();
2763 InitReg(MISCREG_DACR)
2764 .banked();
2765 InitReg(MISCREG_DACR_NS)
2766 .bankedChild()
2767 .privSecure(!aarch32EL3)
2754 .nonSecure().exceptUserMode();
2755 InitReg(MISCREG_DACR_S)
2756 .bankedChild()
2757 .secure().exceptUserMode();
2758 InitReg(MISCREG_DFSR)
2759 .banked();
2760 InitReg(MISCREG_DFSR_NS)
2761 .bankedChild()
2768 .nonSecure().exceptUserMode();
2769 InitReg(MISCREG_DACR_S)
2770 .bankedChild()
2771 .secure().exceptUserMode();
2772 InitReg(MISCREG_DFSR)
2773 .banked();
2774 InitReg(MISCREG_DFSR_NS)
2775 .bankedChild()
2776 .privSecure(!aarch32EL3)
2762 .nonSecure().exceptUserMode();
2763 InitReg(MISCREG_DFSR_S)
2764 .bankedChild()
2765 .secure().exceptUserMode();
2766 InitReg(MISCREG_IFSR)
2767 .banked();
2768 InitReg(MISCREG_IFSR_NS)
2769 .bankedChild()
2777 .nonSecure().exceptUserMode();
2778 InitReg(MISCREG_DFSR_S)
2779 .bankedChild()
2780 .secure().exceptUserMode();
2781 InitReg(MISCREG_IFSR)
2782 .banked();
2783 InitReg(MISCREG_IFSR_NS)
2784 .bankedChild()
2785 .privSecure(!aarch32EL3)
2770 .nonSecure().exceptUserMode();
2771 InitReg(MISCREG_IFSR_S)
2772 .bankedChild()
2773 .secure().exceptUserMode();
2774 InitReg(MISCREG_ADFSR)
2775 .unimplemented()
2776 .warnNotFail()
2777 .banked();
2778 InitReg(MISCREG_ADFSR_NS)
2779 .unimplemented()
2780 .warnNotFail()
2781 .bankedChild()
2786 .nonSecure().exceptUserMode();
2787 InitReg(MISCREG_IFSR_S)
2788 .bankedChild()
2789 .secure().exceptUserMode();
2790 InitReg(MISCREG_ADFSR)
2791 .unimplemented()
2792 .warnNotFail()
2793 .banked();
2794 InitReg(MISCREG_ADFSR_NS)
2795 .unimplemented()
2796 .warnNotFail()
2797 .bankedChild()
2798 .privSecure(!aarch32EL3)
2782 .nonSecure().exceptUserMode();
2783 InitReg(MISCREG_ADFSR_S)
2784 .unimplemented()
2785 .warnNotFail()
2786 .bankedChild()
2787 .secure().exceptUserMode();
2788 InitReg(MISCREG_AIFSR)
2789 .unimplemented()
2790 .warnNotFail()
2791 .banked();
2792 InitReg(MISCREG_AIFSR_NS)
2793 .unimplemented()
2794 .warnNotFail()
2795 .bankedChild()
2799 .nonSecure().exceptUserMode();
2800 InitReg(MISCREG_ADFSR_S)
2801 .unimplemented()
2802 .warnNotFail()
2803 .bankedChild()
2804 .secure().exceptUserMode();
2805 InitReg(MISCREG_AIFSR)
2806 .unimplemented()
2807 .warnNotFail()
2808 .banked();
2809 InitReg(MISCREG_AIFSR_NS)
2810 .unimplemented()
2811 .warnNotFail()
2812 .bankedChild()
2813 .privSecure(!aarch32EL3)
2796 .nonSecure().exceptUserMode();
2797 InitReg(MISCREG_AIFSR_S)
2798 .unimplemented()
2799 .warnNotFail()
2800 .bankedChild()
2801 .secure().exceptUserMode();
2802 InitReg(MISCREG_HADFSR)
2803 .hyp().monNonSecure();
2804 InitReg(MISCREG_HAIFSR)
2805 .hyp().monNonSecure();
2806 InitReg(MISCREG_HSR)
2807 .hyp().monNonSecure();
2808 InitReg(MISCREG_DFAR)
2809 .banked();
2810 InitReg(MISCREG_DFAR_NS)
2811 .bankedChild()
2814 .nonSecure().exceptUserMode();
2815 InitReg(MISCREG_AIFSR_S)
2816 .unimplemented()
2817 .warnNotFail()
2818 .bankedChild()
2819 .secure().exceptUserMode();
2820 InitReg(MISCREG_HADFSR)
2821 .hyp().monNonSecure();
2822 InitReg(MISCREG_HAIFSR)
2823 .hyp().monNonSecure();
2824 InitReg(MISCREG_HSR)
2825 .hyp().monNonSecure();
2826 InitReg(MISCREG_DFAR)
2827 .banked();
2828 InitReg(MISCREG_DFAR_NS)
2829 .bankedChild()
2830 .privSecure(!aarch32EL3)
2812 .nonSecure().exceptUserMode();
2813 InitReg(MISCREG_DFAR_S)
2814 .bankedChild()
2815 .secure().exceptUserMode();
2816 InitReg(MISCREG_IFAR)
2817 .banked();
2818 InitReg(MISCREG_IFAR_NS)
2819 .bankedChild()
2831 .nonSecure().exceptUserMode();
2832 InitReg(MISCREG_DFAR_S)
2833 .bankedChild()
2834 .secure().exceptUserMode();
2835 InitReg(MISCREG_IFAR)
2836 .banked();
2837 InitReg(MISCREG_IFAR_NS)
2838 .bankedChild()
2839 .privSecure(!aarch32EL3)
2820 .nonSecure().exceptUserMode();
2821 InitReg(MISCREG_IFAR_S)
2822 .bankedChild()
2823 .secure().exceptUserMode();
2824 InitReg(MISCREG_HDFAR)
2825 .hyp().monNonSecure();
2826 InitReg(MISCREG_HIFAR)
2827 .hyp().monNonSecure();

--- 6 unchanged lines hidden (view full) ---

2834 InitReg(MISCREG_BPIALLIS)
2835 .unimplemented()
2836 .warnNotFail()
2837 .writes(1).exceptUserMode();
2838 InitReg(MISCREG_PAR)
2839 .banked();
2840 InitReg(MISCREG_PAR_NS)
2841 .bankedChild()
2840 .nonSecure().exceptUserMode();
2841 InitReg(MISCREG_IFAR_S)
2842 .bankedChild()
2843 .secure().exceptUserMode();
2844 InitReg(MISCREG_HDFAR)
2845 .hyp().monNonSecure();
2846 InitReg(MISCREG_HIFAR)
2847 .hyp().monNonSecure();

--- 6 unchanged lines hidden (view full) ---

2854 InitReg(MISCREG_BPIALLIS)
2855 .unimplemented()
2856 .warnNotFail()
2857 .writes(1).exceptUserMode();
2858 InitReg(MISCREG_PAR)
2859 .banked();
2860 InitReg(MISCREG_PAR_NS)
2861 .bankedChild()
2862 .privSecure(!aarch32EL3)
2842 .nonSecure().exceptUserMode();
2843 InitReg(MISCREG_PAR_S)
2844 .bankedChild()
2845 .secure().exceptUserMode();
2846 InitReg(MISCREG_ICIALLU)
2847 .writes(1).exceptUserMode();
2848 InitReg(MISCREG_ICIMVAU)
2849 .unimplemented()

--- 156 unchanged lines hidden (view full) ---

3006 .allPrivileges().exceptUserMode();
3007 InitReg(MISCREG_L2ECTLR)
3008 .unimplemented()
3009 .allPrivileges().exceptUserMode();
3010 InitReg(MISCREG_PRRR)
3011 .banked();
3012 InitReg(MISCREG_PRRR_NS)
3013 .bankedChild()
2863 .nonSecure().exceptUserMode();
2864 InitReg(MISCREG_PAR_S)
2865 .bankedChild()
2866 .secure().exceptUserMode();
2867 InitReg(MISCREG_ICIALLU)
2868 .writes(1).exceptUserMode();
2869 InitReg(MISCREG_ICIMVAU)
2870 .unimplemented()

--- 156 unchanged lines hidden (view full) ---

3027 .allPrivileges().exceptUserMode();
3028 InitReg(MISCREG_L2ECTLR)
3029 .unimplemented()
3030 .allPrivileges().exceptUserMode();
3031 InitReg(MISCREG_PRRR)
3032 .banked();
3033 InitReg(MISCREG_PRRR_NS)
3034 .bankedChild()
3035 .privSecure(!aarch32EL3)
3014 .nonSecure().exceptUserMode();
3015 InitReg(MISCREG_PRRR_S)
3016 .bankedChild()
3017 .secure().exceptUserMode();
3018 InitReg(MISCREG_MAIR0)
3019 .banked();
3020 InitReg(MISCREG_MAIR0_NS)
3021 .bankedChild()
3036 .nonSecure().exceptUserMode();
3037 InitReg(MISCREG_PRRR_S)
3038 .bankedChild()
3039 .secure().exceptUserMode();
3040 InitReg(MISCREG_MAIR0)
3041 .banked();
3042 InitReg(MISCREG_MAIR0_NS)
3043 .bankedChild()
3044 .privSecure(!aarch32EL3)
3022 .nonSecure().exceptUserMode();
3023 InitReg(MISCREG_MAIR0_S)
3024 .bankedChild()
3025 .secure().exceptUserMode();
3026 InitReg(MISCREG_NMRR)
3027 .banked();
3028 InitReg(MISCREG_NMRR_NS)
3029 .bankedChild()
3045 .nonSecure().exceptUserMode();
3046 InitReg(MISCREG_MAIR0_S)
3047 .bankedChild()
3048 .secure().exceptUserMode();
3049 InitReg(MISCREG_NMRR)
3050 .banked();
3051 InitReg(MISCREG_NMRR_NS)
3052 .bankedChild()
3053 .privSecure(!aarch32EL3)
3030 .nonSecure().exceptUserMode();
3031 InitReg(MISCREG_NMRR_S)
3032 .bankedChild()
3033 .secure().exceptUserMode();
3034 InitReg(MISCREG_MAIR1)
3035 .banked();
3036 InitReg(MISCREG_MAIR1_NS)
3037 .bankedChild()
3054 .nonSecure().exceptUserMode();
3055 InitReg(MISCREG_NMRR_S)
3056 .bankedChild()
3057 .secure().exceptUserMode();
3058 InitReg(MISCREG_MAIR1)
3059 .banked();
3060 InitReg(MISCREG_MAIR1_NS)
3061 .bankedChild()
3062 .privSecure(!aarch32EL3)
3038 .nonSecure().exceptUserMode();
3039 InitReg(MISCREG_MAIR1_S)
3040 .bankedChild()
3041 .secure().exceptUserMode();
3042 InitReg(MISCREG_AMAIR0)
3043 .banked();
3044 InitReg(MISCREG_AMAIR0_NS)
3045 .bankedChild()
3063 .nonSecure().exceptUserMode();
3064 InitReg(MISCREG_MAIR1_S)
3065 .bankedChild()
3066 .secure().exceptUserMode();
3067 InitReg(MISCREG_AMAIR0)
3068 .banked();
3069 InitReg(MISCREG_AMAIR0_NS)
3070 .bankedChild()
3071 .privSecure(!aarch32EL3)
3046 .nonSecure().exceptUserMode();
3047 InitReg(MISCREG_AMAIR0_S)
3048 .bankedChild()
3049 .secure().exceptUserMode();
3050 InitReg(MISCREG_AMAIR1)
3051 .banked();
3052 InitReg(MISCREG_AMAIR1_NS)
3053 .bankedChild()
3072 .nonSecure().exceptUserMode();
3073 InitReg(MISCREG_AMAIR0_S)
3074 .bankedChild()
3075 .secure().exceptUserMode();
3076 InitReg(MISCREG_AMAIR1)
3077 .banked();
3078 InitReg(MISCREG_AMAIR1_NS)
3079 .bankedChild()
3080 .privSecure(!aarch32EL3)
3054 .nonSecure().exceptUserMode();
3055 InitReg(MISCREG_AMAIR1_S)
3056 .bankedChild()
3057 .secure().exceptUserMode();
3058 InitReg(MISCREG_HMAIR0)
3059 .hyp().monNonSecure();
3060 InitReg(MISCREG_HMAIR1)
3061 .hyp().monNonSecure();

--- 4 unchanged lines hidden (view full) ---

3066 InitReg(MISCREG_HAMAIR1)
3067 .unimplemented()
3068 .warnNotFail()
3069 .hyp().monNonSecure();
3070 InitReg(MISCREG_VBAR)
3071 .banked();
3072 InitReg(MISCREG_VBAR_NS)
3073 .bankedChild()
3081 .nonSecure().exceptUserMode();
3082 InitReg(MISCREG_AMAIR1_S)
3083 .bankedChild()
3084 .secure().exceptUserMode();
3085 InitReg(MISCREG_HMAIR0)
3086 .hyp().monNonSecure();
3087 InitReg(MISCREG_HMAIR1)
3088 .hyp().monNonSecure();

--- 4 unchanged lines hidden (view full) ---

3093 InitReg(MISCREG_HAMAIR1)
3094 .unimplemented()
3095 .warnNotFail()
3096 .hyp().monNonSecure();
3097 InitReg(MISCREG_VBAR)
3098 .banked();
3099 InitReg(MISCREG_VBAR_NS)
3100 .bankedChild()
3101 .privSecure(!aarch32EL3)
3074 .nonSecure().exceptUserMode();
3075 InitReg(MISCREG_VBAR_S)
3076 .bankedChild()
3077 .secure().exceptUserMode();
3078 InitReg(MISCREG_MVBAR)
3079 .mon().secure().exceptUserMode();
3080 InitReg(MISCREG_RMR)
3081 .unimplemented()

--- 5 unchanged lines hidden (view full) ---

3087 InitReg(MISCREG_FCSEIDR)
3088 .unimplemented()
3089 .warnNotFail()
3090 .allPrivileges().exceptUserMode();
3091 InitReg(MISCREG_CONTEXTIDR)
3092 .banked();
3093 InitReg(MISCREG_CONTEXTIDR_NS)
3094 .bankedChild()
3102 .nonSecure().exceptUserMode();
3103 InitReg(MISCREG_VBAR_S)
3104 .bankedChild()
3105 .secure().exceptUserMode();
3106 InitReg(MISCREG_MVBAR)
3107 .mon().secure().exceptUserMode();
3108 InitReg(MISCREG_RMR)
3109 .unimplemented()

--- 5 unchanged lines hidden (view full) ---

3115 InitReg(MISCREG_FCSEIDR)
3116 .unimplemented()
3117 .warnNotFail()
3118 .allPrivileges().exceptUserMode();
3119 InitReg(MISCREG_CONTEXTIDR)
3120 .banked();
3121 InitReg(MISCREG_CONTEXTIDR_NS)
3122 .bankedChild()
3123 .privSecure(!aarch32EL3)
3095 .nonSecure().exceptUserMode();
3096 InitReg(MISCREG_CONTEXTIDR_S)
3097 .bankedChild()
3098 .secure().exceptUserMode();
3099 InitReg(MISCREG_TPIDRURW)
3100 .banked();
3101 InitReg(MISCREG_TPIDRURW_NS)
3102 .bankedChild()
3124 .nonSecure().exceptUserMode();
3125 InitReg(MISCREG_CONTEXTIDR_S)
3126 .bankedChild()
3127 .secure().exceptUserMode();
3128 InitReg(MISCREG_TPIDRURW)
3129 .banked();
3130 InitReg(MISCREG_TPIDRURW_NS)
3131 .bankedChild()
3103 .allPrivileges().monSecure(0).privSecure(0);
3132 .allPrivileges()
3133 .privSecure(!aarch32EL3)
3134 .monSecure(0);
3104 InitReg(MISCREG_TPIDRURW_S)
3105 .bankedChild()
3106 .secure();
3107 InitReg(MISCREG_TPIDRURO)
3108 .banked();
3109 InitReg(MISCREG_TPIDRURO_NS)
3110 .bankedChild()
3135 InitReg(MISCREG_TPIDRURW_S)
3136 .bankedChild()
3137 .secure();
3138 InitReg(MISCREG_TPIDRURO)
3139 .banked();
3140 InitReg(MISCREG_TPIDRURO_NS)
3141 .bankedChild()
3111 .allPrivileges().secure(0).userNonSecureWrite(0).userSecureRead(1);
3142 .allPrivileges()
3143 .userNonSecureWrite(0).userSecureRead(1)
3144 .privSecure(!aarch32EL3)
3145 .monSecure(0);
3112 InitReg(MISCREG_TPIDRURO_S)
3113 .bankedChild()
3114 .secure().userSecureWrite(0);
3115 InitReg(MISCREG_TPIDRPRW)
3116 .banked();
3117 InitReg(MISCREG_TPIDRPRW_NS)
3118 .bankedChild()
3146 InitReg(MISCREG_TPIDRURO_S)
3147 .bankedChild()
3148 .secure().userSecureWrite(0);
3149 InitReg(MISCREG_TPIDRPRW)
3150 .banked();
3151 InitReg(MISCREG_TPIDRPRW_NS)
3152 .bankedChild()
3119 .nonSecure().exceptUserMode();
3153 .nonSecure().exceptUserMode()
3154 .privSecure(!aarch32EL3);
3120 InitReg(MISCREG_TPIDRPRW_S)
3121 .bankedChild()
3122 .secure().exceptUserMode();
3123 InitReg(MISCREG_HTPIDR)
3124 .hyp().monNonSecure();
3125 InitReg(MISCREG_CNTFRQ)
3126 .unverifiable()
3127 .reads(1).mon();
3128 InitReg(MISCREG_CNTKCTL)
3129 .allPrivileges().exceptUserMode();
3130 InitReg(MISCREG_CNTP_TVAL)
3131 .banked();
3132 InitReg(MISCREG_CNTP_TVAL_NS)
3133 .bankedChild()
3155 InitReg(MISCREG_TPIDRPRW_S)
3156 .bankedChild()
3157 .secure().exceptUserMode();
3158 InitReg(MISCREG_HTPIDR)
3159 .hyp().monNonSecure();
3160 InitReg(MISCREG_CNTFRQ)
3161 .unverifiable()
3162 .reads(1).mon();
3163 InitReg(MISCREG_CNTKCTL)
3164 .allPrivileges().exceptUserMode();
3165 InitReg(MISCREG_CNTP_TVAL)
3166 .banked();
3167 InitReg(MISCREG_CNTP_TVAL_NS)
3168 .bankedChild()
3134 .allPrivileges().monSecure(0).privSecure(0);
3169 .allPrivileges()
3170 .privSecure(!aarch32EL3)
3171 .monSecure(0);
3135 InitReg(MISCREG_CNTP_TVAL_S)
3136 .unimplemented()
3137 .bankedChild()
3138 .secure().user(1);
3139 InitReg(MISCREG_CNTP_CTL)
3140 .banked();
3141 InitReg(MISCREG_CNTP_CTL_NS)
3142 .bankedChild()
3172 InitReg(MISCREG_CNTP_TVAL_S)
3173 .unimplemented()
3174 .bankedChild()
3175 .secure().user(1);
3176 InitReg(MISCREG_CNTP_CTL)
3177 .banked();
3178 InitReg(MISCREG_CNTP_CTL_NS)
3179 .bankedChild()
3143 .allPrivileges().monSecure(0).privSecure(0);
3180 .allPrivileges()
3181 .privSecure(!aarch32EL3)
3182 .monSecure(0);
3144 InitReg(MISCREG_CNTP_CTL_S)
3145 .unimplemented()
3146 .bankedChild()
3147 .secure().user(1);
3148 InitReg(MISCREG_CNTV_TVAL)
3149 .allPrivileges();
3150 InitReg(MISCREG_CNTV_CTL)
3151 .allPrivileges();

--- 50 unchanged lines hidden (view full) ---

3202 .reads(1);
3203 InitReg(MISCREG_CNTVCT)
3204 .unverifiable()
3205 .reads(1);
3206 InitReg(MISCREG_CNTP_CVAL)
3207 .banked();
3208 InitReg(MISCREG_CNTP_CVAL_NS)
3209 .bankedChild()
3183 InitReg(MISCREG_CNTP_CTL_S)
3184 .unimplemented()
3185 .bankedChild()
3186 .secure().user(1);
3187 InitReg(MISCREG_CNTV_TVAL)
3188 .allPrivileges();
3189 InitReg(MISCREG_CNTV_CTL)
3190 .allPrivileges();

--- 50 unchanged lines hidden (view full) ---

3241 .reads(1);
3242 InitReg(MISCREG_CNTVCT)
3243 .unverifiable()
3244 .reads(1);
3245 InitReg(MISCREG_CNTP_CVAL)
3246 .banked();
3247 InitReg(MISCREG_CNTP_CVAL_NS)
3248 .bankedChild()
3210 .allPrivileges().monSecure(0).privSecure(0);
3249 .allPrivileges()
3250 .privSecure(!aarch32EL3)
3251 .monSecure(0);
3211 InitReg(MISCREG_CNTP_CVAL_S)
3212 .unimplemented()
3213 .bankedChild()
3214 .secure().user(1);
3215 InitReg(MISCREG_CNTV_CVAL)
3216 .allPrivileges();
3217 InitReg(MISCREG_CNTVOFF)
3218 .hyp().monNonSecure();

--- 747 unchanged lines hidden --- 		3252 InitReg(MISCREG_CNTP_CVAL_S)
3253 .unimplemented()
3254 .bankedChild()
3255 .secure().user(1);
3256 InitReg(MISCREG_CNTV_CVAL)
3257 .allPrivileges();
3258 InitReg(MISCREG_CNTVOFF)
3259 .hyp().monNonSecure();

--- 747 unchanged lines hidden ---