miscregs.cc (12499:b81688796004) miscregs.cc (12502:ba8a94a77482)
1/*
2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 908 unchanged lines hidden (view full) ---

917 }
918 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
919 // In syscall-emulation mode, this test is skipped and DCZVA is always
920 // allowed at EL0
921 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
922 if (el == EL0 && !sctlr.dze)
923 return false;
924 }
1/*
2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 908 unchanged lines hidden (view full) ---

917 }
918 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
919 // In syscall-emulation mode, this test is skipped and DCZVA is always
920 // allowed at EL0
921 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
922 if (el == EL0 && !sctlr.dze)
923 return false;
924 }
925 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt ||
926 reg == MISCREG_DC_IVAC_Xt) {
925 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
927 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
928 if (el == EL0 && !sctlr.uci)
929 return false;
930 }
931
932 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
933
934 switch (el) {

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3552 InitReg(MISCREG_PAR_EL1)
3553 .allPrivileges().exceptUserMode()
3554 .mapsTo(MISCREG_PAR_NS);
3555 InitReg(MISCREG_IC_IALLU)
3556 .warnNotFail()
3557 .writes(1).exceptUserMode();
3558 InitReg(MISCREG_DC_IVAC_Xt)
3559 .warnNotFail()
926 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
927 if (el == EL0 && !sctlr.uci)
928 return false;
929 }
930
931 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
932
933 switch (el) {

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3551 InitReg(MISCREG_PAR_EL1)
3552 .allPrivileges().exceptUserMode()
3553 .mapsTo(MISCREG_PAR_NS);
3554 InitReg(MISCREG_IC_IALLU)
3555 .warnNotFail()
3556 .writes(1).exceptUserMode();
3557 InitReg(MISCREG_DC_IVAC_Xt)
3558 .warnNotFail()
3560 .writes(1);
3559 .writes(1).exceptUserMode();
3561 InitReg(MISCREG_DC_ISW_Xt)
3562 .warnNotFail()
3563 .writes(1).exceptUserMode();
3564 InitReg(MISCREG_AT_S1E1R_Xt)
3565 .writes(1).exceptUserMode();
3566 InitReg(MISCREG_AT_S1E1W_Xt)
3567 .writes(1).exceptUserMode();
3568 InitReg(MISCREG_AT_S1E0R_Xt)

--- 365 unchanged lines hidden --- 		3560 InitReg(MISCREG_DC_ISW_Xt)
3561 .warnNotFail()
3562 .writes(1).exceptUserMode();
3563 InitReg(MISCREG_AT_S1E1R_Xt)
3564 .writes(1).exceptUserMode();
3565 InitReg(MISCREG_AT_S1E1W_Xt)
3566 .writes(1).exceptUserMode();
3567 InitReg(MISCREG_AT_S1E0R_Xt)

--- 365 unchanged lines hidden ---