Cross Reference: /gem5/src/arch/arm/miscregs.cc

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miscregs.cc (12373:6fdbcd214a3d)	miscregs.cc (12479:c686e4a1fe8f)
1/* 2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 114 unchanged lines hidden (view full) --- 123 // If we get here then it must be a register that we haven't implemented 124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", 125 crn, opc1, crm, opc2); 126 return MISCREG_CP14_UNIMPL; 127} 128 129using namespace std; 130	1/* 2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 114 unchanged lines hidden (view full) --- 123 // If we get here then it must be a register that we haven't implemented 124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", 125 crn, opc1, crm, opc2); 126 return MISCREG_CP14_UNIMPL; 127} 128 129using namespace std; 130
131bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = { 132 // MISCREG_CPSR 133 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 134 // MISCREG_SPSR 135 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 136 // MISCREG_SPSR_FIQ 137 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 138 // MISCREG_SPSR_IRQ 139 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 140 // MISCREG_SPSR_SVC 141 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 142 // MISCREG_SPSR_MON 143 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 144 // MISCREG_SPSR_ABT 145 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 146 // MISCREG_SPSR_HYP 147 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 148 // MISCREG_SPSR_UND 149 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 150 // MISCREG_ELR_HYP 151 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 152 // MISCREG_FPSID 153 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 154 // MISCREG_FPSCR 155 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 156 // MISCREG_MVFR1 157 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 158 // MISCREG_MVFR0 159 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 160 // MISCREG_FPEXC 161 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 162 163 // Helper registers 164 // MISCREG_CPSR_MODE 165 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 166 // MISCREG_CPSR_Q 167 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 168 // MISCREG_FPSCR_Q 169 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 170 // MISCREG_FPSCR_EXC 171 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 172 // MISCREG_LOCKADDR 173 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 174 // MISCREG_LOCKFLAG 175 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 176 // MISCREG_PRRR_MAIR0 177 bitset<NUM_MISCREG_INFOS>(string("00000000000000011001")), 178 // MISCREG_PRRR_MAIR0_NS 179 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")), 180 // MISCREG_PRRR_MAIR0_S 181 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")), 182 // MISCREG_NMRR_MAIR1 183 bitset<NUM_MISCREG_INFOS>(string("00000000000000011001")), 184 // MISCREG_NMRR_MAIR1_NS 185 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")), 186 // MISCREG_NMRR_MAIR1_S 187 bitset<NUM_MISCREG_INFOS>(string("00000000000000101001")), 188 // MISCREG_PMXEVTYPER_PMCCFILTR 189 bitset<NUM_MISCREG_INFOS>(string("00000000000000001001")), 190 // MISCREG_SCTLR_RST 191 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 192 // MISCREG_SEV_MAILBOX 193 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 194 195 // AArch32 CP14 registers 196 // MISCREG_DBGDIDR 197 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 198 // MISCREG_DBGDSCRint 199 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 200 // MISCREG_DBGDCCINT 201 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 202 // MISCREG_DBGDTRTXint 203 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 204 // MISCREG_DBGDTRRXint 205 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 206 // MISCREG_DBGWFAR 207 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 208 // MISCREG_DBGVCR 209 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 210 // MISCREG_DBGDTRRXext 211 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 212 // MISCREG_DBGDSCRext 213 bitset<NUM_MISCREG_INFOS>(string("11111111111111000100")), 214 // MISCREG_DBGDTRTXext 215 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 216 // MISCREG_DBGOSECCR 217 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 218 // MISCREG_DBGBVR0 219 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 220 // MISCREG_DBGBVR1 221 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 222 // MISCREG_DBGBVR2 223 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 224 // MISCREG_DBGBVR3 225 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 226 // MISCREG_DBGBVR4 227 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 228 // MISCREG_DBGBVR5 229 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 230 // MISCREG_DBGBCR0 231 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 232 // MISCREG_DBGBCR1 233 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 234 // MISCREG_DBGBCR2 235 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 236 // MISCREG_DBGBCR3 237 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 238 // MISCREG_DBGBCR4 239 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 240 // MISCREG_DBGBCR5 241 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 242 // MISCREG_DBGWVR0 243 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 244 // MISCREG_DBGWVR1 245 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 246 // MISCREG_DBGWVR2 247 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 248 // MISCREG_DBGWVR3 249 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 250 // MISCREG_DBGWCR0 251 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 252 // MISCREG_DBGWCR1 253 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 254 // MISCREG_DBGWCR2 255 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 256 // MISCREG_DBGWCR3 257 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 258 // MISCREG_DBGDRAR 259 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 260 // MISCREG_DBGBXVR4 261 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 262 // MISCREG_DBGBXVR5 263 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 264 // MISCREG_DBGOSLAR 265 bitset<NUM_MISCREG_INFOS>(string("10101111111111000000")), 266 // MISCREG_DBGOSLSR 267 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 268 // MISCREG_DBGOSDLR 269 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 270 // MISCREG_DBGPRCR 271 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 272 // MISCREG_DBGDSAR 273 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 274 // MISCREG_DBGCLAIMSET 275 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 276 // MISCREG_DBGCLAIMCLR 277 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 278 // MISCREG_DBGAUTHSTATUS 279 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 280 // MISCREG_DBGDEVID2 281 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 282 // MISCREG_DBGDEVID1 283 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 284 // MISCREG_DBGDEVID0 285 bitset<NUM_MISCREG_INFOS>(string("01011111111111000000")), 286 // MISCREG_TEECR 287 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 288 // MISCREG_JIDR 289 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 290 // MISCREG_TEEHBR 291 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 292 // MISCREG_JOSCR 293 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 294 // MISCREG_JMCR 295 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 296 297 // AArch32 CP15 registers 298 // MISCREG_MIDR 299 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 300 // MISCREG_CTR 301 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 302 // MISCREG_TCMTR 303 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 304 // MISCREG_TLBTR 305 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 306 // MISCREG_MPIDR 307 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 308 // MISCREG_REVIDR 309 bitset<NUM_MISCREG_INFOS>(string("01010101010000000100")), 310 // MISCREG_ID_PFR0 311 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 312 // MISCREG_ID_PFR1 313 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 314 // MISCREG_ID_DFR0 315 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 316 // MISCREG_ID_AFR0 317 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 318 // MISCREG_ID_MMFR0 319 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 320 // MISCREG_ID_MMFR1 321 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 322 // MISCREG_ID_MMFR2 323 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 324 // MISCREG_ID_MMFR3 325 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 326 // MISCREG_ID_ISAR0 327 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 328 // MISCREG_ID_ISAR1 329 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 330 // MISCREG_ID_ISAR2 331 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 332 // MISCREG_ID_ISAR3 333 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 334 // MISCREG_ID_ISAR4 335 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 336 // MISCREG_ID_ISAR5 337 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 338 // MISCREG_CCSIDR 339 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 340 // MISCREG_CLIDR 341 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 342 // MISCREG_AIDR 343 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 344 // MISCREG_CSSELR 345 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 346 // MISCREG_CSSELR_NS 347 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 348 // MISCREG_CSSELR_S 349 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 350 // MISCREG_VPIDR 351 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 352 // MISCREG_VMPIDR 353 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 354 // MISCREG_SCTLR 355 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 356 // MISCREG_SCTLR_NS 357 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 358 // MISCREG_SCTLR_S 359 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 360 // MISCREG_ACTLR 361 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 362 // MISCREG_ACTLR_NS 363 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 364 // MISCREG_ACTLR_S 365 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 366 // MISCREG_CPACR 367 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 368 // MISCREG_SCR 369 bitset<NUM_MISCREG_INFOS>(string("11110011000000000001")), 370 // MISCREG_SDER 371 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 372 // MISCREG_NSACR 373 bitset<NUM_MISCREG_INFOS>(string("11110111010000000001")), 374 // MISCREG_HSCTLR 375 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 376 // MISCREG_HACTLR 377 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 378 // MISCREG_HCR 379 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 380 // MISCREG_HDCR 381 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 382 // MISCREG_HCPTR 383 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 384 // MISCREG_HSTR 385 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 386 // MISCREG_HACR 387 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")), 388 // MISCREG_TTBR0 389 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 390 // MISCREG_TTBR0_NS 391 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 392 // MISCREG_TTBR0_S 393 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 394 // MISCREG_TTBR1 395 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 396 // MISCREG_TTBR1_NS 397 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 398 // MISCREG_TTBR1_S 399 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 400 // MISCREG_TTBCR 401 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 402 // MISCREG_TTBCR_NS 403 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 404 // MISCREG_TTBCR_S 405 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 406 // MISCREG_HTCR 407 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 408 // MISCREG_VTCR 409 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 410 // MISCREG_DACR 411 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 412 // MISCREG_DACR_NS 413 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 414 // MISCREG_DACR_S 415 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 416 // MISCREG_DFSR 417 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 418 // MISCREG_DFSR_NS 419 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 420 // MISCREG_DFSR_S 421 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 422 // MISCREG_IFSR 423 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 424 // MISCREG_IFSR_NS 425 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 426 // MISCREG_IFSR_S 427 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 428 // MISCREG_ADFSR 429 bitset<NUM_MISCREG_INFOS>(string("00000000000000010100")), 430 // MISCREG_ADFSR_NS 431 bitset<NUM_MISCREG_INFOS>(string("11001111110000100100")), 432 // MISCREG_ADFSR_S 433 bitset<NUM_MISCREG_INFOS>(string("00110011000000100100")), 434 // MISCREG_AIFSR 435 bitset<NUM_MISCREG_INFOS>(string("00000000000000010100")), 436 // MISCREG_AIFSR_NS 437 bitset<NUM_MISCREG_INFOS>(string("11001111110000100100")), 438 // MISCREG_AIFSR_S 439 bitset<NUM_MISCREG_INFOS>(string("00110011000000100100")), 440 // MISCREG_HADFSR 441 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 442 // MISCREG_HAIFSR 443 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 444 // MISCREG_HSR 445 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 446 // MISCREG_DFAR 447 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 448 // MISCREG_DFAR_NS 449 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 450 // MISCREG_DFAR_S 451 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 452 // MISCREG_IFAR 453 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 454 // MISCREG_IFAR_NS 455 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 456 // MISCREG_IFAR_S 457 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 458 // MISCREG_HDFAR 459 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 460 // MISCREG_HIFAR 461 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 462 // MISCREG_HPFAR 463 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 464 // MISCREG_ICIALLUIS 465 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 466 // MISCREG_BPIALLIS 467 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 468 // MISCREG_PAR 469 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 470 // MISCREG_PAR_NS 471 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 472 // MISCREG_PAR_S 473 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 474 // MISCREG_ICIALLU 475 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 476 // MISCREG_ICIMVAU 477 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 478 // MISCREG_CP15ISB 479 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")), 480 // MISCREG_BPIALL 481 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 482 // MISCREG_BPIMVA 483 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 484 // MISCREG_DCIMVAC 485 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 486 // MISCREG_DCISW 487 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 488 // MISCREG_ATS1CPR 489 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 490 // MISCREG_ATS1CPW 491 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 492 // MISCREG_ATS1CUR 493 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 494 // MISCREG_ATS1CUW 495 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 496 // MISCREG_ATS12NSOPR 497 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")), 498 // MISCREG_ATS12NSOPW 499 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")), 500 // MISCREG_ATS12NSOUR 501 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")), 502 // MISCREG_ATS12NSOUW 503 bitset<NUM_MISCREG_INFOS>(string("10101010000000000001")), 504 // MISCREG_DCCMVAC 505 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 506 // MISCREG_DCCSW 507 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 508 // MISCREG_CP15DSB 509 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")), 510 // MISCREG_CP15DMB 511 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")), 512 // MISCREG_DCCMVAU 513 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 514 // MISCREG_DCCIMVAC 515 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 516 // MISCREG_DCCISW 517 bitset<NUM_MISCREG_INFOS>(string("10101010100000000100")), 518 // MISCREG_ATS1HR 519 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 520 // MISCREG_ATS1HW 521 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 522 // MISCREG_TLBIALLIS 523 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 524 // MISCREG_TLBIMVAIS 525 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 526 // MISCREG_TLBIASIDIS 527 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 528 // MISCREG_TLBIMVAAIS 529 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 530 // MISCREG_TLBIMVALIS 531 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 532 // MISCREG_TLBIMVAALIS 533 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 534 // MISCREG_ITLBIALL 535 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 536 // MISCREG_ITLBIMVA 537 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 538 // MISCREG_ITLBIASID 539 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 540 // MISCREG_DTLBIALL 541 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 542 // MISCREG_DTLBIMVA 543 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 544 // MISCREG_DTLBIASID 545 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 546 // MISCREG_TLBIALL 547 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 548 // MISCREG_TLBIMVA 549 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 550 // MISCREG_TLBIASID 551 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 552 // MISCREG_TLBIMVAA 553 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 554 // MISCREG_TLBIMVAL 555 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 556 // MISCREG_TLBIMVAAL 557 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 558 // MISCREG_TLBIIPAS2IS 559 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 560 // MISCREG_TLBIIPAS2LIS 561 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 562 // MISCREG_TLBIALLHIS 563 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 564 // MISCREG_TLBIMVAHIS 565 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 566 // MISCREG_TLBIALLNSNHIS 567 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 568 // MISCREG_TLBIMVALHIS 569 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 570 // MISCREG_TLBIIPAS2 571 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 572 // MISCREG_TLBIIPAS2L 573 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 574 // MISCREG_TLBIALLH 575 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 576 // MISCREG_TLBIMVAH 577 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 578 // MISCREG_TLBIALLNSNH 579 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 580 // MISCREG_TLBIMVALH 581 bitset<NUM_MISCREG_INFOS>(string("10001000000000000000")), 582 // MISCREG_PMCR 583 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 584 // MISCREG_PMCNTENSET 585 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 586 // MISCREG_PMCNTENCLR 587 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 588 // MISCREG_PMOVSR 589 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 590 // MISCREG_PMSWINC 591 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 592 // MISCREG_PMSELR 593 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 594 // MISCREG_PMCEID0 595 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 596 // MISCREG_PMCEID1 597 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 598 // MISCREG_PMCCNTR 599 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 600 // MISCREG_PMXEVTYPER 601 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 602 // MISCREG_PMCCFILTR 603 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 604 // MISCREG_PMXEVCNTR 605 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 606 // MISCREG_PMUSERENR 607 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")), 608 // MISCREG_PMINTENSET 609 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 610 // MISCREG_PMINTENCLR 611 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 612 // MISCREG_PMOVSSET 613 bitset<NUM_MISCREG_INFOS>(string("11111111111111000000")), 614 // MISCREG_L2CTLR 615 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 616 // MISCREG_L2ECTLR 617 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 618 // MISCREG_PRRR 619 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 620 // MISCREG_PRRR_NS 621 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 622 // MISCREG_PRRR_S 623 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 624 // MISCREG_MAIR0 625 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 626 // MISCREG_MAIR0_NS 627 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 628 // MISCREG_MAIR0_S 629 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 630 // MISCREG_NMRR 631 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 632 // MISCREG_NMRR_NS 633 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 634 // MISCREG_NMRR_S 635 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 636 // MISCREG_MAIR1 637 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 638 // MISCREG_MAIR1_NS 639 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 640 // MISCREG_MAIR1_S 641 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 642 // MISCREG_AMAIR0 643 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 644 // MISCREG_AMAIR0_NS 645 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 646 // MISCREG_AMAIR0_S 647 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 648 // MISCREG_AMAIR1 649 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 650 // MISCREG_AMAIR1_NS 651 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 652 // MISCREG_AMAIR1_S 653 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 654 // MISCREG_HMAIR0 655 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 656 // MISCREG_HMAIR1 657 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 658 // MISCREG_HAMAIR0 659 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")), 660 // MISCREG_HAMAIR1 661 bitset<NUM_MISCREG_INFOS>(string("11001100000000000100")), 662 // MISCREG_VBAR 663 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 664 // MISCREG_VBAR_NS 665 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 666 // MISCREG_VBAR_S 667 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 668 // MISCREG_MVBAR 669 bitset<NUM_MISCREG_INFOS>(string("11110011000000000001")), 670 // MISCREG_RMR 671 bitset<NUM_MISCREG_INFOS>(string("11110011000000000000")), 672 // MISCREG_ISR 673 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 674 // MISCREG_HVBAR 675 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 676 // MISCREG_FCSEIDR 677 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")), 678 // MISCREG_CONTEXTIDR 679 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 680 // MISCREG_CONTEXTIDR_NS 681 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 682 // MISCREG_CONTEXTIDR_S 683 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 684 // MISCREG_TPIDRURW 685 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 686 // MISCREG_TPIDRURW_NS 687 bitset<NUM_MISCREG_INFOS>(string("11001111111111100001")), 688 // MISCREG_TPIDRURW_S 689 bitset<NUM_MISCREG_INFOS>(string("00110011001100100001")), 690 // MISCREG_TPIDRURO 691 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 692 // MISCREG_TPIDRURO_NS 693 bitset<NUM_MISCREG_INFOS>(string("11001111110101100001")), 694 // MISCREG_TPIDRURO_S 695 bitset<NUM_MISCREG_INFOS>(string("00110011000100100001")), 696 // MISCREG_TPIDRPRW 697 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 698 // MISCREG_TPIDRPRW_NS 699 bitset<NUM_MISCREG_INFOS>(string("11001111110000100001")), 700 // MISCREG_TPIDRPRW_S 701 bitset<NUM_MISCREG_INFOS>(string("00110011000000100001")), 702 // MISCREG_HTPIDR 703 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 704 // MISCREG_CNTFRQ 705 bitset<NUM_MISCREG_INFOS>(string("11110101010101000011")), 706 // MISCREG_CNTKCTL 707 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 708 // MISCREG_CNTP_TVAL 709 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 710 // MISCREG_CNTP_TVAL_NS 711 bitset<NUM_MISCREG_INFOS>(string("11001111111111100001")), 712 // MISCREG_CNTP_TVAL_S 713 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")), 714 // MISCREG_CNTP_CTL 715 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 716 // MISCREG_CNTP_CTL_NS 717 bitset<NUM_MISCREG_INFOS>(string("11001111111111100001")), 718 // MISCREG_CNTP_CTL_S 719 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")), 720 // MISCREG_CNTV_TVAL 721 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 722 // MISCREG_CNTV_CTL 723 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 724 // MISCREG_CNTHCTL 725 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")), 726 // MISCREG_CNTHP_TVAL 727 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")), 728 // MISCREG_CNTHP_CTL 729 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")), 730 // MISCREG_IL1DATA0 731 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 732 // MISCREG_IL1DATA1 733 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 734 // MISCREG_IL1DATA2 735 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 736 // MISCREG_IL1DATA3 737 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 738 // MISCREG_DL1DATA0 739 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 740 // MISCREG_DL1DATA1 741 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 742 // MISCREG_DL1DATA2 743 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 744 // MISCREG_DL1DATA3 745 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 746 // MISCREG_DL1DATA4 747 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 748 // MISCREG_RAMINDEX 749 bitset<NUM_MISCREG_INFOS>(string("10101010100000000000")), 750 // MISCREG_L2ACTLR 751 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 752 // MISCREG_CBAR 753 bitset<NUM_MISCREG_INFOS>(string("01010101010000000000")), 754 // MISCREG_HTTBR 755 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 756 // MISCREG_VTTBR 757 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 758 // MISCREG_CNTPCT 759 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")), 760 // MISCREG_CNTVCT 761 bitset<NUM_MISCREG_INFOS>(string("01010101010101000011")), 762 // MISCREG_CNTP_CVAL 763 bitset<NUM_MISCREG_INFOS>(string("00000000000000010001")), 764 // MISCREG_CNTP_CVAL_NS 765 bitset<NUM_MISCREG_INFOS>(string("11001111111111100001")), 766 // MISCREG_CNTP_CVAL_S 767 bitset<NUM_MISCREG_INFOS>(string("00110011001111100000")), 768 // MISCREG_CNTV_CVAL 769 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 770 // MISCREG_CNTVOFF 771 bitset<NUM_MISCREG_INFOS>(string("11001100000000000001")), 772 // MISCREG_CNTHP_CVAL 773 bitset<NUM_MISCREG_INFOS>(string("01001000000000000000")), 774 // MISCREG_CPUMERRSR 775 bitset<NUM_MISCREG_INFOS>(string("11111111110000000000")), 776 // MISCREG_L2MERRSR 777 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")), 778 779 // AArch64 registers (Op0=2) 780 // MISCREG_MDCCINT_EL1 781 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 782 // MISCREG_OSDTRRX_EL1 783 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 784 // MISCREG_MDSCR_EL1 785 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 786 // MISCREG_OSDTRTX_EL1 787 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 788 // MISCREG_OSECCR_EL1 789 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 790 // MISCREG_DBGBVR0_EL1 791 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 792 // MISCREG_DBGBVR1_EL1 793 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 794 // MISCREG_DBGBVR2_EL1 795 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 796 // MISCREG_DBGBVR3_EL1 797 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 798 // MISCREG_DBGBVR4_EL1 799 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 800 // MISCREG_DBGBVR5_EL1 801 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 802 // MISCREG_DBGBCR0_EL1 803 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 804 // MISCREG_DBGBCR1_EL1 805 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 806 // MISCREG_DBGBCR2_EL1 807 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 808 // MISCREG_DBGBCR3_EL1 809 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 810 // MISCREG_DBGBCR4_EL1 811 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 812 // MISCREG_DBGBCR5_EL1 813 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 814 // MISCREG_DBGWVR0_EL1 815 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 816 // MISCREG_DBGWVR1_EL1 817 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 818 // MISCREG_DBGWVR2_EL1 819 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 820 // MISCREG_DBGWVR3_EL1 821 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 822 // MISCREG_DBGWCR0_EL1 823 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 824 // MISCREG_DBGWCR1_EL1 825 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 826 // MISCREG_DBGWCR2_EL1 827 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 828 // MISCREG_DBGWCR3_EL1 829 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 830 // MISCREG_MDCCSR_EL0 831 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 832 // MISCREG_MDDTR_EL0 833 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 834 // MISCREG_MDDTRTX_EL0 835 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 836 // MISCREG_MDDTRRX_EL0 837 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 838 // MISCREG_DBGVCR32_EL2 839 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 840 // MISCREG_MDRAR_EL1 841 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 842 // MISCREG_OSLAR_EL1 843 bitset<NUM_MISCREG_INFOS>(string("10101111111111000001")), 844 // MISCREG_OSLSR_EL1 845 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 846 // MISCREG_OSDLR_EL1 847 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 848 // MISCREG_DBGPRCR_EL1 849 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 850 // MISCREG_DBGCLAIMSET_EL1 851 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 852 // MISCREG_DBGCLAIMCLR_EL1 853 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 854 // MISCREG_DBGAUTHSTATUS_EL1 855 bitset<NUM_MISCREG_INFOS>(string("01011111111111000001")), 856 // MISCREG_TEECR32_EL1 857 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")), 858 // MISCREG_TEEHBR32_EL1 859 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")), 860 861 // AArch64 registers (Op0=1,3) 862 // MISCREG_MIDR_EL1 863 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 864 // MISCREG_MPIDR_EL1 865 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 866 // MISCREG_REVIDR_EL1 867 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 868 // MISCREG_ID_PFR0_EL1 869 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 870 // MISCREG_ID_PFR1_EL1 871 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 872 // MISCREG_ID_DFR0_EL1 873 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 874 // MISCREG_ID_AFR0_EL1 875 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 876 // MISCREG_ID_MMFR0_EL1 877 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 878 // MISCREG_ID_MMFR1_EL1 879 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 880 // MISCREG_ID_MMFR2_EL1 881 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 882 // MISCREG_ID_MMFR3_EL1 883 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 884 // MISCREG_ID_ISAR0_EL1 885 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 886 // MISCREG_ID_ISAR1_EL1 887 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 888 // MISCREG_ID_ISAR2_EL1 889 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 890 // MISCREG_ID_ISAR3_EL1 891 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 892 // MISCREG_ID_ISAR4_EL1 893 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 894 // MISCREG_ID_ISAR5_EL1 895 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 896 // MISCREG_MVFR0_EL1 897 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 898 // MISCREG_MVFR1_EL1 899 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 900 // MISCREG_MVFR2_EL1 901 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 902 // MISCREG_ID_AA64PFR0_EL1 903 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 904 // MISCREG_ID_AA64PFR1_EL1 905 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 906 // MISCREG_ID_AA64DFR0_EL1 907 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 908 // MISCREG_ID_AA64DFR1_EL1 909 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 910 // MISCREG_ID_AA64AFR0_EL1 911 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 912 // MISCREG_ID_AA64AFR1_EL1 913 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 914 // MISCREG_ID_AA64ISAR0_EL1 915 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 916 // MISCREG_ID_AA64ISAR1_EL1 917 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 918 // MISCREG_ID_AA64MMFR0_EL1 919 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 920 // MISCREG_ID_AA64MMFR1_EL1 921 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 922 // MISCREG_CCSIDR_EL1 923 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 924 // MISCREG_CLIDR_EL1 925 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 926 // MISCREG_AIDR_EL1 927 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 928 // MISCREG_CSSELR_EL1 929 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 930 // MISCREG_CTR_EL0 931 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")), 932 // MISCREG_DCZID_EL0 933 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")), 934 // MISCREG_VPIDR_EL2 935 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 936 // MISCREG_VMPIDR_EL2 937 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 938 // MISCREG_SCTLR_EL1 939 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 940 // MISCREG_ACTLR_EL1 941 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 942 // MISCREG_CPACR_EL1 943 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 944 // MISCREG_SCTLR_EL2 945 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 946 // MISCREG_ACTLR_EL2 947 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 948 // MISCREG_HCR_EL2 949 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 950 // MISCREG_MDCR_EL2 951 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 952 // MISCREG_CPTR_EL2 953 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 954 // MISCREG_HSTR_EL2 955 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 956 // MISCREG_HACR_EL2 957 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 958 // MISCREG_SCTLR_EL3 959 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 960 // MISCREG_ACTLR_EL3 961 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 962 // MISCREG_SCR_EL3 963 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 964 // MISCREG_SDER32_EL3 965 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 966 // MISCREG_CPTR_EL3 967 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 968 // MISCREG_MDCR_EL3 969 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 970 // MISCREG_TTBR0_EL1 971 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 972 // MISCREG_TTBR1_EL1 973 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 974 // MISCREG_TCR_EL1 975 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 976 // MISCREG_TTBR0_EL2 977 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 978 // MISCREG_TCR_EL2 979 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 980 // MISCREG_VTTBR_EL2 981 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 982 // MISCREG_VTCR_EL2 983 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 984 // MISCREG_TTBR0_EL3 985 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 986 // MISCREG_TCR_EL3 987 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 988 // MISCREG_DACR32_EL2 989 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 990 // MISCREG_SPSR_EL1 991 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 992 // MISCREG_ELR_EL1 993 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 994 // MISCREG_SP_EL0 995 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 996 // MISCREG_SPSEL 997 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 998 // MISCREG_CURRENTEL 999 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 1000 // MISCREG_NZCV 1001 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1002 // MISCREG_DAIF 1003 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1004 // MISCREG_FPCR 1005 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1006 // MISCREG_FPSR 1007 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1008 // MISCREG_DSPSR_EL0 1009 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1010 // MISCREG_DLR_EL0 1011 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1012 // MISCREG_SPSR_EL2 1013 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1014 // MISCREG_ELR_EL2 1015 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1016 // MISCREG_SP_EL1 1017 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1018 // MISCREG_SPSR_IRQ_AA64 1019 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1020 // MISCREG_SPSR_ABT_AA64 1021 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1022 // MISCREG_SPSR_UND_AA64 1023 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1024 // MISCREG_SPSR_FIQ_AA64 1025 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1026 // MISCREG_SPSR_EL3 1027 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1028 // MISCREG_ELR_EL3 1029 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1030 // MISCREG_SP_EL2 1031 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1032 // MISCREG_AFSR0_EL1 1033 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1034 // MISCREG_AFSR1_EL1 1035 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1036 // MISCREG_ESR_EL1 1037 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1038 // MISCREG_IFSR32_EL2 1039 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1040 // MISCREG_AFSR0_EL2 1041 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1042 // MISCREG_AFSR1_EL2 1043 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1044 // MISCREG_ESR_EL2 1045 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1046 // MISCREG_FPEXC32_EL2 1047 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1048 // MISCREG_AFSR0_EL3 1049 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1050 // MISCREG_AFSR1_EL3 1051 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1052 // MISCREG_ESR_EL3 1053 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1054 // MISCREG_FAR_EL1 1055 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1056 // MISCREG_FAR_EL2 1057 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1058 // MISCREG_HPFAR_EL2 1059 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1060 // MISCREG_FAR_EL3 1061 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1062 // MISCREG_IC_IALLUIS 1063 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1064 // MISCREG_PAR_EL1 1065 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1066 // MISCREG_IC_IALLU 1067 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1068 // MISCREG_DC_IVAC_Xt 1069 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")), 1070 // MISCREG_DC_ISW_Xt 1071 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1072 // MISCREG_AT_S1E1R_Xt 1073 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1074 // MISCREG_AT_S1E1W_Xt 1075 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1076 // MISCREG_AT_S1E0R_Xt 1077 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1078 // MISCREG_AT_S1E0W_Xt 1079 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1080 // MISCREG_DC_CSW_Xt 1081 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1082 // MISCREG_DC_CISW_Xt 1083 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")), 1084 // MISCREG_DC_ZVA_Xt 1085 bitset<NUM_MISCREG_INFOS>(string("10101010100010000101")), 1086 // MISCREG_IC_IVAU_Xt 1087 bitset<NUM_MISCREG_INFOS>(string("10101010101010000001")), 1088 // MISCREG_DC_CVAC_Xt 1089 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")), 1090 // MISCREG_DC_CVAU_Xt 1091 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")), 1092 // MISCREG_DC_CIVAC_Xt 1093 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")), 1094 // MISCREG_AT_S1E2R_Xt 1095 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1096 // MISCREG_AT_S1E2W_Xt 1097 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1098 // MISCREG_AT_S12E1R_Xt 1099 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1100 // MISCREG_AT_S12E1W_Xt 1101 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1102 // MISCREG_AT_S12E0R_Xt 1103 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1104 // MISCREG_AT_S12E0W_Xt 1105 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1106 // MISCREG_AT_S1E3R_Xt 1107 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1108 // MISCREG_AT_S1E3W_Xt 1109 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1110 // MISCREG_TLBI_VMALLE1IS 1111 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1112 // MISCREG_TLBI_VAE1IS_Xt 1113 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1114 // MISCREG_TLBI_ASIDE1IS_Xt 1115 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1116 // MISCREG_TLBI_VAAE1IS_Xt 1117 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1118 // MISCREG_TLBI_VALE1IS_Xt 1119 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1120 // MISCREG_TLBI_VAALE1IS_Xt 1121 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1122 // MISCREG_TLBI_VMALLE1 1123 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1124 // MISCREG_TLBI_VAE1_Xt 1125 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1126 // MISCREG_TLBI_ASIDE1_Xt 1127 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1128 // MISCREG_TLBI_VAAE1_Xt 1129 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1130 // MISCREG_TLBI_VALE1_Xt 1131 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1132 // MISCREG_TLBI_VAALE1_Xt 1133 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")), 1134 // MISCREG_TLBI_IPAS2E1IS_Xt 1135 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1136 // MISCREG_TLBI_IPAS2LE1IS_Xt 1137 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1138 // MISCREG_TLBI_ALLE2IS 1139 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1140 // MISCREG_TLBI_VAE2IS_Xt 1141 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1142 // MISCREG_TLBI_ALLE1IS 1143 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1144 // MISCREG_TLBI_VALE2IS_Xt 1145 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1146 // MISCREG_TLBI_VMALLS12E1IS 1147 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1148 // MISCREG_TLBI_IPAS2E1_Xt 1149 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1150 // MISCREG_TLBI_IPAS2LE1_Xt 1151 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1152 // MISCREG_TLBI_ALLE2 1153 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1154 // MISCREG_TLBI_VAE2_Xt 1155 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1156 // MISCREG_TLBI_ALLE1 1157 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1158 // MISCREG_TLBI_VALE2_Xt 1159 bitset<NUM_MISCREG_INFOS>(string("10001000000000000001")), 1160 // MISCREG_TLBI_VMALLS12E1 1161 bitset<NUM_MISCREG_INFOS>(string("10101000000000000001")), 1162 // MISCREG_TLBI_ALLE3IS 1163 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1164 // MISCREG_TLBI_VAE3IS_Xt 1165 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1166 // MISCREG_TLBI_VALE3IS_Xt 1167 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1168 // MISCREG_TLBI_ALLE3 1169 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1170 // MISCREG_TLBI_VAE3_Xt 1171 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1172 // MISCREG_TLBI_VALE3_Xt 1173 bitset<NUM_MISCREG_INFOS>(string("10100000000000000001")), 1174 // MISCREG_PMINTENSET_EL1 1175 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1176 // MISCREG_PMINTENCLR_EL1 1177 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1178 // MISCREG_PMCR_EL0 1179 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1180 // MISCREG_PMCNTENSET_EL0 1181 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1182 // MISCREG_PMCNTENCLR_EL0 1183 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1184 // MISCREG_PMOVSCLR_EL0 1185 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1186 // MISCREG_PMSWINC_EL0 1187 bitset<NUM_MISCREG_INFOS>(string("10101010101111000001")), 1188 // MISCREG_PMSELR_EL0 1189 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1190 // MISCREG_PMCEID0_EL0 1191 bitset<NUM_MISCREG_INFOS>(string("01010101011111000001")), 1192 // MISCREG_PMCEID1_EL0 1193 bitset<NUM_MISCREG_INFOS>(string("01010101011111000001")), 1194 // MISCREG_PMCCNTR_EL0 1195 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1196 // MISCREG_PMXEVTYPER_EL0 1197 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1198 // MISCREG_PMCCFILTR_EL0 1199 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1200 // MISCREG_PMXEVCNTR_EL0 1201 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1202 // MISCREG_PMUSERENR_EL0 1203 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")), 1204 // MISCREG_PMOVSSET_EL0 1205 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1206 // MISCREG_MAIR_EL1 1207 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1208 // MISCREG_AMAIR_EL1 1209 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1210 // MISCREG_MAIR_EL2 1211 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1212 // MISCREG_AMAIR_EL2 1213 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1214 // MISCREG_MAIR_EL3 1215 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1216 // MISCREG_AMAIR_EL3 1217 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1218 // MISCREG_L2CTLR_EL1 1219 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1220 // MISCREG_L2ECTLR_EL1 1221 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1222 // MISCREG_VBAR_EL1 1223 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1224 // MISCREG_RVBAR_EL1 1225 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 1226 // MISCREG_ISR_EL1 1227 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 1228 // MISCREG_VBAR_EL2 1229 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1230 // MISCREG_RVBAR_EL2 1231 bitset<NUM_MISCREG_INFOS>(string("01010100000000000001")), 1232 // MISCREG_VBAR_EL3 1233 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1234 // MISCREG_RVBAR_EL3 1235 bitset<NUM_MISCREG_INFOS>(string("01010000000000000001")), 1236 // MISCREG_RMR_EL3 1237 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1238 // MISCREG_CONTEXTIDR_EL1 1239 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1240 // MISCREG_TPIDR_EL1 1241 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1242 // MISCREG_TPIDR_EL0 1243 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1244 // MISCREG_TPIDRRO_EL0 1245 bitset<NUM_MISCREG_INFOS>(string("11111111110101000001")), 1246 // MISCREG_TPIDR_EL2 1247 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1248 // MISCREG_TPIDR_EL3 1249 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")), 1250 // MISCREG_CNTKCTL_EL1 1251 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1252 // MISCREG_CNTFRQ_EL0 1253 bitset<NUM_MISCREG_INFOS>(string("11110101010101000001")), 1254 // MISCREG_CNTPCT_EL0 1255 bitset<NUM_MISCREG_INFOS>(string("01010101010101000001")), 1256 // MISCREG_CNTVCT_EL0 1257 bitset<NUM_MISCREG_INFOS>(string("01010101010101000011")), 1258 // MISCREG_CNTP_TVAL_EL0 1259 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1260 // MISCREG_CNTP_CTL_EL0 1261 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1262 // MISCREG_CNTP_CVAL_EL0 1263 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1264 // MISCREG_CNTV_TVAL_EL0 1265 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1266 // MISCREG_CNTV_CTL_EL0 1267 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1268 // MISCREG_CNTV_CVAL_EL0 1269 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1270 // MISCREG_PMEVCNTR0_EL0 1271 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1272 // MISCREG_PMEVCNTR1_EL0 1273 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1274 // MISCREG_PMEVCNTR2_EL0 1275 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1276 // MISCREG_PMEVCNTR3_EL0 1277 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1278 // MISCREG_PMEVCNTR4_EL0 1279 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1280 // MISCREG_PMEVCNTR5_EL0 1281 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1282 // MISCREG_PMEVTYPER0_EL0 1283 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1284 // MISCREG_PMEVTYPER1_EL0 1285 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1286 // MISCREG_PMEVTYPER2_EL0 1287 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1288 // MISCREG_PMEVTYPER3_EL0 1289 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1290 // MISCREG_PMEVTYPER4_EL0 1291 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1292 // MISCREG_PMEVTYPER5_EL0 1293 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1294 // MISCREG_CNTVOFF_EL2 1295 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1296 // MISCREG_CNTHCTL_EL2 1297 bitset<NUM_MISCREG_INFOS>(string("01111000000000000100")), 1298 // MISCREG_CNTHP_TVAL_EL2 1299 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1300 // MISCREG_CNTHP_CTL_EL2 1301 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1302 // MISCREG_CNTHP_CVAL_EL2 1303 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1304 // MISCREG_CNTPS_TVAL_EL1 1305 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1306 // MISCREG_CNTPS_CTL_EL1 1307 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1308 // MISCREG_CNTPS_CVAL_EL1 1309 bitset<NUM_MISCREG_INFOS>(string("01111000000000000000")), 1310 // MISCREG_IL1DATA0_EL1 1311 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1312 // MISCREG_IL1DATA1_EL1 1313 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1314 // MISCREG_IL1DATA2_EL1 1315 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1316 // MISCREG_IL1DATA3_EL1 1317 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1318 // MISCREG_DL1DATA0_EL1 1319 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1320 // MISCREG_DL1DATA1_EL1 1321 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1322 // MISCREG_DL1DATA2_EL1 1323 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1324 // MISCREG_DL1DATA3_EL1 1325 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1326 // MISCREG_DL1DATA4_EL1 1327 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1328 // MISCREG_L2ACTLR_EL1 1329 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1330 // MISCREG_CPUACTLR_EL1 1331 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1332 // MISCREG_CPUECTLR_EL1 1333 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1334 // MISCREG_CPUMERRSR_EL1 1335 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")), 1336 // MISCREG_L2MERRSR_EL1 1337 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")), 1338 // MISCREG_CBAR_EL1 1339 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 1340 // MISCREG_CONTEXTIDR_EL2 1341 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), 1342 1343 // Dummy registers 1344 // MISCREG_NOP 1345 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")), 1346 // MISCREG_RAZ 1347 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), 1348 // MISCREG_CP14_UNIMPL 1349 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")), 1350 // MISCREG_CP15_UNIMPL 1351 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")), 1352 // MISCREG_A64_UNIMPL 1353 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")), 1354 // MISCREG_UNKNOWN 1355 bitset<NUM_MISCREG_INFOS>(string("00000000000000000001")) 1356}; 1357
1358MiscRegIndex 1359decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 1360{ 1361 switch (crn) { 1362 case 0: 1363 switch (opc1) { 1364 case 0: 1365 switch (crm) { --- 2190 unchanged lines hidden (view full) --- 3556 break; 3557 } 3558 break; 3559 } 3560 3561 return MISCREG_UNKNOWN; 3562} 3563	131MiscRegIndex 132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 133{ 134 switch (crn) { 135 case 0: 136 switch (opc1) { 137 case 0: 138 switch (crm) { --- 2190 unchanged lines hidden (view full) --- 2329 break; 2330 } 2331 break; 2332 } 2333 2334 return MISCREG_UNKNOWN; 2335} 2336
	2337bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below 2338 2339void 2340ISA::initializeMiscRegMetadata() 2341{ 2342 // the MiscReg metadata tables are shared across all instances of the 2343 // ISA object, so there's no need to initialize them multiple times. 2344 static bool completed = false; 2345 if (completed) 2346 return; 2347 2348 /** 2349 * Some registers alias with others, and therefore need to be translated. 2350 * When two mapping registers are given, they are the 32b lower and 2351 * upper halves, respectively, of the 64b register being mapped. 2352 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 2353 * 2354 * NAM = "not architecturally mandated", 2355 * from ARM DDI 0487A.i, template text 2356 * "AArch64 System register ___ can be mapped to 2357 * AArch32 System register ___, but this is not 2358 * architecturally mandated." 2359 / 2360* 2361 InitReg(MISCREG_CPSR) 2362 .allPrivileges(); 2363 InitReg(MISCREG_SPSR) 2364 .allPrivileges(); 2365 InitReg(MISCREG_SPSR_FIQ) 2366 .allPrivileges(); 2367 InitReg(MISCREG_SPSR_IRQ) 2368 .allPrivileges(); 2369 InitReg(MISCREG_SPSR_SVC) 2370 .allPrivileges(); 2371 InitReg(MISCREG_SPSR_MON) 2372 .allPrivileges(); 2373 InitReg(MISCREG_SPSR_ABT) 2374 .allPrivileges(); 2375 InitReg(MISCREG_SPSR_HYP) 2376 .allPrivileges(); 2377 InitReg(MISCREG_SPSR_UND) 2378 .allPrivileges(); 2379 InitReg(MISCREG_ELR_HYP) 2380 .allPrivileges(); 2381 InitReg(MISCREG_FPSID) 2382 .allPrivileges(); 2383 InitReg(MISCREG_FPSCR) 2384 .allPrivileges(); 2385 InitReg(MISCREG_MVFR1) 2386 .allPrivileges(); 2387 InitReg(MISCREG_MVFR0) 2388 .allPrivileges(); 2389 InitReg(MISCREG_FPEXC) 2390 .allPrivileges(); 2391 2392 // Helper registers 2393 InitReg(MISCREG_CPSR_MODE) 2394 .allPrivileges(); 2395 InitReg(MISCREG_CPSR_Q) 2396 .allPrivileges(); 2397 InitReg(MISCREG_FPSCR_EXC) 2398 .allPrivileges(); 2399 InitReg(MISCREG_FPSCR_QC) 2400 .allPrivileges(); 2401 InitReg(MISCREG_LOCKADDR) 2402 .allPrivileges(); 2403 InitReg(MISCREG_LOCKFLAG) 2404 .allPrivileges(); 2405 InitReg(MISCREG_PRRR_MAIR0) 2406 .mutex() 2407 .banked(); 2408 InitReg(MISCREG_PRRR_MAIR0_NS) 2409 .mutex() 2410 .bankedChild(); 2411 InitReg(MISCREG_PRRR_MAIR0_S) 2412 .mutex() 2413 .bankedChild(); 2414 InitReg(MISCREG_NMRR_MAIR1) 2415 .mutex() 2416 .banked(); 2417 InitReg(MISCREG_NMRR_MAIR1_NS) 2418 .mutex() 2419 .bankedChild(); 2420 InitReg(MISCREG_NMRR_MAIR1_S) 2421 .mutex() 2422 .bankedChild(); 2423 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR) 2424 .mutex(); 2425 InitReg(MISCREG_SCTLR_RST) 2426 .allPrivileges(); 2427 InitReg(MISCREG_SEV_MAILBOX) 2428 .allPrivileges(); 2429 2430 // AArch32 CP14 registers 2431 InitReg(MISCREG_DBGDIDR) 2432 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2433 InitReg(MISCREG_DBGDSCRint) 2434 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2435 InitReg(MISCREG_DBGDCCINT) 2436 .unimplemented() 2437 .allPrivileges(); 2438 InitReg(MISCREG_DBGDTRTXint) 2439 .unimplemented() 2440 .allPrivileges(); 2441 InitReg(MISCREG_DBGDTRRXint) 2442 .unimplemented() 2443 .allPrivileges(); 2444 InitReg(MISCREG_DBGWFAR) 2445 .unimplemented() 2446 .allPrivileges(); 2447 InitReg(MISCREG_DBGVCR) 2448 .unimplemented() 2449 .allPrivileges(); 2450 InitReg(MISCREG_DBGDTRRXext) 2451 .unimplemented() 2452 .allPrivileges(); 2453 InitReg(MISCREG_DBGDSCRext) 2454 .unimplemented() 2455 .warnNotFail() 2456 .allPrivileges(); 2457 InitReg(MISCREG_DBGDTRTXext) 2458 .unimplemented() 2459 .allPrivileges(); 2460 InitReg(MISCREG_DBGOSECCR) 2461 .unimplemented() 2462 .allPrivileges(); 2463 InitReg(MISCREG_DBGBVR0) 2464 .unimplemented() 2465 .allPrivileges(); 2466 InitReg(MISCREG_DBGBVR1) 2467 .unimplemented() 2468 .allPrivileges(); 2469 InitReg(MISCREG_DBGBVR2) 2470 .unimplemented() 2471 .allPrivileges(); 2472 InitReg(MISCREG_DBGBVR3) 2473 .unimplemented() 2474 .allPrivileges(); 2475 InitReg(MISCREG_DBGBVR4) 2476 .unimplemented() 2477 .allPrivileges(); 2478 InitReg(MISCREG_DBGBVR5) 2479 .unimplemented() 2480 .allPrivileges(); 2481 InitReg(MISCREG_DBGBCR0) 2482 .unimplemented() 2483 .allPrivileges(); 2484 InitReg(MISCREG_DBGBCR1) 2485 .unimplemented() 2486 .allPrivileges(); 2487 InitReg(MISCREG_DBGBCR2) 2488 .unimplemented() 2489 .allPrivileges(); 2490 InitReg(MISCREG_DBGBCR3) 2491 .unimplemented() 2492 .allPrivileges(); 2493 InitReg(MISCREG_DBGBCR4) 2494 .unimplemented() 2495 .allPrivileges(); 2496 InitReg(MISCREG_DBGBCR5) 2497 .unimplemented() 2498 .allPrivileges(); 2499 InitReg(MISCREG_DBGWVR0) 2500 .unimplemented() 2501 .allPrivileges(); 2502 InitReg(MISCREG_DBGWVR1) 2503 .unimplemented() 2504 .allPrivileges(); 2505 InitReg(MISCREG_DBGWVR2) 2506 .unimplemented() 2507 .allPrivileges(); 2508 InitReg(MISCREG_DBGWVR3) 2509 .unimplemented() 2510 .allPrivileges(); 2511 InitReg(MISCREG_DBGWCR0) 2512 .unimplemented() 2513 .allPrivileges(); 2514 InitReg(MISCREG_DBGWCR1) 2515 .unimplemented() 2516 .allPrivileges(); 2517 InitReg(MISCREG_DBGWCR2) 2518 .unimplemented() 2519 .allPrivileges(); 2520 InitReg(MISCREG_DBGWCR3) 2521 .unimplemented() 2522 .allPrivileges(); 2523 InitReg(MISCREG_DBGDRAR) 2524 .unimplemented() 2525 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2526 InitReg(MISCREG_DBGBXVR4) 2527 .unimplemented() 2528 .allPrivileges(); 2529 InitReg(MISCREG_DBGBXVR5) 2530 .unimplemented() 2531 .allPrivileges(); 2532 InitReg(MISCREG_DBGOSLAR) 2533 .unimplemented() 2534 .allPrivileges().monSecureRead(0).monNonSecureRead(0); 2535 InitReg(MISCREG_DBGOSLSR) 2536 .unimplemented() 2537 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2538 InitReg(MISCREG_DBGOSDLR) 2539 .unimplemented() 2540 .allPrivileges(); 2541 InitReg(MISCREG_DBGPRCR) 2542 .unimplemented() 2543 .allPrivileges(); 2544 InitReg(MISCREG_DBGDSAR) 2545 .unimplemented() 2546 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2547 InitReg(MISCREG_DBGCLAIMSET) 2548 .unimplemented() 2549 .allPrivileges(); 2550 InitReg(MISCREG_DBGCLAIMCLR) 2551 .unimplemented() 2552 .allPrivileges(); 2553 InitReg(MISCREG_DBGAUTHSTATUS) 2554 .unimplemented() 2555 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2556 InitReg(MISCREG_DBGDEVID2) 2557 .unimplemented() 2558 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2559 InitReg(MISCREG_DBGDEVID1) 2560 .unimplemented() 2561 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2562 InitReg(MISCREG_DBGDEVID0) 2563 .unimplemented() 2564 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2565 InitReg(MISCREG_TEECR) 2566 .unimplemented() 2567 .allPrivileges(); 2568 InitReg(MISCREG_JIDR) 2569 .allPrivileges(); 2570 InitReg(MISCREG_TEEHBR) 2571 .allPrivileges(); 2572 InitReg(MISCREG_JOSCR) 2573 .allPrivileges(); 2574 InitReg(MISCREG_JMCR) 2575 .allPrivileges(); 2576 2577 // AArch32 CP15 registers 2578 InitReg(MISCREG_MIDR) 2579 .allPrivileges().exceptUserMode().writes(0); 2580 InitReg(MISCREG_CTR) 2581 .allPrivileges().exceptUserMode().writes(0); 2582 InitReg(MISCREG_TCMTR) 2583 .allPrivileges().exceptUserMode().writes(0); 2584 InitReg(MISCREG_TLBTR) 2585 .allPrivileges().exceptUserMode().writes(0); 2586 InitReg(MISCREG_MPIDR) 2587 .allPrivileges().exceptUserMode().writes(0); 2588 InitReg(MISCREG_REVIDR) 2589 .unimplemented() 2590 .warnNotFail() 2591 .allPrivileges().exceptUserMode().writes(0); 2592 InitReg(MISCREG_ID_PFR0) 2593 .allPrivileges().exceptUserMode().writes(0); 2594 InitReg(MISCREG_ID_PFR1) 2595 .allPrivileges().exceptUserMode().writes(0); 2596 InitReg(MISCREG_ID_DFR0) 2597 .allPrivileges().exceptUserMode().writes(0); 2598 InitReg(MISCREG_ID_AFR0) 2599 .allPrivileges().exceptUserMode().writes(0); 2600 InitReg(MISCREG_ID_MMFR0) 2601 .allPrivileges().exceptUserMode().writes(0); 2602 InitReg(MISCREG_ID_MMFR1) 2603 .allPrivileges().exceptUserMode().writes(0); 2604 InitReg(MISCREG_ID_MMFR2) 2605 .allPrivileges().exceptUserMode().writes(0); 2606 InitReg(MISCREG_ID_MMFR3) 2607 .allPrivileges().exceptUserMode().writes(0); 2608 InitReg(MISCREG_ID_ISAR0) 2609 .allPrivileges().exceptUserMode().writes(0); 2610 InitReg(MISCREG_ID_ISAR1) 2611 .allPrivileges().exceptUserMode().writes(0); 2612 InitReg(MISCREG_ID_ISAR2) 2613 .allPrivileges().exceptUserMode().writes(0); 2614 InitReg(MISCREG_ID_ISAR3) 2615 .allPrivileges().exceptUserMode().writes(0); 2616 InitReg(MISCREG_ID_ISAR4) 2617 .allPrivileges().exceptUserMode().writes(0); 2618 InitReg(MISCREG_ID_ISAR5) 2619 .allPrivileges().exceptUserMode().writes(0); 2620 InitReg(MISCREG_CCSIDR) 2621 .allPrivileges().exceptUserMode().writes(0); 2622 InitReg(MISCREG_CLIDR) 2623 .allPrivileges().exceptUserMode().writes(0); 2624 InitReg(MISCREG_AIDR) 2625 .allPrivileges().exceptUserMode().writes(0); 2626 InitReg(MISCREG_CSSELR) 2627 .banked(); 2628 InitReg(MISCREG_CSSELR_NS) 2629 .bankedChild() 2630 .nonSecure().exceptUserMode(); 2631 InitReg(MISCREG_CSSELR_S) 2632 .bankedChild() 2633 .secure().exceptUserMode(); 2634 InitReg(MISCREG_VPIDR) 2635 .hyp().monNonSecure(); 2636 InitReg(MISCREG_VMPIDR) 2637 .hyp().monNonSecure(); 2638 InitReg(MISCREG_SCTLR) 2639 .banked(); 2640 InitReg(MISCREG_SCTLR_NS) 2641 .bankedChild() 2642 .nonSecure().exceptUserMode(); 2643 InitReg(MISCREG_SCTLR_S) 2644 .bankedChild() 2645 .secure().exceptUserMode(); 2646 InitReg(MISCREG_ACTLR) 2647 .banked(); 2648 InitReg(MISCREG_ACTLR_NS) 2649 .bankedChild() 2650 .nonSecure().exceptUserMode(); 2651 InitReg(MISCREG_ACTLR_S) 2652 .bankedChild() 2653 .secure().exceptUserMode(); 2654 InitReg(MISCREG_CPACR) 2655 .allPrivileges().exceptUserMode(); 2656 InitReg(MISCREG_SCR) 2657 .mon().secure().exceptUserMode() 2658 .res0(0xff40) // [31:16], [6] 2659 .res1(0x0030); // [5:4] 2660 InitReg(MISCREG_SDER) 2661 .mon(); 2662 InitReg(MISCREG_NSACR) 2663 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode(); 2664 InitReg(MISCREG_HSCTLR) 2665 .hyp().monNonSecure(); 2666 InitReg(MISCREG_HACTLR) 2667 .hyp().monNonSecure(); 2668 InitReg(MISCREG_HCR) 2669 .hyp().monNonSecure(); 2670 InitReg(MISCREG_HDCR) 2671 .hyp().monNonSecure(); 2672 InitReg(MISCREG_HCPTR) 2673 .hyp().monNonSecure(); 2674 InitReg(MISCREG_HSTR) 2675 .hyp().monNonSecure(); 2676 InitReg(MISCREG_HACR) 2677 .unimplemented() 2678 .warnNotFail() 2679 .hyp().monNonSecure(); 2680 InitReg(MISCREG_TTBR0) 2681 .banked(); 2682 InitReg(MISCREG_TTBR0_NS) 2683 .bankedChild() 2684 .nonSecure().exceptUserMode(); 2685 InitReg(MISCREG_TTBR0_S) 2686 .bankedChild() 2687 .secure().exceptUserMode(); 2688 InitReg(MISCREG_TTBR1) 2689 .banked(); 2690 InitReg(MISCREG_TTBR1_NS) 2691 .bankedChild() 2692 .nonSecure().exceptUserMode(); 2693 InitReg(MISCREG_TTBR1_S) 2694 .bankedChild() 2695 .secure().exceptUserMode(); 2696 InitReg(MISCREG_TTBCR) 2697 .banked(); 2698 InitReg(MISCREG_TTBCR_NS) 2699 .bankedChild() 2700 .nonSecure().exceptUserMode(); 2701 InitReg(MISCREG_TTBCR_S) 2702 .bankedChild() 2703 .secure().exceptUserMode(); 2704 InitReg(MISCREG_HTCR) 2705 .hyp().monNonSecure(); 2706 InitReg(MISCREG_VTCR) 2707 .hyp().monNonSecure(); 2708 InitReg(MISCREG_DACR) 2709 .banked(); 2710 InitReg(MISCREG_DACR_NS) 2711 .bankedChild() 2712 .nonSecure().exceptUserMode(); 2713 InitReg(MISCREG_DACR_S) 2714 .bankedChild() 2715 .secure().exceptUserMode(); 2716 InitReg(MISCREG_DFSR) 2717 .banked(); 2718 InitReg(MISCREG_DFSR_NS) 2719 .bankedChild() 2720 .nonSecure().exceptUserMode(); 2721 InitReg(MISCREG_DFSR_S) 2722 .bankedChild() 2723 .secure().exceptUserMode(); 2724 InitReg(MISCREG_IFSR) 2725 .banked(); 2726 InitReg(MISCREG_IFSR_NS) 2727 .bankedChild() 2728 .nonSecure().exceptUserMode(); 2729 InitReg(MISCREG_IFSR_S) 2730 .bankedChild() 2731 .secure().exceptUserMode(); 2732 InitReg(MISCREG_ADFSR) 2733 .unimplemented() 2734 .warnNotFail() 2735 .banked(); 2736 InitReg(MISCREG_ADFSR_NS) 2737 .unimplemented() 2738 .warnNotFail() 2739 .bankedChild() 2740 .nonSecure().exceptUserMode(); 2741 InitReg(MISCREG_ADFSR_S) 2742 .unimplemented() 2743 .warnNotFail() 2744 .bankedChild() 2745 .secure().exceptUserMode(); 2746 InitReg(MISCREG_AIFSR) 2747 .unimplemented() 2748 .warnNotFail() 2749 .banked(); 2750 InitReg(MISCREG_AIFSR_NS) 2751 .unimplemented() 2752 .warnNotFail() 2753 .bankedChild() 2754 .nonSecure().exceptUserMode(); 2755 InitReg(MISCREG_AIFSR_S) 2756 .unimplemented() 2757 .warnNotFail() 2758 .bankedChild() 2759 .secure().exceptUserMode(); 2760 InitReg(MISCREG_HADFSR) 2761 .hyp().monNonSecure(); 2762 InitReg(MISCREG_HAIFSR) 2763 .hyp().monNonSecure(); 2764 InitReg(MISCREG_HSR) 2765 .hyp().monNonSecure(); 2766 InitReg(MISCREG_DFAR) 2767 .banked(); 2768 InitReg(MISCREG_DFAR_NS) 2769 .bankedChild() 2770 .nonSecure().exceptUserMode(); 2771 InitReg(MISCREG_DFAR_S) 2772 .bankedChild() 2773 .secure().exceptUserMode(); 2774 InitReg(MISCREG_IFAR) 2775 .banked(); 2776 InitReg(MISCREG_IFAR_NS) 2777 .bankedChild() 2778 .nonSecure().exceptUserMode(); 2779 InitReg(MISCREG_IFAR_S) 2780 .bankedChild() 2781 .secure().exceptUserMode(); 2782 InitReg(MISCREG_HDFAR) 2783 .hyp().monNonSecure(); 2784 InitReg(MISCREG_HIFAR) 2785 .hyp().monNonSecure(); 2786 InitReg(MISCREG_HPFAR) 2787 .hyp().monNonSecure(); 2788 InitReg(MISCREG_ICIALLUIS) 2789 .unimplemented() 2790 .warnNotFail() 2791 .writes(1).exceptUserMode(); 2792 InitReg(MISCREG_BPIALLIS) 2793 .unimplemented() 2794 .warnNotFail() 2795 .writes(1).exceptUserMode(); 2796 InitReg(MISCREG_PAR) 2797 .banked(); 2798 InitReg(MISCREG_PAR_NS) 2799 .bankedChild() 2800 .nonSecure().exceptUserMode(); 2801 InitReg(MISCREG_PAR_S) 2802 .bankedChild() 2803 .secure().exceptUserMode(); 2804 InitReg(MISCREG_ICIALLU) 2805 .writes(1).exceptUserMode(); 2806 InitReg(MISCREG_ICIMVAU) 2807 .unimplemented() 2808 .warnNotFail() 2809 .writes(1).exceptUserMode(); 2810 InitReg(MISCREG_CP15ISB) 2811 .writes(1); 2812 InitReg(MISCREG_BPIALL) 2813 .unimplemented() 2814 .warnNotFail() 2815 .writes(1).exceptUserMode(); 2816 InitReg(MISCREG_BPIMVA) 2817 .unimplemented() 2818 .warnNotFail() 2819 .writes(1).exceptUserMode(); 2820 InitReg(MISCREG_DCIMVAC) 2821 .unimplemented() 2822 .warnNotFail() 2823 .writes(1).exceptUserMode(); 2824 InitReg(MISCREG_DCISW) 2825 .unimplemented() 2826 .warnNotFail() 2827 .writes(1).exceptUserMode(); 2828 InitReg(MISCREG_ATS1CPR) 2829 .writes(1).exceptUserMode(); 2830 InitReg(MISCREG_ATS1CPW) 2831 .writes(1).exceptUserMode(); 2832 InitReg(MISCREG_ATS1CUR) 2833 .writes(1).exceptUserMode(); 2834 InitReg(MISCREG_ATS1CUW) 2835 .writes(1).exceptUserMode(); 2836 InitReg(MISCREG_ATS12NSOPR) 2837 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2838 InitReg(MISCREG_ATS12NSOPW) 2839 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2840 InitReg(MISCREG_ATS12NSOUR) 2841 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2842 InitReg(MISCREG_ATS12NSOUW) 2843 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2844 InitReg(MISCREG_DCCMVAC) 2845 .writes(1).exceptUserMode(); 2846 InitReg(MISCREG_DCCSW) 2847 .unimplemented() 2848 .warnNotFail() 2849 .writes(1).exceptUserMode(); 2850 InitReg(MISCREG_CP15DSB) 2851 .writes(1); 2852 InitReg(MISCREG_CP15DMB) 2853 .writes(1); 2854 InitReg(MISCREG_DCCMVAU) 2855 .unimplemented() 2856 .warnNotFail() 2857 .writes(1).exceptUserMode(); 2858 InitReg(MISCREG_DCCIMVAC) 2859 .unimplemented() 2860 .warnNotFail() 2861 .writes(1).exceptUserMode(); 2862 InitReg(MISCREG_DCCISW) 2863 .unimplemented() 2864 .warnNotFail() 2865 .writes(1).exceptUserMode(); 2866 InitReg(MISCREG_ATS1HR) 2867 .monNonSecureWrite().hypWrite(); 2868 InitReg(MISCREG_ATS1HW) 2869 .monNonSecureWrite().hypWrite(); 2870 InitReg(MISCREG_TLBIALLIS) 2871 .writes(1).exceptUserMode(); 2872 InitReg(MISCREG_TLBIMVAIS) 2873 .writes(1).exceptUserMode(); 2874 InitReg(MISCREG_TLBIASIDIS) 2875 .writes(1).exceptUserMode(); 2876 InitReg(MISCREG_TLBIMVAAIS) 2877 .writes(1).exceptUserMode(); 2878 InitReg(MISCREG_TLBIMVALIS) 2879 .unimplemented() 2880 .writes(1).exceptUserMode(); 2881 InitReg(MISCREG_TLBIMVAALIS) 2882 .unimplemented() 2883 .writes(1).exceptUserMode(); 2884 InitReg(MISCREG_ITLBIALL) 2885 .writes(1).exceptUserMode(); 2886 InitReg(MISCREG_ITLBIMVA) 2887 .writes(1).exceptUserMode(); 2888 InitReg(MISCREG_ITLBIASID) 2889 .writes(1).exceptUserMode(); 2890 InitReg(MISCREG_DTLBIALL) 2891 .writes(1).exceptUserMode(); 2892 InitReg(MISCREG_DTLBIMVA) 2893 .writes(1).exceptUserMode(); 2894 InitReg(MISCREG_DTLBIASID) 2895 .writes(1).exceptUserMode(); 2896 InitReg(MISCREG_TLBIALL) 2897 .writes(1).exceptUserMode(); 2898 InitReg(MISCREG_TLBIMVA) 2899 .writes(1).exceptUserMode(); 2900 InitReg(MISCREG_TLBIASID) 2901 .writes(1).exceptUserMode(); 2902 InitReg(MISCREG_TLBIMVAA) 2903 .writes(1).exceptUserMode(); 2904 InitReg(MISCREG_TLBIMVAL) 2905 .unimplemented() 2906 .writes(1).exceptUserMode(); 2907 InitReg(MISCREG_TLBIMVAAL) 2908 .unimplemented() 2909 .writes(1).exceptUserMode(); 2910 InitReg(MISCREG_TLBIIPAS2IS) 2911 .unimplemented() 2912 .monNonSecureWrite().hypWrite(); 2913 InitReg(MISCREG_TLBIIPAS2LIS) 2914 .unimplemented() 2915 .monNonSecureWrite().hypWrite(); 2916 InitReg(MISCREG_TLBIALLHIS) 2917 .monNonSecureWrite().hypWrite(); 2918 InitReg(MISCREG_TLBIMVAHIS) 2919 .monNonSecureWrite().hypWrite(); 2920 InitReg(MISCREG_TLBIALLNSNHIS) 2921 .monNonSecureWrite().hypWrite(); 2922 InitReg(MISCREG_TLBIMVALHIS) 2923 .unimplemented() 2924 .monNonSecureWrite().hypWrite(); 2925 InitReg(MISCREG_TLBIIPAS2) 2926 .unimplemented() 2927 .monNonSecureWrite().hypWrite(); 2928 InitReg(MISCREG_TLBIIPAS2L) 2929 .unimplemented() 2930 .monNonSecureWrite().hypWrite(); 2931 InitReg(MISCREG_TLBIALLH) 2932 .monNonSecureWrite().hypWrite(); 2933 InitReg(MISCREG_TLBIMVAH) 2934 .monNonSecureWrite().hypWrite(); 2935 InitReg(MISCREG_TLBIALLNSNH) 2936 .monNonSecureWrite().hypWrite(); 2937 InitReg(MISCREG_TLBIMVALH) 2938 .unimplemented() 2939 .monNonSecureWrite().hypWrite(); 2940 InitReg(MISCREG_PMCR) 2941 .allPrivileges(); 2942 InitReg(MISCREG_PMCNTENSET) 2943 .allPrivileges(); 2944 InitReg(MISCREG_PMCNTENCLR) 2945 .allPrivileges(); 2946 InitReg(MISCREG_PMOVSR) 2947 .allPrivileges(); 2948 InitReg(MISCREG_PMSWINC) 2949 .allPrivileges(); 2950 InitReg(MISCREG_PMSELR) 2951 .allPrivileges(); 2952 InitReg(MISCREG_PMCEID0) 2953 .allPrivileges(); 2954 InitReg(MISCREG_PMCEID1) 2955 .allPrivileges(); 2956 InitReg(MISCREG_PMCCNTR) 2957 .allPrivileges(); 2958 InitReg(MISCREG_PMXEVTYPER) 2959 .allPrivileges(); 2960 InitReg(MISCREG_PMCCFILTR) 2961 .allPrivileges(); 2962 InitReg(MISCREG_PMXEVCNTR) 2963 .allPrivileges(); 2964 InitReg(MISCREG_PMUSERENR) 2965 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0); 2966 InitReg(MISCREG_PMINTENSET) 2967 .allPrivileges().exceptUserMode(); 2968 InitReg(MISCREG_PMINTENCLR) 2969 .allPrivileges().exceptUserMode(); 2970 InitReg(MISCREG_PMOVSSET) 2971 .unimplemented() 2972 .allPrivileges(); 2973 InitReg(MISCREG_L2CTLR) 2974 .allPrivileges().exceptUserMode(); 2975 InitReg(MISCREG_L2ECTLR) 2976 .unimplemented() 2977 .allPrivileges().exceptUserMode(); 2978 InitReg(MISCREG_PRRR) 2979 .banked(); 2980 InitReg(MISCREG_PRRR_NS) 2981 .bankedChild() 2982 .nonSecure().exceptUserMode(); 2983 InitReg(MISCREG_PRRR_S) 2984 .bankedChild() 2985 .secure().exceptUserMode(); 2986 InitReg(MISCREG_MAIR0) 2987 .banked(); 2988 InitReg(MISCREG_MAIR0_NS) 2989 .bankedChild() 2990 .nonSecure().exceptUserMode(); 2991 InitReg(MISCREG_MAIR0_S) 2992 .bankedChild() 2993 .secure().exceptUserMode(); 2994 InitReg(MISCREG_NMRR) 2995 .banked(); 2996 InitReg(MISCREG_NMRR_NS) 2997 .bankedChild() 2998 .nonSecure().exceptUserMode(); 2999 InitReg(MISCREG_NMRR_S) 3000 .bankedChild() 3001 .secure().exceptUserMode(); 3002 InitReg(MISCREG_MAIR1) 3003 .banked(); 3004 InitReg(MISCREG_MAIR1_NS) 3005 .bankedChild() 3006 .nonSecure().exceptUserMode(); 3007 InitReg(MISCREG_MAIR1_S) 3008 .bankedChild() 3009 .secure().exceptUserMode(); 3010 InitReg(MISCREG_AMAIR0) 3011 .banked(); 3012 InitReg(MISCREG_AMAIR0_NS) 3013 .bankedChild() 3014 .nonSecure().exceptUserMode(); 3015 InitReg(MISCREG_AMAIR0_S) 3016 .bankedChild() 3017 .secure().exceptUserMode(); 3018 InitReg(MISCREG_AMAIR1) 3019 .banked(); 3020 InitReg(MISCREG_AMAIR1_NS) 3021 .bankedChild() 3022 .nonSecure().exceptUserMode(); 3023 InitReg(MISCREG_AMAIR1_S) 3024 .bankedChild() 3025 .secure().exceptUserMode(); 3026 InitReg(MISCREG_HMAIR0) 3027 .hyp().monNonSecure(); 3028 InitReg(MISCREG_HMAIR1) 3029 .hyp().monNonSecure(); 3030 InitReg(MISCREG_HAMAIR0) 3031 .unimplemented() 3032 .warnNotFail() 3033 .hyp().monNonSecure(); 3034 InitReg(MISCREG_HAMAIR1) 3035 .unimplemented() 3036 .warnNotFail() 3037 .hyp().monNonSecure(); 3038 InitReg(MISCREG_VBAR) 3039 .banked(); 3040 InitReg(MISCREG_VBAR_NS) 3041 .bankedChild() 3042 .nonSecure().exceptUserMode(); 3043 InitReg(MISCREG_VBAR_S) 3044 .bankedChild() 3045 .secure().exceptUserMode(); 3046 InitReg(MISCREG_MVBAR) 3047 .mon().secure().exceptUserMode(); 3048 InitReg(MISCREG_RMR) 3049 .unimplemented() 3050 .mon().secure().exceptUserMode(); 3051 InitReg(MISCREG_ISR) 3052 .allPrivileges().exceptUserMode().writes(0); 3053 InitReg(MISCREG_HVBAR) 3054 .hyp().monNonSecure(); 3055 InitReg(MISCREG_FCSEIDR) 3056 .unimplemented() 3057 .warnNotFail() 3058 .allPrivileges().exceptUserMode(); 3059 InitReg(MISCREG_CONTEXTIDR) 3060 .banked(); 3061 InitReg(MISCREG_CONTEXTIDR_NS) 3062 .bankedChild() 3063 .nonSecure().exceptUserMode(); 3064 InitReg(MISCREG_CONTEXTIDR_S) 3065 .bankedChild() 3066 .secure().exceptUserMode(); 3067 InitReg(MISCREG_TPIDRURW) 3068 .banked(); 3069 InitReg(MISCREG_TPIDRURW_NS) 3070 .bankedChild() 3071 .allPrivileges().monSecure(0).privSecure(0); 3072 InitReg(MISCREG_TPIDRURW_S) 3073 .bankedChild() 3074 .secure(); 3075 InitReg(MISCREG_TPIDRURO) 3076 .banked(); 3077 InitReg(MISCREG_TPIDRURO_NS) 3078 .bankedChild() 3079 .allPrivileges().secure(0).userNonSecureWrite(0).userSecureRead(1); 3080 InitReg(MISCREG_TPIDRURO_S) 3081 .bankedChild() 3082 .secure().userSecureWrite(0); 3083 InitReg(MISCREG_TPIDRPRW) 3084 .banked(); 3085 InitReg(MISCREG_TPIDRPRW_NS) 3086 .bankedChild() 3087 .nonSecure().exceptUserMode(); 3088 InitReg(MISCREG_TPIDRPRW_S) 3089 .bankedChild() 3090 .secure().exceptUserMode(); 3091 InitReg(MISCREG_HTPIDR) 3092 .hyp().monNonSecure(); 3093 InitReg(MISCREG_CNTFRQ) 3094 .unverifiable() 3095 .reads(1).mon(); 3096 InitReg(MISCREG_CNTKCTL) 3097 .allPrivileges().exceptUserMode(); 3098 InitReg(MISCREG_CNTP_TVAL) 3099 .banked(); 3100 InitReg(MISCREG_CNTP_TVAL_NS) 3101 .bankedChild() 3102 .allPrivileges().monSecure(0).privSecure(0); 3103 InitReg(MISCREG_CNTP_TVAL_S) 3104 .unimplemented() 3105 .bankedChild() 3106 .secure().user(1); 3107 InitReg(MISCREG_CNTP_CTL) 3108 .banked(); 3109 InitReg(MISCREG_CNTP_CTL_NS) 3110 .bankedChild() 3111 .allPrivileges().monSecure(0).privSecure(0); 3112 InitReg(MISCREG_CNTP_CTL_S) 3113 .unimplemented() 3114 .bankedChild() 3115 .secure().user(1); 3116 InitReg(MISCREG_CNTV_TVAL) 3117 .allPrivileges(); 3118 InitReg(MISCREG_CNTV_CTL) 3119 .allPrivileges(); 3120 InitReg(MISCREG_CNTHCTL) 3121 .unimplemented() 3122 .hypWrite().monNonSecureRead(); 3123 InitReg(MISCREG_CNTHP_TVAL) 3124 .unimplemented() 3125 .hypWrite().monNonSecureRead(); 3126 InitReg(MISCREG_CNTHP_CTL) 3127 .unimplemented() 3128 .hypWrite().monNonSecureRead(); 3129 InitReg(MISCREG_IL1DATA0) 3130 .unimplemented() 3131 .allPrivileges().exceptUserMode(); 3132 InitReg(MISCREG_IL1DATA1) 3133 .unimplemented() 3134 .allPrivileges().exceptUserMode(); 3135 InitReg(MISCREG_IL1DATA2) 3136 .unimplemented() 3137 .allPrivileges().exceptUserMode(); 3138 InitReg(MISCREG_IL1DATA3) 3139 .unimplemented() 3140 .allPrivileges().exceptUserMode(); 3141 InitReg(MISCREG_DL1DATA0) 3142 .unimplemented() 3143 .allPrivileges().exceptUserMode(); 3144 InitReg(MISCREG_DL1DATA1) 3145 .unimplemented() 3146 .allPrivileges().exceptUserMode(); 3147 InitReg(MISCREG_DL1DATA2) 3148 .unimplemented() 3149 .allPrivileges().exceptUserMode(); 3150 InitReg(MISCREG_DL1DATA3) 3151 .unimplemented() 3152 .allPrivileges().exceptUserMode(); 3153 InitReg(MISCREG_DL1DATA4) 3154 .unimplemented() 3155 .allPrivileges().exceptUserMode(); 3156 InitReg(MISCREG_RAMINDEX) 3157 .unimplemented() 3158 .writes(1).exceptUserMode(); 3159 InitReg(MISCREG_L2ACTLR) 3160 .unimplemented() 3161 .allPrivileges().exceptUserMode(); 3162 InitReg(MISCREG_CBAR) 3163 .unimplemented() 3164 .allPrivileges().exceptUserMode().writes(0); 3165 InitReg(MISCREG_HTTBR) 3166 .hyp().monNonSecure(); 3167 InitReg(MISCREG_VTTBR) 3168 .hyp().monNonSecure(); 3169 InitReg(MISCREG_CNTPCT) 3170 .reads(1); 3171 InitReg(MISCREG_CNTVCT) 3172 .unverifiable() 3173 .reads(1); 3174 InitReg(MISCREG_CNTP_CVAL) 3175 .banked(); 3176 InitReg(MISCREG_CNTP_CVAL_NS) 3177 .bankedChild() 3178 .allPrivileges().monSecure(0).privSecure(0); 3179 InitReg(MISCREG_CNTP_CVAL_S) 3180 .unimplemented() 3181 .bankedChild() 3182 .secure().user(1); 3183 InitReg(MISCREG_CNTV_CVAL) 3184 .allPrivileges(); 3185 InitReg(MISCREG_CNTVOFF) 3186 .hyp().monNonSecure(); 3187 InitReg(MISCREG_CNTHP_CVAL) 3188 .unimplemented() 3189 .hypWrite().monNonSecureRead(); 3190 InitReg(MISCREG_CPUMERRSR) 3191 .unimplemented() 3192 .allPrivileges().exceptUserMode(); 3193 InitReg(MISCREG_L2MERRSR) 3194 .unimplemented() 3195 .warnNotFail() 3196 .allPrivileges().exceptUserMode(); 3197 3198 // AArch64 registers (Op0=2); 3199 InitReg(MISCREG_MDCCINT_EL1) 3200 .allPrivileges(); 3201 InitReg(MISCREG_OSDTRRX_EL1) 3202 .allPrivileges() 3203 .mapsTo(MISCREG_DBGDTRRXext); 3204 InitReg(MISCREG_MDSCR_EL1) 3205 .allPrivileges() 3206 .mapsTo(MISCREG_DBGDSCRext); 3207 InitReg(MISCREG_OSDTRTX_EL1) 3208 .allPrivileges() 3209 .mapsTo(MISCREG_DBGDTRTXext); 3210 InitReg(MISCREG_OSECCR_EL1) 3211 .allPrivileges() 3212 .mapsTo(MISCREG_DBGOSECCR); 3213 InitReg(MISCREG_DBGBVR0_EL1) 3214 .allPrivileges() 3215 .mapsTo(MISCREG_DBGBVR0 /, MISCREG_DBGBXVR0 /); 3216 InitReg(MISCREG_DBGBVR1_EL1) 3217 .allPrivileges() 3218 .mapsTo(MISCREG_DBGBVR1 /, MISCREG_DBGBXVR1 /); 3219 InitReg(MISCREG_DBGBVR2_EL1) 3220 .allPrivileges() 3221 .mapsTo(MISCREG_DBGBVR2 /, MISCREG_DBGBXVR2 /); 3222 InitReg(MISCREG_DBGBVR3_EL1) 3223 .allPrivileges() 3224 .mapsTo(MISCREG_DBGBVR3 /, MISCREG_DBGBXVR3 /); 3225 InitReg(MISCREG_DBGBVR4_EL1) 3226 .allPrivileges() 3227 .mapsTo(MISCREG_DBGBVR4 /, MISCREG_DBGBXVR4 /); 3228 InitReg(MISCREG_DBGBVR5_EL1) 3229 .allPrivileges() 3230 .mapsTo(MISCREG_DBGBVR5 /, MISCREG_DBGBXVR5 /); 3231 InitReg(MISCREG_DBGBCR0_EL1) 3232 .allPrivileges() 3233 .mapsTo(MISCREG_DBGBCR0); 3234 InitReg(MISCREG_DBGBCR1_EL1) 3235 .allPrivileges() 3236 .mapsTo(MISCREG_DBGBCR1); 3237 InitReg(MISCREG_DBGBCR2_EL1) 3238 .allPrivileges() 3239 .mapsTo(MISCREG_DBGBCR2); 3240 InitReg(MISCREG_DBGBCR3_EL1) 3241 .allPrivileges() 3242 .mapsTo(MISCREG_DBGBCR3); 3243 InitReg(MISCREG_DBGBCR4_EL1) 3244 .allPrivileges() 3245 .mapsTo(MISCREG_DBGBCR4); 3246 InitReg(MISCREG_DBGBCR5_EL1) 3247 .allPrivileges() 3248 .mapsTo(MISCREG_DBGBCR5); 3249 InitReg(MISCREG_DBGWVR0_EL1) 3250 .allPrivileges() 3251 .mapsTo(MISCREG_DBGWVR0); 3252 InitReg(MISCREG_DBGWVR1_EL1) 3253 .allPrivileges() 3254 .mapsTo(MISCREG_DBGWVR1); 3255 InitReg(MISCREG_DBGWVR2_EL1) 3256 .allPrivileges() 3257 .mapsTo(MISCREG_DBGWVR2); 3258 InitReg(MISCREG_DBGWVR3_EL1) 3259 .allPrivileges() 3260 .mapsTo(MISCREG_DBGWVR3); 3261 InitReg(MISCREG_DBGWCR0_EL1) 3262 .allPrivileges() 3263 .mapsTo(MISCREG_DBGWCR0); 3264 InitReg(MISCREG_DBGWCR1_EL1) 3265 .allPrivileges() 3266 .mapsTo(MISCREG_DBGWCR1); 3267 InitReg(MISCREG_DBGWCR2_EL1) 3268 .allPrivileges() 3269 .mapsTo(MISCREG_DBGWCR2); 3270 InitReg(MISCREG_DBGWCR3_EL1) 3271 .allPrivileges() 3272 .mapsTo(MISCREG_DBGWCR3); 3273 InitReg(MISCREG_MDCCSR_EL0) 3274 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3275 .mapsTo(MISCREG_DBGDSCRint); 3276 InitReg(MISCREG_MDDTR_EL0) 3277 .allPrivileges(); 3278 InitReg(MISCREG_MDDTRTX_EL0) 3279 .allPrivileges(); 3280 InitReg(MISCREG_MDDTRRX_EL0) 3281 .allPrivileges(); 3282 InitReg(MISCREG_DBGVCR32_EL2) 3283 .allPrivileges() 3284 .mapsTo(MISCREG_DBGVCR); 3285 InitReg(MISCREG_MDRAR_EL1) 3286 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3287 .mapsTo(MISCREG_DBGDRAR); 3288 InitReg(MISCREG_OSLAR_EL1) 3289 .allPrivileges().monSecureRead(0).monNonSecureRead(0) 3290 .mapsTo(MISCREG_DBGOSLAR); 3291 InitReg(MISCREG_OSLSR_EL1) 3292 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3293 .mapsTo(MISCREG_DBGOSLSR); 3294 InitReg(MISCREG_OSDLR_EL1) 3295 .allPrivileges() 3296 .mapsTo(MISCREG_DBGOSDLR); 3297 InitReg(MISCREG_DBGPRCR_EL1) 3298 .allPrivileges() 3299 .mapsTo(MISCREG_DBGPRCR); 3300 InitReg(MISCREG_DBGCLAIMSET_EL1) 3301 .allPrivileges() 3302 .mapsTo(MISCREG_DBGCLAIMSET); 3303 InitReg(MISCREG_DBGCLAIMCLR_EL1) 3304 .allPrivileges() 3305 .mapsTo(MISCREG_DBGCLAIMCLR); 3306 InitReg(MISCREG_DBGAUTHSTATUS_EL1) 3307 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3308 .mapsTo(MISCREG_DBGAUTHSTATUS); 3309 InitReg(MISCREG_TEECR32_EL1); 3310 InitReg(MISCREG_TEEHBR32_EL1); 3311 3312 // AArch64 registers (Op0=1,3); 3313 InitReg(MISCREG_MIDR_EL1) 3314 .allPrivileges().exceptUserMode().writes(0); 3315 InitReg(MISCREG_MPIDR_EL1) 3316 .allPrivileges().exceptUserMode().writes(0); 3317 InitReg(MISCREG_REVIDR_EL1) 3318 .allPrivileges().exceptUserMode().writes(0); 3319 InitReg(MISCREG_ID_PFR0_EL1) 3320 .allPrivileges().exceptUserMode().writes(0); 3321 InitReg(MISCREG_ID_PFR1_EL1) 3322 .allPrivileges().exceptUserMode().writes(0); 3323 InitReg(MISCREG_ID_DFR0_EL1) 3324 .allPrivileges().exceptUserMode().writes(0) 3325 .mapsTo(MISCREG_ID_DFR0); 3326 InitReg(MISCREG_ID_AFR0_EL1) 3327 .allPrivileges().exceptUserMode().writes(0); 3328 InitReg(MISCREG_ID_MMFR0_EL1) 3329 .allPrivileges().exceptUserMode().writes(0); 3330 InitReg(MISCREG_ID_MMFR1_EL1) 3331 .allPrivileges().exceptUserMode().writes(0); 3332 InitReg(MISCREG_ID_MMFR2_EL1) 3333 .allPrivileges().exceptUserMode().writes(0); 3334 InitReg(MISCREG_ID_MMFR3_EL1) 3335 .allPrivileges().exceptUserMode().writes(0); 3336 InitReg(MISCREG_ID_ISAR0_EL1) 3337 .allPrivileges().exceptUserMode().writes(0); 3338 InitReg(MISCREG_ID_ISAR1_EL1) 3339 .allPrivileges().exceptUserMode().writes(0); 3340 InitReg(MISCREG_ID_ISAR2_EL1) 3341 .allPrivileges().exceptUserMode().writes(0); 3342 InitReg(MISCREG_ID_ISAR3_EL1) 3343 .allPrivileges().exceptUserMode().writes(0); 3344 InitReg(MISCREG_ID_ISAR4_EL1) 3345 .allPrivileges().exceptUserMode().writes(0); 3346 InitReg(MISCREG_ID_ISAR5_EL1) 3347 .allPrivileges().exceptUserMode().writes(0); 3348 InitReg(MISCREG_MVFR0_EL1) 3349 .allPrivileges().exceptUserMode().writes(0); 3350 InitReg(MISCREG_MVFR1_EL1) 3351 .allPrivileges().exceptUserMode().writes(0); 3352 InitReg(MISCREG_MVFR2_EL1) 3353 .allPrivileges().exceptUserMode().writes(0); 3354 InitReg(MISCREG_ID_AA64PFR0_EL1) 3355 .allPrivileges().exceptUserMode().writes(0); 3356 InitReg(MISCREG_ID_AA64PFR1_EL1) 3357 .allPrivileges().exceptUserMode().writes(0); 3358 InitReg(MISCREG_ID_AA64DFR0_EL1) 3359 .allPrivileges().exceptUserMode().writes(0); 3360 InitReg(MISCREG_ID_AA64DFR1_EL1) 3361 .allPrivileges().exceptUserMode().writes(0); 3362 InitReg(MISCREG_ID_AA64AFR0_EL1) 3363 .allPrivileges().exceptUserMode().writes(0); 3364 InitReg(MISCREG_ID_AA64AFR1_EL1) 3365 .allPrivileges().exceptUserMode().writes(0); 3366 InitReg(MISCREG_ID_AA64ISAR0_EL1) 3367 .allPrivileges().exceptUserMode().writes(0); 3368 InitReg(MISCREG_ID_AA64ISAR1_EL1) 3369 .allPrivileges().exceptUserMode().writes(0); 3370 InitReg(MISCREG_ID_AA64MMFR0_EL1) 3371 .allPrivileges().exceptUserMode().writes(0); 3372 InitReg(MISCREG_ID_AA64MMFR1_EL1) 3373 .allPrivileges().exceptUserMode().writes(0); 3374 InitReg(MISCREG_CCSIDR_EL1) 3375 .allPrivileges().exceptUserMode().writes(0); 3376 InitReg(MISCREG_CLIDR_EL1) 3377 .allPrivileges().exceptUserMode().writes(0); 3378 InitReg(MISCREG_AIDR_EL1) 3379 .allPrivileges().exceptUserMode().writes(0); 3380 InitReg(MISCREG_CSSELR_EL1) 3381 .allPrivileges().exceptUserMode() 3382 .mapsTo(MISCREG_CSSELR_NS); 3383 InitReg(MISCREG_CTR_EL0) 3384 .reads(1); 3385 InitReg(MISCREG_DCZID_EL0) 3386 .reads(1); 3387 InitReg(MISCREG_VPIDR_EL2) 3388 .hyp().mon() 3389 .mapsTo(MISCREG_VPIDR); 3390 InitReg(MISCREG_VMPIDR_EL2) 3391 .hyp().mon() 3392 .mapsTo(MISCREG_VMPIDR); 3393 InitReg(MISCREG_SCTLR_EL1) 3394 .allPrivileges().exceptUserMode() 3395 .mapsTo(MISCREG_SCTLR_NS); 3396 InitReg(MISCREG_ACTLR_EL1) 3397 .allPrivileges().exceptUserMode() 3398 .mapsTo(MISCREG_ACTLR_NS); 3399 InitReg(MISCREG_CPACR_EL1) 3400 .allPrivileges().exceptUserMode() 3401 .mapsTo(MISCREG_CPACR); 3402 InitReg(MISCREG_SCTLR_EL2) 3403 .hyp().mon() 3404 .mapsTo(MISCREG_HSCTLR); 3405 InitReg(MISCREG_ACTLR_EL2) 3406 .hyp().mon() 3407 .mapsTo(MISCREG_HACTLR); 3408 InitReg(MISCREG_HCR_EL2) 3409 .hyp().mon() 3410 .mapsTo(MISCREG_HCR /, MISCREG_HCR2/); 3411 InitReg(MISCREG_MDCR_EL2) 3412 .hyp().mon() 3413 .mapsTo(MISCREG_HDCR); 3414 InitReg(MISCREG_CPTR_EL2) 3415 .hyp().mon() 3416 .mapsTo(MISCREG_HCPTR); 3417 InitReg(MISCREG_HSTR_EL2) 3418 .hyp().mon() 3419 .mapsTo(MISCREG_HSTR); 3420 InitReg(MISCREG_HACR_EL2) 3421 .hyp().mon() 3422 .mapsTo(MISCREG_HACR); 3423 InitReg(MISCREG_SCTLR_EL3) 3424 .mon(); 3425 InitReg(MISCREG_ACTLR_EL3) 3426 .mon(); 3427 InitReg(MISCREG_SCR_EL3) 3428 .mon() 3429 .mapsTo(MISCREG_SCR); // NAM D7-2005 3430 InitReg(MISCREG_SDER32_EL3) 3431 .mon() 3432 .mapsTo(MISCREG_SDER); 3433 InitReg(MISCREG_CPTR_EL3) 3434 .mon(); 3435 InitReg(MISCREG_MDCR_EL3) 3436 .mon(); 3437 InitReg(MISCREG_TTBR0_EL1) 3438 .allPrivileges().exceptUserMode() 3439 .mapsTo(MISCREG_TTBR0_NS); 3440 InitReg(MISCREG_TTBR1_EL1) 3441 .allPrivileges().exceptUserMode() 3442 .mapsTo(MISCREG_TTBR1_NS); 3443 InitReg(MISCREG_TCR_EL1) 3444 .allPrivileges().exceptUserMode() 3445 .mapsTo(MISCREG_TTBCR_NS); 3446 InitReg(MISCREG_TTBR0_EL2) 3447 .hyp().mon() 3448 .mapsTo(MISCREG_HTTBR); 3449 InitReg(MISCREG_TCR_EL2) 3450 .hyp().mon() 3451 .mapsTo(MISCREG_HTCR); 3452 InitReg(MISCREG_VTTBR_EL2) 3453 .hyp().mon() 3454 .mapsTo(MISCREG_VTTBR); 3455 InitReg(MISCREG_VTCR_EL2) 3456 .hyp().mon() 3457 .mapsTo(MISCREG_VTCR); 3458 InitReg(MISCREG_TTBR0_EL3) 3459 .mon(); 3460 InitReg(MISCREG_TCR_EL3) 3461 .mon(); 3462 InitReg(MISCREG_DACR32_EL2) 3463 .hyp().mon() 3464 .mapsTo(MISCREG_DACR_NS); 3465 InitReg(MISCREG_SPSR_EL1) 3466 .allPrivileges().exceptUserMode() 3467 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1 3468 InitReg(MISCREG_ELR_EL1) 3469 .allPrivileges().exceptUserMode(); 3470 InitReg(MISCREG_SP_EL0) 3471 .allPrivileges().exceptUserMode(); 3472 InitReg(MISCREG_SPSEL) 3473 .allPrivileges().exceptUserMode(); 3474 InitReg(MISCREG_CURRENTEL) 3475 .allPrivileges().exceptUserMode().writes(0); 3476 InitReg(MISCREG_NZCV) 3477 .allPrivileges(); 3478 InitReg(MISCREG_DAIF) 3479 .allPrivileges(); 3480 InitReg(MISCREG_FPCR) 3481 .allPrivileges(); 3482 InitReg(MISCREG_FPSR) 3483 .allPrivileges(); 3484 InitReg(MISCREG_DSPSR_EL0) 3485 .allPrivileges(); 3486 InitReg(MISCREG_DLR_EL0) 3487 .allPrivileges(); 3488 InitReg(MISCREG_SPSR_EL2) 3489 .hyp().mon() 3490 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2 3491 InitReg(MISCREG_ELR_EL2) 3492 .hyp().mon(); 3493 InitReg(MISCREG_SP_EL1) 3494 .hyp().mon(); 3495 InitReg(MISCREG_SPSR_IRQ_AA64) 3496 .hyp().mon(); 3497 InitReg(MISCREG_SPSR_ABT_AA64) 3498 .hyp().mon(); 3499 InitReg(MISCREG_SPSR_UND_AA64) 3500 .hyp().mon(); 3501 InitReg(MISCREG_SPSR_FIQ_AA64) 3502 .hyp().mon(); 3503 InitReg(MISCREG_SPSR_EL3) 3504 .mon() 3505 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3 3506 InitReg(MISCREG_ELR_EL3) 3507 .mon(); 3508 InitReg(MISCREG_SP_EL2) 3509 .mon(); 3510 InitReg(MISCREG_AFSR0_EL1) 3511 .allPrivileges().exceptUserMode() 3512 .mapsTo(MISCREG_ADFSR_NS); 3513 InitReg(MISCREG_AFSR1_EL1) 3514 .allPrivileges().exceptUserMode() 3515 .mapsTo(MISCREG_AIFSR_NS); 3516 InitReg(MISCREG_ESR_EL1) 3517 .allPrivileges().exceptUserMode(); 3518 InitReg(MISCREG_IFSR32_EL2) 3519 .hyp().mon() 3520 .mapsTo(MISCREG_IFSR_NS); 3521 InitReg(MISCREG_AFSR0_EL2) 3522 .hyp().mon() 3523 .mapsTo(MISCREG_HADFSR); 3524 InitReg(MISCREG_AFSR1_EL2) 3525 .hyp().mon() 3526 .mapsTo(MISCREG_HAIFSR); 3527 InitReg(MISCREG_ESR_EL2) 3528 .hyp().mon() 3529 .mapsTo(MISCREG_HSR); 3530 InitReg(MISCREG_FPEXC32_EL2) 3531 .hyp().mon(); 3532 InitReg(MISCREG_AFSR0_EL3) 3533 .mon(); 3534 InitReg(MISCREG_AFSR1_EL3) 3535 .mon(); 3536 InitReg(MISCREG_ESR_EL3) 3537 .mon(); 3538 InitReg(MISCREG_FAR_EL1) 3539 .allPrivileges().exceptUserMode() 3540 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS); 3541 InitReg(MISCREG_FAR_EL2) 3542 .hyp().mon() 3543 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR); 3544 InitReg(MISCREG_HPFAR_EL2) 3545 .hyp().mon() 3546 .mapsTo(MISCREG_HPFAR); 3547 InitReg(MISCREG_FAR_EL3) 3548 .mon(); 3549 InitReg(MISCREG_IC_IALLUIS) 3550 .warnNotFail() 3551 .writes(1).exceptUserMode(); 3552 InitReg(MISCREG_PAR_EL1) 3553 .allPrivileges().exceptUserMode() 3554 .mapsTo(MISCREG_PAR_NS); 3555 InitReg(MISCREG_IC_IALLU) 3556 .warnNotFail() 3557 .writes(1).exceptUserMode(); 3558 InitReg(MISCREG_DC_IVAC_Xt) 3559 .warnNotFail() 3560 .writes(1); 3561 InitReg(MISCREG_DC_ISW_Xt) 3562 .warnNotFail() 3563 .writes(1).exceptUserMode(); 3564 InitReg(MISCREG_AT_S1E1R_Xt) 3565 .writes(1).exceptUserMode(); 3566 InitReg(MISCREG_AT_S1E1W_Xt) 3567 .writes(1).exceptUserMode(); 3568 InitReg(MISCREG_AT_S1E0R_Xt) 3569 .writes(1).exceptUserMode(); 3570 InitReg(MISCREG_AT_S1E0W_Xt) 3571 .writes(1).exceptUserMode(); 3572 InitReg(MISCREG_DC_CSW_Xt) 3573 .warnNotFail() 3574 .writes(1).exceptUserMode(); 3575 InitReg(MISCREG_DC_CISW_Xt) 3576 .warnNotFail() 3577 .writes(1).exceptUserMode(); 3578 InitReg(MISCREG_DC_ZVA_Xt) 3579 .warnNotFail() 3580 .writes(1).userSecureWrite(0); 3581 InitReg(MISCREG_IC_IVAU_Xt) 3582 .writes(1); 3583 InitReg(MISCREG_DC_CVAC_Xt) 3584 .warnNotFail() 3585 .writes(1); 3586 InitReg(MISCREG_DC_CVAU_Xt) 3587 .warnNotFail() 3588 .writes(1); 3589 InitReg(MISCREG_DC_CIVAC_Xt) 3590 .warnNotFail() 3591 .writes(1); 3592 InitReg(MISCREG_AT_S1E2R_Xt) 3593 .monNonSecureWrite().hypWrite(); 3594 InitReg(MISCREG_AT_S1E2W_Xt) 3595 .monNonSecureWrite().hypWrite(); 3596 InitReg(MISCREG_AT_S12E1R_Xt) 3597 .hypWrite().monSecureWrite().monNonSecureWrite(); 3598 InitReg(MISCREG_AT_S12E1W_Xt) 3599 .hypWrite().monSecureWrite().monNonSecureWrite(); 3600 InitReg(MISCREG_AT_S12E0R_Xt) 3601 .hypWrite().monSecureWrite().monNonSecureWrite(); 3602 InitReg(MISCREG_AT_S12E0W_Xt) 3603 .hypWrite().monSecureWrite().monNonSecureWrite(); 3604 InitReg(MISCREG_AT_S1E3R_Xt) 3605 .monSecureWrite().monNonSecureWrite(); 3606 InitReg(MISCREG_AT_S1E3W_Xt) 3607 .monSecureWrite().monNonSecureWrite(); 3608 InitReg(MISCREG_TLBI_VMALLE1IS) 3609 .writes(1).exceptUserMode(); 3610 InitReg(MISCREG_TLBI_VAE1IS_Xt) 3611 .writes(1).exceptUserMode(); 3612 InitReg(MISCREG_TLBI_ASIDE1IS_Xt) 3613 .writes(1).exceptUserMode(); 3614 InitReg(MISCREG_TLBI_VAAE1IS_Xt) 3615 .writes(1).exceptUserMode(); 3616 InitReg(MISCREG_TLBI_VALE1IS_Xt) 3617 .writes(1).exceptUserMode(); 3618 InitReg(MISCREG_TLBI_VAALE1IS_Xt) 3619 .writes(1).exceptUserMode(); 3620 InitReg(MISCREG_TLBI_VMALLE1) 3621 .writes(1).exceptUserMode(); 3622 InitReg(MISCREG_TLBI_VAE1_Xt) 3623 .writes(1).exceptUserMode(); 3624 InitReg(MISCREG_TLBI_ASIDE1_Xt) 3625 .writes(1).exceptUserMode(); 3626 InitReg(MISCREG_TLBI_VAAE1_Xt) 3627 .writes(1).exceptUserMode(); 3628 InitReg(MISCREG_TLBI_VALE1_Xt) 3629 .writes(1).exceptUserMode(); 3630 InitReg(MISCREG_TLBI_VAALE1_Xt) 3631 .writes(1).exceptUserMode(); 3632 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt) 3633 .hypWrite().monSecureWrite().monNonSecureWrite(); 3634 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt) 3635 .hypWrite().monSecureWrite().monNonSecureWrite(); 3636 InitReg(MISCREG_TLBI_ALLE2IS) 3637 .monNonSecureWrite().hypWrite(); 3638 InitReg(MISCREG_TLBI_VAE2IS_Xt) 3639 .monNonSecureWrite().hypWrite(); 3640 InitReg(MISCREG_TLBI_ALLE1IS) 3641 .hypWrite().monSecureWrite().monNonSecureWrite(); 3642 InitReg(MISCREG_TLBI_VALE2IS_Xt) 3643 .monNonSecureWrite().hypWrite(); 3644 InitReg(MISCREG_TLBI_VMALLS12E1IS) 3645 .hypWrite().monSecureWrite().monNonSecureWrite(); 3646 InitReg(MISCREG_TLBI_IPAS2E1_Xt) 3647 .hypWrite().monSecureWrite().monNonSecureWrite(); 3648 InitReg(MISCREG_TLBI_IPAS2LE1_Xt) 3649 .hypWrite().monSecureWrite().monNonSecureWrite(); 3650 InitReg(MISCREG_TLBI_ALLE2) 3651 .monNonSecureWrite().hypWrite(); 3652 InitReg(MISCREG_TLBI_VAE2_Xt) 3653 .monNonSecureWrite().hypWrite(); 3654 InitReg(MISCREG_TLBI_ALLE1) 3655 .hypWrite().monSecureWrite().monNonSecureWrite(); 3656 InitReg(MISCREG_TLBI_VALE2_Xt) 3657 .monNonSecureWrite().hypWrite(); 3658 InitReg(MISCREG_TLBI_VMALLS12E1) 3659 .hypWrite().monSecureWrite().monNonSecureWrite(); 3660 InitReg(MISCREG_TLBI_ALLE3IS) 3661 .monSecureWrite().monNonSecureWrite(); 3662 InitReg(MISCREG_TLBI_VAE3IS_Xt) 3663 .monSecureWrite().monNonSecureWrite(); 3664 InitReg(MISCREG_TLBI_VALE3IS_Xt) 3665 .monSecureWrite().monNonSecureWrite(); 3666 InitReg(MISCREG_TLBI_ALLE3) 3667 .monSecureWrite().monNonSecureWrite(); 3668 InitReg(MISCREG_TLBI_VAE3_Xt) 3669 .monSecureWrite().monNonSecureWrite(); 3670 InitReg(MISCREG_TLBI_VALE3_Xt) 3671 .monSecureWrite().monNonSecureWrite(); 3672 InitReg(MISCREG_PMINTENSET_EL1) 3673 .allPrivileges().exceptUserMode() 3674 .mapsTo(MISCREG_PMINTENSET); 3675 InitReg(MISCREG_PMINTENCLR_EL1) 3676 .allPrivileges().exceptUserMode() 3677 .mapsTo(MISCREG_PMINTENCLR); 3678 InitReg(MISCREG_PMCR_EL0) 3679 .allPrivileges() 3680 .mapsTo(MISCREG_PMCR); 3681 InitReg(MISCREG_PMCNTENSET_EL0) 3682 .allPrivileges() 3683 .mapsTo(MISCREG_PMCNTENSET); 3684 InitReg(MISCREG_PMCNTENCLR_EL0) 3685 .allPrivileges() 3686 .mapsTo(MISCREG_PMCNTENCLR); 3687 InitReg(MISCREG_PMOVSCLR_EL0) 3688 .allPrivileges(); 3689// .mapsTo(MISCREG_PMOVSCLR); 3690 InitReg(MISCREG_PMSWINC_EL0) 3691 .writes(1).user() 3692 .mapsTo(MISCREG_PMSWINC); 3693 InitReg(MISCREG_PMSELR_EL0) 3694 .allPrivileges() 3695 .mapsTo(MISCREG_PMSELR); 3696 InitReg(MISCREG_PMCEID0_EL0) 3697 .reads(1).user() 3698 .mapsTo(MISCREG_PMCEID0); 3699 InitReg(MISCREG_PMCEID1_EL0) 3700 .reads(1).user() 3701 .mapsTo(MISCREG_PMCEID1); 3702 InitReg(MISCREG_PMCCNTR_EL0) 3703 .allPrivileges() 3704 .mapsTo(MISCREG_PMCCNTR); 3705 InitReg(MISCREG_PMXEVTYPER_EL0) 3706 .allPrivileges() 3707 .mapsTo(MISCREG_PMXEVTYPER); 3708 InitReg(MISCREG_PMCCFILTR_EL0) 3709 .allPrivileges(); 3710 InitReg(MISCREG_PMXEVCNTR_EL0) 3711 .allPrivileges() 3712 .mapsTo(MISCREG_PMXEVCNTR); 3713 InitReg(MISCREG_PMUSERENR_EL0) 3714 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0) 3715 .mapsTo(MISCREG_PMUSERENR); 3716 InitReg(MISCREG_PMOVSSET_EL0) 3717 .allPrivileges() 3718 .mapsTo(MISCREG_PMOVSSET); 3719 InitReg(MISCREG_MAIR_EL1) 3720 .allPrivileges().exceptUserMode() 3721 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS); 3722 InitReg(MISCREG_AMAIR_EL1) 3723 .allPrivileges().exceptUserMode() 3724 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS); 3725 InitReg(MISCREG_MAIR_EL2) 3726 .hyp().mon() 3727 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1); 3728 InitReg(MISCREG_AMAIR_EL2) 3729 .hyp().mon() 3730 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1); 3731 InitReg(MISCREG_MAIR_EL3) 3732 .mon(); 3733 InitReg(MISCREG_AMAIR_EL3) 3734 .mon(); 3735 InitReg(MISCREG_L2CTLR_EL1) 3736 .allPrivileges().exceptUserMode(); 3737 InitReg(MISCREG_L2ECTLR_EL1) 3738 .allPrivileges().exceptUserMode(); 3739 InitReg(MISCREG_VBAR_EL1) 3740 .allPrivileges().exceptUserMode() 3741 .mapsTo(MISCREG_VBAR_NS); 3742 InitReg(MISCREG_RVBAR_EL1) 3743 .allPrivileges().exceptUserMode().writes(0); 3744 InitReg(MISCREG_ISR_EL1) 3745 .allPrivileges().exceptUserMode().writes(0); 3746 InitReg(MISCREG_VBAR_EL2) 3747 .hyp().mon() 3748 .mapsTo(MISCREG_HVBAR); 3749 InitReg(MISCREG_RVBAR_EL2) 3750 .mon().hyp().writes(0); 3751 InitReg(MISCREG_VBAR_EL3) 3752 .mon(); 3753 InitReg(MISCREG_RVBAR_EL3) 3754 .mon().writes(0); 3755 InitReg(MISCREG_RMR_EL3) 3756 .mon(); 3757 InitReg(MISCREG_CONTEXTIDR_EL1) 3758 .allPrivileges().exceptUserMode() 3759 .mapsTo(MISCREG_CONTEXTIDR_NS); 3760 InitReg(MISCREG_TPIDR_EL1) 3761 .allPrivileges().exceptUserMode() 3762 .mapsTo(MISCREG_TPIDRPRW_NS); 3763 InitReg(MISCREG_TPIDR_EL0) 3764 .allPrivileges() 3765 .mapsTo(MISCREG_TPIDRURW_NS); 3766 InitReg(MISCREG_TPIDRRO_EL0) 3767 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0) 3768 .mapsTo(MISCREG_TPIDRURO_NS); 3769 InitReg(MISCREG_TPIDR_EL2) 3770 .hyp().mon() 3771 .mapsTo(MISCREG_HTPIDR); 3772 InitReg(MISCREG_TPIDR_EL3) 3773 .mon(); 3774 InitReg(MISCREG_CNTKCTL_EL1) 3775 .allPrivileges().exceptUserMode() 3776 .mapsTo(MISCREG_CNTKCTL); 3777 InitReg(MISCREG_CNTFRQ_EL0) 3778 .reads(1).mon() 3779 .mapsTo(MISCREG_CNTFRQ); 3780 InitReg(MISCREG_CNTPCT_EL0) 3781 .reads(1) 3782 .mapsTo(MISCREG_CNTPCT); /* 64b / 3783* InitReg(MISCREG_CNTVCT_EL0) 3784 .unverifiable() 3785 .reads(1) 3786 .mapsTo(MISCREG_CNTVCT); /* 64b / 3787* InitReg(MISCREG_CNTP_TVAL_EL0) 3788 .allPrivileges() 3789 .mapsTo(MISCREG_CNTP_TVAL_NS); 3790 InitReg(MISCREG_CNTP_CTL_EL0) 3791 .allPrivileges() 3792 .mapsTo(MISCREG_CNTP_CTL_NS); 3793 InitReg(MISCREG_CNTP_CVAL_EL0) 3794 .allPrivileges() 3795 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b / 3796* InitReg(MISCREG_CNTV_TVAL_EL0) 3797 .allPrivileges() 3798 .mapsTo(MISCREG_CNTV_TVAL); 3799 InitReg(MISCREG_CNTV_CTL_EL0) 3800 .allPrivileges() 3801 .mapsTo(MISCREG_CNTV_CTL); 3802 InitReg(MISCREG_CNTV_CVAL_EL0) 3803 .allPrivileges() 3804 .mapsTo(MISCREG_CNTV_CVAL); /* 64b / 3805* InitReg(MISCREG_PMEVCNTR0_EL0) 3806 .allPrivileges(); 3807// .mapsTo(MISCREG_PMEVCNTR0); 3808 InitReg(MISCREG_PMEVCNTR1_EL0) 3809 .allPrivileges(); 3810// .mapsTo(MISCREG_PMEVCNTR1); 3811 InitReg(MISCREG_PMEVCNTR2_EL0) 3812 .allPrivileges(); 3813// .mapsTo(MISCREG_PMEVCNTR2); 3814 InitReg(MISCREG_PMEVCNTR3_EL0) 3815 .allPrivileges(); 3816// .mapsTo(MISCREG_PMEVCNTR3); 3817 InitReg(MISCREG_PMEVCNTR4_EL0) 3818 .allPrivileges(); 3819// .mapsTo(MISCREG_PMEVCNTR4); 3820 InitReg(MISCREG_PMEVCNTR5_EL0) 3821 .allPrivileges(); 3822// .mapsTo(MISCREG_PMEVCNTR5); 3823 InitReg(MISCREG_PMEVTYPER0_EL0) 3824 .allPrivileges(); 3825// .mapsTo(MISCREG_PMEVTYPER0); 3826 InitReg(MISCREG_PMEVTYPER1_EL0) 3827 .allPrivileges(); 3828// .mapsTo(MISCREG_PMEVTYPER1); 3829 InitReg(MISCREG_PMEVTYPER2_EL0) 3830 .allPrivileges(); 3831// .mapsTo(MISCREG_PMEVTYPER2); 3832 InitReg(MISCREG_PMEVTYPER3_EL0) 3833 .allPrivileges(); 3834// .mapsTo(MISCREG_PMEVTYPER3); 3835 InitReg(MISCREG_PMEVTYPER4_EL0) 3836 .allPrivileges(); 3837// .mapsTo(MISCREG_PMEVTYPER4); 3838 InitReg(MISCREG_PMEVTYPER5_EL0) 3839 .allPrivileges(); 3840// .mapsTo(MISCREG_PMEVTYPER5); 3841 InitReg(MISCREG_CNTVOFF_EL2) 3842 .hyp().mon() 3843 .mapsTo(MISCREG_CNTVOFF); /* 64b / 3844* InitReg(MISCREG_CNTHCTL_EL2) 3845 .unimplemented() 3846 .warnNotFail() 3847 .mon().monNonSecureWrite(0).hypWrite() 3848 .mapsTo(MISCREG_CNTHCTL); 3849 InitReg(MISCREG_CNTHP_TVAL_EL2) 3850 .unimplemented() 3851 .mon().monNonSecureWrite(0).hypWrite() 3852 .mapsTo(MISCREG_CNTHP_TVAL); 3853 InitReg(MISCREG_CNTHP_CTL_EL2) 3854 .unimplemented() 3855 .mon().monNonSecureWrite(0).hypWrite() 3856 .mapsTo(MISCREG_CNTHP_CTL); 3857 InitReg(MISCREG_CNTHP_CVAL_EL2) 3858 .unimplemented() 3859 .mon().monNonSecureWrite(0).hypWrite() 3860 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b / 3861* InitReg(MISCREG_CNTPS_TVAL_EL1) 3862 .unimplemented() 3863 .mon().monNonSecureWrite(0).hypWrite(); 3864 InitReg(MISCREG_CNTPS_CTL_EL1) 3865 .unimplemented() 3866 .mon().monNonSecureWrite(0).hypWrite(); 3867 InitReg(MISCREG_CNTPS_CVAL_EL1) 3868 .unimplemented() 3869 .mon().monNonSecureWrite(0).hypWrite(); 3870 InitReg(MISCREG_IL1DATA0_EL1) 3871 .allPrivileges().exceptUserMode(); 3872 InitReg(MISCREG_IL1DATA1_EL1) 3873 .allPrivileges().exceptUserMode(); 3874 InitReg(MISCREG_IL1DATA2_EL1) 3875 .allPrivileges().exceptUserMode(); 3876 InitReg(MISCREG_IL1DATA3_EL1) 3877 .allPrivileges().exceptUserMode(); 3878 InitReg(MISCREG_DL1DATA0_EL1) 3879 .allPrivileges().exceptUserMode(); 3880 InitReg(MISCREG_DL1DATA1_EL1) 3881 .allPrivileges().exceptUserMode(); 3882 InitReg(MISCREG_DL1DATA2_EL1) 3883 .allPrivileges().exceptUserMode(); 3884 InitReg(MISCREG_DL1DATA3_EL1) 3885 .allPrivileges().exceptUserMode(); 3886 InitReg(MISCREG_DL1DATA4_EL1) 3887 .allPrivileges().exceptUserMode(); 3888 InitReg(MISCREG_L2ACTLR_EL1) 3889 .allPrivileges().exceptUserMode(); 3890 InitReg(MISCREG_CPUACTLR_EL1) 3891 .allPrivileges().exceptUserMode(); 3892 InitReg(MISCREG_CPUECTLR_EL1) 3893 .allPrivileges().exceptUserMode(); 3894 InitReg(MISCREG_CPUMERRSR_EL1) 3895 .allPrivileges().exceptUserMode(); 3896 InitReg(MISCREG_L2MERRSR_EL1) 3897 .unimplemented() 3898 .warnNotFail() 3899 .allPrivileges().exceptUserMode(); 3900 InitReg(MISCREG_CBAR_EL1) 3901 .allPrivileges().exceptUserMode().writes(0); 3902 InitReg(MISCREG_CONTEXTIDR_EL2) 3903 .mon().hyp(); 3904 3905 // Dummy registers 3906 InitReg(MISCREG_NOP) 3907 .allPrivileges(); 3908 InitReg(MISCREG_RAZ) 3909 .allPrivileges().exceptUserMode().writes(0); 3910 InitReg(MISCREG_CP14_UNIMPL) 3911 .unimplemented() 3912 .warnNotFail(); 3913 InitReg(MISCREG_CP15_UNIMPL) 3914 .unimplemented() 3915 .warnNotFail(); 3916 InitReg(MISCREG_A64_UNIMPL) 3917 .unimplemented() 3918 .warnNotFail(); 3919 InitReg(MISCREG_UNKNOWN); 3920 3921 // Register mappings for some unimplemented registers: 3922 // ESR_EL1 -> DFSR 3923 // RMR_EL1 -> RMR 3924 // RMR_EL2 -> HRMR 3925 // DBGDTR_EL0 -> DBGDTR{R or T}Xint 3926 // DBGDTRRX_EL0 -> DBGDTRRXint 3927 // DBGDTRTX_EL0 -> DBGDTRRXint 3928 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5) 3929 3930 completed = true; 3931} 3932
3564} // namespace ArmISA	3933} // namespace ArmISA