miscregs.cc (11939:9d1795bb5931) miscregs.cc (12240:cb3c69c2d2bf)
1/*
2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1061 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1062 // MISCREG_IC_IALLUIS
1063 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1064 // MISCREG_PAR_EL1
1065 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1066 // MISCREG_IC_IALLU
1067 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1068 // MISCREG_DC_IVAC_Xt
1/*
2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1061 bitset<NUM_MISCREG_INFOS>(string("11110000000000000001")),
1062 // MISCREG_IC_IALLUIS
1063 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1064 // MISCREG_PAR_EL1
1065 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1066 // MISCREG_IC_IALLU
1067 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1068 // MISCREG_DC_IVAC_Xt
1069 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1069 bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")),
1070 // MISCREG_DC_ISW_Xt
1071 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1072 // MISCREG_AT_S1E1R_Xt
1073 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1074 // MISCREG_AT_S1E1W_Xt
1075 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1076 // MISCREG_AT_S1E0R_Xt
1077 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),

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2144 }
2145 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
2146 // In syscall-emulation mode, this test is skipped and DCZVA is always
2147 // allowed at EL0
2148 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2149 if (el == EL0 && !sctlr.dze)
2150 return false;
2151 }
1070 // MISCREG_DC_ISW_Xt
1071 bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
1072 // MISCREG_AT_S1E1R_Xt
1073 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1074 // MISCREG_AT_S1E1W_Xt
1075 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),
1076 // MISCREG_AT_S1E0R_Xt
1077 bitset<NUM_MISCREG_INFOS>(string("10101010100000000001")),

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2144 }
2145 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
2146 // In syscall-emulation mode, this test is skipped and DCZVA is always
2147 // allowed at EL0
2148 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2149 if (el == EL0 && !sctlr.dze)
2150 return false;
2151 }
2152 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
2152 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt ||
2153 reg == MISCREG_DC_IVAC_Xt) {
2153 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2154 if (el == EL0 && !sctlr.uci)
2155 return false;
2156 }
2157
2158 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
2159
2160 switch (el) {

--- 1403 unchanged lines hidden --- 		2154 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2155 if (el == EL0 && !sctlr.uci)
2156 return false;
2157 }
2158
2159 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
2160
2161 switch (el) {

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