miscregs.cc (11587:b7c4aa85db2a) miscregs.cc (11771:764eae95bbbb)
1/*
2 * Copyright (c) 2010-2013, 2015-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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2034 // can't do permissions checkes on the root of a banked pair of regs
2035 assert(!miscRegInfo[reg][MISCREG_BANKED]);
2036 return canWrite;
2037}
2038
2039int
2040flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc)
2041{
1/*
2 * Copyright (c) 2010-2013, 2015-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 2025 unchanged lines hidden (view full) ---

2034 // can't do permissions checkes on the root of a banked pair of regs
2035 assert(!miscRegInfo[reg][MISCREG_BANKED]);
2036 return canWrite;
2037}
2038
2039int
2040flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc)
2041{
2042 int reg_as_int = static_cast<int>(reg);
2043 if (miscRegInfo[reg][MISCREG_BANKED]) {
2044 SCR scr = tc->readMiscReg(MISCREG_SCR);
2045 reg_as_int += (ArmSystem::haveSecurity(tc) && !scr.ns) ? 2 : 1;
2046 }
2047 return reg_as_int;
2042 SCR scr = tc->readMiscReg(MISCREG_SCR);
2043 return flattenMiscRegNsBanked(reg, tc, scr.ns);
2048}
2049
2050int
2051flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns)
2052{
2053 int reg_as_int = static_cast<int>(reg);
2054 if (miscRegInfo[reg][MISCREG_BANKED]) {
2044}
2045
2046int
2047flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns)
2048{
2049 int reg_as_int = static_cast<int>(reg);
2050 if (miscRegInfo[reg][MISCREG_BANKED]) {
2055 reg_as_int += (ArmSystem::haveSecurity(tc) && !ns) ? 2 : 1;
2051 reg_as_int += (ArmSystem::haveSecurity(tc) &&
2052 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
2056 }
2057 return reg_as_int;
2058}
2059
2060
2061/**
2062 * If the reg is a child reg of a banked set, then the parent is the last
2063 * banked one in the list. This is messy, and the wish is to eventually have

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2054 return reg_as_int;
2055}
2056
2057
2058/**
2059 * If the reg is a child reg of a banked set, then the parent is the last
2060 * banked one in the list. This is messy, and the wish is to eventually have

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