miscregs.cc (10845:75df7a87be83) miscregs.cc (10856:d02b45a554b5)
1/*
2 * Copyright (c) 2010-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1329 // MISCREG_CPUECTLR_EL1
1330 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1331 // MISCREG_CPUMERRSR_EL1
1332 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1333 // MISCREG_L2MERRSR_EL1
1334 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
1335 // MISCREG_CBAR_EL1
1336 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1/*
2 * Copyright (c) 2010-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1329 // MISCREG_CPUECTLR_EL1
1330 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1331 // MISCREG_CPUMERRSR_EL1
1332 bitset<NUM_MISCREG_INFOS>(string("11111111110000000001")),
1333 // MISCREG_L2MERRSR_EL1
1334 bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
1335 // MISCREG_CBAR_EL1
1336 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1337 // MISCREG_CONTEXTIDR_EL2
1338 bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
1337
1338 // Dummy registers
1339 // MISCREG_NOP
1340 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1341 // MISCREG_RAZ
1342 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1343 // MISCREG_CP14_UNIMPL
1344 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")),

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3338 }
3339 break;
3340 }
3341 break;
3342 case 4:
3343 switch (crm) {
3344 case 0:
3345 switch (op2) {
1339
1340 // Dummy registers
1341 // MISCREG_NOP
1342 bitset<NUM_MISCREG_INFOS>(string("11111111111111000001")),
1343 // MISCREG_RAZ
1344 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
1345 // MISCREG_CP14_UNIMPL
1346 bitset<NUM_MISCREG_INFOS>(string("00000000000000000100")),

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3340 }
3341 break;
3342 }
3343 break;
3344 case 4:
3345 switch (crm) {
3346 case 0:
3347 switch (op2) {
3348 case 1:
3349 return MISCREG_CONTEXTIDR_EL2;
3346 case 2:
3347 return MISCREG_TPIDR_EL2;
3348 }
3349 break;
3350 }
3351 break;
3352 case 6:
3353 switch (crm) {

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3351 return MISCREG_TPIDR_EL2;
3352 }
3353 break;
3354 }
3355 break;
3356 case 6:
3357 switch (crm) {

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