miscregs.cc (10604:4e09ae443c96) miscregs.cc (10828:2e989cde3f2e)
1/*
1/*
2 * Copyright (c) 2010-2013 ARM Limited
2 * Copyright (c) 2010-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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38 * Ali Saidi
39 * Giacomo Gabrielli
40 */
41
42#include "arch/arm/isa.hh"
43#include "arch/arm/miscregs.hh"
44#include "base/misc.hh"
45#include "cpu/thread_context.hh"
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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38 * Ali Saidi
39 * Giacomo Gabrielli
40 */
41
42#include "arch/arm/isa.hh"
43#include "arch/arm/miscregs.hh"
44#include "base/misc.hh"
45#include "cpu/thread_context.hh"
46#include "sim/full_system.hh"
46
47namespace ArmISA
48{
49
50MiscRegIndex
51decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
52{
53 switch(crn) {

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2133 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
2134 return false;
2135 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
2136 if (reg == MISCREG_DAIF) {
2137 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2138 if (el == EL0 && !sctlr.uma)
2139 return false;
2140 }
47
48namespace ArmISA
49{
50
51MiscRegIndex
52decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
53{
54 switch(crn) {

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2134 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
2135 return false;
2136 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
2137 if (reg == MISCREG_DAIF) {
2138 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2139 if (el == EL0 && !sctlr.uma)
2140 return false;
2141 }
2141 if (reg == MISCREG_DC_ZVA_Xt) {
2142 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
2143 // In syscall-emulation mode, this test is skipped and DCZVA is always
2144 // allowed at EL0
2142 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2143 if (el == EL0 && !sctlr.dze)
2144 return false;
2145 }
2146 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
2147 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2148 if (el == EL0 && !sctlr.uci)
2149 return false;

--- 1407 unchanged lines hidden --- 		2145 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2146 if (el == EL0 && !sctlr.dze)
2147 return false;
2148 }
2149 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
2150 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
2151 if (el == EL0 && !sctlr.uci)
2152 return false;

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