| miscregs.cc (10283:79fde1c67ed8) | miscregs.cc (10421:d469fdcd937e) |
|---|---|
| 1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 2020 unchanged lines hidden (view full) --- 2029 panic("Unrecognized mode setting in CPSR.\n"); 2030 } 2031 // can't do permissions checkes on the root of a banked pair of regs 2032 assert(!miscRegInfo[reg][MISCREG_BANKED]); 2033 return canWrite; 2034} 2035 2036int | 1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 2020 unchanged lines hidden (view full) --- 2029 panic("Unrecognized mode setting in CPSR.\n"); 2030 } 2031 // can't do permissions checkes on the root of a banked pair of regs 2032 assert(!miscRegInfo[reg][MISCREG_BANKED]); 2033 return canWrite; 2034} 2035 2036int |
| 2037flattenMiscRegNsBanked(int reg, ThreadContext *tc) | 2037flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc) |
| 2038{ | 2038{ |
| 2039 int reg_as_int = static_cast<int>(reg); |
|
| 2039 if (miscRegInfo[reg][MISCREG_BANKED]) { 2040 SCR scr = tc->readMiscReg(MISCREG_SCR); | 2040 if (miscRegInfo[reg][MISCREG_BANKED]) { 2041 SCR scr = tc->readMiscReg(MISCREG_SCR); |
| 2041 reg += (ArmSystem::haveSecurity(tc) && !scr.ns) ? 2 : 1; | 2042 reg_as_int += (ArmSystem::haveSecurity(tc) && !scr.ns) ? 2 : 1; |
| 2042 } | 2043 } |
| 2043 return reg; | 2044 return reg_as_int; |
| 2044} 2045 2046int | 2045} 2046 2047int |
| 2047flattenMiscRegNsBanked(int reg, ThreadContext *tc, bool ns) | 2048flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns) |
| 2048{ | 2049{ |
| 2050 int reg_as_int = static_cast<int>(reg); |
|
| 2049 if (miscRegInfo[reg][MISCREG_BANKED]) { | 2051 if (miscRegInfo[reg][MISCREG_BANKED]) { |
| 2050 reg += (ArmSystem::haveSecurity(tc) && !ns) ? 2 : 1; | 2052 reg_as_int += (ArmSystem::haveSecurity(tc) && !ns) ? 2 : 1; |
| 2051 } | 2053 } |
| 2052 return reg; | 2054 return reg_as_int; |
| 2053} 2054 2055 2056/** 2057 * If the reg is a child reg of a banked set, then the parent is the last 2058 * banked one in the list. This is messy, and the wish is to eventually have 2059 * the bitmap replaced with a better data structure. the preUnflatten function 2060 * initializes a lookup table to speed up the search for these banked --- 1489 unchanged lines hidden --- | 2055} 2056 2057 2058/** 2059 * If the reg is a child reg of a banked set, then the parent is the last 2060 * banked one in the list. This is messy, and the wish is to eventually have 2061 * the bitmap replaced with a better data structure. the preUnflatten function 2062 * initializes a lookup table to speed up the search for these banked --- 1489 unchanged lines hidden --- |