Cross Reference: /gem5/src/arch/arm/miscregs.cc

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1/*

3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 * Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include <tuple>
45
46#include "arch/arm/isa.hh"
47#include "base/logging.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51namespace ArmISA
52{
53
54MiscRegIndex
55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56{
57 switch(crn) {
58 case 0:
59 switch (opc1) {
60 case 0:
61 switch (opc2) {
62 case 0:
63 switch (crm) {
64 case 0:
65 return MISCREG_DBGDIDR;
66 case 1:
67 return MISCREG_DBGDSCRint;
68 }
69 break;
70 }
71 break;
72 case 7:
73 switch (opc2) {
74 case 0:
75 switch (crm) {
76 case 0:
77 return MISCREG_JIDR;
78 }
79 break;
80 }
81 break;
82 }
83 break;
84 case 1:
85 switch (opc1) {
86 case 6:
87 switch (crm) {
88 case 0:
89 switch (opc2) {
90 case 0:
91 return MISCREG_TEEHBR;
92 }
93 break;
94 }
95 break;
96 case 7:
97 switch (crm) {
98 case 0:
99 switch (opc2) {
100 case 0:
101 return MISCREG_JOSCR;
102 }
103 break;
104 }
105 break;
106 }
107 break;
108 case 2:
109 switch (opc1) {
110 case 7:
111 switch (crm) {
112 case 0:
113 switch (opc2) {
114 case 0:
115 return MISCREG_JMCR;
116 }
117 break;
118 }
119 break;
120 }
121 break;
122 }
123 // If we get here then it must be a register that we haven't implemented
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn, opc1, crm, opc2);
126 return MISCREG_CP14_UNIMPL;
127}
128
129using namespace std;
130
131MiscRegIndex
132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133{
134 switch (crn) {
135 case 0:
136 switch (opc1) {
137 case 0:
138 switch (crm) {
139 case 0:
140 switch (opc2) {
141 case 1:
142 return MISCREG_CTR;
143 case 2:
144 return MISCREG_TCMTR;
145 case 3:
146 return MISCREG_TLBTR;
147 case 5:
148 return MISCREG_MPIDR;
149 case 6:
150 return MISCREG_REVIDR;
151 default:
152 return MISCREG_MIDR;
153 }
154 break;
155 case 1:
156 switch (opc2) {
157 case 0:
158 return MISCREG_ID_PFR0;
159 case 1:
160 return MISCREG_ID_PFR1;
161 case 2:
162 return MISCREG_ID_DFR0;
163 case 3:
164 return MISCREG_ID_AFR0;
165 case 4:
166 return MISCREG_ID_MMFR0;
167 case 5:
168 return MISCREG_ID_MMFR1;
169 case 6:
170 return MISCREG_ID_MMFR2;
171 case 7:
172 return MISCREG_ID_MMFR3;
173 }
174 break;
175 case 2:
176 switch (opc2) {
177 case 0:
178 return MISCREG_ID_ISAR0;
179 case 1:
180 return MISCREG_ID_ISAR1;
181 case 2:
182 return MISCREG_ID_ISAR2;
183 case 3:
184 return MISCREG_ID_ISAR3;
185 case 4:
186 return MISCREG_ID_ISAR4;
187 case 5:
188 return MISCREG_ID_ISAR5;
189 case 6:
190 case 7:
191 return MISCREG_RAZ; // read as zero
192 }
193 break;
194 default:
195 return MISCREG_RAZ; // read as zero
196 }
197 break;
198 case 1:
199 if (crm == 0) {
200 switch (opc2) {
201 case 0:
202 return MISCREG_CCSIDR;
203 case 1:
204 return MISCREG_CLIDR;
205 case 7:
206 return MISCREG_AIDR;
207 }
208 }
209 break;
210 case 2:
211 if (crm == 0 && opc2 == 0) {
212 return MISCREG_CSSELR;
213 }
214 break;
215 case 4:
216 if (crm == 0) {
217 if (opc2 == 0)
218 return MISCREG_VPIDR;
219 else if (opc2 == 5)
220 return MISCREG_VMPIDR;
221 }
222 break;
223 }
224 break;
225 case 1:
226 if (opc1 == 0) {
227 if (crm == 0) {
228 switch (opc2) {
229 case 0:
230 return MISCREG_SCTLR;
231 case 1:
232 return MISCREG_ACTLR;
233 case 0x2:
234 return MISCREG_CPACR;
235 }
236 } else if (crm == 1) {
237 switch (opc2) {
238 case 0:
239 return MISCREG_SCR;
240 case 1:
241 return MISCREG_SDER;
242 case 2:
243 return MISCREG_NSACR;
244 }
245 }
246 } else if (opc1 == 4) {
247 if (crm == 0) {
248 if (opc2 == 0)
249 return MISCREG_HSCTLR;
250 else if (opc2 == 1)
251 return MISCREG_HACTLR;
252 } else if (crm == 1) {
253 switch (opc2) {
254 case 0:
255 return MISCREG_HCR;
256 case 1:
257 return MISCREG_HDCR;
258 case 2:
259 return MISCREG_HCPTR;
260 case 3:
261 return MISCREG_HSTR;
262 case 7:
263 return MISCREG_HACR;
264 }
265 }
266 }
267 break;
268 case 2:
269 if (opc1 == 0 && crm == 0) {
270 switch (opc2) {
271 case 0:
272 return MISCREG_TTBR0;
273 case 1:
274 return MISCREG_TTBR1;
275 case 2:
276 return MISCREG_TTBCR;
277 }
278 } else if (opc1 == 4) {
279 if (crm == 0 && opc2 == 2)
280 return MISCREG_HTCR;
281 else if (crm == 1 && opc2 == 2)
282 return MISCREG_VTCR;
283 }
284 break;
285 case 3:
286 if (opc1 == 0 && crm == 0 && opc2 == 0) {
287 return MISCREG_DACR;
288 }
289 break;
290 case 4:
291 if (opc1 == 0 && crm == 6 && opc2 == 0) {
292 return MISCREG_ICC_PMR;
293 }
294 break;
295 case 5:
296 if (opc1 == 0) {
297 if (crm == 0) {
298 if (opc2 == 0) {
299 return MISCREG_DFSR;
300 } else if (opc2 == 1) {
301 return MISCREG_IFSR;
302 }
303 } else if (crm == 1) {
304 if (opc2 == 0) {
305 return MISCREG_ADFSR;
306 } else if (opc2 == 1) {
307 return MISCREG_AIFSR;
308 }
309 }
310 } else if (opc1 == 4) {
311 if (crm == 1) {
312 if (opc2 == 0)
313 return MISCREG_HADFSR;
314 else if (opc2 == 1)
315 return MISCREG_HAIFSR;
316 } else if (crm == 2 && opc2 == 0) {
317 return MISCREG_HSR;
318 }
319 }
320 break;
321 case 6:
322 if (opc1 == 0 && crm == 0) {
323 switch (opc2) {
324 case 0:
325 return MISCREG_DFAR;
326 case 2:
327 return MISCREG_IFAR;
328 }
329 } else if (opc1 == 4 && crm == 0) {
330 switch (opc2) {
331 case 0:
332 return MISCREG_HDFAR;
333 case 2:
334 return MISCREG_HIFAR;
335 case 4:
336 return MISCREG_HPFAR;
337 }
338 }
339 break;
340 case 7:
341 if (opc1 == 0) {
342 switch (crm) {
343 case 0:
344 if (opc2 == 4) {
345 return MISCREG_NOP;
346 }
347 break;
348 case 1:
349 switch (opc2) {
350 case 0:
351 return MISCREG_ICIALLUIS;
352 case 6:
353 return MISCREG_BPIALLIS;
354 }
355 break;
356 case 4:
357 if (opc2 == 0) {
358 return MISCREG_PAR;
359 }
360 break;
361 case 5:
362 switch (opc2) {
363 case 0:
364 return MISCREG_ICIALLU;
365 case 1:
366 return MISCREG_ICIMVAU;
367 case 4:
368 return MISCREG_CP15ISB;
369 case 6:
370 return MISCREG_BPIALL;
371 case 7:
372 return MISCREG_BPIMVA;
373 }
374 break;
375 case 6:
376 if (opc2 == 1) {
377 return MISCREG_DCIMVAC;
378 } else if (opc2 == 2) {
379 return MISCREG_DCISW;
380 }
381 break;
382 case 8:
383 switch (opc2) {
384 case 0:
385 return MISCREG_ATS1CPR;
386 case 1:
387 return MISCREG_ATS1CPW;
388 case 2:
389 return MISCREG_ATS1CUR;
390 case 3:
391 return MISCREG_ATS1CUW;
392 case 4:
393 return MISCREG_ATS12NSOPR;
394 case 5:
395 return MISCREG_ATS12NSOPW;
396 case 6:
397 return MISCREG_ATS12NSOUR;
398 case 7:
399 return MISCREG_ATS12NSOUW;
400 }
401 break;
402 case 10:
403 switch (opc2) {
404 case 1:
405 return MISCREG_DCCMVAC;
406 case 2:
407 return MISCREG_DCCSW;
408 case 4:
409 return MISCREG_CP15DSB;
410 case 5:
411 return MISCREG_CP15DMB;
412 }
413 break;
414 case 11:
415 if (opc2 == 1) {
416 return MISCREG_DCCMVAU;
417 }
418 break;
419 case 13:
420 if (opc2 == 1) {
421 return MISCREG_NOP;
422 }
423 break;
424 case 14:
425 if (opc2 == 1) {
426 return MISCREG_DCCIMVAC;
427 } else if (opc2 == 2) {
428 return MISCREG_DCCISW;
429 }
430 break;
431 }
432 } else if (opc1 == 4 && crm == 8) {
433 if (opc2 == 0)
434 return MISCREG_ATS1HR;
435 else if (opc2 == 1)
436 return MISCREG_ATS1HW;
437 }
438 break;
439 case 8:
440 if (opc1 == 0) {
441 switch (crm) {
442 case 3:
443 switch (opc2) {
444 case 0:
445 return MISCREG_TLBIALLIS;
446 case 1:
447 return MISCREG_TLBIMVAIS;
448 case 2:
449 return MISCREG_TLBIASIDIS;
450 case 3:
451 return MISCREG_TLBIMVAAIS;
452 case 5:
453 return MISCREG_TLBIMVALIS;
454 case 7:
455 return MISCREG_TLBIMVAALIS;
456 }
457 break;
458 case 5:
459 switch (opc2) {
460 case 0:
461 return MISCREG_ITLBIALL;
462 case 1:
463 return MISCREG_ITLBIMVA;
464 case 2:
465 return MISCREG_ITLBIASID;
466 }
467 break;
468 case 6:
469 switch (opc2) {
470 case 0:
471 return MISCREG_DTLBIALL;
472 case 1:
473 return MISCREG_DTLBIMVA;
474 case 2:
475 return MISCREG_DTLBIASID;
476 }
477 break;
478 case 7:
479 switch (opc2) {
480 case 0:
481 return MISCREG_TLBIALL;
482 case 1:
483 return MISCREG_TLBIMVA;
484 case 2:
485 return MISCREG_TLBIASID;
486 case 3:
487 return MISCREG_TLBIMVAA;
488 case 5:
489 return MISCREG_TLBIMVAL;
490 case 7:
491 return MISCREG_TLBIMVAAL;
492 }
493 break;
494 }
495 } else if (opc1 == 4) {
496 if (crm == 0) {
497 switch (opc2) {
498 case 1:
499 return MISCREG_TLBIIPAS2IS;
500 case 5:
501 return MISCREG_TLBIIPAS2LIS;
502 }
503 } else if (crm == 3) {
504 switch (opc2) {
505 case 0:
506 return MISCREG_TLBIALLHIS;
507 case 1:
508 return MISCREG_TLBIMVAHIS;
509 case 4:
510 return MISCREG_TLBIALLNSNHIS;
511 case 5:
512 return MISCREG_TLBIMVALHIS;
513 }
514 } else if (crm == 4) {
515 switch (opc2) {
516 case 1:
517 return MISCREG_TLBIIPAS2;
518 case 5:
519 return MISCREG_TLBIIPAS2L;
520 }
521 } else if (crm == 7) {
522 switch (opc2) {
523 case 0:
524 return MISCREG_TLBIALLH;
525 case 1:
526 return MISCREG_TLBIMVAH;
527 case 4:
528 return MISCREG_TLBIALLNSNH;
529 case 5:
530 return MISCREG_TLBIMVALH;
531 }
532 }
533 }
534 break;
535 case 9:
536 // Every cop register with CRn = 9 and CRm in
537 // {0-2}, {5-8} is implementation defined regardless
538 // of opc1 and opc2.
539 switch (crm) {
540 case 0:
541 case 1:
542 case 2:
543 case 5:
544 case 6:
545 case 7:
546 case 8:
547 return MISCREG_IMPDEF_UNIMPL;
548 }
549 if (opc1 == 0) {
550 switch (crm) {
551 case 12:
552 switch (opc2) {
553 case 0:
554 return MISCREG_PMCR;
555 case 1:
556 return MISCREG_PMCNTENSET;
557 case 2:
558 return MISCREG_PMCNTENCLR;
559 case 3:
560 return MISCREG_PMOVSR;
561 case 4:
562 return MISCREG_PMSWINC;
563 case 5:
564 return MISCREG_PMSELR;
565 case 6:
566 return MISCREG_PMCEID0;
567 case 7:
568 return MISCREG_PMCEID1;
569 }
570 break;
571 case 13:
572 switch (opc2) {
573 case 0:
574 return MISCREG_PMCCNTR;
575 case 1:
576 // Selector is PMSELR.SEL
577 return MISCREG_PMXEVTYPER_PMCCFILTR;
578 case 2:
579 return MISCREG_PMXEVCNTR;
580 }
581 break;
582 case 14:
583 switch (opc2) {
584 case 0:
585 return MISCREG_PMUSERENR;
586 case 1:
587 return MISCREG_PMINTENSET;
588 case 2:
589 return MISCREG_PMINTENCLR;
590 case 3:
591 return MISCREG_PMOVSSET;
592 }
593 break;
594 }
595 } else if (opc1 == 1) {
596 switch (crm) {
597 case 0:
598 switch (opc2) {
599 case 2: // L2CTLR, L2 Control Register
600 return MISCREG_L2CTLR;
601 case 3:
602 return MISCREG_L2ECTLR;
603 }
604 break;
605 break;
606 }
607 }
608 break;
609 case 10:
610 if (opc1 == 0) {
611 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
612 if (crm < 2) {
613 return MISCREG_IMPDEF_UNIMPL;
614 } else if (crm == 2) { // TEX Remap Registers
615 if (opc2 == 0) {
616 // Selector is TTBCR.EAE
617 return MISCREG_PRRR_MAIR0;
618 } else if (opc2 == 1) {
619 // Selector is TTBCR.EAE
620 return MISCREG_NMRR_MAIR1;
621 }
622 } else if (crm == 3) {
623 if (opc2 == 0) {
624 return MISCREG_AMAIR0;
625 } else if (opc2 == 1) {
626 return MISCREG_AMAIR1;
627 }
628 }
629 } else if (opc1 == 4) {
630 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
631 if (crm == 2) {
632 if (opc2 == 0)
633 return MISCREG_HMAIR0;
634 else if (opc2 == 1)
635 return MISCREG_HMAIR1;
636 } else if (crm == 3) {
637 if (opc2 == 0)
638 return MISCREG_HAMAIR0;
639 else if (opc2 == 1)
640 return MISCREG_HAMAIR1;
641 }
642 }
643 break;
644 case 11:
645 if (opc1 <=7) {
646 switch (crm) {
647 case 0:
648 case 1:
649 case 2:
650 case 3:
651 case 4:
652 case 5:
653 case 6:
654 case 7:
655 case 8:
656 case 15:
657 // Reserved for DMA operations for TCM access
658 return MISCREG_IMPDEF_UNIMPL;
659 default:
660 break;
661 }
662 }
663 break;
664 case 12:
665 if (opc1 == 0) {
666 if (crm == 0) {
667 if (opc2 == 0) {
668 return MISCREG_VBAR;
669 } else if (opc2 == 1) {
670 return MISCREG_MVBAR;
671 }
672 } else if (crm == 1) {
673 if (opc2 == 0) {
674 return MISCREG_ISR;
675 }
676 } else if (crm == 8) {
677 switch (opc2) {
678 case 0:
679 return MISCREG_ICC_IAR0;
680 case 1:
681 return MISCREG_ICC_EOIR0;
682 case 2:
683 return MISCREG_ICC_HPPIR0;
684 case 3:
685 return MISCREG_ICC_BPR0;
686 case 4:
687 return MISCREG_ICC_AP0R0;
688 case 5:
689 return MISCREG_ICC_AP0R1;
690 case 6:
691 return MISCREG_ICC_AP0R2;
692 case 7:
693 return MISCREG_ICC_AP0R3;
694 }
695 } else if (crm == 9) {
696 switch (opc2) {
697 case 0:
698 return MISCREG_ICC_AP1R0;
699 case 1:
700 return MISCREG_ICC_AP1R1;
701 case 2:
702 return MISCREG_ICC_AP1R2;
703 case 3:
704 return MISCREG_ICC_AP1R3;
705 }
706 } else if (crm == 11) {
707 switch (opc2) {
708 case 1:
709 return MISCREG_ICC_DIR;
710 case 3:
711 return MISCREG_ICC_RPR;
712 }
713 } else if (crm == 12) {
714 switch (opc2) {
715 case 0:
716 return MISCREG_ICC_IAR1;
717 case 1:
718 return MISCREG_ICC_EOIR1;
719 case 2:
720 return MISCREG_ICC_HPPIR1;
721 case 3:
722 return MISCREG_ICC_BPR1;
723 case 4:
724 return MISCREG_ICC_CTLR;
725 case 5:
726 return MISCREG_ICC_SRE;
727 case 6:
728 return MISCREG_ICC_IGRPEN0;
729 case 7:
730 return MISCREG_ICC_IGRPEN1;
731 }
732 }
733 } else if (opc1 == 4) {
734 if (crm == 0 && opc2 == 0) {
735 return MISCREG_HVBAR;
736 } else if (crm == 8) {
737 switch (opc2) {
738 case 0:
739 return MISCREG_ICH_AP0R0;
740 case 1:
741 return MISCREG_ICH_AP0R1;
742 case 2:
743 return MISCREG_ICH_AP0R2;
744 case 3:
745 return MISCREG_ICH_AP0R3;
746 }
747 } else if (crm == 9) {
748 switch (opc2) {
749 case 0:
750 return MISCREG_ICH_AP1R0;
751 case 1:
752 return MISCREG_ICH_AP1R1;
753 case 2:
754 return MISCREG_ICH_AP1R2;
755 case 3:
756 return MISCREG_ICH_AP1R3;
757 case 5:
758 return MISCREG_ICC_HSRE;
759 }
760 } else if (crm == 11) {
761 switch (opc2) {
762 case 0:
763 return MISCREG_ICH_HCR;
764 case 1:
765 return MISCREG_ICH_VTR;
766 case 2:
767 return MISCREG_ICH_MISR;
768 case 3:
769 return MISCREG_ICH_EISR;
770 case 5:
771 return MISCREG_ICH_ELRSR;
772 case 7:
773 return MISCREG_ICH_VMCR;
774 }
775 } else if (crm == 12) {
776 switch (opc2) {
777 case 0:
778 return MISCREG_ICH_LR0;
779 case 1:
780 return MISCREG_ICH_LR1;
781 case 2:
782 return MISCREG_ICH_LR2;
783 case 3:
784 return MISCREG_ICH_LR3;
785 case 4:
786 return MISCREG_ICH_LR4;
787 case 5:
788 return MISCREG_ICH_LR5;
789 case 6:
790 return MISCREG_ICH_LR6;
791 case 7:
792 return MISCREG_ICH_LR7;
793 }
794 } else if (crm == 13) {
795 switch (opc2) {
796 case 0:
797 return MISCREG_ICH_LR8;
798 case 1:
799 return MISCREG_ICH_LR9;
800 case 2:
801 return MISCREG_ICH_LR10;
802 case 3:
803 return MISCREG_ICH_LR11;
804 case 4:
805 return MISCREG_ICH_LR12;
806 case 5:
807 return MISCREG_ICH_LR13;
808 case 6:
809 return MISCREG_ICH_LR14;
810 case 7:
811 return MISCREG_ICH_LR15;
812 }
813 } else if (crm == 14) {
814 switch (opc2) {
815 case 0:
816 return MISCREG_ICH_LRC0;
817 case 1:
818 return MISCREG_ICH_LRC1;
819 case 2:
820 return MISCREG_ICH_LRC2;
821 case 3:
822 return MISCREG_ICH_LRC3;
823 case 4:
824 return MISCREG_ICH_LRC4;
825 case 5:
826 return MISCREG_ICH_LRC5;
827 case 6:
828 return MISCREG_ICH_LRC6;
829 case 7:
830 return MISCREG_ICH_LRC7;
831 }
832 } else if (crm == 15) {
833 switch (opc2) {
834 case 0:
835 return MISCREG_ICH_LRC8;
836 case 1:
837 return MISCREG_ICH_LRC9;
838 case 2:
839 return MISCREG_ICH_LRC10;
840 case 3:
841 return MISCREG_ICH_LRC11;
842 case 4:
843 return MISCREG_ICH_LRC12;
844 case 5:
845 return MISCREG_ICH_LRC13;
846 case 6:
847 return MISCREG_ICH_LRC14;
848 case 7:
849 return MISCREG_ICH_LRC15;
850 }
851 }
852 } else if (opc1 == 6) {
853 if (crm == 12) {
854 switch (opc2) {
855 case 4:
856 return MISCREG_ICC_MCTLR;
857 case 5:
858 return MISCREG_ICC_MSRE;
859 case 7:
860 return MISCREG_ICC_MGRPEN1;
861 }
862 }
863 }
864 break;
865 case 13:
866 if (opc1 == 0) {
867 if (crm == 0) {
868 switch (opc2) {
869 case 0:
870 return MISCREG_FCSEIDR;
871 case 1:
872 return MISCREG_CONTEXTIDR;
873 case 2:
874 return MISCREG_TPIDRURW;
875 case 3:
876 return MISCREG_TPIDRURO;
877 case 4:
878 return MISCREG_TPIDRPRW;
879 }
880 }
881 } else if (opc1 == 4) {
882 if (crm == 0 && opc2 == 2)
883 return MISCREG_HTPIDR;
884 }
885 break;
886 case 14:
887 if (opc1 == 0) {
888 switch (crm) {
889 case 0:
890 if (opc2 == 0)
891 return MISCREG_CNTFRQ;
892 break;
893 case 1:
894 if (opc2 == 0)
895 return MISCREG_CNTKCTL;
896 break;
897 case 2:
898 if (opc2 == 0)
899 return MISCREG_CNTP_TVAL;
900 else if (opc2 == 1)
901 return MISCREG_CNTP_CTL;
902 break;
903 case 3:
904 if (opc2 == 0)
905 return MISCREG_CNTV_TVAL;
906 else if (opc2 == 1)
907 return MISCREG_CNTV_CTL;
908 break;
909 }
910 } else if (opc1 == 4) {
911 if (crm == 1 && opc2 == 0) {
912 return MISCREG_CNTHCTL;
913 } else if (crm == 2) {
914 if (opc2 == 0)
915 return MISCREG_CNTHP_TVAL;
916 else if (opc2 == 1)
917 return MISCREG_CNTHP_CTL;
918 }
919 }
920 break;
921 case 15:
922 // Implementation defined
923 return MISCREG_IMPDEF_UNIMPL;
924 }
925 // Unrecognized register
926 return MISCREG_CP15_UNIMPL;
927}
928
929MiscRegIndex
930decodeCP15Reg64(unsigned crm, unsigned opc1)
931{
932 switch (crm) {
933 case 2:
934 switch (opc1) {
935 case 0:
936 return MISCREG_TTBR0;
937 case 1:
938 return MISCREG_TTBR1;
939 case 4:
940 return MISCREG_HTTBR;
941 case 6:
942 return MISCREG_VTTBR;
943 }
944 break;
945 case 7:
946 if (opc1 == 0)
947 return MISCREG_PAR;
948 break;
949 case 14:
950 switch (opc1) {
951 case 0:
952 return MISCREG_CNTPCT;
953 case 1:
954 return MISCREG_CNTVCT;
955 case 2:
956 return MISCREG_CNTP_CVAL;
957 case 3:
958 return MISCREG_CNTV_CVAL;
959 case 4:
960 return MISCREG_CNTVOFF;
961 case 6:
962 return MISCREG_CNTHP_CVAL;
963 }
964 break;
965 case 15:
966 if (opc1 == 0)
967 return MISCREG_CPUMERRSR;
968 else if (opc1 == 1)
969 return MISCREG_L2MERRSR;
970 break;
971 }
972 // Unrecognized register
973 return MISCREG_CP15_UNIMPL;
974}
975
976std::tuple<bool, bool>
977canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
978{
979 bool secure = !scr.ns;
980 bool canRead = false;
981 bool undefined = false;
982
983 switch (cpsr.mode) {
984 case MODE_USER:
985 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
986 miscRegInfo[reg][MISCREG_USR_NS_RD];
987 break;
988 case MODE_FIQ:
989 case MODE_IRQ:
990 case MODE_SVC:
991 case MODE_ABORT:
992 case MODE_UNDEFINED:
993 case MODE_SYSTEM:
994 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
995 miscRegInfo[reg][MISCREG_PRI_NS_RD];
996 break;
997 case MODE_MON:
998 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
999 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1000 break;
1001 case MODE_HYP:
1002 canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1003 break;
1004 default:
1005 undefined = true;
1006 }
1007 // can't do permissions checkes on the root of a banked pair of regs
1008 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1009 return std::make_tuple(canRead, undefined);
1010}
1011
1012std::tuple<bool, bool>
1013canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
1014{
1015 bool secure = !scr.ns;
1016 bool canWrite = false;
1017 bool undefined = false;
1018
1019 switch (cpsr.mode) {
1020 case MODE_USER:
1021 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1022 miscRegInfo[reg][MISCREG_USR_NS_WR];
1023 break;
1024 case MODE_FIQ:
1025 case MODE_IRQ:
1026 case MODE_SVC:
1027 case MODE_ABORT:
1028 case MODE_UNDEFINED:
1029 case MODE_SYSTEM:
1030 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1031 miscRegInfo[reg][MISCREG_PRI_NS_WR];
1032 break;
1033 case MODE_MON:
1034 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1035 miscRegInfo[reg][MISCREG_MON_NS1_WR];
1036 break;
1037 case MODE_HYP:
1038 canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
1039 break;
1040 default:
1041 undefined = true;
1042 }
1043 // can't do permissions checkes on the root of a banked pair of regs
1044 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1045 return std::make_tuple(canWrite, undefined);
1046}
1047
1048int
1049snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
1050{
1051 SCR scr = tc->readMiscReg(MISCREG_SCR);
1052 return snsBankedIndex(reg, tc, scr.ns);
1053}
1054
1055int
1056snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
1057{
1058 int reg_as_int = static_cast<int>(reg);
1059 if (miscRegInfo[reg][MISCREG_BANKED]) {
1060 reg_as_int += (ArmSystem::haveSecurity(tc) &&
1061 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
1062 }
1063 return reg_as_int;
1064}
1065
1066
1067/**
1068 * If the reg is a child reg of a banked set, then the parent is the last
1069 * banked one in the list. This is messy, and the wish is to eventually have
1070 * the bitmap replaced with a better data structure. the preUnflatten function
1071 * initializes a lookup table to speed up the search for these banked
1072 * registers.
1073 */
1074
1075int unflattenResultMiscReg[NUM_MISCREGS];
1076
1077void
1078preUnflattenMiscReg()
1079{
1080 int reg = -1;
1081 for (int i = 0 ; i < NUM_MISCREGS; i++){
1082 if (miscRegInfo[i][MISCREG_BANKED])
1083 reg = i;
1084 if (miscRegInfo[i][MISCREG_BANKED_CHILD])
1085 unflattenResultMiscReg[i] = reg;
1086 else
1087 unflattenResultMiscReg[i] = i;
1088 // if this assert fails, no parent was found, and something is broken
1089 assert(unflattenResultMiscReg[i] > -1);
1090 }
1091}
1092
1093int
1094unflattenMiscReg(int reg)
1095{
1096 return unflattenResultMiscReg[reg];
1097}
1098
1099bool
1100canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1101{
1102 // Check for SP_EL0 access while SPSEL == 0
1103 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1104 return false;
1105
1106 // Check for RVBAR access
1107 if (reg == MISCREG_RVBAR_EL1) {
1108 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1109 if (highest_el == EL2 || highest_el == EL3)
1110 return false;
1111 }
1112 if (reg == MISCREG_RVBAR_EL2) {
1113 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1114 if (highest_el == EL3)
1115 return false;
1116 }
1117
1118 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1119
1120 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
1121 case EL0:
1122 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1123 miscRegInfo[reg][MISCREG_USR_NS_RD];
1124 case EL1:
1125 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1126 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1127 case EL2:
1128 return miscRegInfo[reg][MISCREG_HYP_RD];
1129 case EL3:
1130 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1131 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1132 default:
1133 panic("Invalid exception level");
1134 }
1135}
1136
1137bool
1138canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1139{
1140 // Check for SP_EL0 access while SPSEL == 0
1141 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1142 return false;
1143 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
1144 if (reg == MISCREG_DAIF) {
1145 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1146 if (el == EL0 && !sctlr.uma)
1147 return false;
1148 }
1149 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
1150 // In syscall-emulation mode, this test is skipped and DCZVA is always
1151 // allowed at EL0
1152 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1153 if (el == EL0 && !sctlr.dze)
1154 return false;
1155 }
1156 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
1157 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1158 if (el == EL0 && !sctlr.uci)
1159 return false;
1160 }
1161
1162 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1163
1164 switch (el) {
1165 case EL0:
1166 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1167 miscRegInfo[reg][MISCREG_USR_NS_WR];
1168 case EL1:
1169 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1170 miscRegInfo[reg][MISCREG_PRI_NS_WR];
1171 case EL2:
1172 return miscRegInfo[reg][MISCREG_HYP_WR];
1173 case EL3:
1174 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1175 miscRegInfo[reg][MISCREG_MON_NS1_WR];
1176 default:
1177 panic("Invalid exception level");
1178 }
1179}
1180
1181MiscRegIndex
1182decodeAArch64SysReg(unsigned op0, unsigned op1,
1183 unsigned crn, unsigned crm,
1184 unsigned op2)
1185{
1186 switch (op0) {
1187 case 1:
1188 switch (crn) {
1189 case 7:
1190 switch (op1) {
1191 case 0:
1192 switch (crm) {
1193 case 1:
1194 switch (op2) {
1195 case 0:
1196 return MISCREG_IC_IALLUIS;
1197 }
1198 break;
1199 case 5:
1200 switch (op2) {
1201 case 0:
1202 return MISCREG_IC_IALLU;
1203 }
1204 break;
1205 case 6:
1206 switch (op2) {
1207 case 1:
1208 return MISCREG_DC_IVAC_Xt;
1209 case 2:
1210 return MISCREG_DC_ISW_Xt;
1211 }
1212 break;
1213 case 8:
1214 switch (op2) {
1215 case 0:
1216 return MISCREG_AT_S1E1R_Xt;
1217 case 1:
1218 return MISCREG_AT_S1E1W_Xt;
1219 case 2:
1220 return MISCREG_AT_S1E0R_Xt;
1221 case 3:
1222 return MISCREG_AT_S1E0W_Xt;
1223 }
1224 break;
1225 case 10:
1226 switch (op2) {
1227 case 2:
1228 return MISCREG_DC_CSW_Xt;
1229 }
1230 break;
1231 case 14:
1232 switch (op2) {
1233 case 2:
1234 return MISCREG_DC_CISW_Xt;
1235 }
1236 break;
1237 }
1238 break;
1239 case 3:
1240 switch (crm) {
1241 case 4:
1242 switch (op2) {
1243 case 1:
1244 return MISCREG_DC_ZVA_Xt;
1245 }
1246 break;
1247 case 5:
1248 switch (op2) {
1249 case 1:
1250 return MISCREG_IC_IVAU_Xt;
1251 }
1252 break;
1253 case 10:
1254 switch (op2) {
1255 case 1:
1256 return MISCREG_DC_CVAC_Xt;
1257 }
1258 break;
1259 case 11:
1260 switch (op2) {
1261 case 1:
1262 return MISCREG_DC_CVAU_Xt;
1263 }
1264 break;
1265 case 14:
1266 switch (op2) {
1267 case 1:
1268 return MISCREG_DC_CIVAC_Xt;
1269 }
1270 break;
1271 }
1272 break;
1273 case 4:
1274 switch (crm) {
1275 case 8:
1276 switch (op2) {
1277 case 0:
1278 return MISCREG_AT_S1E2R_Xt;
1279 case 1:
1280 return MISCREG_AT_S1E2W_Xt;
1281 case 4:
1282 return MISCREG_AT_S12E1R_Xt;
1283 case 5:
1284 return MISCREG_AT_S12E1W_Xt;
1285 case 6:
1286 return MISCREG_AT_S12E0R_Xt;
1287 case 7:
1288 return MISCREG_AT_S12E0W_Xt;
1289 }
1290 break;
1291 }
1292 break;
1293 case 6:
1294 switch (crm) {
1295 case 8:
1296 switch (op2) {
1297 case 0:
1298 return MISCREG_AT_S1E3R_Xt;
1299 case 1:
1300 return MISCREG_AT_S1E3W_Xt;
1301 }
1302 break;
1303 }
1304 break;
1305 }
1306 break;
1307 case 8:
1308 switch (op1) {
1309 case 0:
1310 switch (crm) {
1311 case 3:
1312 switch (op2) {
1313 case 0:
1314 return MISCREG_TLBI_VMALLE1IS;
1315 case 1:
1316 return MISCREG_TLBI_VAE1IS_Xt;
1317 case 2:
1318 return MISCREG_TLBI_ASIDE1IS_Xt;
1319 case 3:
1320 return MISCREG_TLBI_VAAE1IS_Xt;
1321 case 5:
1322 return MISCREG_TLBI_VALE1IS_Xt;
1323 case 7:
1324 return MISCREG_TLBI_VAALE1IS_Xt;
1325 }
1326 break;
1327 case 7:
1328 switch (op2) {
1329 case 0:
1330 return MISCREG_TLBI_VMALLE1;
1331 case 1:
1332 return MISCREG_TLBI_VAE1_Xt;
1333 case 2:
1334 return MISCREG_TLBI_ASIDE1_Xt;
1335 case 3:
1336 return MISCREG_TLBI_VAAE1_Xt;
1337 case 5:
1338 return MISCREG_TLBI_VALE1_Xt;
1339 case 7:
1340 return MISCREG_TLBI_VAALE1_Xt;
1341 }
1342 break;
1343 }
1344 break;
1345 case 4:
1346 switch (crm) {
1347 case 0:
1348 switch (op2) {
1349 case 1:
1350 return MISCREG_TLBI_IPAS2E1IS_Xt;
1351 case 5:
1352 return MISCREG_TLBI_IPAS2LE1IS_Xt;
1353 }
1354 break;
1355 case 3:
1356 switch (op2) {
1357 case 0:
1358 return MISCREG_TLBI_ALLE2IS;
1359 case 1:
1360 return MISCREG_TLBI_VAE2IS_Xt;
1361 case 4:
1362 return MISCREG_TLBI_ALLE1IS;
1363 case 5:
1364 return MISCREG_TLBI_VALE2IS_Xt;
1365 case 6:
1366 return MISCREG_TLBI_VMALLS12E1IS;
1367 }
1368 break;
1369 case 4:
1370 switch (op2) {
1371 case 1:
1372 return MISCREG_TLBI_IPAS2E1_Xt;
1373 case 5:
1374 return MISCREG_TLBI_IPAS2LE1_Xt;
1375 }
1376 break;
1377 case 7:
1378 switch (op2) {
1379 case 0:
1380 return MISCREG_TLBI_ALLE2;
1381 case 1:
1382 return MISCREG_TLBI_VAE2_Xt;
1383 case 4:
1384 return MISCREG_TLBI_ALLE1;
1385 case 5:
1386 return MISCREG_TLBI_VALE2_Xt;
1387 case 6:
1388 return MISCREG_TLBI_VMALLS12E1;
1389 }
1390 break;
1391 }
1392 break;
1393 case 6:
1394 switch (crm) {
1395 case 3:
1396 switch (op2) {
1397 case 0:
1398 return MISCREG_TLBI_ALLE3IS;
1399 case 1:
1400 return MISCREG_TLBI_VAE3IS_Xt;
1401 case 5:
1402 return MISCREG_TLBI_VALE3IS_Xt;
1403 }
1404 break;
1405 case 7:
1406 switch (op2) {
1407 case 0:
1408 return MISCREG_TLBI_ALLE3;
1409 case 1:
1410 return MISCREG_TLBI_VAE3_Xt;
1411 case 5:
1412 return MISCREG_TLBI_VALE3_Xt;
1413 }
1414 break;
1415 }
1416 break;
1417 }
1418 break;
1419 case 11:
1420 case 15:
1421 // SYS Instruction with CRn = { 11, 15 }
1422 // (Trappable by HCR_EL2.TIDCP)
1423 return MISCREG_IMPDEF_UNIMPL;
1424 }
1425 break;
1426 case 2:
1427 switch (crn) {
1428 case 0:
1429 switch (op1) {
1430 case 0:
1431 switch (crm) {
1432 case 0:
1433 switch (op2) {
1434 case 2:
1435 return MISCREG_OSDTRRX_EL1;
1436 case 4:
1437 return MISCREG_DBGBVR0_EL1;
1438 case 5:
1439 return MISCREG_DBGBCR0_EL1;
1440 case 6:
1441 return MISCREG_DBGWVR0_EL1;
1442 case 7:
1443 return MISCREG_DBGWCR0_EL1;
1444 }
1445 break;
1446 case 1:
1447 switch (op2) {
1448 case 4:
1449 return MISCREG_DBGBVR1_EL1;
1450 case 5:
1451 return MISCREG_DBGBCR1_EL1;
1452 case 6:
1453 return MISCREG_DBGWVR1_EL1;
1454 case 7:
1455 return MISCREG_DBGWCR1_EL1;
1456 }
1457 break;
1458 case 2:
1459 switch (op2) {
1460 case 0:
1461 return MISCREG_MDCCINT_EL1;
1462 case 2:
1463 return MISCREG_MDSCR_EL1;
1464 case 4:
1465 return MISCREG_DBGBVR2_EL1;
1466 case 5:
1467 return MISCREG_DBGBCR2_EL1;
1468 case 6:
1469 return MISCREG_DBGWVR2_EL1;
1470 case 7:
1471 return MISCREG_DBGWCR2_EL1;
1472 }
1473 break;
1474 case 3:
1475 switch (op2) {
1476 case 2:
1477 return MISCREG_OSDTRTX_EL1;
1478 case 4:
1479 return MISCREG_DBGBVR3_EL1;
1480 case 5:
1481 return MISCREG_DBGBCR3_EL1;
1482 case 6:
1483 return MISCREG_DBGWVR3_EL1;
1484 case 7:
1485 return MISCREG_DBGWCR3_EL1;
1486 }
1487 break;
1488 case 4:
1489 switch (op2) {
1490 case 4:
1491 return MISCREG_DBGBVR4_EL1;
1492 case 5:
1493 return MISCREG_DBGBCR4_EL1;
1494 }
1495 break;
1496 case 5:
1497 switch (op2) {
1498 case 4:
1499 return MISCREG_DBGBVR5_EL1;
1500 case 5:
1501 return MISCREG_DBGBCR5_EL1;
1502 }
1503 break;
1504 case 6:
1505 switch (op2) {
1506 case 2:
1507 return MISCREG_OSECCR_EL1;
1508 }
1509 break;
1510 }
1511 break;
1512 case 2:
1513 switch (crm) {
1514 case 0:
1515 switch (op2) {
1516 case 0:
1517 return MISCREG_TEECR32_EL1;
1518 }
1519 break;
1520 }
1521 break;
1522 case 3:
1523 switch (crm) {
1524 case 1:
1525 switch (op2) {
1526 case 0:
1527 return MISCREG_MDCCSR_EL0;
1528 }
1529 break;
1530 case 4:
1531 switch (op2) {
1532 case 0:
1533 return MISCREG_MDDTR_EL0;
1534 }
1535 break;
1536 case 5:
1537 switch (op2) {
1538 case 0:
1539 return MISCREG_MDDTRRX_EL0;
1540 }
1541 break;
1542 }
1543 break;
1544 case 4:
1545 switch (crm) {
1546 case 7:
1547 switch (op2) {
1548 case 0:
1549 return MISCREG_DBGVCR32_EL2;
1550 }
1551 break;
1552 }
1553 break;
1554 }
1555 break;
1556 case 1:
1557 switch (op1) {
1558 case 0:
1559 switch (crm) {
1560 case 0:
1561 switch (op2) {
1562 case 0:
1563 return MISCREG_MDRAR_EL1;
1564 case 4:
1565 return MISCREG_OSLAR_EL1;
1566 }
1567 break;
1568 case 1:
1569 switch (op2) {
1570 case 4:
1571 return MISCREG_OSLSR_EL1;
1572 }
1573 break;
1574 case 3:
1575 switch (op2) {
1576 case 4:
1577 return MISCREG_OSDLR_EL1;
1578 }
1579 break;
1580 case 4:
1581 switch (op2) {
1582 case 4:
1583 return MISCREG_DBGPRCR_EL1;
1584 }
1585 break;
1586 }
1587 break;
1588 case 2:
1589 switch (crm) {
1590 case 0:
1591 switch (op2) {
1592 case 0:
1593 return MISCREG_TEEHBR32_EL1;
1594 }
1595 break;
1596 }
1597 break;
1598 }
1599 break;
1600 case 7:
1601 switch (op1) {
1602 case 0:
1603 switch (crm) {
1604 case 8:
1605 switch (op2) {
1606 case 6:
1607 return MISCREG_DBGCLAIMSET_EL1;
1608 }
1609 break;
1610 case 9:
1611 switch (op2) {
1612 case 6:
1613 return MISCREG_DBGCLAIMCLR_EL1;
1614 }
1615 break;
1616 case 14:
1617 switch (op2) {
1618 case 6:
1619 return MISCREG_DBGAUTHSTATUS_EL1;
1620 }
1621 break;
1622 }
1623 break;
1624 }
1625 break;
1626 }
1627 break;
1628 case 3:
1629 switch (crn) {
1630 case 0:
1631 switch (op1) {
1632 case 0:
1633 switch (crm) {
1634 case 0:
1635 switch (op2) {
1636 case 0:
1637 return MISCREG_MIDR_EL1;
1638 case 5:
1639 return MISCREG_MPIDR_EL1;
1640 case 6:
1641 return MISCREG_REVIDR_EL1;
1642 }
1643 break;
1644 case 1:
1645 switch (op2) {
1646 case 0:
1647 return MISCREG_ID_PFR0_EL1;
1648 case 1:
1649 return MISCREG_ID_PFR1_EL1;
1650 case 2:
1651 return MISCREG_ID_DFR0_EL1;
1652 case 3:
1653 return MISCREG_ID_AFR0_EL1;
1654 case 4:
1655 return MISCREG_ID_MMFR0_EL1;
1656 case 5:
1657 return MISCREG_ID_MMFR1_EL1;
1658 case 6:
1659 return MISCREG_ID_MMFR2_EL1;
1660 case 7:
1661 return MISCREG_ID_MMFR3_EL1;
1662 }
1663 break;
1664 case 2:
1665 switch (op2) {
1666 case 0:
1667 return MISCREG_ID_ISAR0_EL1;
1668 case 1:
1669 return MISCREG_ID_ISAR1_EL1;
1670 case 2:
1671 return MISCREG_ID_ISAR2_EL1;
1672 case 3:
1673 return MISCREG_ID_ISAR3_EL1;
1674 case 4:
1675 return MISCREG_ID_ISAR4_EL1;
1676 case 5:
1677 return MISCREG_ID_ISAR5_EL1;
1678 }
1679 break;
1680 case 3:
1681 switch (op2) {
1682 case 0:
1683 return MISCREG_MVFR0_EL1;
1684 case 1:
1685 return MISCREG_MVFR1_EL1;
1686 case 2:
1687 return MISCREG_MVFR2_EL1;
1688 case 3 ... 7:
1689 return MISCREG_RAZ;
1690 }
1691 break;
1692 case 4:
1693 switch (op2) {
1694 case 0:
1695 return MISCREG_ID_AA64PFR0_EL1;
1696 case 1:
1697 return MISCREG_ID_AA64PFR1_EL1;
1698 case 2 ... 3:
1699 return MISCREG_RAZ;
1700 case 4:
1701 return MISCREG_ID_AA64ZFR0_EL1;
1702 case 5 ... 7:
1703 return MISCREG_RAZ;
1704 }
1705 break;
1706 case 5:
1707 switch (op2) {
1708 case 0:
1709 return MISCREG_ID_AA64DFR0_EL1;
1710 case 1:
1711 return MISCREG_ID_AA64DFR1_EL1;
1712 case 4:
1713 return MISCREG_ID_AA64AFR0_EL1;
1714 case 5:
1715 return MISCREG_ID_AA64AFR1_EL1;
1716 case 2:
1717 case 3:
1718 case 6:
1719 case 7:
1720 return MISCREG_RAZ;
1721 }
1722 break;
1723 case 6:
1724 switch (op2) {
1725 case 0:
1726 return MISCREG_ID_AA64ISAR0_EL1;
1727 case 1:
1728 return MISCREG_ID_AA64ISAR1_EL1;
1729 case 2 ... 7:
1730 return MISCREG_RAZ;
1731 }
1732 break;
1733 case 7:
1734 switch (op2) {
1735 case 0:
1736 return MISCREG_ID_AA64MMFR0_EL1;
1737 case 1:
1738 return MISCREG_ID_AA64MMFR1_EL1;
1739 case 2:
1740 return MISCREG_ID_AA64MMFR2_EL1;
1741 case 3 ... 7:
1742 return MISCREG_RAZ;
1743 }
1744 break;
1745 }
1746 break;
1747 case 1:
1748 switch (crm) {
1749 case 0:
1750 switch (op2) {
1751 case 0:
1752 return MISCREG_CCSIDR_EL1;
1753 case 1:
1754 return MISCREG_CLIDR_EL1;
1755 case 7:
1756 return MISCREG_AIDR_EL1;
1757 }
1758 break;
1759 }
1760 break;
1761 case 2:
1762 switch (crm) {
1763 case 0:
1764 switch (op2) {
1765 case 0:
1766 return MISCREG_CSSELR_EL1;
1767 }
1768 break;
1769 }
1770 break;
1771 case 3:
1772 switch (crm) {
1773 case 0:
1774 switch (op2) {
1775 case 1:
1776 return MISCREG_CTR_EL0;
1777 case 7:
1778 return MISCREG_DCZID_EL0;
1779 }
1780 break;
1781 }
1782 break;
1783 case 4:
1784 switch (crm) {
1785 case 0:
1786 switch (op2) {
1787 case 0:
1788 return MISCREG_VPIDR_EL2;
1789 case 5:
1790 return MISCREG_VMPIDR_EL2;
1791 }
1792 break;
1793 }
1794 break;
1795 }
1796 break;
1797 case 1:
1798 switch (op1) {
1799 case 0:
1800 switch (crm) {
1801 case 0:
1802 switch (op2) {
1803 case 0:
1804 return MISCREG_SCTLR_EL1;
1805 case 1:
1806 return MISCREG_ACTLR_EL1;
1807 case 2:
1808 return MISCREG_CPACR_EL1;
1809 }
1810 break;
1811 case 2:
1812 switch (op2) {
1813 case 0:
1814 return MISCREG_ZCR_EL1;
1815 }
1816 break;
1817 }
1818 break;
1819 case 4:
1820 switch (crm) {
1821 case 0:
1822 switch (op2) {
1823 case 0:
1824 return MISCREG_SCTLR_EL2;
1825 case 1:
1826 return MISCREG_ACTLR_EL2;
1827 }
1828 break;
1829 case 1:
1830 switch (op2) {
1831 case 0:
1832 return MISCREG_HCR_EL2;
1833 case 1:
1834 return MISCREG_MDCR_EL2;
1835 case 2:
1836 return MISCREG_CPTR_EL2;
1837 case 3:
1838 return MISCREG_HSTR_EL2;
1839 case 7:
1840 return MISCREG_HACR_EL2;
1841 }
1842 break;
1843 case 2:
1844 switch (op2) {
1845 case 0:
1846 return MISCREG_ZCR_EL2;
1847 }
1848 break;
1849 }
1850 break;
1851 case 5:
1852 switch (crm) {
1853 case 2:
1854 switch (op2) {
1855 case 0:
1856 return MISCREG_ZCR_EL12;
1857 }
1858 break;
1859 }
1860 break;
1861 case 6:
1862 switch (crm) {
1863 case 0:
1864 switch (op2) {
1865 case 0:
1866 return MISCREG_SCTLR_EL3;
1867 case 1:
1868 return MISCREG_ACTLR_EL3;
1869 }
1870 break;
1871 case 1:
1872 switch (op2) {
1873 case 0:
1874 return MISCREG_SCR_EL3;
1875 case 1:
1876 return MISCREG_SDER32_EL3;
1877 case 2:
1878 return MISCREG_CPTR_EL3;
1879 }
1880 break;
1881 case 2:
1882 switch (op2) {
1883 case 0:
1884 return MISCREG_ZCR_EL3;
1885 }
1886 break;
1887 case 3:
1888 switch (op2) {
1889 case 1:
1890 return MISCREG_MDCR_EL3;
1891 }
1892 break;
1893 }
1894 break;
1895 }
1896 break;
1897 case 2:
1898 switch (op1) {
1899 case 0:
1900 switch (crm) {
1901 case 0:
1902 switch (op2) {
1903 case 0:
1904 return MISCREG_TTBR0_EL1;
1905 case 1:
1906 return MISCREG_TTBR1_EL1;
1907 case 2:
1908 return MISCREG_TCR_EL1;
1909 }
1910 break;
1911 }
1912 break;
1913 case 4:
1914 switch (crm) {
1915 case 0:
1916 switch (op2) {
1917 case 0:
1918 return MISCREG_TTBR0_EL2;
1919 case 1:
1920 return MISCREG_TTBR1_EL2;
1921 case 2:
1922 return MISCREG_TCR_EL2;
1923 }
1924 break;
1925 case 1:
1926 switch (op2) {
1927 case 0:
1928 return MISCREG_VTTBR_EL2;
1929 case 2:
1930 return MISCREG_VTCR_EL2;
1931 }
1932 break;
1933 }
1934 break;
1935 case 6:
1936 switch (crm) {
1937 case 0:
1938 switch (op2) {
1939 case 0:
1940 return MISCREG_TTBR0_EL3;
1941 case 2:
1942 return MISCREG_TCR_EL3;
1943 }
1944 break;
1945 }
1946 break;
1947 }
1948 break;
1949 case 3:
1950 switch (op1) {
1951 case 4:
1952 switch (crm) {
1953 case 0:
1954 switch (op2) {
1955 case 0:
1956 return MISCREG_DACR32_EL2;
1957 }
1958 break;
1959 }
1960 break;
1961 }
1962 break;
1963 case 4:
1964 switch (op1) {
1965 case 0:
1966 switch (crm) {
1967 case 0:
1968 switch (op2) {
1969 case 0:
1970 return MISCREG_SPSR_EL1;
1971 case 1:
1972 return MISCREG_ELR_EL1;
1973 }
1974 break;
1975 case 1:
1976 switch (op2) {
1977 case 0:
1978 return MISCREG_SP_EL0;
1979 }
1980 break;
1981 case 2:
1982 switch (op2) {
1983 case 0:
1984 return MISCREG_SPSEL;
1985 case 2:
1986 return MISCREG_CURRENTEL;

1987 case 3:
1988 return MISCREG_PAN;

1989 }
1990 break;
1991 case 6:
1992 switch (op2) {
1993 case 0:
1994 return MISCREG_ICC_PMR_EL1;
1995 }
1996 break;
1997 }
1998 break;
1999 case 3:
2000 switch (crm) {
2001 case 2:
2002 switch (op2) {
2003 case 0:
2004 return MISCREG_NZCV;
2005 case 1:
2006 return MISCREG_DAIF;
2007 }
2008 break;
2009 case 4:
2010 switch (op2) {
2011 case 0:
2012 return MISCREG_FPCR;
2013 case 1:
2014 return MISCREG_FPSR;
2015 }
2016 break;
2017 case 5:
2018 switch (op2) {
2019 case 0:
2020 return MISCREG_DSPSR_EL0;
2021 case 1:
2022 return MISCREG_DLR_EL0;
2023 }
2024 break;
2025 }
2026 break;
2027 case 4:
2028 switch (crm) {
2029 case 0:
2030 switch (op2) {
2031 case 0:
2032 return MISCREG_SPSR_EL2;
2033 case 1:
2034 return MISCREG_ELR_EL2;
2035 }
2036 break;
2037 case 1:
2038 switch (op2) {
2039 case 0:
2040 return MISCREG_SP_EL1;
2041 }
2042 break;
2043 case 3:
2044 switch (op2) {
2045 case 0:
2046 return MISCREG_SPSR_IRQ_AA64;
2047 case 1:
2048 return MISCREG_SPSR_ABT_AA64;
2049 case 2:
2050 return MISCREG_SPSR_UND_AA64;
2051 case 3:
2052 return MISCREG_SPSR_FIQ_AA64;
2053 }
2054 break;
2055 }
2056 break;
2057 case 6:
2058 switch (crm) {
2059 case 0:
2060 switch (op2) {
2061 case 0:
2062 return MISCREG_SPSR_EL3;
2063 case 1:
2064 return MISCREG_ELR_EL3;
2065 }
2066 break;
2067 case 1:
2068 switch (op2) {
2069 case 0:
2070 return MISCREG_SP_EL2;
2071 }
2072 break;
2073 }
2074 break;
2075 }
2076 break;
2077 case 5:
2078 switch (op1) {
2079 case 0:
2080 switch (crm) {
2081 case 1:
2082 switch (op2) {
2083 case 0:
2084 return MISCREG_AFSR0_EL1;
2085 case 1:
2086 return MISCREG_AFSR1_EL1;
2087 }
2088 break;
2089 case 2:
2090 switch (op2) {
2091 case 0:
2092 return MISCREG_ESR_EL1;
2093 }
2094 break;
2095 case 3:
2096 switch (op2) {
2097 case 0:
2098 return MISCREG_ERRIDR_EL1;
2099 case 1:
2100 return MISCREG_ERRSELR_EL1;
2101 }
2102 break;
2103 case 4:
2104 switch (op2) {
2105 case 0:
2106 return MISCREG_ERXFR_EL1;
2107 case 1:
2108 return MISCREG_ERXCTLR_EL1;
2109 case 2:
2110 return MISCREG_ERXSTATUS_EL1;
2111 case 3:
2112 return MISCREG_ERXADDR_EL1;
2113 }
2114 break;
2115 case 5:
2116 switch (op2) {
2117 case 0:
2118 return MISCREG_ERXMISC0_EL1;
2119 case 1:
2120 return MISCREG_ERXMISC1_EL1;
2121 }
2122 break;
2123 }
2124 break;
2125 case 4:
2126 switch (crm) {
2127 case 0:
2128 switch (op2) {
2129 case 1:
2130 return MISCREG_IFSR32_EL2;
2131 }
2132 break;
2133 case 1:
2134 switch (op2) {
2135 case 0:
2136 return MISCREG_AFSR0_EL2;
2137 case 1:
2138 return MISCREG_AFSR1_EL2;
2139 }
2140 break;
2141 case 2:
2142 switch (op2) {
2143 case 0:
2144 return MISCREG_ESR_EL2;
2145 case 3:
2146 return MISCREG_VSESR_EL2;
2147 }
2148 break;
2149 case 3:
2150 switch (op2) {
2151 case 0:
2152 return MISCREG_FPEXC32_EL2;
2153 }
2154 break;
2155 }
2156 break;
2157 case 6:
2158 switch (crm) {
2159 case 1:
2160 switch (op2) {
2161 case 0:
2162 return MISCREG_AFSR0_EL3;
2163 case 1:
2164 return MISCREG_AFSR1_EL3;
2165 }
2166 break;
2167 case 2:
2168 switch (op2) {
2169 case 0:
2170 return MISCREG_ESR_EL3;
2171 }
2172 break;
2173 }
2174 break;
2175 }
2176 break;
2177 case 6:
2178 switch (op1) {
2179 case 0:
2180 switch (crm) {
2181 case 0:
2182 switch (op2) {
2183 case 0:
2184 return MISCREG_FAR_EL1;
2185 }
2186 break;
2187 }
2188 break;
2189 case 4:
2190 switch (crm) {
2191 case 0:
2192 switch (op2) {
2193 case 0:
2194 return MISCREG_FAR_EL2;
2195 case 4:
2196 return MISCREG_HPFAR_EL2;
2197 }
2198 break;
2199 }
2200 break;
2201 case 6:
2202 switch (crm) {
2203 case 0:
2204 switch (op2) {
2205 case 0:
2206 return MISCREG_FAR_EL3;
2207 }
2208 break;
2209 }
2210 break;
2211 }
2212 break;
2213 case 7:
2214 switch (op1) {
2215 case 0:
2216 switch (crm) {
2217 case 4:
2218 switch (op2) {
2219 case 0:
2220 return MISCREG_PAR_EL1;
2221 }
2222 break;
2223 }
2224 break;
2225 }
2226 break;
2227 case 9:
2228 switch (op1) {
2229 case 0:
2230 switch (crm) {
2231 case 14:
2232 switch (op2) {
2233 case 1:
2234 return MISCREG_PMINTENSET_EL1;
2235 case 2:
2236 return MISCREG_PMINTENCLR_EL1;
2237 }
2238 break;
2239 }
2240 break;
2241 case 3:
2242 switch (crm) {
2243 case 12:
2244 switch (op2) {
2245 case 0:
2246 return MISCREG_PMCR_EL0;
2247 case 1:
2248 return MISCREG_PMCNTENSET_EL0;
2249 case 2:
2250 return MISCREG_PMCNTENCLR_EL0;
2251 case 3:
2252 return MISCREG_PMOVSCLR_EL0;
2253 case 4:
2254 return MISCREG_PMSWINC_EL0;
2255 case 5:
2256 return MISCREG_PMSELR_EL0;
2257 case 6:
2258 return MISCREG_PMCEID0_EL0;
2259 case 7:
2260 return MISCREG_PMCEID1_EL0;
2261 }
2262 break;
2263 case 13:
2264 switch (op2) {
2265 case 0:
2266 return MISCREG_PMCCNTR_EL0;
2267 case 1:
2268 return MISCREG_PMXEVTYPER_EL0;
2269 case 2:
2270 return MISCREG_PMXEVCNTR_EL0;
2271 }
2272 break;
2273 case 14:
2274 switch (op2) {
2275 case 0:
2276 return MISCREG_PMUSERENR_EL0;
2277 case 3:
2278 return MISCREG_PMOVSSET_EL0;
2279 }
2280 break;
2281 }
2282 break;
2283 }
2284 break;
2285 case 10:
2286 switch (op1) {
2287 case 0:
2288 switch (crm) {
2289 case 2:
2290 switch (op2) {
2291 case 0:
2292 return MISCREG_MAIR_EL1;
2293 }
2294 break;
2295 case 3:
2296 switch (op2) {
2297 case 0:
2298 return MISCREG_AMAIR_EL1;
2299 }
2300 break;
2301 }
2302 break;
2303 case 4:
2304 switch (crm) {
2305 case 2:
2306 switch (op2) {
2307 case 0:
2308 return MISCREG_MAIR_EL2;
2309 }
2310 break;
2311 case 3:
2312 switch (op2) {
2313 case 0:
2314 return MISCREG_AMAIR_EL2;
2315 }
2316 break;
2317 }
2318 break;
2319 case 6:
2320 switch (crm) {
2321 case 2:
2322 switch (op2) {
2323 case 0:
2324 return MISCREG_MAIR_EL3;
2325 }
2326 break;
2327 case 3:
2328 switch (op2) {
2329 case 0:
2330 return MISCREG_AMAIR_EL3;
2331 }
2332 break;
2333 }
2334 break;
2335 }
2336 break;
2337 case 11:
2338 switch (op1) {
2339 case 1:
2340 switch (crm) {
2341 case 0:
2342 switch (op2) {
2343 case 2:
2344 return MISCREG_L2CTLR_EL1;
2345 case 3:
2346 return MISCREG_L2ECTLR_EL1;
2347 }
2348 break;
2349 }
2350 M5_FALLTHROUGH;
2351 default:
2352 // S3_<op1>_11_<Cm>_<op2>
2353 return MISCREG_IMPDEF_UNIMPL;
2354 }
2355 M5_UNREACHABLE;
2356 case 12:
2357 switch (op1) {
2358 case 0:
2359 switch (crm) {
2360 case 0:
2361 switch (op2) {
2362 case 0:
2363 return MISCREG_VBAR_EL1;
2364 case 1:
2365 return MISCREG_RVBAR_EL1;
2366 }
2367 break;
2368 case 1:
2369 switch (op2) {
2370 case 0:
2371 return MISCREG_ISR_EL1;
2372 case 1:
2373 return MISCREG_DISR_EL1;
2374 }
2375 break;
2376 case 8:
2377 switch (op2) {
2378 case 0:
2379 return MISCREG_ICC_IAR0_EL1;
2380 case 1:
2381 return MISCREG_ICC_EOIR0_EL1;
2382 case 2:
2383 return MISCREG_ICC_HPPIR0_EL1;
2384 case 3:
2385 return MISCREG_ICC_BPR0_EL1;
2386 case 4:
2387 return MISCREG_ICC_AP0R0_EL1;
2388 case 5:
2389 return MISCREG_ICC_AP0R1_EL1;
2390 case 6:
2391 return MISCREG_ICC_AP0R2_EL1;
2392 case 7:
2393 return MISCREG_ICC_AP0R3_EL1;
2394 }
2395 break;
2396 case 9:
2397 switch (op2) {
2398 case 0:
2399 return MISCREG_ICC_AP1R0_EL1;
2400 case 1:
2401 return MISCREG_ICC_AP1R1_EL1;
2402 case 2:
2403 return MISCREG_ICC_AP1R2_EL1;
2404 case 3:
2405 return MISCREG_ICC_AP1R3_EL1;
2406 }
2407 break;
2408 case 11:
2409 switch (op2) {
2410 case 1:
2411 return MISCREG_ICC_DIR_EL1;
2412 case 3:
2413 return MISCREG_ICC_RPR_EL1;
2414 case 5:
2415 return MISCREG_ICC_SGI1R_EL1;
2416 case 6:
2417 return MISCREG_ICC_ASGI1R_EL1;
2418 case 7:
2419 return MISCREG_ICC_SGI0R_EL1;
2420 }
2421 break;
2422 case 12:
2423 switch (op2) {
2424 case 0:
2425 return MISCREG_ICC_IAR1_EL1;
2426 case 1:
2427 return MISCREG_ICC_EOIR1_EL1;
2428 case 2:
2429 return MISCREG_ICC_HPPIR1_EL1;
2430 case 3:
2431 return MISCREG_ICC_BPR1_EL1;
2432 case 4:
2433 return MISCREG_ICC_CTLR_EL1;
2434 case 5:
2435 return MISCREG_ICC_SRE_EL1;
2436 case 6:
2437 return MISCREG_ICC_IGRPEN0_EL1;
2438 case 7:
2439 return MISCREG_ICC_IGRPEN1_EL1;
2440 }
2441 break;
2442 }
2443 break;
2444 case 4:
2445 switch (crm) {
2446 case 0:
2447 switch (op2) {
2448 case 0:
2449 return MISCREG_VBAR_EL2;
2450 case 1:
2451 return MISCREG_RVBAR_EL2;
2452 }
2453 break;
2454 case 1:
2455 switch (op2) {
2456 case 1:
2457 return MISCREG_VDISR_EL2;
2458 }
2459 break;
2460 case 8:
2461 switch (op2) {
2462 case 0:
2463 return MISCREG_ICH_AP0R0_EL2;
2464 case 1:
2465 return MISCREG_ICH_AP0R1_EL2;
2466 case 2:
2467 return MISCREG_ICH_AP0R2_EL2;
2468 case 3:
2469 return MISCREG_ICH_AP0R3_EL2;
2470 }
2471 break;
2472 case 9:
2473 switch (op2) {
2474 case 0:
2475 return MISCREG_ICH_AP1R0_EL2;
2476 case 1:
2477 return MISCREG_ICH_AP1R1_EL2;
2478 case 2:
2479 return MISCREG_ICH_AP1R2_EL2;
2480 case 3:
2481 return MISCREG_ICH_AP1R3_EL2;
2482 case 5:
2483 return MISCREG_ICC_SRE_EL2;
2484 }
2485 break;
2486 case 11:
2487 switch (op2) {
2488 case 0:
2489 return MISCREG_ICH_HCR_EL2;
2490 case 1:
2491 return MISCREG_ICH_VTR_EL2;
2492 case 2:
2493 return MISCREG_ICH_MISR_EL2;
2494 case 3:
2495 return MISCREG_ICH_EISR_EL2;
2496 case 5:
2497 return MISCREG_ICH_ELRSR_EL2;
2498 case 7:
2499 return MISCREG_ICH_VMCR_EL2;
2500 }
2501 break;
2502 case 12:
2503 switch (op2) {
2504 case 0:
2505 return MISCREG_ICH_LR0_EL2;
2506 case 1:
2507 return MISCREG_ICH_LR1_EL2;
2508 case 2:
2509 return MISCREG_ICH_LR2_EL2;
2510 case 3:
2511 return MISCREG_ICH_LR3_EL2;
2512 case 4:
2513 return MISCREG_ICH_LR4_EL2;
2514 case 5:
2515 return MISCREG_ICH_LR5_EL2;
2516 case 6:
2517 return MISCREG_ICH_LR6_EL2;
2518 case 7:
2519 return MISCREG_ICH_LR7_EL2;
2520 }
2521 break;
2522 case 13:
2523 switch (op2) {
2524 case 0:
2525 return MISCREG_ICH_LR8_EL2;
2526 case 1:
2527 return MISCREG_ICH_LR9_EL2;
2528 case 2:
2529 return MISCREG_ICH_LR10_EL2;
2530 case 3:
2531 return MISCREG_ICH_LR11_EL2;
2532 case 4:
2533 return MISCREG_ICH_LR12_EL2;
2534 case 5:
2535 return MISCREG_ICH_LR13_EL2;
2536 case 6:
2537 return MISCREG_ICH_LR14_EL2;
2538 case 7:
2539 return MISCREG_ICH_LR15_EL2;
2540 }
2541 break;
2542 }
2543 break;
2544 case 6:
2545 switch (crm) {
2546 case 0:
2547 switch (op2) {
2548 case 0:
2549 return MISCREG_VBAR_EL3;
2550 case 1:
2551 return MISCREG_RVBAR_EL3;
2552 case 2:
2553 return MISCREG_RMR_EL3;
2554 }
2555 break;
2556 case 12:
2557 switch (op2) {
2558 case 4:
2559 return MISCREG_ICC_CTLR_EL3;
2560 case 5:
2561 return MISCREG_ICC_SRE_EL3;
2562 case 7:
2563 return MISCREG_ICC_IGRPEN1_EL3;
2564 }
2565 break;
2566 }
2567 break;
2568 }
2569 break;
2570 case 13:
2571 switch (op1) {
2572 case 0:
2573 switch (crm) {
2574 case 0:
2575 switch (op2) {
2576 case 1:
2577 return MISCREG_CONTEXTIDR_EL1;
2578 case 4:
2579 return MISCREG_TPIDR_EL1;
2580 }
2581 break;
2582 }
2583 break;
2584 case 3:
2585 switch (crm) {
2586 case 0:
2587 switch (op2) {
2588 case 2:
2589 return MISCREG_TPIDR_EL0;
2590 case 3:
2591 return MISCREG_TPIDRRO_EL0;
2592 }
2593 break;
2594 }
2595 break;
2596 case 4:
2597 switch (crm) {
2598 case 0:
2599 switch (op2) {
2600 case 1:
2601 return MISCREG_CONTEXTIDR_EL2;
2602 case 2:
2603 return MISCREG_TPIDR_EL2;
2604 }
2605 break;
2606 }
2607 break;
2608 case 6:
2609 switch (crm) {
2610 case 0:
2611 switch (op2) {
2612 case 2:
2613 return MISCREG_TPIDR_EL3;
2614 }
2615 break;
2616 }
2617 break;
2618 }
2619 break;
2620 case 14:
2621 switch (op1) {
2622 case 0:
2623 switch (crm) {
2624 case 1:
2625 switch (op2) {
2626 case 0:
2627 return MISCREG_CNTKCTL_EL1;
2628 }
2629 break;
2630 }
2631 break;
2632 case 3:
2633 switch (crm) {
2634 case 0:
2635 switch (op2) {
2636 case 0:
2637 return MISCREG_CNTFRQ_EL0;
2638 case 1:
2639 return MISCREG_CNTPCT_EL0;
2640 case 2:
2641 return MISCREG_CNTVCT_EL0;
2642 }
2643 break;
2644 case 2:
2645 switch (op2) {
2646 case 0:
2647 return MISCREG_CNTP_TVAL_EL0;
2648 case 1:
2649 return MISCREG_CNTP_CTL_EL0;
2650 case 2:
2651 return MISCREG_CNTP_CVAL_EL0;
2652 }
2653 break;
2654 case 3:
2655 switch (op2) {
2656 case 0:
2657 return MISCREG_CNTV_TVAL_EL0;
2658 case 1:
2659 return MISCREG_CNTV_CTL_EL0;
2660 case 2:
2661 return MISCREG_CNTV_CVAL_EL0;
2662 }
2663 break;
2664 case 8:
2665 switch (op2) {
2666 case 0:
2667 return MISCREG_PMEVCNTR0_EL0;
2668 case 1:
2669 return MISCREG_PMEVCNTR1_EL0;
2670 case 2:
2671 return MISCREG_PMEVCNTR2_EL0;
2672 case 3:
2673 return MISCREG_PMEVCNTR3_EL0;
2674 case 4:
2675 return MISCREG_PMEVCNTR4_EL0;
2676 case 5:
2677 return MISCREG_PMEVCNTR5_EL0;
2678 }
2679 break;
2680 case 12:
2681 switch (op2) {
2682 case 0:
2683 return MISCREG_PMEVTYPER0_EL0;
2684 case 1:
2685 return MISCREG_PMEVTYPER1_EL0;
2686 case 2:
2687 return MISCREG_PMEVTYPER2_EL0;
2688 case 3:
2689 return MISCREG_PMEVTYPER3_EL0;
2690 case 4:
2691 return MISCREG_PMEVTYPER4_EL0;
2692 case 5:
2693 return MISCREG_PMEVTYPER5_EL0;
2694 }
2695 break;
2696 case 15:
2697 switch (op2) {
2698 case 7:
2699 return MISCREG_PMCCFILTR_EL0;
2700 }
2701 }
2702 break;
2703 case 4:
2704 switch (crm) {
2705 case 0:
2706 switch (op2) {
2707 case 3:
2708 return MISCREG_CNTVOFF_EL2;
2709 }
2710 break;
2711 case 1:
2712 switch (op2) {
2713 case 0:
2714 return MISCREG_CNTHCTL_EL2;
2715 }
2716 break;
2717 case 2:
2718 switch (op2) {
2719 case 0:
2720 return MISCREG_CNTHP_TVAL_EL2;
2721 case 1:
2722 return MISCREG_CNTHP_CTL_EL2;
2723 case 2:
2724 return MISCREG_CNTHP_CVAL_EL2;
2725 }
2726 break;
2727 case 3:
2728 switch (op2) {
2729 case 0:
2730 return MISCREG_CNTHV_TVAL_EL2;
2731 case 1:
2732 return MISCREG_CNTHV_CTL_EL2;
2733 case 2:
2734 return MISCREG_CNTHV_CVAL_EL2;
2735 }
2736 break;
2737 }
2738 break;
2739 case 7:
2740 switch (crm) {
2741 case 2:
2742 switch (op2) {
2743 case 0:
2744 return MISCREG_CNTPS_TVAL_EL1;
2745 case 1:
2746 return MISCREG_CNTPS_CTL_EL1;
2747 case 2:
2748 return MISCREG_CNTPS_CVAL_EL1;
2749 }
2750 break;
2751 }
2752 break;
2753 }
2754 break;
2755 case 15:
2756 switch (op1) {
2757 case 0:
2758 switch (crm) {
2759 case 0:
2760 switch (op2) {
2761 case 0:
2762 return MISCREG_IL1DATA0_EL1;
2763 case 1:
2764 return MISCREG_IL1DATA1_EL1;
2765 case 2:
2766 return MISCREG_IL1DATA2_EL1;
2767 case 3:
2768 return MISCREG_IL1DATA3_EL1;
2769 }
2770 break;
2771 case 1:
2772 switch (op2) {
2773 case 0:
2774 return MISCREG_DL1DATA0_EL1;
2775 case 1:
2776 return MISCREG_DL1DATA1_EL1;
2777 case 2:
2778 return MISCREG_DL1DATA2_EL1;
2779 case 3:
2780 return MISCREG_DL1DATA3_EL1;
2781 case 4:
2782 return MISCREG_DL1DATA4_EL1;
2783 }
2784 break;
2785 }
2786 break;
2787 case 1:
2788 switch (crm) {
2789 case 0:
2790 switch (op2) {
2791 case 0:
2792 return MISCREG_L2ACTLR_EL1;
2793 }
2794 break;
2795 case 2:
2796 switch (op2) {
2797 case 0:
2798 return MISCREG_CPUACTLR_EL1;
2799 case 1:
2800 return MISCREG_CPUECTLR_EL1;
2801 case 2:
2802 return MISCREG_CPUMERRSR_EL1;
2803 case 3:
2804 return MISCREG_L2MERRSR_EL1;
2805 }
2806 break;
2807 case 3:
2808 switch (op2) {
2809 case 0:
2810 return MISCREG_CBAR_EL1;
2811
2812 }
2813 break;
2814 }
2815 break;
2816 }
2817 // S3_<op1>_15_<Cm>_<op2>
2818 return MISCREG_IMPDEF_UNIMPL;
2819 }
2820 break;
2821 }
2822
2823 return MISCREG_UNKNOWN;
2824}
2825
2826bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2827
2828void
2829ISA::initializeMiscRegMetadata()
2830{
2831 // the MiscReg metadata tables are shared across all instances of the
2832 // ISA object, so there's no need to initialize them multiple times.
2833 static bool completed = false;
2834 if (completed)
2835 return;
2836
2837 // This boolean variable specifies if the system is running in aarch32 at
2838 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2839 // is running in aarch64 (aarch32EL3 = false)
2840 bool aarch32EL3 = haveSecurity && !highestELIs64;
2841
2842 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2843 // unsupported
2844 bool SPAN = false;
2845
2846 // Implicit error synchronization event enable (Arm 8.2+), unsupported
2847 bool IESB = false;
2848
2849 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2850 // unsupported
2851 bool LSMAOE = false;
2852
2853 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2854 bool nTLSMD = false;
2855
2856 // Pointer authentication (Arm 8.3+), unsupported
2857 bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2858 bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2859 bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2860 bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2861
2862 /**
2863 * Some registers alias with others, and therefore need to be translated.
2864 * When two mapping registers are given, they are the 32b lower and
2865 * upper halves, respectively, of the 64b register being mapped.
2866 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2867 *
2868 * NAM = "not architecturally mandated",
2869 * from ARM DDI 0487A.i, template text
2870 * "AArch64 System register ___ can be mapped to
2871 * AArch32 System register ___, but this is not
2872 * architecturally mandated."
2873 */
2874
2875 InitReg(MISCREG_CPSR)
2876 .allPrivileges();
2877 InitReg(MISCREG_SPSR)
2878 .allPrivileges();
2879 InitReg(MISCREG_SPSR_FIQ)
2880 .allPrivileges();
2881 InitReg(MISCREG_SPSR_IRQ)
2882 .allPrivileges();
2883 InitReg(MISCREG_SPSR_SVC)
2884 .allPrivileges();
2885 InitReg(MISCREG_SPSR_MON)
2886 .allPrivileges();
2887 InitReg(MISCREG_SPSR_ABT)
2888 .allPrivileges();
2889 InitReg(MISCREG_SPSR_HYP)
2890 .allPrivileges();
2891 InitReg(MISCREG_SPSR_UND)
2892 .allPrivileges();
2893 InitReg(MISCREG_ELR_HYP)
2894 .allPrivileges();
2895 InitReg(MISCREG_FPSID)
2896 .allPrivileges();
2897 InitReg(MISCREG_FPSCR)
2898 .allPrivileges();
2899 InitReg(MISCREG_MVFR1)
2900 .allPrivileges();
2901 InitReg(MISCREG_MVFR0)
2902 .allPrivileges();
2903 InitReg(MISCREG_FPEXC)
2904 .allPrivileges();
2905
2906 // Helper registers
2907 InitReg(MISCREG_CPSR_MODE)
2908 .allPrivileges();
2909 InitReg(MISCREG_CPSR_Q)
2910 .allPrivileges();
2911 InitReg(MISCREG_FPSCR_EXC)
2912 .allPrivileges();
2913 InitReg(MISCREG_FPSCR_QC)
2914 .allPrivileges();
2915 InitReg(MISCREG_LOCKADDR)
2916 .allPrivileges();
2917 InitReg(MISCREG_LOCKFLAG)
2918 .allPrivileges();
2919 InitReg(MISCREG_PRRR_MAIR0)
2920 .mutex()
2921 .banked();
2922 InitReg(MISCREG_PRRR_MAIR0_NS)
2923 .mutex()
2924 .privSecure(!aarch32EL3)
2925 .bankedChild();
2926 InitReg(MISCREG_PRRR_MAIR0_S)
2927 .mutex()
2928 .bankedChild();
2929 InitReg(MISCREG_NMRR_MAIR1)
2930 .mutex()
2931 .banked();
2932 InitReg(MISCREG_NMRR_MAIR1_NS)
2933 .mutex()
2934 .privSecure(!aarch32EL3)
2935 .bankedChild();
2936 InitReg(MISCREG_NMRR_MAIR1_S)
2937 .mutex()
2938 .bankedChild();
2939 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2940 .mutex();
2941 InitReg(MISCREG_SCTLR_RST)
2942 .allPrivileges();
2943 InitReg(MISCREG_SEV_MAILBOX)
2944 .allPrivileges();
2945
2946 // AArch32 CP14 registers
2947 InitReg(MISCREG_DBGDIDR)
2948 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2949 InitReg(MISCREG_DBGDSCRint)
2950 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2951 InitReg(MISCREG_DBGDCCINT)
2952 .unimplemented()
2953 .allPrivileges();
2954 InitReg(MISCREG_DBGDTRTXint)
2955 .unimplemented()
2956 .allPrivileges();
2957 InitReg(MISCREG_DBGDTRRXint)
2958 .unimplemented()
2959 .allPrivileges();
2960 InitReg(MISCREG_DBGWFAR)
2961 .unimplemented()
2962 .allPrivileges();
2963 InitReg(MISCREG_DBGVCR)
2964 .unimplemented()
2965 .allPrivileges();
2966 InitReg(MISCREG_DBGDTRRXext)
2967 .unimplemented()
2968 .allPrivileges();
2969 InitReg(MISCREG_DBGDSCRext)
2970 .unimplemented()
2971 .warnNotFail()
2972 .allPrivileges();
2973 InitReg(MISCREG_DBGDTRTXext)
2974 .unimplemented()
2975 .allPrivileges();
2976 InitReg(MISCREG_DBGOSECCR)
2977 .unimplemented()
2978 .allPrivileges();
2979 InitReg(MISCREG_DBGBVR0)
2980 .unimplemented()
2981 .allPrivileges();
2982 InitReg(MISCREG_DBGBVR1)
2983 .unimplemented()
2984 .allPrivileges();
2985 InitReg(MISCREG_DBGBVR2)
2986 .unimplemented()
2987 .allPrivileges();
2988 InitReg(MISCREG_DBGBVR3)
2989 .unimplemented()
2990 .allPrivileges();
2991 InitReg(MISCREG_DBGBVR4)
2992 .unimplemented()
2993 .allPrivileges();
2994 InitReg(MISCREG_DBGBVR5)
2995 .unimplemented()
2996 .allPrivileges();
2997 InitReg(MISCREG_DBGBCR0)
2998 .unimplemented()
2999 .allPrivileges();
3000 InitReg(MISCREG_DBGBCR1)
3001 .unimplemented()
3002 .allPrivileges();
3003 InitReg(MISCREG_DBGBCR2)
3004 .unimplemented()
3005 .allPrivileges();
3006 InitReg(MISCREG_DBGBCR3)
3007 .unimplemented()
3008 .allPrivileges();
3009 InitReg(MISCREG_DBGBCR4)
3010 .unimplemented()
3011 .allPrivileges();
3012 InitReg(MISCREG_DBGBCR5)
3013 .unimplemented()
3014 .allPrivileges();
3015 InitReg(MISCREG_DBGWVR0)
3016 .unimplemented()
3017 .allPrivileges();
3018 InitReg(MISCREG_DBGWVR1)
3019 .unimplemented()
3020 .allPrivileges();
3021 InitReg(MISCREG_DBGWVR2)
3022 .unimplemented()
3023 .allPrivileges();
3024 InitReg(MISCREG_DBGWVR3)
3025 .unimplemented()
3026 .allPrivileges();
3027 InitReg(MISCREG_DBGWCR0)
3028 .unimplemented()
3029 .allPrivileges();
3030 InitReg(MISCREG_DBGWCR1)
3031 .unimplemented()
3032 .allPrivileges();
3033 InitReg(MISCREG_DBGWCR2)
3034 .unimplemented()
3035 .allPrivileges();
3036 InitReg(MISCREG_DBGWCR3)
3037 .unimplemented()
3038 .allPrivileges();
3039 InitReg(MISCREG_DBGDRAR)
3040 .unimplemented()
3041 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3042 InitReg(MISCREG_DBGBXVR4)
3043 .unimplemented()
3044 .allPrivileges();
3045 InitReg(MISCREG_DBGBXVR5)
3046 .unimplemented()
3047 .allPrivileges();
3048 InitReg(MISCREG_DBGOSLAR)
3049 .unimplemented()
3050 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3051 InitReg(MISCREG_DBGOSLSR)
3052 .unimplemented()
3053 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3054 InitReg(MISCREG_DBGOSDLR)
3055 .unimplemented()
3056 .allPrivileges();
3057 InitReg(MISCREG_DBGPRCR)
3058 .unimplemented()
3059 .allPrivileges();
3060 InitReg(MISCREG_DBGDSAR)
3061 .unimplemented()
3062 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3063 InitReg(MISCREG_DBGCLAIMSET)
3064 .unimplemented()
3065 .allPrivileges();
3066 InitReg(MISCREG_DBGCLAIMCLR)
3067 .unimplemented()
3068 .allPrivileges();
3069 InitReg(MISCREG_DBGAUTHSTATUS)
3070 .unimplemented()
3071 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3072 InitReg(MISCREG_DBGDEVID2)
3073 .unimplemented()
3074 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3075 InitReg(MISCREG_DBGDEVID1)
3076 .unimplemented()
3077 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3078 InitReg(MISCREG_DBGDEVID0)
3079 .unimplemented()
3080 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3081 InitReg(MISCREG_TEECR)
3082 .unimplemented()
3083 .allPrivileges();
3084 InitReg(MISCREG_JIDR)
3085 .allPrivileges();
3086 InitReg(MISCREG_TEEHBR)
3087 .allPrivileges();
3088 InitReg(MISCREG_JOSCR)
3089 .allPrivileges();
3090 InitReg(MISCREG_JMCR)
3091 .allPrivileges();
3092
3093 // AArch32 CP15 registers
3094 InitReg(MISCREG_MIDR)
3095 .allPrivileges().exceptUserMode().writes(0);
3096 InitReg(MISCREG_CTR)
3097 .allPrivileges().exceptUserMode().writes(0);
3098 InitReg(MISCREG_TCMTR)
3099 .allPrivileges().exceptUserMode().writes(0);
3100 InitReg(MISCREG_TLBTR)
3101 .allPrivileges().exceptUserMode().writes(0);
3102 InitReg(MISCREG_MPIDR)
3103 .allPrivileges().exceptUserMode().writes(0);
3104 InitReg(MISCREG_REVIDR)
3105 .unimplemented()
3106 .warnNotFail()
3107 .allPrivileges().exceptUserMode().writes(0);
3108 InitReg(MISCREG_ID_PFR0)
3109 .allPrivileges().exceptUserMode().writes(0);
3110 InitReg(MISCREG_ID_PFR1)
3111 .allPrivileges().exceptUserMode().writes(0);
3112 InitReg(MISCREG_ID_DFR0)
3113 .allPrivileges().exceptUserMode().writes(0);
3114 InitReg(MISCREG_ID_AFR0)
3115 .allPrivileges().exceptUserMode().writes(0);
3116 InitReg(MISCREG_ID_MMFR0)
3117 .allPrivileges().exceptUserMode().writes(0);
3118 InitReg(MISCREG_ID_MMFR1)
3119 .allPrivileges().exceptUserMode().writes(0);
3120 InitReg(MISCREG_ID_MMFR2)
3121 .allPrivileges().exceptUserMode().writes(0);
3122 InitReg(MISCREG_ID_MMFR3)
3123 .allPrivileges().exceptUserMode().writes(0);
3124 InitReg(MISCREG_ID_ISAR0)
3125 .allPrivileges().exceptUserMode().writes(0);
3126 InitReg(MISCREG_ID_ISAR1)
3127 .allPrivileges().exceptUserMode().writes(0);
3128 InitReg(MISCREG_ID_ISAR2)
3129 .allPrivileges().exceptUserMode().writes(0);
3130 InitReg(MISCREG_ID_ISAR3)
3131 .allPrivileges().exceptUserMode().writes(0);
3132 InitReg(MISCREG_ID_ISAR4)
3133 .allPrivileges().exceptUserMode().writes(0);
3134 InitReg(MISCREG_ID_ISAR5)
3135 .allPrivileges().exceptUserMode().writes(0);
3136 InitReg(MISCREG_CCSIDR)
3137 .allPrivileges().exceptUserMode().writes(0);
3138 InitReg(MISCREG_CLIDR)
3139 .allPrivileges().exceptUserMode().writes(0);
3140 InitReg(MISCREG_AIDR)
3141 .allPrivileges().exceptUserMode().writes(0);
3142 InitReg(MISCREG_CSSELR)
3143 .banked();
3144 InitReg(MISCREG_CSSELR_NS)
3145 .bankedChild()
3146 .privSecure(!aarch32EL3)
3147 .nonSecure().exceptUserMode();
3148 InitReg(MISCREG_CSSELR_S)
3149 .bankedChild()
3150 .secure().exceptUserMode();
3151 InitReg(MISCREG_VPIDR)
3152 .hyp().monNonSecure();
3153 InitReg(MISCREG_VMPIDR)
3154 .hyp().monNonSecure();
3155 InitReg(MISCREG_SCTLR)
3156 .banked()
3157 // readMiscRegNoEffect() uses this metadata
3158 // despite using children (below) as backing store
3159 .res0(0x8d22c600)
3160 .res1(0x00400800 | (SPAN ? 0 : 0x800000)
3161 | (LSMAOE ? 0 : 0x10)
3162 | (nTLSMD ? 0 : 0x8));
3163 InitReg(MISCREG_SCTLR_NS)
3164 .bankedChild()
3165 .privSecure(!aarch32EL3)
3166 .nonSecure().exceptUserMode();
3167 InitReg(MISCREG_SCTLR_S)
3168 .bankedChild()
3169 .secure().exceptUserMode();
3170 InitReg(MISCREG_ACTLR)
3171 .banked();
3172 InitReg(MISCREG_ACTLR_NS)
3173 .bankedChild()
3174 .privSecure(!aarch32EL3)
3175 .nonSecure().exceptUserMode();
3176 InitReg(MISCREG_ACTLR_S)
3177 .bankedChild()
3178 .secure().exceptUserMode();
3179 InitReg(MISCREG_CPACR)
3180 .allPrivileges().exceptUserMode();
3181 InitReg(MISCREG_SCR)
3182 .mon().secure().exceptUserMode()
3183 .res0(0xff40) // [31:16], [6]
3184 .res1(0x0030); // [5:4]
3185 InitReg(MISCREG_SDER)
3186 .mon();
3187 InitReg(MISCREG_NSACR)
3188 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3189 InitReg(MISCREG_HSCTLR)
3190 .hyp().monNonSecure()
3191 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3192 | (IESB ? 0 : 0x200000)
3193 | (EnDA ? 0 : 0x8000000)
3194 | (EnIB ? 0 : 0x40000000)
3195 | (EnIA ? 0 : 0x80000000))
3196 .res1(0x30c50830);
3197 InitReg(MISCREG_HACTLR)
3198 .hyp().monNonSecure();
3199 InitReg(MISCREG_HCR)
3200 .hyp().monNonSecure();
3201 InitReg(MISCREG_HDCR)
3202 .hyp().monNonSecure();
3203 InitReg(MISCREG_HCPTR)
3204 .hyp().monNonSecure();
3205 InitReg(MISCREG_HSTR)
3206 .hyp().monNonSecure();
3207 InitReg(MISCREG_HACR)
3208 .unimplemented()
3209 .warnNotFail()
3210 .hyp().monNonSecure();
3211 InitReg(MISCREG_TTBR0)
3212 .banked();
3213 InitReg(MISCREG_TTBR0_NS)
3214 .bankedChild()
3215 .privSecure(!aarch32EL3)
3216 .nonSecure().exceptUserMode();
3217 InitReg(MISCREG_TTBR0_S)
3218 .bankedChild()
3219 .secure().exceptUserMode();
3220 InitReg(MISCREG_TTBR1)
3221 .banked();
3222 InitReg(MISCREG_TTBR1_NS)
3223 .bankedChild()
3224 .privSecure(!aarch32EL3)
3225 .nonSecure().exceptUserMode();
3226 InitReg(MISCREG_TTBR1_S)
3227 .bankedChild()
3228 .secure().exceptUserMode();
3229 InitReg(MISCREG_TTBCR)
3230 .banked();
3231 InitReg(MISCREG_TTBCR_NS)
3232 .bankedChild()
3233 .privSecure(!aarch32EL3)
3234 .nonSecure().exceptUserMode();
3235 InitReg(MISCREG_TTBCR_S)
3236 .bankedChild()
3237 .secure().exceptUserMode();
3238 InitReg(MISCREG_HTCR)
3239 .hyp().monNonSecure();
3240 InitReg(MISCREG_VTCR)
3241 .hyp().monNonSecure();
3242 InitReg(MISCREG_DACR)
3243 .banked();
3244 InitReg(MISCREG_DACR_NS)
3245 .bankedChild()
3246 .privSecure(!aarch32EL3)
3247 .nonSecure().exceptUserMode();
3248 InitReg(MISCREG_DACR_S)
3249 .bankedChild()
3250 .secure().exceptUserMode();
3251 InitReg(MISCREG_DFSR)
3252 .banked();
3253 InitReg(MISCREG_DFSR_NS)
3254 .bankedChild()
3255 .privSecure(!aarch32EL3)
3256 .nonSecure().exceptUserMode();
3257 InitReg(MISCREG_DFSR_S)
3258 .bankedChild()
3259 .secure().exceptUserMode();
3260 InitReg(MISCREG_IFSR)
3261 .banked();
3262 InitReg(MISCREG_IFSR_NS)
3263 .bankedChild()
3264 .privSecure(!aarch32EL3)
3265 .nonSecure().exceptUserMode();
3266 InitReg(MISCREG_IFSR_S)
3267 .bankedChild()
3268 .secure().exceptUserMode();
3269 InitReg(MISCREG_ADFSR)
3270 .unimplemented()
3271 .warnNotFail()
3272 .banked();
3273 InitReg(MISCREG_ADFSR_NS)
3274 .unimplemented()
3275 .warnNotFail()
3276 .bankedChild()
3277 .privSecure(!aarch32EL3)
3278 .nonSecure().exceptUserMode();
3279 InitReg(MISCREG_ADFSR_S)
3280 .unimplemented()
3281 .warnNotFail()
3282 .bankedChild()
3283 .secure().exceptUserMode();
3284 InitReg(MISCREG_AIFSR)
3285 .unimplemented()
3286 .warnNotFail()
3287 .banked();
3288 InitReg(MISCREG_AIFSR_NS)
3289 .unimplemented()
3290 .warnNotFail()
3291 .bankedChild()
3292 .privSecure(!aarch32EL3)
3293 .nonSecure().exceptUserMode();
3294 InitReg(MISCREG_AIFSR_S)
3295 .unimplemented()
3296 .warnNotFail()
3297 .bankedChild()
3298 .secure().exceptUserMode();
3299 InitReg(MISCREG_HADFSR)
3300 .hyp().monNonSecure();
3301 InitReg(MISCREG_HAIFSR)
3302 .hyp().monNonSecure();
3303 InitReg(MISCREG_HSR)
3304 .hyp().monNonSecure();
3305 InitReg(MISCREG_DFAR)
3306 .banked();
3307 InitReg(MISCREG_DFAR_NS)
3308 .bankedChild()
3309 .privSecure(!aarch32EL3)
3310 .nonSecure().exceptUserMode();
3311 InitReg(MISCREG_DFAR_S)
3312 .bankedChild()
3313 .secure().exceptUserMode();
3314 InitReg(MISCREG_IFAR)
3315 .banked();
3316 InitReg(MISCREG_IFAR_NS)
3317 .bankedChild()
3318 .privSecure(!aarch32EL3)
3319 .nonSecure().exceptUserMode();
3320 InitReg(MISCREG_IFAR_S)
3321 .bankedChild()
3322 .secure().exceptUserMode();
3323 InitReg(MISCREG_HDFAR)
3324 .hyp().monNonSecure();
3325 InitReg(MISCREG_HIFAR)
3326 .hyp().monNonSecure();
3327 InitReg(MISCREG_HPFAR)
3328 .hyp().monNonSecure();
3329 InitReg(MISCREG_ICIALLUIS)
3330 .unimplemented()
3331 .warnNotFail()
3332 .writes(1).exceptUserMode();
3333 InitReg(MISCREG_BPIALLIS)
3334 .unimplemented()
3335 .warnNotFail()
3336 .writes(1).exceptUserMode();
3337 InitReg(MISCREG_PAR)
3338 .banked();
3339 InitReg(MISCREG_PAR_NS)
3340 .bankedChild()
3341 .privSecure(!aarch32EL3)
3342 .nonSecure().exceptUserMode();
3343 InitReg(MISCREG_PAR_S)
3344 .bankedChild()
3345 .secure().exceptUserMode();
3346 InitReg(MISCREG_ICIALLU)
3347 .writes(1).exceptUserMode();
3348 InitReg(MISCREG_ICIMVAU)
3349 .unimplemented()
3350 .warnNotFail()
3351 .writes(1).exceptUserMode();
3352 InitReg(MISCREG_CP15ISB)
3353 .writes(1);
3354 InitReg(MISCREG_BPIALL)
3355 .unimplemented()
3356 .warnNotFail()
3357 .writes(1).exceptUserMode();
3358 InitReg(MISCREG_BPIMVA)
3359 .unimplemented()
3360 .warnNotFail()
3361 .writes(1).exceptUserMode();
3362 InitReg(MISCREG_DCIMVAC)
3363 .unimplemented()
3364 .warnNotFail()
3365 .writes(1).exceptUserMode();
3366 InitReg(MISCREG_DCISW)
3367 .unimplemented()
3368 .warnNotFail()
3369 .writes(1).exceptUserMode();
3370 InitReg(MISCREG_ATS1CPR)
3371 .writes(1).exceptUserMode();
3372 InitReg(MISCREG_ATS1CPW)
3373 .writes(1).exceptUserMode();
3374 InitReg(MISCREG_ATS1CUR)
3375 .writes(1).exceptUserMode();
3376 InitReg(MISCREG_ATS1CUW)
3377 .writes(1).exceptUserMode();
3378 InitReg(MISCREG_ATS12NSOPR)
3379 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3380 InitReg(MISCREG_ATS12NSOPW)
3381 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3382 InitReg(MISCREG_ATS12NSOUR)
3383 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3384 InitReg(MISCREG_ATS12NSOUW)
3385 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3386 InitReg(MISCREG_DCCMVAC)
3387 .writes(1).exceptUserMode();
3388 InitReg(MISCREG_DCCSW)
3389 .unimplemented()
3390 .warnNotFail()
3391 .writes(1).exceptUserMode();
3392 InitReg(MISCREG_CP15DSB)
3393 .writes(1);
3394 InitReg(MISCREG_CP15DMB)
3395 .writes(1);
3396 InitReg(MISCREG_DCCMVAU)
3397 .unimplemented()
3398 .warnNotFail()
3399 .writes(1).exceptUserMode();
3400 InitReg(MISCREG_DCCIMVAC)
3401 .unimplemented()
3402 .warnNotFail()
3403 .writes(1).exceptUserMode();
3404 InitReg(MISCREG_DCCISW)
3405 .unimplemented()
3406 .warnNotFail()
3407 .writes(1).exceptUserMode();
3408 InitReg(MISCREG_ATS1HR)
3409 .monNonSecureWrite().hypWrite();
3410 InitReg(MISCREG_ATS1HW)
3411 .monNonSecureWrite().hypWrite();
3412 InitReg(MISCREG_TLBIALLIS)
3413 .writes(1).exceptUserMode();
3414 InitReg(MISCREG_TLBIMVAIS)
3415 .writes(1).exceptUserMode();
3416 InitReg(MISCREG_TLBIASIDIS)
3417 .writes(1).exceptUserMode();
3418 InitReg(MISCREG_TLBIMVAAIS)
3419 .writes(1).exceptUserMode();
3420 InitReg(MISCREG_TLBIMVALIS)
3421 .writes(1).exceptUserMode();
3422 InitReg(MISCREG_TLBIMVAALIS)
3423 .writes(1).exceptUserMode();
3424 InitReg(MISCREG_ITLBIALL)
3425 .writes(1).exceptUserMode();
3426 InitReg(MISCREG_ITLBIMVA)
3427 .writes(1).exceptUserMode();
3428 InitReg(MISCREG_ITLBIASID)
3429 .writes(1).exceptUserMode();
3430 InitReg(MISCREG_DTLBIALL)
3431 .writes(1).exceptUserMode();
3432 InitReg(MISCREG_DTLBIMVA)
3433 .writes(1).exceptUserMode();
3434 InitReg(MISCREG_DTLBIASID)
3435 .writes(1).exceptUserMode();
3436 InitReg(MISCREG_TLBIALL)
3437 .writes(1).exceptUserMode();
3438 InitReg(MISCREG_TLBIMVA)
3439 .writes(1).exceptUserMode();
3440 InitReg(MISCREG_TLBIASID)
3441 .writes(1).exceptUserMode();
3442 InitReg(MISCREG_TLBIMVAA)
3443 .writes(1).exceptUserMode();
3444 InitReg(MISCREG_TLBIMVAL)
3445 .writes(1).exceptUserMode();
3446 InitReg(MISCREG_TLBIMVAAL)
3447 .writes(1).exceptUserMode();
3448 InitReg(MISCREG_TLBIIPAS2IS)
3449 .monNonSecureWrite().hypWrite();
3450 InitReg(MISCREG_TLBIIPAS2LIS)
3451 .monNonSecureWrite().hypWrite();
3452 InitReg(MISCREG_TLBIALLHIS)
3453 .monNonSecureWrite().hypWrite();
3454 InitReg(MISCREG_TLBIMVAHIS)
3455 .monNonSecureWrite().hypWrite();
3456 InitReg(MISCREG_TLBIALLNSNHIS)
3457 .monNonSecureWrite().hypWrite();
3458 InitReg(MISCREG_TLBIMVALHIS)
3459 .monNonSecureWrite().hypWrite();
3460 InitReg(MISCREG_TLBIIPAS2)
3461 .monNonSecureWrite().hypWrite();
3462 InitReg(MISCREG_TLBIIPAS2L)
3463 .monNonSecureWrite().hypWrite();
3464 InitReg(MISCREG_TLBIALLH)
3465 .monNonSecureWrite().hypWrite();
3466 InitReg(MISCREG_TLBIMVAH)
3467 .monNonSecureWrite().hypWrite();
3468 InitReg(MISCREG_TLBIALLNSNH)
3469 .monNonSecureWrite().hypWrite();
3470 InitReg(MISCREG_TLBIMVALH)
3471 .monNonSecureWrite().hypWrite();
3472 InitReg(MISCREG_PMCR)
3473 .allPrivileges();
3474 InitReg(MISCREG_PMCNTENSET)
3475 .allPrivileges();
3476 InitReg(MISCREG_PMCNTENCLR)
3477 .allPrivileges();
3478 InitReg(MISCREG_PMOVSR)
3479 .allPrivileges();
3480 InitReg(MISCREG_PMSWINC)
3481 .allPrivileges();
3482 InitReg(MISCREG_PMSELR)
3483 .allPrivileges();
3484 InitReg(MISCREG_PMCEID0)
3485 .allPrivileges();
3486 InitReg(MISCREG_PMCEID1)
3487 .allPrivileges();
3488 InitReg(MISCREG_PMCCNTR)
3489 .allPrivileges();
3490 InitReg(MISCREG_PMXEVTYPER)
3491 .allPrivileges();
3492 InitReg(MISCREG_PMCCFILTR)
3493 .allPrivileges();
3494 InitReg(MISCREG_PMXEVCNTR)
3495 .allPrivileges();
3496 InitReg(MISCREG_PMUSERENR)
3497 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3498 InitReg(MISCREG_PMINTENSET)
3499 .allPrivileges().exceptUserMode();
3500 InitReg(MISCREG_PMINTENCLR)
3501 .allPrivileges().exceptUserMode();
3502 InitReg(MISCREG_PMOVSSET)
3503 .unimplemented()
3504 .allPrivileges();
3505 InitReg(MISCREG_L2CTLR)
3506 .allPrivileges().exceptUserMode();
3507 InitReg(MISCREG_L2ECTLR)
3508 .unimplemented()
3509 .allPrivileges().exceptUserMode();
3510 InitReg(MISCREG_PRRR)
3511 .banked();
3512 InitReg(MISCREG_PRRR_NS)
3513 .bankedChild()
3514 .privSecure(!aarch32EL3)
3515 .nonSecure().exceptUserMode();
3516 InitReg(MISCREG_PRRR_S)
3517 .bankedChild()
3518 .secure().exceptUserMode();
3519 InitReg(MISCREG_MAIR0)
3520 .banked();
3521 InitReg(MISCREG_MAIR0_NS)
3522 .bankedChild()
3523 .privSecure(!aarch32EL3)
3524 .nonSecure().exceptUserMode();
3525 InitReg(MISCREG_MAIR0_S)
3526 .bankedChild()
3527 .secure().exceptUserMode();
3528 InitReg(MISCREG_NMRR)
3529 .banked();
3530 InitReg(MISCREG_NMRR_NS)
3531 .bankedChild()
3532 .privSecure(!aarch32EL3)
3533 .nonSecure().exceptUserMode();
3534 InitReg(MISCREG_NMRR_S)
3535 .bankedChild()
3536 .secure().exceptUserMode();
3537 InitReg(MISCREG_MAIR1)
3538 .banked();
3539 InitReg(MISCREG_MAIR1_NS)
3540 .bankedChild()
3541 .privSecure(!aarch32EL3)
3542 .nonSecure().exceptUserMode();
3543 InitReg(MISCREG_MAIR1_S)
3544 .bankedChild()
3545 .secure().exceptUserMode();
3546 InitReg(MISCREG_AMAIR0)
3547 .banked();
3548 InitReg(MISCREG_AMAIR0_NS)
3549 .bankedChild()
3550 .privSecure(!aarch32EL3)
3551 .nonSecure().exceptUserMode();
3552 InitReg(MISCREG_AMAIR0_S)
3553 .bankedChild()
3554 .secure().exceptUserMode();
3555 InitReg(MISCREG_AMAIR1)
3556 .banked();
3557 InitReg(MISCREG_AMAIR1_NS)
3558 .bankedChild()
3559 .privSecure(!aarch32EL3)
3560 .nonSecure().exceptUserMode();
3561 InitReg(MISCREG_AMAIR1_S)
3562 .bankedChild()
3563 .secure().exceptUserMode();
3564 InitReg(MISCREG_HMAIR0)
3565 .hyp().monNonSecure();
3566 InitReg(MISCREG_HMAIR1)
3567 .hyp().monNonSecure();
3568 InitReg(MISCREG_HAMAIR0)
3569 .unimplemented()
3570 .warnNotFail()
3571 .hyp().monNonSecure();
3572 InitReg(MISCREG_HAMAIR1)
3573 .unimplemented()
3574 .warnNotFail()
3575 .hyp().monNonSecure();
3576 InitReg(MISCREG_VBAR)
3577 .banked();
3578 InitReg(MISCREG_VBAR_NS)
3579 .bankedChild()
3580 .privSecure(!aarch32EL3)
3581 .nonSecure().exceptUserMode();
3582 InitReg(MISCREG_VBAR_S)
3583 .bankedChild()
3584 .secure().exceptUserMode();
3585 InitReg(MISCREG_MVBAR)
3586 .mon().secure()
3587 .hypRead(FullSystem && system->highestEL() == EL2)
3588 .privRead(FullSystem && system->highestEL() == EL1)
3589 .exceptUserMode();
3590 InitReg(MISCREG_RMR)
3591 .unimplemented()
3592 .mon().secure().exceptUserMode();
3593 InitReg(MISCREG_ISR)
3594 .allPrivileges().exceptUserMode().writes(0);
3595 InitReg(MISCREG_HVBAR)
3596 .hyp().monNonSecure()
3597 .res0(0x1f);
3598 InitReg(MISCREG_FCSEIDR)
3599 .unimplemented()
3600 .warnNotFail()
3601 .allPrivileges().exceptUserMode();
3602 InitReg(MISCREG_CONTEXTIDR)
3603 .banked();
3604 InitReg(MISCREG_CONTEXTIDR_NS)
3605 .bankedChild()
3606 .privSecure(!aarch32EL3)
3607 .nonSecure().exceptUserMode();
3608 InitReg(MISCREG_CONTEXTIDR_S)
3609 .bankedChild()
3610 .secure().exceptUserMode();
3611 InitReg(MISCREG_TPIDRURW)
3612 .banked();
3613 InitReg(MISCREG_TPIDRURW_NS)
3614 .bankedChild()
3615 .allPrivileges()
3616 .privSecure(!aarch32EL3)
3617 .monSecure(0);
3618 InitReg(MISCREG_TPIDRURW_S)
3619 .bankedChild()
3620 .secure();
3621 InitReg(MISCREG_TPIDRURO)
3622 .banked();
3623 InitReg(MISCREG_TPIDRURO_NS)
3624 .bankedChild()
3625 .allPrivileges()
3626 .userNonSecureWrite(0).userSecureRead(1)
3627 .privSecure(!aarch32EL3)
3628 .monSecure(0);
3629 InitReg(MISCREG_TPIDRURO_S)
3630 .bankedChild()
3631 .secure().userSecureWrite(0);
3632 InitReg(MISCREG_TPIDRPRW)
3633 .banked();
3634 InitReg(MISCREG_TPIDRPRW_NS)
3635 .bankedChild()
3636 .nonSecure().exceptUserMode()
3637 .privSecure(!aarch32EL3);
3638 InitReg(MISCREG_TPIDRPRW_S)
3639 .bankedChild()
3640 .secure().exceptUserMode();
3641 InitReg(MISCREG_HTPIDR)
3642 .hyp().monNonSecure();
3643 InitReg(MISCREG_CNTFRQ)
3644 .unverifiable()
3645 .reads(1).mon();
3646 InitReg(MISCREG_CNTKCTL)
3647 .allPrivileges().exceptUserMode();
3648 InitReg(MISCREG_CNTP_TVAL)
3649 .banked();
3650 InitReg(MISCREG_CNTP_TVAL_NS)
3651 .bankedChild()
3652 .allPrivileges()
3653 .privSecure(!aarch32EL3)
3654 .monSecure(0);
3655 InitReg(MISCREG_CNTP_TVAL_S)
3656 .bankedChild()
3657 .secure().user(1);
3658 InitReg(MISCREG_CNTP_CTL)
3659 .banked();
3660 InitReg(MISCREG_CNTP_CTL_NS)
3661 .bankedChild()
3662 .allPrivileges()
3663 .privSecure(!aarch32EL3)
3664 .monSecure(0);
3665 InitReg(MISCREG_CNTP_CTL_S)
3666 .bankedChild()
3667 .secure().user(1);
3668 InitReg(MISCREG_CNTV_TVAL)
3669 .allPrivileges();
3670 InitReg(MISCREG_CNTV_CTL)
3671 .allPrivileges();
3672 InitReg(MISCREG_CNTHCTL)
3673 .hypWrite().monNonSecureRead();
3674 InitReg(MISCREG_CNTHP_TVAL)
3675 .hypWrite().monNonSecureRead();
3676 InitReg(MISCREG_CNTHP_CTL)
3677 .hypWrite().monNonSecureRead();
3678 InitReg(MISCREG_IL1DATA0)
3679 .unimplemented()
3680 .allPrivileges().exceptUserMode();
3681 InitReg(MISCREG_IL1DATA1)
3682 .unimplemented()
3683 .allPrivileges().exceptUserMode();
3684 InitReg(MISCREG_IL1DATA2)
3685 .unimplemented()
3686 .allPrivileges().exceptUserMode();
3687 InitReg(MISCREG_IL1DATA3)
3688 .unimplemented()
3689 .allPrivileges().exceptUserMode();
3690 InitReg(MISCREG_DL1DATA0)
3691 .unimplemented()
3692 .allPrivileges().exceptUserMode();
3693 InitReg(MISCREG_DL1DATA1)
3694 .unimplemented()
3695 .allPrivileges().exceptUserMode();
3696 InitReg(MISCREG_DL1DATA2)
3697 .unimplemented()
3698 .allPrivileges().exceptUserMode();
3699 InitReg(MISCREG_DL1DATA3)
3700 .unimplemented()
3701 .allPrivileges().exceptUserMode();
3702 InitReg(MISCREG_DL1DATA4)
3703 .unimplemented()
3704 .allPrivileges().exceptUserMode();
3705 InitReg(MISCREG_RAMINDEX)
3706 .unimplemented()
3707 .writes(1).exceptUserMode();
3708 InitReg(MISCREG_L2ACTLR)
3709 .unimplemented()
3710 .allPrivileges().exceptUserMode();
3711 InitReg(MISCREG_CBAR)
3712 .unimplemented()
3713 .allPrivileges().exceptUserMode().writes(0);
3714 InitReg(MISCREG_HTTBR)
3715 .hyp().monNonSecure();
3716 InitReg(MISCREG_VTTBR)
3717 .hyp().monNonSecure();
3718 InitReg(MISCREG_CNTPCT)
3719 .reads(1);
3720 InitReg(MISCREG_CNTVCT)
3721 .unverifiable()
3722 .reads(1);
3723 InitReg(MISCREG_CNTP_CVAL)
3724 .banked();
3725 InitReg(MISCREG_CNTP_CVAL_NS)
3726 .bankedChild()
3727 .allPrivileges()
3728 .privSecure(!aarch32EL3)
3729 .monSecure(0);
3730 InitReg(MISCREG_CNTP_CVAL_S)
3731 .bankedChild()
3732 .secure().user(1);
3733 InitReg(MISCREG_CNTV_CVAL)
3734 .allPrivileges();
3735 InitReg(MISCREG_CNTVOFF)
3736 .hyp().monNonSecure();
3737 InitReg(MISCREG_CNTHP_CVAL)
3738 .hypWrite().monNonSecureRead();
3739 InitReg(MISCREG_CPUMERRSR)
3740 .unimplemented()
3741 .allPrivileges().exceptUserMode();
3742 InitReg(MISCREG_L2MERRSR)
3743 .unimplemented()
3744 .warnNotFail()
3745 .allPrivileges().exceptUserMode();
3746
3747 // AArch64 registers (Op0=2);
3748 InitReg(MISCREG_MDCCINT_EL1)
3749 .allPrivileges();
3750 InitReg(MISCREG_OSDTRRX_EL1)
3751 .allPrivileges()
3752 .mapsTo(MISCREG_DBGDTRRXext);
3753 InitReg(MISCREG_MDSCR_EL1)
3754 .allPrivileges()
3755 .mapsTo(MISCREG_DBGDSCRext);
3756 InitReg(MISCREG_OSDTRTX_EL1)
3757 .allPrivileges()
3758 .mapsTo(MISCREG_DBGDTRTXext);
3759 InitReg(MISCREG_OSECCR_EL1)
3760 .allPrivileges()
3761 .mapsTo(MISCREG_DBGOSECCR);
3762 InitReg(MISCREG_DBGBVR0_EL1)
3763 .allPrivileges()
3764 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3765 InitReg(MISCREG_DBGBVR1_EL1)
3766 .allPrivileges()
3767 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3768 InitReg(MISCREG_DBGBVR2_EL1)
3769 .allPrivileges()
3770 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3771 InitReg(MISCREG_DBGBVR3_EL1)
3772 .allPrivileges()
3773 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3774 InitReg(MISCREG_DBGBVR4_EL1)
3775 .allPrivileges()
3776 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3777 InitReg(MISCREG_DBGBVR5_EL1)
3778 .allPrivileges()
3779 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3780 InitReg(MISCREG_DBGBCR0_EL1)
3781 .allPrivileges()
3782 .mapsTo(MISCREG_DBGBCR0);
3783 InitReg(MISCREG_DBGBCR1_EL1)
3784 .allPrivileges()
3785 .mapsTo(MISCREG_DBGBCR1);
3786 InitReg(MISCREG_DBGBCR2_EL1)
3787 .allPrivileges()
3788 .mapsTo(MISCREG_DBGBCR2);
3789 InitReg(MISCREG_DBGBCR3_EL1)
3790 .allPrivileges()
3791 .mapsTo(MISCREG_DBGBCR3);
3792 InitReg(MISCREG_DBGBCR4_EL1)
3793 .allPrivileges()
3794 .mapsTo(MISCREG_DBGBCR4);
3795 InitReg(MISCREG_DBGBCR5_EL1)
3796 .allPrivileges()
3797 .mapsTo(MISCREG_DBGBCR5);
3798 InitReg(MISCREG_DBGWVR0_EL1)
3799 .allPrivileges()
3800 .mapsTo(MISCREG_DBGWVR0);
3801 InitReg(MISCREG_DBGWVR1_EL1)
3802 .allPrivileges()
3803 .mapsTo(MISCREG_DBGWVR1);
3804 InitReg(MISCREG_DBGWVR2_EL1)
3805 .allPrivileges()
3806 .mapsTo(MISCREG_DBGWVR2);
3807 InitReg(MISCREG_DBGWVR3_EL1)
3808 .allPrivileges()
3809 .mapsTo(MISCREG_DBGWVR3);
3810 InitReg(MISCREG_DBGWCR0_EL1)
3811 .allPrivileges()
3812 .mapsTo(MISCREG_DBGWCR0);
3813 InitReg(MISCREG_DBGWCR1_EL1)
3814 .allPrivileges()
3815 .mapsTo(MISCREG_DBGWCR1);
3816 InitReg(MISCREG_DBGWCR2_EL1)
3817 .allPrivileges()
3818 .mapsTo(MISCREG_DBGWCR2);
3819 InitReg(MISCREG_DBGWCR3_EL1)
3820 .allPrivileges()
3821 .mapsTo(MISCREG_DBGWCR3);
3822 InitReg(MISCREG_MDCCSR_EL0)
3823 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3824 .mapsTo(MISCREG_DBGDSCRint);
3825 InitReg(MISCREG_MDDTR_EL0)
3826 .allPrivileges();
3827 InitReg(MISCREG_MDDTRTX_EL0)
3828 .allPrivileges();
3829 InitReg(MISCREG_MDDTRRX_EL0)
3830 .allPrivileges();
3831 InitReg(MISCREG_DBGVCR32_EL2)
3832 .allPrivileges()
3833 .mapsTo(MISCREG_DBGVCR);
3834 InitReg(MISCREG_MDRAR_EL1)
3835 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3836 .mapsTo(MISCREG_DBGDRAR);
3837 InitReg(MISCREG_OSLAR_EL1)
3838 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3839 .mapsTo(MISCREG_DBGOSLAR);
3840 InitReg(MISCREG_OSLSR_EL1)
3841 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3842 .mapsTo(MISCREG_DBGOSLSR);
3843 InitReg(MISCREG_OSDLR_EL1)
3844 .allPrivileges()
3845 .mapsTo(MISCREG_DBGOSDLR);
3846 InitReg(MISCREG_DBGPRCR_EL1)
3847 .allPrivileges()
3848 .mapsTo(MISCREG_DBGPRCR);
3849 InitReg(MISCREG_DBGCLAIMSET_EL1)
3850 .allPrivileges()
3851 .mapsTo(MISCREG_DBGCLAIMSET);
3852 InitReg(MISCREG_DBGCLAIMCLR_EL1)
3853 .allPrivileges()
3854 .mapsTo(MISCREG_DBGCLAIMCLR);
3855 InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3856 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3857 .mapsTo(MISCREG_DBGAUTHSTATUS);
3858 InitReg(MISCREG_TEECR32_EL1);
3859 InitReg(MISCREG_TEEHBR32_EL1);
3860
3861 // AArch64 registers (Op0=1,3);
3862 InitReg(MISCREG_MIDR_EL1)
3863 .allPrivileges().exceptUserMode().writes(0);
3864 InitReg(MISCREG_MPIDR_EL1)
3865 .allPrivileges().exceptUserMode().writes(0);
3866 InitReg(MISCREG_REVIDR_EL1)
3867 .allPrivileges().exceptUserMode().writes(0);
3868 InitReg(MISCREG_ID_PFR0_EL1)
3869 .allPrivileges().exceptUserMode().writes(0)
3870 .mapsTo(MISCREG_ID_PFR0);
3871 InitReg(MISCREG_ID_PFR1_EL1)
3872 .allPrivileges().exceptUserMode().writes(0)
3873 .mapsTo(MISCREG_ID_PFR1);
3874 InitReg(MISCREG_ID_DFR0_EL1)
3875 .allPrivileges().exceptUserMode().writes(0)
3876 .mapsTo(MISCREG_ID_DFR0);
3877 InitReg(MISCREG_ID_AFR0_EL1)
3878 .allPrivileges().exceptUserMode().writes(0)
3879 .mapsTo(MISCREG_ID_AFR0);
3880 InitReg(MISCREG_ID_MMFR0_EL1)
3881 .allPrivileges().exceptUserMode().writes(0)
3882 .mapsTo(MISCREG_ID_MMFR0);
3883 InitReg(MISCREG_ID_MMFR1_EL1)
3884 .allPrivileges().exceptUserMode().writes(0)
3885 .mapsTo(MISCREG_ID_MMFR1);
3886 InitReg(MISCREG_ID_MMFR2_EL1)
3887 .allPrivileges().exceptUserMode().writes(0)
3888 .mapsTo(MISCREG_ID_MMFR2);
3889 InitReg(MISCREG_ID_MMFR3_EL1)
3890 .allPrivileges().exceptUserMode().writes(0)
3891 .mapsTo(MISCREG_ID_MMFR3);
3892 InitReg(MISCREG_ID_ISAR0_EL1)
3893 .allPrivileges().exceptUserMode().writes(0)
3894 .mapsTo(MISCREG_ID_ISAR0);
3895 InitReg(MISCREG_ID_ISAR1_EL1)
3896 .allPrivileges().exceptUserMode().writes(0)
3897 .mapsTo(MISCREG_ID_ISAR1);
3898 InitReg(MISCREG_ID_ISAR2_EL1)
3899 .allPrivileges().exceptUserMode().writes(0)
3900 .mapsTo(MISCREG_ID_ISAR2);
3901 InitReg(MISCREG_ID_ISAR3_EL1)
3902 .allPrivileges().exceptUserMode().writes(0)
3903 .mapsTo(MISCREG_ID_ISAR3);
3904 InitReg(MISCREG_ID_ISAR4_EL1)
3905 .allPrivileges().exceptUserMode().writes(0)
3906 .mapsTo(MISCREG_ID_ISAR4);
3907 InitReg(MISCREG_ID_ISAR5_EL1)
3908 .allPrivileges().exceptUserMode().writes(0)
3909 .mapsTo(MISCREG_ID_ISAR5);
3910 InitReg(MISCREG_MVFR0_EL1)
3911 .allPrivileges().exceptUserMode().writes(0);
3912 InitReg(MISCREG_MVFR1_EL1)
3913 .allPrivileges().exceptUserMode().writes(0);
3914 InitReg(MISCREG_MVFR2_EL1)
3915 .allPrivileges().exceptUserMode().writes(0);
3916 InitReg(MISCREG_ID_AA64PFR0_EL1)
3917 .allPrivileges().exceptUserMode().writes(0);
3918 InitReg(MISCREG_ID_AA64PFR1_EL1)
3919 .allPrivileges().exceptUserMode().writes(0);
3920 InitReg(MISCREG_ID_AA64DFR0_EL1)
3921 .allPrivileges().exceptUserMode().writes(0);
3922 InitReg(MISCREG_ID_AA64DFR1_EL1)
3923 .allPrivileges().exceptUserMode().writes(0);
3924 InitReg(MISCREG_ID_AA64AFR0_EL1)
3925 .allPrivileges().exceptUserMode().writes(0);
3926 InitReg(MISCREG_ID_AA64AFR1_EL1)
3927 .allPrivileges().exceptUserMode().writes(0);
3928 InitReg(MISCREG_ID_AA64ISAR0_EL1)
3929 .allPrivileges().exceptUserMode().writes(0);
3930 InitReg(MISCREG_ID_AA64ISAR1_EL1)
3931 .allPrivileges().exceptUserMode().writes(0);
3932 InitReg(MISCREG_ID_AA64MMFR0_EL1)
3933 .allPrivileges().exceptUserMode().writes(0);
3934 InitReg(MISCREG_ID_AA64MMFR1_EL1)
3935 .allPrivileges().exceptUserMode().writes(0);
3936 InitReg(MISCREG_ID_AA64MMFR2_EL1)
3937 .allPrivileges().exceptUserMode().writes(0);
3938 InitReg(MISCREG_CCSIDR_EL1)
3939 .allPrivileges().exceptUserMode().writes(0);
3940 InitReg(MISCREG_CLIDR_EL1)
3941 .allPrivileges().exceptUserMode().writes(0);
3942 InitReg(MISCREG_AIDR_EL1)
3943 .allPrivileges().exceptUserMode().writes(0);
3944 InitReg(MISCREG_CSSELR_EL1)
3945 .allPrivileges().exceptUserMode()
3946 .mapsTo(MISCREG_CSSELR_NS);
3947 InitReg(MISCREG_CTR_EL0)
3948 .reads(1);
3949 InitReg(MISCREG_DCZID_EL0)
3950 .reads(1);
3951 InitReg(MISCREG_VPIDR_EL2)
3952 .hyp().mon()
3953 .mapsTo(MISCREG_VPIDR);
3954 InitReg(MISCREG_VMPIDR_EL2)
3955 .hyp().mon()
3956 .mapsTo(MISCREG_VMPIDR);
3957 InitReg(MISCREG_SCTLR_EL1)
3958 .allPrivileges().exceptUserMode()
3959 .res0( 0x20440 | (EnDB ? 0 : 0x2000)
3960 | (IESB ? 0 : 0x200000)
3961 | (EnDA ? 0 : 0x8000000)
3962 | (EnIB ? 0 : 0x40000000)
3963 | (EnIA ? 0 : 0x80000000))
3964 .res1(0x500800 | (SPAN ? 0 : 0x800000)
3965 | (nTLSMD ? 0 : 0x8000000)
3966 | (LSMAOE ? 0 : 0x10000000))
3967 .mapsTo(MISCREG_SCTLR_NS);
3968 InitReg(MISCREG_ACTLR_EL1)
3969 .allPrivileges().exceptUserMode()
3970 .mapsTo(MISCREG_ACTLR_NS);
3971 InitReg(MISCREG_CPACR_EL1)
3972 .allPrivileges().exceptUserMode()
3973 .mapsTo(MISCREG_CPACR);
3974 InitReg(MISCREG_SCTLR_EL2)
3975 .hyp().mon()
3976 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3977 | (IESB ? 0 : 0x200000)
3978 | (EnDA ? 0 : 0x8000000)
3979 | (EnIB ? 0 : 0x40000000)
3980 | (EnIA ? 0 : 0x80000000))
3981 .res1(0x30c50830)
3982 .mapsTo(MISCREG_HSCTLR);
3983 InitReg(MISCREG_ACTLR_EL2)
3984 .hyp().mon()
3985 .mapsTo(MISCREG_HACTLR);
3986 InitReg(MISCREG_HCR_EL2)
3987 .hyp().mon()
3988 .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
3989 InitReg(MISCREG_MDCR_EL2)
3990 .hyp().mon()
3991 .mapsTo(MISCREG_HDCR);
3992 InitReg(MISCREG_CPTR_EL2)
3993 .hyp().mon()
3994 .mapsTo(MISCREG_HCPTR);
3995 InitReg(MISCREG_HSTR_EL2)
3996 .hyp().mon()
3997 .mapsTo(MISCREG_HSTR);
3998 InitReg(MISCREG_HACR_EL2)
3999 .hyp().mon()
4000 .mapsTo(MISCREG_HACR);
4001 InitReg(MISCREG_SCTLR_EL3)
4002 .mon()
4003 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4004 | (IESB ? 0 : 0x200000)
4005 | (EnDA ? 0 : 0x8000000)
4006 | (EnIB ? 0 : 0x40000000)
4007 | (EnIA ? 0 : 0x80000000))
4008 .res1(0x30c50830);
4009 InitReg(MISCREG_ACTLR_EL3)
4010 .mon();
4011 InitReg(MISCREG_SCR_EL3)
4012 .mon()
4013 .mapsTo(MISCREG_SCR); // NAM D7-2005
4014 InitReg(MISCREG_SDER32_EL3)
4015 .mon()
4016 .mapsTo(MISCREG_SDER);
4017 InitReg(MISCREG_CPTR_EL3)
4018 .mon();
4019 InitReg(MISCREG_MDCR_EL3)
4020 .mon();
4021 InitReg(MISCREG_TTBR0_EL1)
4022 .allPrivileges().exceptUserMode()
4023 .mapsTo(MISCREG_TTBR0_NS);
4024 InitReg(MISCREG_TTBR1_EL1)
4025 .allPrivileges().exceptUserMode()
4026 .mapsTo(MISCREG_TTBR1_NS);
4027 InitReg(MISCREG_TCR_EL1)
4028 .allPrivileges().exceptUserMode()
4029 .mapsTo(MISCREG_TTBCR_NS);
4030 InitReg(MISCREG_TTBR0_EL2)
4031 .hyp().mon()
4032 .mapsTo(MISCREG_HTTBR);
4033 InitReg(MISCREG_TTBR1_EL2)
4034 .hyp().mon();
4035 InitReg(MISCREG_TCR_EL2)
4036 .hyp().mon()
4037 .mapsTo(MISCREG_HTCR);
4038 InitReg(MISCREG_VTTBR_EL2)
4039 .hyp().mon()
4040 .mapsTo(MISCREG_VTTBR);
4041 InitReg(MISCREG_VTCR_EL2)
4042 .hyp().mon()
4043 .mapsTo(MISCREG_VTCR);
4044 InitReg(MISCREG_TTBR0_EL3)
4045 .mon();
4046 InitReg(MISCREG_TCR_EL3)
4047 .mon();
4048 InitReg(MISCREG_DACR32_EL2)
4049 .hyp().mon()
4050 .mapsTo(MISCREG_DACR_NS);
4051 InitReg(MISCREG_SPSR_EL1)
4052 .allPrivileges().exceptUserMode()
4053 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
4054 InitReg(MISCREG_ELR_EL1)
4055 .allPrivileges().exceptUserMode();
4056 InitReg(MISCREG_SP_EL0)
4057 .allPrivileges().exceptUserMode();
4058 InitReg(MISCREG_SPSEL)
4059 .allPrivileges().exceptUserMode();
4060 InitReg(MISCREG_CURRENTEL)
4061 .allPrivileges().exceptUserMode().writes(0);

4062 InitReg(MISCREG_PAN)
4063 .allPrivileges().exceptUserMode()
4064 .implemented(havePAN);

4065 InitReg(MISCREG_NZCV)
4066 .allPrivileges();
4067 InitReg(MISCREG_DAIF)
4068 .allPrivileges();
4069 InitReg(MISCREG_FPCR)
4070 .allPrivileges();
4071 InitReg(MISCREG_FPSR)
4072 .allPrivileges();
4073 InitReg(MISCREG_DSPSR_EL0)
4074 .allPrivileges();
4075 InitReg(MISCREG_DLR_EL0)
4076 .allPrivileges();
4077 InitReg(MISCREG_SPSR_EL2)
4078 .hyp().mon()
4079 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
4080 InitReg(MISCREG_ELR_EL2)
4081 .hyp().mon();
4082 InitReg(MISCREG_SP_EL1)
4083 .hyp().mon();
4084 InitReg(MISCREG_SPSR_IRQ_AA64)
4085 .hyp().mon();
4086 InitReg(MISCREG_SPSR_ABT_AA64)
4087 .hyp().mon();
4088 InitReg(MISCREG_SPSR_UND_AA64)
4089 .hyp().mon();
4090 InitReg(MISCREG_SPSR_FIQ_AA64)
4091 .hyp().mon();
4092 InitReg(MISCREG_SPSR_EL3)
4093 .mon()
4094 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
4095 InitReg(MISCREG_ELR_EL3)
4096 .mon();
4097 InitReg(MISCREG_SP_EL2)
4098 .mon();
4099 InitReg(MISCREG_AFSR0_EL1)
4100 .allPrivileges().exceptUserMode()
4101 .mapsTo(MISCREG_ADFSR_NS);
4102 InitReg(MISCREG_AFSR1_EL1)
4103 .allPrivileges().exceptUserMode()
4104 .mapsTo(MISCREG_AIFSR_NS);
4105 InitReg(MISCREG_ESR_EL1)
4106 .allPrivileges().exceptUserMode();
4107 InitReg(MISCREG_IFSR32_EL2)
4108 .hyp().mon()
4109 .mapsTo(MISCREG_IFSR_NS);
4110 InitReg(MISCREG_AFSR0_EL2)
4111 .hyp().mon()
4112 .mapsTo(MISCREG_HADFSR);
4113 InitReg(MISCREG_AFSR1_EL2)
4114 .hyp().mon()
4115 .mapsTo(MISCREG_HAIFSR);
4116 InitReg(MISCREG_ESR_EL2)
4117 .hyp().mon()
4118 .mapsTo(MISCREG_HSR);
4119 InitReg(MISCREG_FPEXC32_EL2)
4120 .hyp().mon().mapsTo(MISCREG_FPEXC);
4121 InitReg(MISCREG_AFSR0_EL3)
4122 .mon();
4123 InitReg(MISCREG_AFSR1_EL3)
4124 .mon();
4125 InitReg(MISCREG_ESR_EL3)
4126 .mon();
4127 InitReg(MISCREG_FAR_EL1)
4128 .allPrivileges().exceptUserMode()
4129 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
4130 InitReg(MISCREG_FAR_EL2)
4131 .hyp().mon()
4132 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
4133 InitReg(MISCREG_HPFAR_EL2)
4134 .hyp().mon()
4135 .mapsTo(MISCREG_HPFAR);
4136 InitReg(MISCREG_FAR_EL3)
4137 .mon();
4138 InitReg(MISCREG_IC_IALLUIS)
4139 .warnNotFail()
4140 .writes(1).exceptUserMode();
4141 InitReg(MISCREG_PAR_EL1)
4142 .allPrivileges().exceptUserMode()
4143 .mapsTo(MISCREG_PAR_NS);
4144 InitReg(MISCREG_IC_IALLU)
4145 .warnNotFail()
4146 .writes(1).exceptUserMode();
4147 InitReg(MISCREG_DC_IVAC_Xt)
4148 .warnNotFail()
4149 .writes(1).exceptUserMode();
4150 InitReg(MISCREG_DC_ISW_Xt)
4151 .warnNotFail()
4152 .writes(1).exceptUserMode();
4153 InitReg(MISCREG_AT_S1E1R_Xt)
4154 .writes(1).exceptUserMode();
4155 InitReg(MISCREG_AT_S1E1W_Xt)
4156 .writes(1).exceptUserMode();
4157 InitReg(MISCREG_AT_S1E0R_Xt)
4158 .writes(1).exceptUserMode();
4159 InitReg(MISCREG_AT_S1E0W_Xt)
4160 .writes(1).exceptUserMode();
4161 InitReg(MISCREG_DC_CSW_Xt)
4162 .warnNotFail()
4163 .writes(1).exceptUserMode();
4164 InitReg(MISCREG_DC_CISW_Xt)
4165 .warnNotFail()
4166 .writes(1).exceptUserMode();
4167 InitReg(MISCREG_DC_ZVA_Xt)
4168 .warnNotFail()
4169 .writes(1).userSecureWrite(0);
4170 InitReg(MISCREG_IC_IVAU_Xt)
4171 .writes(1);
4172 InitReg(MISCREG_DC_CVAC_Xt)
4173 .warnNotFail()
4174 .writes(1);
4175 InitReg(MISCREG_DC_CVAU_Xt)
4176 .warnNotFail()
4177 .writes(1);
4178 InitReg(MISCREG_DC_CIVAC_Xt)
4179 .warnNotFail()
4180 .writes(1);
4181 InitReg(MISCREG_AT_S1E2R_Xt)
4182 .monNonSecureWrite().hypWrite();
4183 InitReg(MISCREG_AT_S1E2W_Xt)
4184 .monNonSecureWrite().hypWrite();
4185 InitReg(MISCREG_AT_S12E1R_Xt)
4186 .hypWrite().monSecureWrite().monNonSecureWrite();
4187 InitReg(MISCREG_AT_S12E1W_Xt)
4188 .hypWrite().monSecureWrite().monNonSecureWrite();
4189 InitReg(MISCREG_AT_S12E0R_Xt)
4190 .hypWrite().monSecureWrite().monNonSecureWrite();
4191 InitReg(MISCREG_AT_S12E0W_Xt)
4192 .hypWrite().monSecureWrite().monNonSecureWrite();
4193 InitReg(MISCREG_AT_S1E3R_Xt)
4194 .monSecureWrite().monNonSecureWrite();
4195 InitReg(MISCREG_AT_S1E3W_Xt)
4196 .monSecureWrite().monNonSecureWrite();
4197 InitReg(MISCREG_TLBI_VMALLE1IS)
4198 .writes(1).exceptUserMode();
4199 InitReg(MISCREG_TLBI_VAE1IS_Xt)
4200 .writes(1).exceptUserMode();
4201 InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
4202 .writes(1).exceptUserMode();
4203 InitReg(MISCREG_TLBI_VAAE1IS_Xt)
4204 .writes(1).exceptUserMode();
4205 InitReg(MISCREG_TLBI_VALE1IS_Xt)
4206 .writes(1).exceptUserMode();
4207 InitReg(MISCREG_TLBI_VAALE1IS_Xt)
4208 .writes(1).exceptUserMode();
4209 InitReg(MISCREG_TLBI_VMALLE1)
4210 .writes(1).exceptUserMode();
4211 InitReg(MISCREG_TLBI_VAE1_Xt)
4212 .writes(1).exceptUserMode();
4213 InitReg(MISCREG_TLBI_ASIDE1_Xt)
4214 .writes(1).exceptUserMode();
4215 InitReg(MISCREG_TLBI_VAAE1_Xt)
4216 .writes(1).exceptUserMode();
4217 InitReg(MISCREG_TLBI_VALE1_Xt)
4218 .writes(1).exceptUserMode();
4219 InitReg(MISCREG_TLBI_VAALE1_Xt)
4220 .writes(1).exceptUserMode();
4221 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
4222 .hypWrite().monSecureWrite().monNonSecureWrite();
4223 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
4224 .hypWrite().monSecureWrite().monNonSecureWrite();
4225 InitReg(MISCREG_TLBI_ALLE2IS)
4226 .monNonSecureWrite().hypWrite();
4227 InitReg(MISCREG_TLBI_VAE2IS_Xt)
4228 .monNonSecureWrite().hypWrite();
4229 InitReg(MISCREG_TLBI_ALLE1IS)
4230 .hypWrite().monSecureWrite().monNonSecureWrite();
4231 InitReg(MISCREG_TLBI_VALE2IS_Xt)
4232 .monNonSecureWrite().hypWrite();
4233 InitReg(MISCREG_TLBI_VMALLS12E1IS)
4234 .hypWrite().monSecureWrite().monNonSecureWrite();
4235 InitReg(MISCREG_TLBI_IPAS2E1_Xt)
4236 .hypWrite().monSecureWrite().monNonSecureWrite();
4237 InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
4238 .hypWrite().monSecureWrite().monNonSecureWrite();
4239 InitReg(MISCREG_TLBI_ALLE2)
4240 .monNonSecureWrite().hypWrite();
4241 InitReg(MISCREG_TLBI_VAE2_Xt)
4242 .monNonSecureWrite().hypWrite();
4243 InitReg(MISCREG_TLBI_ALLE1)
4244 .hypWrite().monSecureWrite().monNonSecureWrite();
4245 InitReg(MISCREG_TLBI_VALE2_Xt)
4246 .monNonSecureWrite().hypWrite();
4247 InitReg(MISCREG_TLBI_VMALLS12E1)
4248 .hypWrite().monSecureWrite().monNonSecureWrite();
4249 InitReg(MISCREG_TLBI_ALLE3IS)
4250 .monSecureWrite().monNonSecureWrite();
4251 InitReg(MISCREG_TLBI_VAE3IS_Xt)
4252 .monSecureWrite().monNonSecureWrite();
4253 InitReg(MISCREG_TLBI_VALE3IS_Xt)
4254 .monSecureWrite().monNonSecureWrite();
4255 InitReg(MISCREG_TLBI_ALLE3)
4256 .monSecureWrite().monNonSecureWrite();
4257 InitReg(MISCREG_TLBI_VAE3_Xt)
4258 .monSecureWrite().monNonSecureWrite();
4259 InitReg(MISCREG_TLBI_VALE3_Xt)
4260 .monSecureWrite().monNonSecureWrite();
4261 InitReg(MISCREG_PMINTENSET_EL1)
4262 .allPrivileges().exceptUserMode()
4263 .mapsTo(MISCREG_PMINTENSET);
4264 InitReg(MISCREG_PMINTENCLR_EL1)
4265 .allPrivileges().exceptUserMode()
4266 .mapsTo(MISCREG_PMINTENCLR);
4267 InitReg(MISCREG_PMCR_EL0)
4268 .allPrivileges()
4269 .mapsTo(MISCREG_PMCR);
4270 InitReg(MISCREG_PMCNTENSET_EL0)
4271 .allPrivileges()
4272 .mapsTo(MISCREG_PMCNTENSET);
4273 InitReg(MISCREG_PMCNTENCLR_EL0)
4274 .allPrivileges()
4275 .mapsTo(MISCREG_PMCNTENCLR);
4276 InitReg(MISCREG_PMOVSCLR_EL0)
4277 .allPrivileges();
4278// .mapsTo(MISCREG_PMOVSCLR);
4279 InitReg(MISCREG_PMSWINC_EL0)
4280 .writes(1).user()
4281 .mapsTo(MISCREG_PMSWINC);
4282 InitReg(MISCREG_PMSELR_EL0)
4283 .allPrivileges()
4284 .mapsTo(MISCREG_PMSELR);
4285 InitReg(MISCREG_PMCEID0_EL0)
4286 .reads(1).user()
4287 .mapsTo(MISCREG_PMCEID0);
4288 InitReg(MISCREG_PMCEID1_EL0)
4289 .reads(1).user()
4290 .mapsTo(MISCREG_PMCEID1);
4291 InitReg(MISCREG_PMCCNTR_EL0)
4292 .allPrivileges()
4293 .mapsTo(MISCREG_PMCCNTR);
4294 InitReg(MISCREG_PMXEVTYPER_EL0)
4295 .allPrivileges()
4296 .mapsTo(MISCREG_PMXEVTYPER);
4297 InitReg(MISCREG_PMCCFILTR_EL0)
4298 .allPrivileges();
4299 InitReg(MISCREG_PMXEVCNTR_EL0)
4300 .allPrivileges()
4301 .mapsTo(MISCREG_PMXEVCNTR);
4302 InitReg(MISCREG_PMUSERENR_EL0)
4303 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4304 .mapsTo(MISCREG_PMUSERENR);
4305 InitReg(MISCREG_PMOVSSET_EL0)
4306 .allPrivileges()
4307 .mapsTo(MISCREG_PMOVSSET);
4308 InitReg(MISCREG_MAIR_EL1)
4309 .allPrivileges().exceptUserMode()
4310 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
4311 InitReg(MISCREG_AMAIR_EL1)
4312 .allPrivileges().exceptUserMode()
4313 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
4314 InitReg(MISCREG_MAIR_EL2)
4315 .hyp().mon()
4316 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
4317 InitReg(MISCREG_AMAIR_EL2)
4318 .hyp().mon()
4319 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
4320 InitReg(MISCREG_MAIR_EL3)
4321 .mon();
4322 InitReg(MISCREG_AMAIR_EL3)
4323 .mon();
4324 InitReg(MISCREG_L2CTLR_EL1)
4325 .allPrivileges().exceptUserMode();
4326 InitReg(MISCREG_L2ECTLR_EL1)
4327 .allPrivileges().exceptUserMode();
4328 InitReg(MISCREG_VBAR_EL1)
4329 .allPrivileges().exceptUserMode()
4330 .mapsTo(MISCREG_VBAR_NS);
4331 InitReg(MISCREG_RVBAR_EL1)
4332 .allPrivileges().exceptUserMode().writes(0);
4333 InitReg(MISCREG_ISR_EL1)
4334 .allPrivileges().exceptUserMode().writes(0);
4335 InitReg(MISCREG_VBAR_EL2)
4336 .hyp().mon()
4337 .res0(0x7ff)
4338 .mapsTo(MISCREG_HVBAR);
4339 InitReg(MISCREG_RVBAR_EL2)
4340 .mon().hyp().writes(0);
4341 InitReg(MISCREG_VBAR_EL3)
4342 .mon();
4343 InitReg(MISCREG_RVBAR_EL3)
4344 .mon().writes(0);
4345 InitReg(MISCREG_RMR_EL3)
4346 .mon();
4347 InitReg(MISCREG_CONTEXTIDR_EL1)
4348 .allPrivileges().exceptUserMode()
4349 .mapsTo(MISCREG_CONTEXTIDR_NS);
4350 InitReg(MISCREG_TPIDR_EL1)
4351 .allPrivileges().exceptUserMode()
4352 .mapsTo(MISCREG_TPIDRPRW_NS);
4353 InitReg(MISCREG_TPIDR_EL0)
4354 .allPrivileges()
4355 .mapsTo(MISCREG_TPIDRURW_NS);
4356 InitReg(MISCREG_TPIDRRO_EL0)
4357 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4358 .mapsTo(MISCREG_TPIDRURO_NS);
4359 InitReg(MISCREG_TPIDR_EL2)
4360 .hyp().mon()
4361 .mapsTo(MISCREG_HTPIDR);
4362 InitReg(MISCREG_TPIDR_EL3)
4363 .mon();
4364 InitReg(MISCREG_CNTKCTL_EL1)
4365 .allPrivileges().exceptUserMode()
4366 .mapsTo(MISCREG_CNTKCTL);
4367 InitReg(MISCREG_CNTFRQ_EL0)
4368 .reads(1).mon()
4369 .mapsTo(MISCREG_CNTFRQ);
4370 InitReg(MISCREG_CNTPCT_EL0)
4371 .reads(1)
4372 .mapsTo(MISCREG_CNTPCT); /* 64b */
4373 InitReg(MISCREG_CNTVCT_EL0)
4374 .unverifiable()
4375 .reads(1)
4376 .mapsTo(MISCREG_CNTVCT); /* 64b */
4377 InitReg(MISCREG_CNTP_TVAL_EL0)
4378 .allPrivileges()
4379 .mapsTo(MISCREG_CNTP_TVAL_NS);
4380 InitReg(MISCREG_CNTP_CTL_EL0)
4381 .allPrivileges()
4382 .mapsTo(MISCREG_CNTP_CTL_NS);
4383 InitReg(MISCREG_CNTP_CVAL_EL0)
4384 .allPrivileges()
4385 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
4386 InitReg(MISCREG_CNTV_TVAL_EL0)
4387 .allPrivileges()
4388 .mapsTo(MISCREG_CNTV_TVAL);
4389 InitReg(MISCREG_CNTV_CTL_EL0)
4390 .allPrivileges()
4391 .mapsTo(MISCREG_CNTV_CTL);
4392 InitReg(MISCREG_CNTV_CVAL_EL0)
4393 .allPrivileges()
4394 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
4395 InitReg(MISCREG_PMEVCNTR0_EL0)
4396 .allPrivileges();
4397// .mapsTo(MISCREG_PMEVCNTR0);
4398 InitReg(MISCREG_PMEVCNTR1_EL0)
4399 .allPrivileges();
4400// .mapsTo(MISCREG_PMEVCNTR1);
4401 InitReg(MISCREG_PMEVCNTR2_EL0)
4402 .allPrivileges();
4403// .mapsTo(MISCREG_PMEVCNTR2);
4404 InitReg(MISCREG_PMEVCNTR3_EL0)
4405 .allPrivileges();
4406// .mapsTo(MISCREG_PMEVCNTR3);
4407 InitReg(MISCREG_PMEVCNTR4_EL0)
4408 .allPrivileges();
4409// .mapsTo(MISCREG_PMEVCNTR4);
4410 InitReg(MISCREG_PMEVCNTR5_EL0)
4411 .allPrivileges();
4412// .mapsTo(MISCREG_PMEVCNTR5);
4413 InitReg(MISCREG_PMEVTYPER0_EL0)
4414 .allPrivileges();
4415// .mapsTo(MISCREG_PMEVTYPER0);
4416 InitReg(MISCREG_PMEVTYPER1_EL0)
4417 .allPrivileges();
4418// .mapsTo(MISCREG_PMEVTYPER1);
4419 InitReg(MISCREG_PMEVTYPER2_EL0)
4420 .allPrivileges();
4421// .mapsTo(MISCREG_PMEVTYPER2);
4422 InitReg(MISCREG_PMEVTYPER3_EL0)
4423 .allPrivileges();
4424// .mapsTo(MISCREG_PMEVTYPER3);
4425 InitReg(MISCREG_PMEVTYPER4_EL0)
4426 .allPrivileges();
4427// .mapsTo(MISCREG_PMEVTYPER4);
4428 InitReg(MISCREG_PMEVTYPER5_EL0)
4429 .allPrivileges();
4430// .mapsTo(MISCREG_PMEVTYPER5);
4431 InitReg(MISCREG_CNTVOFF_EL2)
4432 .hyp().mon()
4433 .mapsTo(MISCREG_CNTVOFF); /* 64b */
4434 InitReg(MISCREG_CNTHCTL_EL2)
4435 .mon().hyp()
4436 .mapsTo(MISCREG_CNTHCTL);
4437 InitReg(MISCREG_CNTHP_TVAL_EL2)
4438 .mon().hyp()
4439 .mapsTo(MISCREG_CNTHP_TVAL);
4440 InitReg(MISCREG_CNTHP_CTL_EL2)
4441 .mon().hyp()
4442 .mapsTo(MISCREG_CNTHP_CTL);
4443 InitReg(MISCREG_CNTHP_CVAL_EL2)
4444 .mon().hyp()
4445 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
4446 InitReg(MISCREG_CNTPS_TVAL_EL1)
4447 .mon().privSecure();
4448 InitReg(MISCREG_CNTPS_CTL_EL1)
4449 .mon().privSecure();
4450 InitReg(MISCREG_CNTPS_CVAL_EL1)
4451 .mon().privSecure();
4452 InitReg(MISCREG_IL1DATA0_EL1)
4453 .allPrivileges().exceptUserMode();
4454 InitReg(MISCREG_IL1DATA1_EL1)
4455 .allPrivileges().exceptUserMode();
4456 InitReg(MISCREG_IL1DATA2_EL1)
4457 .allPrivileges().exceptUserMode();
4458 InitReg(MISCREG_IL1DATA3_EL1)
4459 .allPrivileges().exceptUserMode();
4460 InitReg(MISCREG_DL1DATA0_EL1)
4461 .allPrivileges().exceptUserMode();
4462 InitReg(MISCREG_DL1DATA1_EL1)
4463 .allPrivileges().exceptUserMode();
4464 InitReg(MISCREG_DL1DATA2_EL1)
4465 .allPrivileges().exceptUserMode();
4466 InitReg(MISCREG_DL1DATA3_EL1)
4467 .allPrivileges().exceptUserMode();
4468 InitReg(MISCREG_DL1DATA4_EL1)
4469 .allPrivileges().exceptUserMode();
4470 InitReg(MISCREG_L2ACTLR_EL1)
4471 .allPrivileges().exceptUserMode();
4472 InitReg(MISCREG_CPUACTLR_EL1)
4473 .allPrivileges().exceptUserMode();
4474 InitReg(MISCREG_CPUECTLR_EL1)
4475 .allPrivileges().exceptUserMode();
4476 InitReg(MISCREG_CPUMERRSR_EL1)
4477 .allPrivileges().exceptUserMode();
4478 InitReg(MISCREG_L2MERRSR_EL1)
4479 .unimplemented()
4480 .warnNotFail()
4481 .allPrivileges().exceptUserMode();
4482 InitReg(MISCREG_CBAR_EL1)
4483 .allPrivileges().exceptUserMode().writes(0);
4484 InitReg(MISCREG_CONTEXTIDR_EL2)
4485 .mon().hyp();
4486
4487 // GICv3 AArch64
4488 InitReg(MISCREG_ICC_PMR_EL1)
4489 .res0(0xffffff00) // [31:8]
4490 .allPrivileges().exceptUserMode()
4491 .mapsTo(MISCREG_ICC_PMR);
4492 InitReg(MISCREG_ICC_IAR0_EL1)
4493 .allPrivileges().exceptUserMode().writes(0)
4494 .mapsTo(MISCREG_ICC_IAR0);
4495 InitReg(MISCREG_ICC_EOIR0_EL1)
4496 .allPrivileges().exceptUserMode().reads(0)
4497 .mapsTo(MISCREG_ICC_EOIR0);
4498 InitReg(MISCREG_ICC_HPPIR0_EL1)
4499 .allPrivileges().exceptUserMode().writes(0)
4500 .mapsTo(MISCREG_ICC_HPPIR0);
4501 InitReg(MISCREG_ICC_BPR0_EL1)
4502 .res0(0xfffffff8) // [31:3]
4503 .allPrivileges().exceptUserMode()
4504 .mapsTo(MISCREG_ICC_BPR0);
4505 InitReg(MISCREG_ICC_AP0R0_EL1)
4506 .allPrivileges().exceptUserMode()
4507 .mapsTo(MISCREG_ICC_AP0R0);
4508 InitReg(MISCREG_ICC_AP0R1_EL1)
4509 .allPrivileges().exceptUserMode()
4510 .mapsTo(MISCREG_ICC_AP0R1);
4511 InitReg(MISCREG_ICC_AP0R2_EL1)
4512 .allPrivileges().exceptUserMode()
4513 .mapsTo(MISCREG_ICC_AP0R2);
4514 InitReg(MISCREG_ICC_AP0R3_EL1)
4515 .allPrivileges().exceptUserMode()
4516 .mapsTo(MISCREG_ICC_AP0R3);
4517 InitReg(MISCREG_ICC_AP1R0_EL1)
4518 .banked()
4519 .mapsTo(MISCREG_ICC_AP1R0);
4520 InitReg(MISCREG_ICC_AP1R0_EL1_NS)
4521 .bankedChild()
4522 .allPrivileges().exceptUserMode()
4523 .mapsTo(MISCREG_ICC_AP1R0_NS);
4524 InitReg(MISCREG_ICC_AP1R0_EL1_S)
4525 .bankedChild()
4526 .allPrivileges().exceptUserMode()
4527 .mapsTo(MISCREG_ICC_AP1R0_S);
4528 InitReg(MISCREG_ICC_AP1R1_EL1)
4529 .banked()
4530 .mapsTo(MISCREG_ICC_AP1R1);
4531 InitReg(MISCREG_ICC_AP1R1_EL1_NS)
4532 .bankedChild()
4533 .allPrivileges().exceptUserMode()
4534 .mapsTo(MISCREG_ICC_AP1R1_NS);
4535 InitReg(MISCREG_ICC_AP1R1_EL1_S)
4536 .bankedChild()
4537 .allPrivileges().exceptUserMode()
4538 .mapsTo(MISCREG_ICC_AP1R1_S);
4539 InitReg(MISCREG_ICC_AP1R2_EL1)
4540 .banked()
4541 .mapsTo(MISCREG_ICC_AP1R2);
4542 InitReg(MISCREG_ICC_AP1R2_EL1_NS)
4543 .bankedChild()
4544 .allPrivileges().exceptUserMode()
4545 .mapsTo(MISCREG_ICC_AP1R2_NS);
4546 InitReg(MISCREG_ICC_AP1R2_EL1_S)
4547 .bankedChild()
4548 .allPrivileges().exceptUserMode()
4549 .mapsTo(MISCREG_ICC_AP1R2_S);
4550 InitReg(MISCREG_ICC_AP1R3_EL1)
4551 .banked()
4552 .mapsTo(MISCREG_ICC_AP1R3);
4553 InitReg(MISCREG_ICC_AP1R3_EL1_NS)
4554 .bankedChild()
4555 .allPrivileges().exceptUserMode()
4556 .mapsTo(MISCREG_ICC_AP1R3_NS);
4557 InitReg(MISCREG_ICC_AP1R3_EL1_S)
4558 .bankedChild()
4559 .allPrivileges().exceptUserMode()
4560 .mapsTo(MISCREG_ICC_AP1R3_S);
4561 InitReg(MISCREG_ICC_DIR_EL1)
4562 .res0(0xFF000000) // [31:24]
4563 .allPrivileges().exceptUserMode().reads(0)
4564 .mapsTo(MISCREG_ICC_DIR);
4565 InitReg(MISCREG_ICC_RPR_EL1)
4566 .allPrivileges().exceptUserMode().writes(0)
4567 .mapsTo(MISCREG_ICC_RPR);
4568 InitReg(MISCREG_ICC_SGI1R_EL1)
4569 .allPrivileges().exceptUserMode().reads(0)
4570 .mapsTo(MISCREG_ICC_SGI1R);
4571 InitReg(MISCREG_ICC_ASGI1R_EL1)
4572 .allPrivileges().exceptUserMode().reads(0)
4573 .mapsTo(MISCREG_ICC_ASGI1R);
4574 InitReg(MISCREG_ICC_SGI0R_EL1)
4575 .allPrivileges().exceptUserMode().reads(0)
4576 .mapsTo(MISCREG_ICC_SGI0R);
4577 InitReg(MISCREG_ICC_IAR1_EL1)
4578 .allPrivileges().exceptUserMode().writes(0)
4579 .mapsTo(MISCREG_ICC_IAR1);
4580 InitReg(MISCREG_ICC_EOIR1_EL1)
4581 .res0(0xFF000000) // [31:24]
4582 .allPrivileges().exceptUserMode().reads(0)
4583 .mapsTo(MISCREG_ICC_EOIR1);
4584 InitReg(MISCREG_ICC_HPPIR1_EL1)
4585 .allPrivileges().exceptUserMode().writes(0)
4586 .mapsTo(MISCREG_ICC_HPPIR1);
4587 InitReg(MISCREG_ICC_BPR1_EL1)
4588 .banked()
4589 .mapsTo(MISCREG_ICC_BPR1);
4590 InitReg(MISCREG_ICC_BPR1_EL1_NS)
4591 .bankedChild()
4592 .res0(0xfffffff8) // [31:3]
4593 .allPrivileges().exceptUserMode()
4594 .mapsTo(MISCREG_ICC_BPR1_NS);
4595 InitReg(MISCREG_ICC_BPR1_EL1_S)
4596 .bankedChild()
4597 .res0(0xfffffff8) // [31:3]
4598 .secure().exceptUserMode()
4599 .mapsTo(MISCREG_ICC_BPR1_S);
4600 InitReg(MISCREG_ICC_CTLR_EL1)
4601 .banked()
4602 .mapsTo(MISCREG_ICC_CTLR);
4603 InitReg(MISCREG_ICC_CTLR_EL1_NS)
4604 .bankedChild()
4605 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4606 .allPrivileges().exceptUserMode()
4607 .mapsTo(MISCREG_ICC_CTLR_NS);
4608 InitReg(MISCREG_ICC_CTLR_EL1_S)
4609 .bankedChild()
4610 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4611 .secure().exceptUserMode()
4612 .mapsTo(MISCREG_ICC_CTLR_S);
4613 InitReg(MISCREG_ICC_SRE_EL1)
4614 .banked()
4615 .mapsTo(MISCREG_ICC_SRE);
4616 InitReg(MISCREG_ICC_SRE_EL1_NS)
4617 .bankedChild()
4618 .res0(0xFFFFFFF8) // [31:3]
4619 .allPrivileges().exceptUserMode()
4620 .mapsTo(MISCREG_ICC_SRE_NS);
4621 InitReg(MISCREG_ICC_SRE_EL1_S)
4622 .bankedChild()
4623 .res0(0xFFFFFFF8) // [31:3]
4624 .secure().exceptUserMode()
4625 .mapsTo(MISCREG_ICC_SRE_S);
4626 InitReg(MISCREG_ICC_IGRPEN0_EL1)
4627 .res0(0xFFFFFFFE) // [31:1]
4628 .allPrivileges().exceptUserMode()
4629 .mapsTo(MISCREG_ICC_IGRPEN0);
4630 InitReg(MISCREG_ICC_IGRPEN1_EL1)
4631 .banked()
4632 .mapsTo(MISCREG_ICC_IGRPEN1);
4633 InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
4634 .bankedChild()
4635 .res0(0xFFFFFFFE) // [31:1]
4636 .allPrivileges().exceptUserMode()
4637 .mapsTo(MISCREG_ICC_IGRPEN1_NS);
4638 InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
4639 .bankedChild()
4640 .res0(0xFFFFFFFE) // [31:1]
4641 .secure().exceptUserMode()
4642 .mapsTo(MISCREG_ICC_IGRPEN1_S);
4643 InitReg(MISCREG_ICC_SRE_EL2)
4644 .hyp().mon()
4645 .mapsTo(MISCREG_ICC_HSRE);
4646 InitReg(MISCREG_ICC_CTLR_EL3)
4647 .allPrivileges().exceptUserMode()
4648 .mapsTo(MISCREG_ICC_MCTLR);
4649 InitReg(MISCREG_ICC_SRE_EL3)
4650 .allPrivileges().exceptUserMode()
4651 .mapsTo(MISCREG_ICC_MSRE);
4652 InitReg(MISCREG_ICC_IGRPEN1_EL3)
4653 .allPrivileges().exceptUserMode()
4654 .mapsTo(MISCREG_ICC_MGRPEN1);
4655
4656 InitReg(MISCREG_ICH_AP0R0_EL2)
4657 .hyp().mon()
4658 .mapsTo(MISCREG_ICH_AP0R0);
4659 InitReg(MISCREG_ICH_AP0R1_EL2)
4660 .hyp().mon()
4661 .unimplemented()
4662 .mapsTo(MISCREG_ICH_AP0R1);
4663 InitReg(MISCREG_ICH_AP0R2_EL2)
4664 .hyp().mon()
4665 .unimplemented()
4666 .mapsTo(MISCREG_ICH_AP0R2);
4667 InitReg(MISCREG_ICH_AP0R3_EL2)
4668 .hyp().mon()
4669 .unimplemented()
4670 .mapsTo(MISCREG_ICH_AP0R3);
4671 InitReg(MISCREG_ICH_AP1R0_EL2)
4672 .hyp().mon()
4673 .mapsTo(MISCREG_ICH_AP1R0);
4674 InitReg(MISCREG_ICH_AP1R1_EL2)
4675 .hyp().mon()
4676 .unimplemented()
4677 .mapsTo(MISCREG_ICH_AP1R1);
4678 InitReg(MISCREG_ICH_AP1R2_EL2)
4679 .hyp().mon()
4680 .unimplemented()
4681 .mapsTo(MISCREG_ICH_AP1R2);
4682 InitReg(MISCREG_ICH_AP1R3_EL2)
4683 .hyp().mon()
4684 .unimplemented()
4685 .mapsTo(MISCREG_ICH_AP1R3);
4686 InitReg(MISCREG_ICH_HCR_EL2)
4687 .hyp().mon()
4688 .mapsTo(MISCREG_ICH_HCR);
4689 InitReg(MISCREG_ICH_VTR_EL2)
4690 .hyp().mon().writes(0)
4691 .mapsTo(MISCREG_ICH_VTR);
4692 InitReg(MISCREG_ICH_MISR_EL2)
4693 .hyp().mon().writes(0)
4694 .mapsTo(MISCREG_ICH_MISR);
4695 InitReg(MISCREG_ICH_EISR_EL2)
4696 .hyp().mon().writes(0)
4697 .mapsTo(MISCREG_ICH_EISR);
4698 InitReg(MISCREG_ICH_ELRSR_EL2)
4699 .hyp().mon().writes(0)
4700 .mapsTo(MISCREG_ICH_ELRSR);
4701 InitReg(MISCREG_ICH_VMCR_EL2)
4702 .hyp().mon()
4703 .mapsTo(MISCREG_ICH_VMCR);
4704 InitReg(MISCREG_ICH_LR0_EL2)
4705 .hyp().mon()
4706 .allPrivileges().exceptUserMode();
4707 InitReg(MISCREG_ICH_LR1_EL2)
4708 .hyp().mon()
4709 .allPrivileges().exceptUserMode();
4710 InitReg(MISCREG_ICH_LR2_EL2)
4711 .hyp().mon()
4712 .allPrivileges().exceptUserMode();
4713 InitReg(MISCREG_ICH_LR3_EL2)
4714 .hyp().mon()
4715 .allPrivileges().exceptUserMode();
4716 InitReg(MISCREG_ICH_LR4_EL2)
4717 .hyp().mon()
4718 .allPrivileges().exceptUserMode();
4719 InitReg(MISCREG_ICH_LR5_EL2)
4720 .hyp().mon()
4721 .allPrivileges().exceptUserMode();
4722 InitReg(MISCREG_ICH_LR6_EL2)
4723 .hyp().mon()
4724 .allPrivileges().exceptUserMode();
4725 InitReg(MISCREG_ICH_LR7_EL2)
4726 .hyp().mon()
4727 .allPrivileges().exceptUserMode();
4728 InitReg(MISCREG_ICH_LR8_EL2)
4729 .hyp().mon()
4730 .allPrivileges().exceptUserMode();
4731 InitReg(MISCREG_ICH_LR9_EL2)
4732 .hyp().mon()
4733 .allPrivileges().exceptUserMode();
4734 InitReg(MISCREG_ICH_LR10_EL2)
4735 .hyp().mon()
4736 .allPrivileges().exceptUserMode();
4737 InitReg(MISCREG_ICH_LR11_EL2)
4738 .hyp().mon()
4739 .allPrivileges().exceptUserMode();
4740 InitReg(MISCREG_ICH_LR12_EL2)
4741 .hyp().mon()
4742 .allPrivileges().exceptUserMode();
4743 InitReg(MISCREG_ICH_LR13_EL2)
4744 .hyp().mon()
4745 .allPrivileges().exceptUserMode();
4746 InitReg(MISCREG_ICH_LR14_EL2)
4747 .hyp().mon()
4748 .allPrivileges().exceptUserMode();
4749 InitReg(MISCREG_ICH_LR15_EL2)
4750 .hyp().mon()
4751 .allPrivileges().exceptUserMode();
4752
4753 // GICv3 AArch32
4754 InitReg(MISCREG_ICC_AP0R0)
4755 .allPrivileges().exceptUserMode();
4756 InitReg(MISCREG_ICC_AP0R1)
4757 .allPrivileges().exceptUserMode();
4758 InitReg(MISCREG_ICC_AP0R2)
4759 .allPrivileges().exceptUserMode();
4760 InitReg(MISCREG_ICC_AP0R3)
4761 .allPrivileges().exceptUserMode();
4762 InitReg(MISCREG_ICC_AP1R0)
4763 .allPrivileges().exceptUserMode();
4764 InitReg(MISCREG_ICC_AP1R0_NS)
4765 .allPrivileges().exceptUserMode();
4766 InitReg(MISCREG_ICC_AP1R0_S)
4767 .allPrivileges().exceptUserMode();
4768 InitReg(MISCREG_ICC_AP1R1)
4769 .allPrivileges().exceptUserMode();
4770 InitReg(MISCREG_ICC_AP1R1_NS)
4771 .allPrivileges().exceptUserMode();
4772 InitReg(MISCREG_ICC_AP1R1_S)
4773 .allPrivileges().exceptUserMode();
4774 InitReg(MISCREG_ICC_AP1R2)
4775 .allPrivileges().exceptUserMode();
4776 InitReg(MISCREG_ICC_AP1R2_NS)
4777 .allPrivileges().exceptUserMode();
4778 InitReg(MISCREG_ICC_AP1R2_S)
4779 .allPrivileges().exceptUserMode();
4780 InitReg(MISCREG_ICC_AP1R3)
4781 .allPrivileges().exceptUserMode();
4782 InitReg(MISCREG_ICC_AP1R3_NS)
4783 .allPrivileges().exceptUserMode();
4784 InitReg(MISCREG_ICC_AP1R3_S)
4785 .allPrivileges().exceptUserMode();
4786 InitReg(MISCREG_ICC_ASGI1R)
4787 .allPrivileges().exceptUserMode().reads(0);
4788 InitReg(MISCREG_ICC_BPR0)
4789 .allPrivileges().exceptUserMode();
4790 InitReg(MISCREG_ICC_BPR1)
4791 .allPrivileges().exceptUserMode();
4792 InitReg(MISCREG_ICC_BPR1_NS)
4793 .allPrivileges().exceptUserMode();
4794 InitReg(MISCREG_ICC_BPR1_S)
4795 .allPrivileges().exceptUserMode();
4796 InitReg(MISCREG_ICC_CTLR)
4797 .allPrivileges().exceptUserMode();
4798 InitReg(MISCREG_ICC_CTLR_NS)
4799 .allPrivileges().exceptUserMode();
4800 InitReg(MISCREG_ICC_CTLR_S)
4801 .allPrivileges().exceptUserMode();
4802 InitReg(MISCREG_ICC_DIR)
4803 .allPrivileges().exceptUserMode().reads(0);
4804 InitReg(MISCREG_ICC_EOIR0)
4805 .allPrivileges().exceptUserMode().reads(0);
4806 InitReg(MISCREG_ICC_EOIR1)
4807 .allPrivileges().exceptUserMode().reads(0);
4808 InitReg(MISCREG_ICC_HPPIR0)
4809 .allPrivileges().exceptUserMode().writes(0);
4810 InitReg(MISCREG_ICC_HPPIR1)
4811 .allPrivileges().exceptUserMode().writes(0);
4812 InitReg(MISCREG_ICC_HSRE)
4813 .allPrivileges().exceptUserMode();
4814 InitReg(MISCREG_ICC_IAR0)
4815 .allPrivileges().exceptUserMode().writes(0);
4816 InitReg(MISCREG_ICC_IAR1)
4817 .allPrivileges().exceptUserMode().writes(0);
4818 InitReg(MISCREG_ICC_IGRPEN0)
4819 .allPrivileges().exceptUserMode();
4820 InitReg(MISCREG_ICC_IGRPEN1)
4821 .allPrivileges().exceptUserMode();
4822 InitReg(MISCREG_ICC_IGRPEN1_NS)
4823 .allPrivileges().exceptUserMode();
4824 InitReg(MISCREG_ICC_IGRPEN1_S)
4825 .allPrivileges().exceptUserMode();
4826 InitReg(MISCREG_ICC_MCTLR)
4827 .allPrivileges().exceptUserMode();
4828 InitReg(MISCREG_ICC_MGRPEN1)
4829 .allPrivileges().exceptUserMode();
4830 InitReg(MISCREG_ICC_MSRE)
4831 .allPrivileges().exceptUserMode();
4832 InitReg(MISCREG_ICC_PMR)
4833 .allPrivileges().exceptUserMode();
4834 InitReg(MISCREG_ICC_RPR)
4835 .allPrivileges().exceptUserMode().writes(0);
4836 InitReg(MISCREG_ICC_SGI0R)
4837 .allPrivileges().exceptUserMode().reads(0);
4838 InitReg(MISCREG_ICC_SGI1R)
4839 .allPrivileges().exceptUserMode().reads(0);
4840 InitReg(MISCREG_ICC_SRE)
4841 .allPrivileges().exceptUserMode();
4842 InitReg(MISCREG_ICC_SRE_NS)
4843 .allPrivileges().exceptUserMode();
4844 InitReg(MISCREG_ICC_SRE_S)
4845 .allPrivileges().exceptUserMode();
4846
4847 InitReg(MISCREG_ICH_AP0R0)
4848 .hyp().mon();
4849 InitReg(MISCREG_ICH_AP0R1)
4850 .hyp().mon();
4851 InitReg(MISCREG_ICH_AP0R2)
4852 .hyp().mon();
4853 InitReg(MISCREG_ICH_AP0R3)
4854 .hyp().mon();
4855 InitReg(MISCREG_ICH_AP1R0)
4856 .hyp().mon();
4857 InitReg(MISCREG_ICH_AP1R1)
4858 .hyp().mon();
4859 InitReg(MISCREG_ICH_AP1R2)
4860 .hyp().mon();
4861 InitReg(MISCREG_ICH_AP1R3)
4862 .hyp().mon();
4863 InitReg(MISCREG_ICH_HCR)
4864 .hyp().mon();
4865 InitReg(MISCREG_ICH_VTR)
4866 .hyp().mon().writes(0);
4867 InitReg(MISCREG_ICH_MISR)
4868 .hyp().mon().writes(0);
4869 InitReg(MISCREG_ICH_EISR)
4870 .hyp().mon().writes(0);
4871 InitReg(MISCREG_ICH_ELRSR)
4872 .hyp().mon().writes(0);
4873 InitReg(MISCREG_ICH_VMCR)
4874 .hyp().mon();
4875 InitReg(MISCREG_ICH_LR0)
4876 .hyp().mon();
4877 InitReg(MISCREG_ICH_LR1)
4878 .hyp().mon();
4879 InitReg(MISCREG_ICH_LR2)
4880 .hyp().mon();
4881 InitReg(MISCREG_ICH_LR3)
4882 .hyp().mon();
4883 InitReg(MISCREG_ICH_LR4)
4884 .hyp().mon();
4885 InitReg(MISCREG_ICH_LR5)
4886 .hyp().mon();
4887 InitReg(MISCREG_ICH_LR6)
4888 .hyp().mon();
4889 InitReg(MISCREG_ICH_LR7)
4890 .hyp().mon();
4891 InitReg(MISCREG_ICH_LR8)
4892 .hyp().mon();
4893 InitReg(MISCREG_ICH_LR9)
4894 .hyp().mon();
4895 InitReg(MISCREG_ICH_LR10)
4896 .hyp().mon();
4897 InitReg(MISCREG_ICH_LR11)
4898 .hyp().mon();
4899 InitReg(MISCREG_ICH_LR12)
4900 .hyp().mon();
4901 InitReg(MISCREG_ICH_LR13)
4902 .hyp().mon();
4903 InitReg(MISCREG_ICH_LR14)
4904 .hyp().mon();
4905 InitReg(MISCREG_ICH_LR15)
4906 .hyp().mon();
4907 InitReg(MISCREG_ICH_LRC0)
4908 .mapsTo(MISCREG_ICH_LR0)
4909 .hyp().mon();
4910 InitReg(MISCREG_ICH_LRC1)
4911 .mapsTo(MISCREG_ICH_LR1)
4912 .hyp().mon();
4913 InitReg(MISCREG_ICH_LRC2)
4914 .mapsTo(MISCREG_ICH_LR2)
4915 .hyp().mon();
4916 InitReg(MISCREG_ICH_LRC3)
4917 .mapsTo(MISCREG_ICH_LR3)
4918 .hyp().mon();
4919 InitReg(MISCREG_ICH_LRC4)
4920 .mapsTo(MISCREG_ICH_LR4)
4921 .hyp().mon();
4922 InitReg(MISCREG_ICH_LRC5)
4923 .mapsTo(MISCREG_ICH_LR5)
4924 .hyp().mon();
4925 InitReg(MISCREG_ICH_LRC6)
4926 .mapsTo(MISCREG_ICH_LR6)
4927 .hyp().mon();
4928 InitReg(MISCREG_ICH_LRC7)
4929 .mapsTo(MISCREG_ICH_LR7)
4930 .hyp().mon();
4931 InitReg(MISCREG_ICH_LRC8)
4932 .mapsTo(MISCREG_ICH_LR8)
4933 .hyp().mon();
4934 InitReg(MISCREG_ICH_LRC9)
4935 .mapsTo(MISCREG_ICH_LR9)
4936 .hyp().mon();
4937 InitReg(MISCREG_ICH_LRC10)
4938 .mapsTo(MISCREG_ICH_LR10)
4939 .hyp().mon();
4940 InitReg(MISCREG_ICH_LRC11)
4941 .mapsTo(MISCREG_ICH_LR11)
4942 .hyp().mon();
4943 InitReg(MISCREG_ICH_LRC12)
4944 .mapsTo(MISCREG_ICH_LR12)
4945 .hyp().mon();
4946 InitReg(MISCREG_ICH_LRC13)
4947 .mapsTo(MISCREG_ICH_LR13)
4948 .hyp().mon();
4949 InitReg(MISCREG_ICH_LRC14)
4950 .mapsTo(MISCREG_ICH_LR14)
4951 .hyp().mon();
4952 InitReg(MISCREG_ICH_LRC15)
4953 .mapsTo(MISCREG_ICH_LR15)
4954 .hyp().mon();
4955
4956 InitReg(MISCREG_CNTHV_CTL_EL2)
4957 .mon().hyp();
4958 InitReg(MISCREG_CNTHV_CVAL_EL2)
4959 .mon().hyp();
4960 InitReg(MISCREG_CNTHV_TVAL_EL2)
4961 .mon().hyp();
4962
4963 // SVE
4964 InitReg(MISCREG_ID_AA64ZFR0_EL1)
4965 .allPrivileges().exceptUserMode().writes(0);
4966 InitReg(MISCREG_ZCR_EL3)
4967 .mon();
4968 InitReg(MISCREG_ZCR_EL2)
4969 .hyp().mon();
4970 InitReg(MISCREG_ZCR_EL12)
4971 .unimplemented().warnNotFail();
4972 InitReg(MISCREG_ZCR_EL1)
4973 .allPrivileges().exceptUserMode();
4974
4975 // Dummy registers
4976 InitReg(MISCREG_NOP)
4977 .allPrivileges();
4978 InitReg(MISCREG_RAZ)
4979 .allPrivileges().exceptUserMode().writes(0);
4980 InitReg(MISCREG_CP14_UNIMPL)
4981 .unimplemented()
4982 .warnNotFail();
4983 InitReg(MISCREG_CP15_UNIMPL)
4984 .unimplemented()
4985 .warnNotFail();
4986 InitReg(MISCREG_UNKNOWN);
4987 InitReg(MISCREG_IMPDEF_UNIMPL)
4988 .unimplemented()
4989 .warnNotFail(impdefAsNop);
4990
4991 // RAS extension (unimplemented)
4992 InitReg(MISCREG_ERRIDR_EL1)
4993 .unimplemented()
4994 .warnNotFail();
4995 InitReg(MISCREG_ERRSELR_EL1)
4996 .unimplemented()
4997 .warnNotFail();
4998 InitReg(MISCREG_ERXFR_EL1)
4999 .unimplemented()
5000 .warnNotFail();
5001 InitReg(MISCREG_ERXCTLR_EL1)
5002 .unimplemented()
5003 .warnNotFail();
5004 InitReg(MISCREG_ERXSTATUS_EL1)
5005 .unimplemented()
5006 .warnNotFail();
5007 InitReg(MISCREG_ERXADDR_EL1)
5008 .unimplemented()
5009 .warnNotFail();
5010 InitReg(MISCREG_ERXMISC0_EL1)
5011 .unimplemented()
5012 .warnNotFail();
5013 InitReg(MISCREG_ERXMISC1_EL1)
5014 .unimplemented()
5015 .warnNotFail();
5016 InitReg(MISCREG_DISR_EL1)
5017 .unimplemented()
5018 .warnNotFail();
5019 InitReg(MISCREG_VSESR_EL2)
5020 .unimplemented()
5021 .warnNotFail();
5022 InitReg(MISCREG_VDISR_EL2)
5023 .unimplemented()
5024 .warnNotFail();
5025
5026 // Register mappings for some unimplemented registers:
5027 // ESR_EL1 -> DFSR
5028 // RMR_EL1 -> RMR
5029 // RMR_EL2 -> HRMR
5030 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
5031 // DBGDTRRX_EL0 -> DBGDTRRXint
5032 // DBGDTRTX_EL0 -> DBGDTRRXint
5033 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
5034
5035 completed = true;
5036}
5037
5038} // namespace ArmISA