Cross Reference: /gem5/src/arch/arm/miscregs.cc

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1/*
2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 * Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include <tuple>
45
46#include "arch/arm/isa.hh"
47#include "base/logging.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51namespace ArmISA
52{
53
54MiscRegIndex
55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56{
57 switch(crn) {
58 case 0:
59 switch (opc1) {
60 case 0:
61 switch (opc2) {
62 case 0:
63 switch (crm) {
64 case 0:
65 return MISCREG_DBGDIDR;
66 case 1:
67 return MISCREG_DBGDSCRint;
68 }
69 break;
70 }
71 break;
72 case 7:
73 switch (opc2) {
74 case 0:
75 switch (crm) {
76 case 0:
77 return MISCREG_JIDR;
78 }
79 break;
80 }
81 break;
82 }
83 break;
84 case 1:
85 switch (opc1) {
86 case 6:
87 switch (crm) {
88 case 0:
89 switch (opc2) {
90 case 0:
91 return MISCREG_TEEHBR;
92 }
93 break;
94 }
95 break;
96 case 7:
97 switch (crm) {
98 case 0:
99 switch (opc2) {
100 case 0:
101 return MISCREG_JOSCR;
102 }
103 break;
104 }
105 break;
106 }
107 break;
108 case 2:
109 switch (opc1) {
110 case 7:
111 switch (crm) {
112 case 0:
113 switch (opc2) {
114 case 0:
115 return MISCREG_JMCR;
116 }
117 break;
118 }
119 break;
120 }
121 break;
122 }
123 // If we get here then it must be a register that we haven't implemented
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn, opc1, crm, opc2);
126 return MISCREG_CP14_UNIMPL;
127}
128
129using namespace std;
130
131MiscRegIndex
132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133{
134 switch (crn) {
135 case 0:
136 switch (opc1) {
137 case 0:
138 switch (crm) {
139 case 0:
140 switch (opc2) {
141 case 1:
142 return MISCREG_CTR;
143 case 2:
144 return MISCREG_TCMTR;
145 case 3:
146 return MISCREG_TLBTR;
147 case 5:
148 return MISCREG_MPIDR;
149 case 6:
150 return MISCREG_REVIDR;
151 default:
152 return MISCREG_MIDR;
153 }
154 break;
155 case 1:
156 switch (opc2) {
157 case 0:
158 return MISCREG_ID_PFR0;
159 case 1:
160 return MISCREG_ID_PFR1;
161 case 2:
162 return MISCREG_ID_DFR0;
163 case 3:
164 return MISCREG_ID_AFR0;
165 case 4:
166 return MISCREG_ID_MMFR0;
167 case 5:
168 return MISCREG_ID_MMFR1;
169 case 6:
170 return MISCREG_ID_MMFR2;
171 case 7:
172 return MISCREG_ID_MMFR3;
173 }
174 break;
175 case 2:
176 switch (opc2) {
177 case 0:
178 return MISCREG_ID_ISAR0;
179 case 1:
180 return MISCREG_ID_ISAR1;
181 case 2:
182 return MISCREG_ID_ISAR2;
183 case 3:
184 return MISCREG_ID_ISAR3;
185 case 4:
186 return MISCREG_ID_ISAR4;
187 case 5:
188 return MISCREG_ID_ISAR5;
189 case 6:
190 case 7:
191 return MISCREG_RAZ; // read as zero
192 }
193 break;
194 default:
195 return MISCREG_RAZ; // read as zero
196 }
197 break;
198 case 1:
199 if (crm == 0) {
200 switch (opc2) {
201 case 0:
202 return MISCREG_CCSIDR;
203 case 1:
204 return MISCREG_CLIDR;
205 case 7:
206 return MISCREG_AIDR;
207 }
208 }
209 break;
210 case 2:
211 if (crm == 0 && opc2 == 0) {
212 return MISCREG_CSSELR;
213 }
214 break;
215 case 4:
216 if (crm == 0) {
217 if (opc2 == 0)
218 return MISCREG_VPIDR;
219 else if (opc2 == 5)
220 return MISCREG_VMPIDR;
221 }
222 break;
223 }
224 break;
225 case 1:
226 if (opc1 == 0) {
227 if (crm == 0) {
228 switch (opc2) {
229 case 0:
230 return MISCREG_SCTLR;
231 case 1:
232 return MISCREG_ACTLR;
233 case 0x2:
234 return MISCREG_CPACR;
235 }
236 } else if (crm == 1) {
237 switch (opc2) {
238 case 0:
239 return MISCREG_SCR;
240 case 1:
241 return MISCREG_SDER;
242 case 2:
243 return MISCREG_NSACR;
244 }
245 }
246 } else if (opc1 == 4) {
247 if (crm == 0) {
248 if (opc2 == 0)
249 return MISCREG_HSCTLR;
250 else if (opc2 == 1)
251 return MISCREG_HACTLR;
252 } else if (crm == 1) {
253 switch (opc2) {
254 case 0:
255 return MISCREG_HCR;
256 case 1:
257 return MISCREG_HDCR;
258 case 2:
259 return MISCREG_HCPTR;
260 case 3:
261 return MISCREG_HSTR;
262 case 7:
263 return MISCREG_HACR;
264 }
265 }
266 }
267 break;
268 case 2:
269 if (opc1 == 0 && crm == 0) {
270 switch (opc2) {
271 case 0:
272 return MISCREG_TTBR0;
273 case 1:
274 return MISCREG_TTBR1;
275 case 2:
276 return MISCREG_TTBCR;
277 }
278 } else if (opc1 == 4) {
279 if (crm == 0 && opc2 == 2)
280 return MISCREG_HTCR;
281 else if (crm == 1 && opc2 == 2)
282 return MISCREG_VTCR;
283 }
284 break;
285 case 3:
286 if (opc1 == 0 && crm == 0 && opc2 == 0) {
287 return MISCREG_DACR;
288 }
289 break;
290 case 5:
291 if (opc1 == 0) {
292 if (crm == 0) {
293 if (opc2 == 0) {
294 return MISCREG_DFSR;
295 } else if (opc2 == 1) {
296 return MISCREG_IFSR;
297 }
298 } else if (crm == 1) {
299 if (opc2 == 0) {
300 return MISCREG_ADFSR;
301 } else if (opc2 == 1) {
302 return MISCREG_AIFSR;
303 }
304 }
305 } else if (opc1 == 4) {
306 if (crm == 1) {
307 if (opc2 == 0)
308 return MISCREG_HADFSR;
309 else if (opc2 == 1)
310 return MISCREG_HAIFSR;
311 } else if (crm == 2 && opc2 == 0) {
312 return MISCREG_HSR;
313 }
314 }
315 break;
316 case 6:
317 if (opc1 == 0 && crm == 0) {
318 switch (opc2) {
319 case 0:
320 return MISCREG_DFAR;
321 case 2:
322 return MISCREG_IFAR;
323 }
324 } else if (opc1 == 4 && crm == 0) {
325 switch (opc2) {
326 case 0:
327 return MISCREG_HDFAR;
328 case 2:
329 return MISCREG_HIFAR;
330 case 4:
331 return MISCREG_HPFAR;
332 }
333 }
334 break;
335 case 7:
336 if (opc1 == 0) {
337 switch (crm) {
338 case 0:
339 if (opc2 == 4) {
340 return MISCREG_NOP;
341 }
342 break;
343 case 1:
344 switch (opc2) {
345 case 0:
346 return MISCREG_ICIALLUIS;
347 case 6:
348 return MISCREG_BPIALLIS;
349 }
350 break;
351 case 4:
352 if (opc2 == 0) {
353 return MISCREG_PAR;
354 }
355 break;
356 case 5:
357 switch (opc2) {
358 case 0:
359 return MISCREG_ICIALLU;
360 case 1:
361 return MISCREG_ICIMVAU;
362 case 4:
363 return MISCREG_CP15ISB;
364 case 6:
365 return MISCREG_BPIALL;
366 case 7:
367 return MISCREG_BPIMVA;
368 }
369 break;
370 case 6:
371 if (opc2 == 1) {
372 return MISCREG_DCIMVAC;
373 } else if (opc2 == 2) {
374 return MISCREG_DCISW;
375 }
376 break;
377 case 8:
378 switch (opc2) {
379 case 0:
380 return MISCREG_ATS1CPR;
381 case 1:
382 return MISCREG_ATS1CPW;
383 case 2:
384 return MISCREG_ATS1CUR;
385 case 3:
386 return MISCREG_ATS1CUW;
387 case 4:
388 return MISCREG_ATS12NSOPR;
389 case 5:
390 return MISCREG_ATS12NSOPW;
391 case 6:
392 return MISCREG_ATS12NSOUR;
393 case 7:
394 return MISCREG_ATS12NSOUW;
395 }
396 break;
397 case 10:
398 switch (opc2) {
399 case 1:
400 return MISCREG_DCCMVAC;
401 case 2:
402 return MISCREG_DCCSW;
403 case 4:
404 return MISCREG_CP15DSB;
405 case 5:
406 return MISCREG_CP15DMB;
407 }
408 break;
409 case 11:
410 if (opc2 == 1) {
411 return MISCREG_DCCMVAU;
412 }
413 break;
414 case 13:
415 if (opc2 == 1) {
416 return MISCREG_NOP;
417 }
418 break;
419 case 14:
420 if (opc2 == 1) {
421 return MISCREG_DCCIMVAC;
422 } else if (opc2 == 2) {
423 return MISCREG_DCCISW;
424 }
425 break;
426 }
427 } else if (opc1 == 4 && crm == 8) {
428 if (opc2 == 0)
429 return MISCREG_ATS1HR;
430 else if (opc2 == 1)
431 return MISCREG_ATS1HW;
432 }
433 break;
434 case 8:
435 if (opc1 == 0) {
436 switch (crm) {
437 case 3:
438 switch (opc2) {
439 case 0:
440 return MISCREG_TLBIALLIS;
441 case 1:
442 return MISCREG_TLBIMVAIS;
443 case 2:
444 return MISCREG_TLBIASIDIS;
445 case 3:
446 return MISCREG_TLBIMVAAIS;
447 case 5:
448 return MISCREG_TLBIMVALIS;
449 case 7:
450 return MISCREG_TLBIMVAALIS;
451 }
452 break;
453 case 5:
454 switch (opc2) {
455 case 0:
456 return MISCREG_ITLBIALL;
457 case 1:
458 return MISCREG_ITLBIMVA;
459 case 2:
460 return MISCREG_ITLBIASID;
461 }
462 break;
463 case 6:
464 switch (opc2) {
465 case 0:
466 return MISCREG_DTLBIALL;
467 case 1:
468 return MISCREG_DTLBIMVA;
469 case 2:
470 return MISCREG_DTLBIASID;
471 }
472 break;
473 case 7:
474 switch (opc2) {
475 case 0:
476 return MISCREG_TLBIALL;
477 case 1:
478 return MISCREG_TLBIMVA;
479 case 2:
480 return MISCREG_TLBIASID;
481 case 3:
482 return MISCREG_TLBIMVAA;
483 case 5:
484 return MISCREG_TLBIMVAL;
485 case 7:
486 return MISCREG_TLBIMVAAL;
487 }
488 break;
489 }
490 } else if (opc1 == 4) {

~~491~~ if (crm == 3) {

491 if (crm == 0) {

492 switch (opc2) {

493 case 1:
494 return MISCREG_TLBIIPAS2IS;
495 case 5:
496 return MISCREG_TLBIIPAS2LIS;
497 }
498 } else if (crm == 3) {
499 switch (opc2) {

500 case 0:
501 return MISCREG_TLBIALLHIS;
502 case 1:
503 return MISCREG_TLBIMVAHIS;
504 case 4:
505 return MISCREG_TLBIALLNSNHIS;
506 case 5:
507 return MISCREG_TLBIMVALHIS;
508 }

509 } else if (crm == 4) {
510 switch (opc2) {
511 case 1:
512 return MISCREG_TLBIIPAS2;
513 case 5:
514 return MISCREG_TLBIIPAS2L;
515 }

516 } else if (crm == 7) {
517 switch (opc2) {
518 case 0:
519 return MISCREG_TLBIALLH;
520 case 1:
521 return MISCREG_TLBIMVAH;
522 case 4:
523 return MISCREG_TLBIALLNSNH;
524 case 5:
525 return MISCREG_TLBIMVALH;
526 }
527 }
528 }
529 break;
530 case 9:
531 // Every cop register with CRn = 9 and CRm in
532 // {0-2}, {5-8} is implementation defined regardless
533 // of opc1 and opc2.
534 switch (crm) {
535 case 0:
536 case 1:
537 case 2:
538 case 5:
539 case 6:
540 case 7:
541 case 8:
542 return MISCREG_IMPDEF_UNIMPL;
543 }
544 if (opc1 == 0) {
545 switch (crm) {
546 case 12:
547 switch (opc2) {
548 case 0:
549 return MISCREG_PMCR;
550 case 1:
551 return MISCREG_PMCNTENSET;
552 case 2:
553 return MISCREG_PMCNTENCLR;
554 case 3:
555 return MISCREG_PMOVSR;
556 case 4:
557 return MISCREG_PMSWINC;
558 case 5:
559 return MISCREG_PMSELR;
560 case 6:
561 return MISCREG_PMCEID0;
562 case 7:
563 return MISCREG_PMCEID1;
564 }
565 break;
566 case 13:
567 switch (opc2) {
568 case 0:
569 return MISCREG_PMCCNTR;
570 case 1:
571 // Selector is PMSELR.SEL
572 return MISCREG_PMXEVTYPER_PMCCFILTR;
573 case 2:
574 return MISCREG_PMXEVCNTR;
575 }
576 break;
577 case 14:
578 switch (opc2) {
579 case 0:
580 return MISCREG_PMUSERENR;
581 case 1:
582 return MISCREG_PMINTENSET;
583 case 2:
584 return MISCREG_PMINTENCLR;
585 case 3:
586 return MISCREG_PMOVSSET;
587 }
588 break;
589 }
590 } else if (opc1 == 1) {
591 switch (crm) {
592 case 0:
593 switch (opc2) {
594 case 2: // L2CTLR, L2 Control Register
595 return MISCREG_L2CTLR;
596 case 3:
597 return MISCREG_L2ECTLR;
598 }
599 break;
600 break;
601 }
602 }
603 break;
604 case 10:
605 if (opc1 == 0) {
606 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
607 if (crm < 2) {
608 return MISCREG_IMPDEF_UNIMPL;
609 } else if (crm == 2) { // TEX Remap Registers
610 if (opc2 == 0) {
611 // Selector is TTBCR.EAE
612 return MISCREG_PRRR_MAIR0;
613 } else if (opc2 == 1) {
614 // Selector is TTBCR.EAE
615 return MISCREG_NMRR_MAIR1;
616 }
617 } else if (crm == 3) {
618 if (opc2 == 0) {
619 return MISCREG_AMAIR0;
620 } else if (opc2 == 1) {
621 return MISCREG_AMAIR1;
622 }
623 }
624 } else if (opc1 == 4) {
625 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
626 if (crm == 2) {
627 if (opc2 == 0)
628 return MISCREG_HMAIR0;
629 else if (opc2 == 1)
630 return MISCREG_HMAIR1;
631 } else if (crm == 3) {
632 if (opc2 == 0)
633 return MISCREG_HAMAIR0;
634 else if (opc2 == 1)
635 return MISCREG_HAMAIR1;
636 }
637 }
638 break;
639 case 11:
640 if (opc1 <=7) {
641 switch (crm) {
642 case 0:
643 case 1:
644 case 2:
645 case 3:
646 case 4:
647 case 5:
648 case 6:
649 case 7:
650 case 8:
651 case 15:
652 // Reserved for DMA operations for TCM access
653 return MISCREG_IMPDEF_UNIMPL;
654 default:
655 break;
656 }
657 }
658 break;
659 case 12:
660 if (opc1 == 0) {
661 if (crm == 0) {
662 if (opc2 == 0) {
663 return MISCREG_VBAR;
664 } else if (opc2 == 1) {
665 return MISCREG_MVBAR;
666 }
667 } else if (crm == 1) {
668 if (opc2 == 0) {
669 return MISCREG_ISR;
670 }
671 }
672 } else if (opc1 == 4) {
673 if (crm == 0 && opc2 == 0)
674 return MISCREG_HVBAR;
675 }
676 break;
677 case 13:
678 if (opc1 == 0) {
679 if (crm == 0) {
680 switch (opc2) {
681 case 0:
682 return MISCREG_FCSEIDR;
683 case 1:
684 return MISCREG_CONTEXTIDR;
685 case 2:
686 return MISCREG_TPIDRURW;
687 case 3:
688 return MISCREG_TPIDRURO;
689 case 4:
690 return MISCREG_TPIDRPRW;
691 }
692 }
693 } else if (opc1 == 4) {
694 if (crm == 0 && opc2 == 2)
695 return MISCREG_HTPIDR;
696 }
697 break;
698 case 14:
699 if (opc1 == 0) {
700 switch (crm) {
701 case 0:
702 if (opc2 == 0)
703 return MISCREG_CNTFRQ;
704 break;
705 case 1:
706 if (opc2 == 0)
707 return MISCREG_CNTKCTL;
708 break;
709 case 2:
710 if (opc2 == 0)
711 return MISCREG_CNTP_TVAL;
712 else if (opc2 == 1)
713 return MISCREG_CNTP_CTL;
714 break;
715 case 3:
716 if (opc2 == 0)
717 return MISCREG_CNTV_TVAL;
718 else if (opc2 == 1)
719 return MISCREG_CNTV_CTL;
720 break;
721 }
722 } else if (opc1 == 4) {
723 if (crm == 1 && opc2 == 0) {
724 return MISCREG_CNTHCTL;
725 } else if (crm == 2) {
726 if (opc2 == 0)
727 return MISCREG_CNTHP_TVAL;
728 else if (opc2 == 1)
729 return MISCREG_CNTHP_CTL;
730 }
731 }
732 break;
733 case 15:
734 // Implementation defined
735 return MISCREG_IMPDEF_UNIMPL;
736 }
737 // Unrecognized register
738 return MISCREG_CP15_UNIMPL;
739}
740
741MiscRegIndex
742decodeCP15Reg64(unsigned crm, unsigned opc1)
743{
744 switch (crm) {
745 case 2:
746 switch (opc1) {
747 case 0:
748 return MISCREG_TTBR0;
749 case 1:
750 return MISCREG_TTBR1;
751 case 4:
752 return MISCREG_HTTBR;
753 case 6:
754 return MISCREG_VTTBR;
755 }
756 break;
757 case 7:
758 if (opc1 == 0)
759 return MISCREG_PAR;
760 break;
761 case 14:
762 switch (opc1) {
763 case 0:
764 return MISCREG_CNTPCT;
765 case 1:
766 return MISCREG_CNTVCT;
767 case 2:
768 return MISCREG_CNTP_CVAL;
769 case 3:
770 return MISCREG_CNTV_CVAL;
771 case 4:
772 return MISCREG_CNTVOFF;
773 case 6:
774 return MISCREG_CNTHP_CVAL;
775 }
776 break;
777 case 15:
778 if (opc1 == 0)
779 return MISCREG_CPUMERRSR;
780 else if (opc1 == 1)
781 return MISCREG_L2MERRSR;
782 break;
783 }
784 // Unrecognized register
785 return MISCREG_CP15_UNIMPL;
786}
787
788std::tuple<bool, bool>
789canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
790{
791 bool secure = !scr.ns;
792 bool canRead = false;
793 bool undefined = false;
794
795 switch (cpsr.mode) {
796 case MODE_USER:
797 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
798 miscRegInfo[reg][MISCREG_USR_NS_RD];
799 break;
800 case MODE_FIQ:
801 case MODE_IRQ:
802 case MODE_SVC:
803 case MODE_ABORT:
804 case MODE_UNDEFINED:
805 case MODE_SYSTEM:
806 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
807 miscRegInfo[reg][MISCREG_PRI_NS_RD];
808 break;
809 case MODE_MON:
810 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
811 miscRegInfo[reg][MISCREG_MON_NS1_RD];
812 break;
813 case MODE_HYP:
814 canRead = miscRegInfo[reg][MISCREG_HYP_RD];
815 break;
816 default:
817 undefined = true;
818 }
819 // can't do permissions checkes on the root of a banked pair of regs
820 assert(!miscRegInfo[reg][MISCREG_BANKED]);
821 return std::make_tuple(canRead, undefined);
822}
823
824std::tuple<bool, bool>
825canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
826{
827 bool secure = !scr.ns;
828 bool canWrite = false;
829 bool undefined = false;
830
831 switch (cpsr.mode) {
832 case MODE_USER:
833 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
834 miscRegInfo[reg][MISCREG_USR_NS_WR];
835 break;
836 case MODE_FIQ:
837 case MODE_IRQ:
838 case MODE_SVC:
839 case MODE_ABORT:
840 case MODE_UNDEFINED:
841 case MODE_SYSTEM:
842 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
843 miscRegInfo[reg][MISCREG_PRI_NS_WR];
844 break;
845 case MODE_MON:
846 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
847 miscRegInfo[reg][MISCREG_MON_NS1_WR];
848 break;
849 case MODE_HYP:
850 canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
851 break;
852 default:
853 undefined = true;
854 }
855 // can't do permissions checkes on the root of a banked pair of regs
856 assert(!miscRegInfo[reg][MISCREG_BANKED]);
857 return std::make_tuple(canWrite, undefined);
858}
859
860int
861snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
862{
863 SCR scr = tc->readMiscReg(MISCREG_SCR);
864 return snsBankedIndex(reg, tc, scr.ns);
865}
866
867int
868snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
869{
870 int reg_as_int = static_cast<int>(reg);
871 if (miscRegInfo[reg][MISCREG_BANKED]) {
872 reg_as_int += (ArmSystem::haveSecurity(tc) &&
873 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
874 }
875 return reg_as_int;
876}
877
878
879/**
880 * If the reg is a child reg of a banked set, then the parent is the last
881 * banked one in the list. This is messy, and the wish is to eventually have
882 * the bitmap replaced with a better data structure. the preUnflatten function
883 * initializes a lookup table to speed up the search for these banked
884 * registers.
885 */
886
887int unflattenResultMiscReg[NUM_MISCREGS];
888
889void
890preUnflattenMiscReg()
891{
892 int reg = -1;
893 for (int i = 0 ; i < NUM_MISCREGS; i++){
894 if (miscRegInfo[i][MISCREG_BANKED])
895 reg = i;
896 if (miscRegInfo[i][MISCREG_BANKED_CHILD])
897 unflattenResultMiscReg[i] = reg;
898 else
899 unflattenResultMiscReg[i] = i;
900 // if this assert fails, no parent was found, and something is broken
901 assert(unflattenResultMiscReg[i] > -1);
902 }
903}
904
905int
906unflattenMiscReg(int reg)
907{
908 return unflattenResultMiscReg[reg];
909}
910
911bool
912canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
913{
914 // Check for SP_EL0 access while SPSEL == 0
915 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
916 return false;
917
918 // Check for RVBAR access
919 if (reg == MISCREG_RVBAR_EL1) {
920 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
921 if (highest_el == EL2 || highest_el == EL3)
922 return false;
923 }
924 if (reg == MISCREG_RVBAR_EL2) {
925 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
926 if (highest_el == EL3)
927 return false;
928 }
929
930 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
931
932 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
933 case EL0:
934 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
935 miscRegInfo[reg][MISCREG_USR_NS_RD];
936 case EL1:
937 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
938 miscRegInfo[reg][MISCREG_PRI_NS_RD];
939 case EL2:
940 return miscRegInfo[reg][MISCREG_HYP_RD];
941 case EL3:
942 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
943 miscRegInfo[reg][MISCREG_MON_NS1_RD];
944 default:
945 panic("Invalid exception level");
946 }
947}
948
949bool
950canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
951{
952 // Check for SP_EL0 access while SPSEL == 0
953 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
954 return false;
955 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
956 if (reg == MISCREG_DAIF) {
957 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
958 if (el == EL0 && !sctlr.uma)
959 return false;
960 }
961 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
962 // In syscall-emulation mode, this test is skipped and DCZVA is always
963 // allowed at EL0
964 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
965 if (el == EL0 && !sctlr.dze)
966 return false;
967 }
968 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
969 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
970 if (el == EL0 && !sctlr.uci)
971 return false;
972 }
973
974 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
975
976 switch (el) {
977 case EL0:
978 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
979 miscRegInfo[reg][MISCREG_USR_NS_WR];
980 case EL1:
981 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
982 miscRegInfo[reg][MISCREG_PRI_NS_WR];
983 case EL2:
984 return miscRegInfo[reg][MISCREG_HYP_WR];
985 case EL3:
986 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
987 miscRegInfo[reg][MISCREG_MON_NS1_WR];
988 default:
989 panic("Invalid exception level");
990 }
991}
992
993MiscRegIndex
994decodeAArch64SysReg(unsigned op0, unsigned op1,
995 unsigned crn, unsigned crm,
996 unsigned op2)
997{
998 switch (op0) {
999 case 1:
1000 switch (crn) {
1001 case 7:
1002 switch (op1) {
1003 case 0:
1004 switch (crm) {
1005 case 1:
1006 switch (op2) {
1007 case 0:
1008 return MISCREG_IC_IALLUIS;
1009 }
1010 break;
1011 case 5:
1012 switch (op2) {
1013 case 0:
1014 return MISCREG_IC_IALLU;
1015 }
1016 break;
1017 case 6:
1018 switch (op2) {
1019 case 1:
1020 return MISCREG_DC_IVAC_Xt;
1021 case 2:
1022 return MISCREG_DC_ISW_Xt;
1023 }
1024 break;
1025 case 8:
1026 switch (op2) {
1027 case 0:
1028 return MISCREG_AT_S1E1R_Xt;
1029 case 1:
1030 return MISCREG_AT_S1E1W_Xt;
1031 case 2:
1032 return MISCREG_AT_S1E0R_Xt;
1033 case 3:
1034 return MISCREG_AT_S1E0W_Xt;
1035 }
1036 break;
1037 case 10:
1038 switch (op2) {
1039 case 2:
1040 return MISCREG_DC_CSW_Xt;
1041 }
1042 break;
1043 case 14:
1044 switch (op2) {
1045 case 2:
1046 return MISCREG_DC_CISW_Xt;
1047 }
1048 break;
1049 }
1050 break;
1051 case 3:
1052 switch (crm) {
1053 case 4:
1054 switch (op2) {
1055 case 1:
1056 return MISCREG_DC_ZVA_Xt;
1057 }
1058 break;
1059 case 5:
1060 switch (op2) {
1061 case 1:
1062 return MISCREG_IC_IVAU_Xt;
1063 }
1064 break;
1065 case 10:
1066 switch (op2) {
1067 case 1:
1068 return MISCREG_DC_CVAC_Xt;
1069 }
1070 break;
1071 case 11:
1072 switch (op2) {
1073 case 1:
1074 return MISCREG_DC_CVAU_Xt;
1075 }
1076 break;
1077 case 14:
1078 switch (op2) {
1079 case 1:
1080 return MISCREG_DC_CIVAC_Xt;
1081 }
1082 break;
1083 }
1084 break;
1085 case 4:
1086 switch (crm) {
1087 case 8:
1088 switch (op2) {
1089 case 0:
1090 return MISCREG_AT_S1E2R_Xt;
1091 case 1:
1092 return MISCREG_AT_S1E2W_Xt;
1093 case 4:
1094 return MISCREG_AT_S12E1R_Xt;
1095 case 5:
1096 return MISCREG_AT_S12E1W_Xt;
1097 case 6:
1098 return MISCREG_AT_S12E0R_Xt;
1099 case 7:
1100 return MISCREG_AT_S12E0W_Xt;
1101 }
1102 break;
1103 }
1104 break;
1105 case 6:
1106 switch (crm) {
1107 case 8:
1108 switch (op2) {
1109 case 0:
1110 return MISCREG_AT_S1E3R_Xt;
1111 case 1:
1112 return MISCREG_AT_S1E3W_Xt;
1113 }
1114 break;
1115 }
1116 break;
1117 }
1118 break;
1119 case 8:
1120 switch (op1) {
1121 case 0:
1122 switch (crm) {
1123 case 3:
1124 switch (op2) {
1125 case 0:
1126 return MISCREG_TLBI_VMALLE1IS;
1127 case 1:
1128 return MISCREG_TLBI_VAE1IS_Xt;
1129 case 2:
1130 return MISCREG_TLBI_ASIDE1IS_Xt;
1131 case 3:
1132 return MISCREG_TLBI_VAAE1IS_Xt;
1133 case 5:
1134 return MISCREG_TLBI_VALE1IS_Xt;
1135 case 7:
1136 return MISCREG_TLBI_VAALE1IS_Xt;
1137 }
1138 break;
1139 case 7:
1140 switch (op2) {
1141 case 0:
1142 return MISCREG_TLBI_VMALLE1;
1143 case 1:
1144 return MISCREG_TLBI_VAE1_Xt;
1145 case 2:
1146 return MISCREG_TLBI_ASIDE1_Xt;
1147 case 3:
1148 return MISCREG_TLBI_VAAE1_Xt;
1149 case 5:
1150 return MISCREG_TLBI_VALE1_Xt;
1151 case 7:
1152 return MISCREG_TLBI_VAALE1_Xt;
1153 }
1154 break;
1155 }
1156 break;
1157 case 4:
1158 switch (crm) {
1159 case 0:
1160 switch (op2) {
1161 case 1:
1162 return MISCREG_TLBI_IPAS2E1IS_Xt;
1163 case 5:
1164 return MISCREG_TLBI_IPAS2LE1IS_Xt;
1165 }
1166 break;
1167 case 3:
1168 switch (op2) {
1169 case 0:
1170 return MISCREG_TLBI_ALLE2IS;
1171 case 1:
1172 return MISCREG_TLBI_VAE2IS_Xt;
1173 case 4:
1174 return MISCREG_TLBI_ALLE1IS;
1175 case 5:
1176 return MISCREG_TLBI_VALE2IS_Xt;
1177 case 6:
1178 return MISCREG_TLBI_VMALLS12E1IS;
1179 }
1180 break;
1181 case 4:
1182 switch (op2) {
1183 case 1:
1184 return MISCREG_TLBI_IPAS2E1_Xt;
1185 case 5:
1186 return MISCREG_TLBI_IPAS2LE1_Xt;
1187 }
1188 break;
1189 case 7:
1190 switch (op2) {
1191 case 0:
1192 return MISCREG_TLBI_ALLE2;
1193 case 1:
1194 return MISCREG_TLBI_VAE2_Xt;
1195 case 4:
1196 return MISCREG_TLBI_ALLE1;
1197 case 5:
1198 return MISCREG_TLBI_VALE2_Xt;
1199 case 6:
1200 return MISCREG_TLBI_VMALLS12E1;
1201 }
1202 break;
1203 }
1204 break;
1205 case 6:
1206 switch (crm) {
1207 case 3:
1208 switch (op2) {
1209 case 0:
1210 return MISCREG_TLBI_ALLE3IS;
1211 case 1:
1212 return MISCREG_TLBI_VAE3IS_Xt;
1213 case 5:
1214 return MISCREG_TLBI_VALE3IS_Xt;
1215 }
1216 break;
1217 case 7:
1218 switch (op2) {
1219 case 0:
1220 return MISCREG_TLBI_ALLE3;
1221 case 1:
1222 return MISCREG_TLBI_VAE3_Xt;
1223 case 5:
1224 return MISCREG_TLBI_VALE3_Xt;
1225 }
1226 break;
1227 }
1228 break;
1229 }
1230 break;
1231 }
1232 break;
1233 case 2:
1234 switch (crn) {
1235 case 0:
1236 switch (op1) {
1237 case 0:
1238 switch (crm) {
1239 case 0:
1240 switch (op2) {
1241 case 2:
1242 return MISCREG_OSDTRRX_EL1;
1243 case 4:
1244 return MISCREG_DBGBVR0_EL1;
1245 case 5:
1246 return MISCREG_DBGBCR0_EL1;
1247 case 6:
1248 return MISCREG_DBGWVR0_EL1;
1249 case 7:
1250 return MISCREG_DBGWCR0_EL1;
1251 }
1252 break;
1253 case 1:
1254 switch (op2) {
1255 case 4:
1256 return MISCREG_DBGBVR1_EL1;
1257 case 5:
1258 return MISCREG_DBGBCR1_EL1;
1259 case 6:
1260 return MISCREG_DBGWVR1_EL1;
1261 case 7:
1262 return MISCREG_DBGWCR1_EL1;
1263 }
1264 break;
1265 case 2:
1266 switch (op2) {
1267 case 0:
1268 return MISCREG_MDCCINT_EL1;
1269 case 2:
1270 return MISCREG_MDSCR_EL1;
1271 case 4:
1272 return MISCREG_DBGBVR2_EL1;
1273 case 5:
1274 return MISCREG_DBGBCR2_EL1;
1275 case 6:
1276 return MISCREG_DBGWVR2_EL1;
1277 case 7:
1278 return MISCREG_DBGWCR2_EL1;
1279 }
1280 break;
1281 case 3:
1282 switch (op2) {
1283 case 2:
1284 return MISCREG_OSDTRTX_EL1;
1285 case 4:
1286 return MISCREG_DBGBVR3_EL1;
1287 case 5:
1288 return MISCREG_DBGBCR3_EL1;
1289 case 6:
1290 return MISCREG_DBGWVR3_EL1;
1291 case 7:
1292 return MISCREG_DBGWCR3_EL1;
1293 }
1294 break;
1295 case 4:
1296 switch (op2) {
1297 case 4:
1298 return MISCREG_DBGBVR4_EL1;
1299 case 5:
1300 return MISCREG_DBGBCR4_EL1;
1301 }
1302 break;
1303 case 5:
1304 switch (op2) {
1305 case 4:
1306 return MISCREG_DBGBVR5_EL1;
1307 case 5:
1308 return MISCREG_DBGBCR5_EL1;
1309 }
1310 break;
1311 case 6:
1312 switch (op2) {
1313 case 2:
1314 return MISCREG_OSECCR_EL1;
1315 }
1316 break;
1317 }
1318 break;
1319 case 2:
1320 switch (crm) {
1321 case 0:
1322 switch (op2) {
1323 case 0:
1324 return MISCREG_TEECR32_EL1;
1325 }
1326 break;
1327 }
1328 break;
1329 case 3:
1330 switch (crm) {
1331 case 1:
1332 switch (op2) {
1333 case 0:
1334 return MISCREG_MDCCSR_EL0;
1335 }
1336 break;
1337 case 4:
1338 switch (op2) {
1339 case 0:
1340 return MISCREG_MDDTR_EL0;
1341 }
1342 break;
1343 case 5:
1344 switch (op2) {
1345 case 0:
1346 return MISCREG_MDDTRRX_EL0;
1347 }
1348 break;
1349 }
1350 break;
1351 case 4:
1352 switch (crm) {
1353 case 7:
1354 switch (op2) {
1355 case 0:
1356 return MISCREG_DBGVCR32_EL2;
1357 }
1358 break;
1359 }
1360 break;
1361 }
1362 break;
1363 case 1:
1364 switch (op1) {
1365 case 0:
1366 switch (crm) {
1367 case 0:
1368 switch (op2) {
1369 case 0:
1370 return MISCREG_MDRAR_EL1;
1371 case 4:
1372 return MISCREG_OSLAR_EL1;
1373 }
1374 break;
1375 case 1:
1376 switch (op2) {
1377 case 4:
1378 return MISCREG_OSLSR_EL1;
1379 }
1380 break;
1381 case 3:
1382 switch (op2) {
1383 case 4:
1384 return MISCREG_OSDLR_EL1;
1385 }
1386 break;
1387 case 4:
1388 switch (op2) {
1389 case 4:
1390 return MISCREG_DBGPRCR_EL1;
1391 }
1392 break;
1393 }
1394 break;
1395 case 2:
1396 switch (crm) {
1397 case 0:
1398 switch (op2) {
1399 case 0:
1400 return MISCREG_TEEHBR32_EL1;
1401 }
1402 break;
1403 }
1404 break;
1405 }
1406 break;
1407 case 7:
1408 switch (op1) {
1409 case 0:
1410 switch (crm) {
1411 case 8:
1412 switch (op2) {
1413 case 6:
1414 return MISCREG_DBGCLAIMSET_EL1;
1415 }
1416 break;
1417 case 9:
1418 switch (op2) {
1419 case 6:
1420 return MISCREG_DBGCLAIMCLR_EL1;
1421 }
1422 break;
1423 case 14:
1424 switch (op2) {
1425 case 6:
1426 return MISCREG_DBGAUTHSTATUS_EL1;
1427 }
1428 break;
1429 }
1430 break;
1431 }
1432 break;
1433 }
1434 break;
1435 case 3:
1436 switch (crn) {
1437 case 0:
1438 switch (op1) {
1439 case 0:
1440 switch (crm) {
1441 case 0:
1442 switch (op2) {
1443 case 0:
1444 return MISCREG_MIDR_EL1;
1445 case 5:
1446 return MISCREG_MPIDR_EL1;
1447 case 6:
1448 return MISCREG_REVIDR_EL1;
1449 }
1450 break;
1451 case 1:
1452 switch (op2) {
1453 case 0:
1454 return MISCREG_ID_PFR0_EL1;
1455 case 1:
1456 return MISCREG_ID_PFR1_EL1;
1457 case 2:
1458 return MISCREG_ID_DFR0_EL1;
1459 case 3:
1460 return MISCREG_ID_AFR0_EL1;
1461 case 4:
1462 return MISCREG_ID_MMFR0_EL1;
1463 case 5:
1464 return MISCREG_ID_MMFR1_EL1;
1465 case 6:
1466 return MISCREG_ID_MMFR2_EL1;
1467 case 7:
1468 return MISCREG_ID_MMFR3_EL1;
1469 }
1470 break;
1471 case 2:
1472 switch (op2) {
1473 case 0:
1474 return MISCREG_ID_ISAR0_EL1;
1475 case 1:
1476 return MISCREG_ID_ISAR1_EL1;
1477 case 2:
1478 return MISCREG_ID_ISAR2_EL1;
1479 case 3:
1480 return MISCREG_ID_ISAR3_EL1;
1481 case 4:
1482 return MISCREG_ID_ISAR4_EL1;
1483 case 5:
1484 return MISCREG_ID_ISAR5_EL1;
1485 }
1486 break;
1487 case 3:
1488 switch (op2) {
1489 case 0:
1490 return MISCREG_MVFR0_EL1;
1491 case 1:
1492 return MISCREG_MVFR1_EL1;
1493 case 2:
1494 return MISCREG_MVFR2_EL1;
1495 case 3 ... 7:
1496 return MISCREG_RAZ;
1497 }
1498 break;
1499 case 4:
1500 switch (op2) {
1501 case 0:
1502 return MISCREG_ID_AA64PFR0_EL1;
1503 case 1:
1504 return MISCREG_ID_AA64PFR1_EL1;
1505 case 2 ... 7:
1506 return MISCREG_RAZ;
1507 }
1508 break;
1509 case 5:
1510 switch (op2) {
1511 case 0:
1512 return MISCREG_ID_AA64DFR0_EL1;
1513 case 1:
1514 return MISCREG_ID_AA64DFR1_EL1;
1515 case 4:
1516 return MISCREG_ID_AA64AFR0_EL1;
1517 case 5:
1518 return MISCREG_ID_AA64AFR1_EL1;
1519 case 2:
1520 case 3:
1521 case 6:
1522 case 7:
1523 return MISCREG_RAZ;
1524 }
1525 break;
1526 case 6:
1527 switch (op2) {
1528 case 0:
1529 return MISCREG_ID_AA64ISAR0_EL1;
1530 case 1:
1531 return MISCREG_ID_AA64ISAR1_EL1;
1532 case 2 ... 7:
1533 return MISCREG_RAZ;
1534 }
1535 break;
1536 case 7:
1537 switch (op2) {
1538 case 0:
1539 return MISCREG_ID_AA64MMFR0_EL1;
1540 case 1:
1541 return MISCREG_ID_AA64MMFR1_EL1;
1542 case 2 ... 7:
1543 return MISCREG_RAZ;
1544 }
1545 break;
1546 }
1547 break;
1548 case 1:
1549 switch (crm) {
1550 case 0:
1551 switch (op2) {
1552 case 0:
1553 return MISCREG_CCSIDR_EL1;
1554 case 1:
1555 return MISCREG_CLIDR_EL1;
1556 case 7:
1557 return MISCREG_AIDR_EL1;
1558 }
1559 break;
1560 }
1561 break;
1562 case 2:
1563 switch (crm) {
1564 case 0:
1565 switch (op2) {
1566 case 0:
1567 return MISCREG_CSSELR_EL1;
1568 }
1569 break;
1570 }
1571 break;
1572 case 3:
1573 switch (crm) {
1574 case 0:
1575 switch (op2) {
1576 case 1:
1577 return MISCREG_CTR_EL0;
1578 case 7:
1579 return MISCREG_DCZID_EL0;
1580 }
1581 break;
1582 }
1583 break;
1584 case 4:
1585 switch (crm) {
1586 case 0:
1587 switch (op2) {
1588 case 0:
1589 return MISCREG_VPIDR_EL2;
1590 case 5:
1591 return MISCREG_VMPIDR_EL2;
1592 }
1593 break;
1594 }
1595 break;
1596 }
1597 break;
1598 case 1:
1599 switch (op1) {
1600 case 0:
1601 switch (crm) {
1602 case 0:
1603 switch (op2) {
1604 case 0:
1605 return MISCREG_SCTLR_EL1;
1606 case 1:
1607 return MISCREG_ACTLR_EL1;
1608 case 2:
1609 return MISCREG_CPACR_EL1;
1610 }
1611 break;
1612 }
1613 break;
1614 case 4:
1615 switch (crm) {
1616 case 0:
1617 switch (op2) {
1618 case 0:
1619 return MISCREG_SCTLR_EL2;
1620 case 1:
1621 return MISCREG_ACTLR_EL2;
1622 }
1623 break;
1624 case 1:
1625 switch (op2) {
1626 case 0:
1627 return MISCREG_HCR_EL2;
1628 case 1:
1629 return MISCREG_MDCR_EL2;
1630 case 2:
1631 return MISCREG_CPTR_EL2;
1632 case 3:
1633 return MISCREG_HSTR_EL2;
1634 case 7:
1635 return MISCREG_HACR_EL2;
1636 }
1637 break;
1638 }
1639 break;
1640 case 6:
1641 switch (crm) {
1642 case 0:
1643 switch (op2) {
1644 case 0:
1645 return MISCREG_SCTLR_EL3;
1646 case 1:
1647 return MISCREG_ACTLR_EL3;
1648 }
1649 break;
1650 case 1:
1651 switch (op2) {
1652 case 0:
1653 return MISCREG_SCR_EL3;
1654 case 1:
1655 return MISCREG_SDER32_EL3;
1656 case 2:
1657 return MISCREG_CPTR_EL3;
1658 }
1659 break;
1660 case 3:
1661 switch (op2) {
1662 case 1:
1663 return MISCREG_MDCR_EL3;
1664 }
1665 break;
1666 }
1667 break;
1668 }
1669 break;
1670 case 2:
1671 switch (op1) {
1672 case 0:
1673 switch (crm) {
1674 case 0:
1675 switch (op2) {
1676 case 0:
1677 return MISCREG_TTBR0_EL1;
1678 case 1:
1679 return MISCREG_TTBR1_EL1;
1680 case 2:
1681 return MISCREG_TCR_EL1;
1682 }
1683 break;
1684 }
1685 break;
1686 case 4:
1687 switch (crm) {
1688 case 0:
1689 switch (op2) {
1690 case 0:
1691 return MISCREG_TTBR0_EL2;
1692 case 2:
1693 return MISCREG_TCR_EL2;
1694 }
1695 break;
1696 case 1:
1697 switch (op2) {
1698 case 0:
1699 return MISCREG_VTTBR_EL2;
1700 case 2:
1701 return MISCREG_VTCR_EL2;
1702 }
1703 break;
1704 }
1705 break;
1706 case 6:
1707 switch (crm) {
1708 case 0:
1709 switch (op2) {
1710 case 0:
1711 return MISCREG_TTBR0_EL3;
1712 case 2:
1713 return MISCREG_TCR_EL3;
1714 }
1715 break;
1716 }
1717 break;
1718 }
1719 break;
1720 case 3:
1721 switch (op1) {
1722 case 4:
1723 switch (crm) {
1724 case 0:
1725 switch (op2) {
1726 case 0:
1727 return MISCREG_DACR32_EL2;
1728 }
1729 break;
1730 }
1731 break;
1732 }
1733 break;
1734 case 4:
1735 switch (op1) {
1736 case 0:
1737 switch (crm) {
1738 case 0:
1739 switch (op2) {
1740 case 0:
1741 return MISCREG_SPSR_EL1;
1742 case 1:
1743 return MISCREG_ELR_EL1;
1744 }
1745 break;
1746 case 1:
1747 switch (op2) {
1748 case 0:
1749 return MISCREG_SP_EL0;
1750 }
1751 break;
1752 case 2:
1753 switch (op2) {
1754 case 0:
1755 return MISCREG_SPSEL;
1756 case 2:
1757 return MISCREG_CURRENTEL;
1758 }
1759 break;
1760 }
1761 break;
1762 case 3:
1763 switch (crm) {
1764 case 2:
1765 switch (op2) {
1766 case 0:
1767 return MISCREG_NZCV;
1768 case 1:
1769 return MISCREG_DAIF;
1770 }
1771 break;
1772 case 4:
1773 switch (op2) {
1774 case 0:
1775 return MISCREG_FPCR;
1776 case 1:
1777 return MISCREG_FPSR;
1778 }
1779 break;
1780 case 5:
1781 switch (op2) {
1782 case 0:
1783 return MISCREG_DSPSR_EL0;
1784 case 1:
1785 return MISCREG_DLR_EL0;
1786 }
1787 break;
1788 }
1789 break;
1790 case 4:
1791 switch (crm) {
1792 case 0:
1793 switch (op2) {
1794 case 0:
1795 return MISCREG_SPSR_EL2;
1796 case 1:
1797 return MISCREG_ELR_EL2;
1798 }
1799 break;
1800 case 1:
1801 switch (op2) {
1802 case 0:
1803 return MISCREG_SP_EL1;
1804 }
1805 break;
1806 case 3:
1807 switch (op2) {
1808 case 0:
1809 return MISCREG_SPSR_IRQ_AA64;
1810 case 1:
1811 return MISCREG_SPSR_ABT_AA64;
1812 case 2:
1813 return MISCREG_SPSR_UND_AA64;
1814 case 3:
1815 return MISCREG_SPSR_FIQ_AA64;
1816 }
1817 break;
1818 }
1819 break;
1820 case 6:
1821 switch (crm) {
1822 case 0:
1823 switch (op2) {
1824 case 0:
1825 return MISCREG_SPSR_EL3;
1826 case 1:
1827 return MISCREG_ELR_EL3;
1828 }
1829 break;
1830 case 1:
1831 switch (op2) {
1832 case 0:
1833 return MISCREG_SP_EL2;
1834 }
1835 break;
1836 }
1837 break;
1838 }
1839 break;
1840 case 5:
1841 switch (op1) {
1842 case 0:
1843 switch (crm) {
1844 case 1:
1845 switch (op2) {
1846 case 0:
1847 return MISCREG_AFSR0_EL1;
1848 case 1:
1849 return MISCREG_AFSR1_EL1;
1850 }
1851 break;
1852 case 2:
1853 switch (op2) {
1854 case 0:
1855 return MISCREG_ESR_EL1;
1856 }
1857 break;
1858 }
1859 break;
1860 case 4:
1861 switch (crm) {
1862 case 0:
1863 switch (op2) {
1864 case 1:
1865 return MISCREG_IFSR32_EL2;
1866 }
1867 break;
1868 case 1:
1869 switch (op2) {
1870 case 0:
1871 return MISCREG_AFSR0_EL2;
1872 case 1:
1873 return MISCREG_AFSR1_EL2;
1874 }
1875 break;
1876 case 2:
1877 switch (op2) {
1878 case 0:
1879 return MISCREG_ESR_EL2;
1880 }
1881 break;
1882 case 3:
1883 switch (op2) {
1884 case 0:
1885 return MISCREG_FPEXC32_EL2;
1886 }
1887 break;
1888 }
1889 break;
1890 case 6:
1891 switch (crm) {
1892 case 1:
1893 switch (op2) {
1894 case 0:
1895 return MISCREG_AFSR0_EL3;
1896 case 1:
1897 return MISCREG_AFSR1_EL3;
1898 }
1899 break;
1900 case 2:
1901 switch (op2) {
1902 case 0:
1903 return MISCREG_ESR_EL3;
1904 }
1905 break;
1906 }
1907 break;
1908 }
1909 break;
1910 case 6:
1911 switch (op1) {
1912 case 0:
1913 switch (crm) {
1914 case 0:
1915 switch (op2) {
1916 case 0:
1917 return MISCREG_FAR_EL1;
1918 }
1919 break;
1920 }
1921 break;
1922 case 4:
1923 switch (crm) {
1924 case 0:
1925 switch (op2) {
1926 case 0:
1927 return MISCREG_FAR_EL2;
1928 case 4:
1929 return MISCREG_HPFAR_EL2;
1930 }
1931 break;
1932 }
1933 break;
1934 case 6:
1935 switch (crm) {
1936 case 0:
1937 switch (op2) {
1938 case 0:
1939 return MISCREG_FAR_EL3;
1940 }
1941 break;
1942 }
1943 break;
1944 }
1945 break;
1946 case 7:
1947 switch (op1) {
1948 case 0:
1949 switch (crm) {
1950 case 4:
1951 switch (op2) {
1952 case 0:
1953 return MISCREG_PAR_EL1;
1954 }
1955 break;
1956 }
1957 break;
1958 }
1959 break;
1960 case 9:
1961 switch (op1) {
1962 case 0:
1963 switch (crm) {
1964 case 14:
1965 switch (op2) {
1966 case 1:
1967 return MISCREG_PMINTENSET_EL1;
1968 case 2:
1969 return MISCREG_PMINTENCLR_EL1;
1970 }
1971 break;
1972 }
1973 break;
1974 case 3:
1975 switch (crm) {
1976 case 12:
1977 switch (op2) {
1978 case 0:
1979 return MISCREG_PMCR_EL0;
1980 case 1:
1981 return MISCREG_PMCNTENSET_EL0;
1982 case 2:
1983 return MISCREG_PMCNTENCLR_EL0;
1984 case 3:
1985 return MISCREG_PMOVSCLR_EL0;
1986 case 4:
1987 return MISCREG_PMSWINC_EL0;
1988 case 5:
1989 return MISCREG_PMSELR_EL0;
1990 case 6:
1991 return MISCREG_PMCEID0_EL0;
1992 case 7:
1993 return MISCREG_PMCEID1_EL0;
1994 }
1995 break;
1996 case 13:
1997 switch (op2) {
1998 case 0:
1999 return MISCREG_PMCCNTR_EL0;
2000 case 1:
2001 return MISCREG_PMXEVTYPER_EL0;
2002 case 2:
2003 return MISCREG_PMXEVCNTR_EL0;
2004 }
2005 break;
2006 case 14:
2007 switch (op2) {
2008 case 0:
2009 return MISCREG_PMUSERENR_EL0;
2010 case 3:
2011 return MISCREG_PMOVSSET_EL0;
2012 }
2013 break;
2014 }
2015 break;
2016 }
2017 break;
2018 case 10:
2019 switch (op1) {
2020 case 0:
2021 switch (crm) {
2022 case 2:
2023 switch (op2) {
2024 case 0:
2025 return MISCREG_MAIR_EL1;
2026 }
2027 break;
2028 case 3:
2029 switch (op2) {
2030 case 0:
2031 return MISCREG_AMAIR_EL1;
2032 }
2033 break;
2034 }
2035 break;
2036 case 4:
2037 switch (crm) {
2038 case 2:
2039 switch (op2) {
2040 case 0:
2041 return MISCREG_MAIR_EL2;
2042 }
2043 break;
2044 case 3:
2045 switch (op2) {
2046 case 0:
2047 return MISCREG_AMAIR_EL2;
2048 }
2049 break;
2050 }
2051 break;
2052 case 6:
2053 switch (crm) {
2054 case 2:
2055 switch (op2) {
2056 case 0:
2057 return MISCREG_MAIR_EL3;
2058 }
2059 break;
2060 case 3:
2061 switch (op2) {
2062 case 0:
2063 return MISCREG_AMAIR_EL3;
2064 }
2065 break;
2066 }
2067 break;
2068 }
2069 break;
2070 case 11:
2071 switch (op1) {
2072 case 1:
2073 switch (crm) {
2074 case 0:
2075 switch (op2) {
2076 case 2:
2077 return MISCREG_L2CTLR_EL1;
2078 case 3:
2079 return MISCREG_L2ECTLR_EL1;
2080 }
2081 break;
2082 }
2083 break;
2084 }
2085 break;
2086 case 12:
2087 switch (op1) {
2088 case 0:
2089 switch (crm) {
2090 case 0:
2091 switch (op2) {
2092 case 0:
2093 return MISCREG_VBAR_EL1;
2094 case 1:
2095 return MISCREG_RVBAR_EL1;
2096 }
2097 break;
2098 case 1:
2099 switch (op2) {
2100 case 0:
2101 return MISCREG_ISR_EL1;
2102 }
2103 break;
2104 }
2105 break;
2106 case 4:
2107 switch (crm) {
2108 case 0:
2109 switch (op2) {
2110 case 0:
2111 return MISCREG_VBAR_EL2;
2112 case 1:
2113 return MISCREG_RVBAR_EL2;
2114 }
2115 break;
2116 }
2117 break;
2118 case 6:
2119 switch (crm) {
2120 case 0:
2121 switch (op2) {
2122 case 0:
2123 return MISCREG_VBAR_EL3;
2124 case 1:
2125 return MISCREG_RVBAR_EL3;
2126 case 2:
2127 return MISCREG_RMR_EL3;
2128 }
2129 break;
2130 }
2131 break;
2132 }
2133 break;
2134 case 13:
2135 switch (op1) {
2136 case 0:
2137 switch (crm) {
2138 case 0:
2139 switch (op2) {
2140 case 1:
2141 return MISCREG_CONTEXTIDR_EL1;
2142 case 4:
2143 return MISCREG_TPIDR_EL1;
2144 }
2145 break;
2146 }
2147 break;
2148 case 3:
2149 switch (crm) {
2150 case 0:
2151 switch (op2) {
2152 case 2:
2153 return MISCREG_TPIDR_EL0;
2154 case 3:
2155 return MISCREG_TPIDRRO_EL0;
2156 }
2157 break;
2158 }
2159 break;
2160 case 4:
2161 switch (crm) {
2162 case 0:
2163 switch (op2) {
2164 case 1:
2165 return MISCREG_CONTEXTIDR_EL2;
2166 case 2:
2167 return MISCREG_TPIDR_EL2;
2168 }
2169 break;
2170 }
2171 break;
2172 case 6:
2173 switch (crm) {
2174 case 0:
2175 switch (op2) {
2176 case 2:
2177 return MISCREG_TPIDR_EL3;
2178 }
2179 break;
2180 }
2181 break;
2182 }
2183 break;
2184 case 14:
2185 switch (op1) {
2186 case 0:
2187 switch (crm) {
2188 case 1:
2189 switch (op2) {
2190 case 0:
2191 return MISCREG_CNTKCTL_EL1;
2192 }
2193 break;
2194 }
2195 break;
2196 case 3:
2197 switch (crm) {
2198 case 0:
2199 switch (op2) {
2200 case 0:
2201 return MISCREG_CNTFRQ_EL0;
2202 case 1:
2203 return MISCREG_CNTPCT_EL0;
2204 case 2:
2205 return MISCREG_CNTVCT_EL0;
2206 }
2207 break;
2208 case 2:
2209 switch (op2) {
2210 case 0:
2211 return MISCREG_CNTP_TVAL_EL0;
2212 case 1:
2213 return MISCREG_CNTP_CTL_EL0;
2214 case 2:
2215 return MISCREG_CNTP_CVAL_EL0;
2216 }
2217 break;
2218 case 3:
2219 switch (op2) {
2220 case 0:
2221 return MISCREG_CNTV_TVAL_EL0;
2222 case 1:
2223 return MISCREG_CNTV_CTL_EL0;
2224 case 2:
2225 return MISCREG_CNTV_CVAL_EL0;
2226 }
2227 break;
2228 case 8:
2229 switch (op2) {
2230 case 0:
2231 return MISCREG_PMEVCNTR0_EL0;
2232 case 1:
2233 return MISCREG_PMEVCNTR1_EL0;
2234 case 2:
2235 return MISCREG_PMEVCNTR2_EL0;
2236 case 3:
2237 return MISCREG_PMEVCNTR3_EL0;
2238 case 4:
2239 return MISCREG_PMEVCNTR4_EL0;
2240 case 5:
2241 return MISCREG_PMEVCNTR5_EL0;
2242 }
2243 break;
2244 case 12:
2245 switch (op2) {
2246 case 0:
2247 return MISCREG_PMEVTYPER0_EL0;
2248 case 1:
2249 return MISCREG_PMEVTYPER1_EL0;
2250 case 2:
2251 return MISCREG_PMEVTYPER2_EL0;
2252 case 3:
2253 return MISCREG_PMEVTYPER3_EL0;
2254 case 4:
2255 return MISCREG_PMEVTYPER4_EL0;
2256 case 5:
2257 return MISCREG_PMEVTYPER5_EL0;
2258 }
2259 break;
2260 case 15:
2261 switch (op2) {
2262 case 7:
2263 return MISCREG_PMCCFILTR_EL0;
2264 }
2265 }
2266 break;
2267 case 4:
2268 switch (crm) {
2269 case 0:
2270 switch (op2) {
2271 case 3:
2272 return MISCREG_CNTVOFF_EL2;
2273 }
2274 break;
2275 case 1:
2276 switch (op2) {
2277 case 0:
2278 return MISCREG_CNTHCTL_EL2;
2279 }
2280 break;
2281 case 2:
2282 switch (op2) {
2283 case 0:
2284 return MISCREG_CNTHP_TVAL_EL2;
2285 case 1:
2286 return MISCREG_CNTHP_CTL_EL2;
2287 case 2:
2288 return MISCREG_CNTHP_CVAL_EL2;
2289 }
2290 break;
2291 }
2292 break;
2293 case 7:
2294 switch (crm) {
2295 case 2:
2296 switch (op2) {
2297 case 0:
2298 return MISCREG_CNTPS_TVAL_EL1;
2299 case 1:
2300 return MISCREG_CNTPS_CTL_EL1;
2301 case 2:
2302 return MISCREG_CNTPS_CVAL_EL1;
2303 }
2304 break;
2305 }
2306 break;
2307 }
2308 break;
2309 case 15:
2310 switch (op1) {
2311 case 0:
2312 switch (crm) {
2313 case 0:
2314 switch (op2) {
2315 case 0:
2316 return MISCREG_IL1DATA0_EL1;
2317 case 1:
2318 return MISCREG_IL1DATA1_EL1;
2319 case 2:
2320 return MISCREG_IL1DATA2_EL1;
2321 case 3:
2322 return MISCREG_IL1DATA3_EL1;
2323 }
2324 break;
2325 case 1:
2326 switch (op2) {
2327 case 0:
2328 return MISCREG_DL1DATA0_EL1;
2329 case 1:
2330 return MISCREG_DL1DATA1_EL1;
2331 case 2:
2332 return MISCREG_DL1DATA2_EL1;
2333 case 3:
2334 return MISCREG_DL1DATA3_EL1;
2335 case 4:
2336 return MISCREG_DL1DATA4_EL1;
2337 }
2338 break;
2339 }
2340 break;
2341 case 1:
2342 switch (crm) {
2343 case 0:
2344 switch (op2) {
2345 case 0:
2346 return MISCREG_L2ACTLR_EL1;
2347 }
2348 break;
2349 case 2:
2350 switch (op2) {
2351 case 0:
2352 return MISCREG_CPUACTLR_EL1;
2353 case 1:
2354 return MISCREG_CPUECTLR_EL1;
2355 case 2:
2356 return MISCREG_CPUMERRSR_EL1;
2357 case 3:
2358 return MISCREG_L2MERRSR_EL1;
2359 }
2360 break;
2361 case 3:
2362 switch (op2) {
2363 case 0:
2364 return MISCREG_CBAR_EL1;
2365
2366 }
2367 break;
2368 }
2369 break;
2370 }
2371 break;
2372 }
2373 break;
2374 }
2375
2376 return MISCREG_UNKNOWN;
2377}
2378
2379bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2380
2381void
2382ISA::initializeMiscRegMetadata()
2383{
2384 // the MiscReg metadata tables are shared across all instances of the
2385 // ISA object, so there's no need to initialize them multiple times.
2386 static bool completed = false;
2387 if (completed)
2388 return;
2389
2390 /**
2391 * Some registers alias with others, and therefore need to be translated.
2392 * When two mapping registers are given, they are the 32b lower and
2393 * upper halves, respectively, of the 64b register being mapped.
2394 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2395 *
2396 * NAM = "not architecturally mandated",
2397 * from ARM DDI 0487A.i, template text
2398 * "AArch64 System register ___ can be mapped to
2399 * AArch32 System register ___, but this is not
2400 * architecturally mandated."
2401 */
2402
2403 InitReg(MISCREG_CPSR)
2404 .allPrivileges();
2405 InitReg(MISCREG_SPSR)
2406 .allPrivileges();
2407 InitReg(MISCREG_SPSR_FIQ)
2408 .allPrivileges();
2409 InitReg(MISCREG_SPSR_IRQ)
2410 .allPrivileges();
2411 InitReg(MISCREG_SPSR_SVC)
2412 .allPrivileges();
2413 InitReg(MISCREG_SPSR_MON)
2414 .allPrivileges();
2415 InitReg(MISCREG_SPSR_ABT)
2416 .allPrivileges();
2417 InitReg(MISCREG_SPSR_HYP)
2418 .allPrivileges();
2419 InitReg(MISCREG_SPSR_UND)
2420 .allPrivileges();
2421 InitReg(MISCREG_ELR_HYP)
2422 .allPrivileges();
2423 InitReg(MISCREG_FPSID)
2424 .allPrivileges();
2425 InitReg(MISCREG_FPSCR)
2426 .allPrivileges();
2427 InitReg(MISCREG_MVFR1)
2428 .allPrivileges();
2429 InitReg(MISCREG_MVFR0)
2430 .allPrivileges();
2431 InitReg(MISCREG_FPEXC)
2432 .allPrivileges();
2433
2434 // Helper registers
2435 InitReg(MISCREG_CPSR_MODE)
2436 .allPrivileges();
2437 InitReg(MISCREG_CPSR_Q)
2438 .allPrivileges();
2439 InitReg(MISCREG_FPSCR_EXC)
2440 .allPrivileges();
2441 InitReg(MISCREG_FPSCR_QC)
2442 .allPrivileges();
2443 InitReg(MISCREG_LOCKADDR)
2444 .allPrivileges();
2445 InitReg(MISCREG_LOCKFLAG)
2446 .allPrivileges();
2447 InitReg(MISCREG_PRRR_MAIR0)
2448 .mutex()
2449 .banked();
2450 InitReg(MISCREG_PRRR_MAIR0_NS)
2451 .mutex()
2452 .bankedChild();
2453 InitReg(MISCREG_PRRR_MAIR0_S)
2454 .mutex()
2455 .bankedChild();
2456 InitReg(MISCREG_NMRR_MAIR1)
2457 .mutex()
2458 .banked();
2459 InitReg(MISCREG_NMRR_MAIR1_NS)
2460 .mutex()
2461 .bankedChild();
2462 InitReg(MISCREG_NMRR_MAIR1_S)
2463 .mutex()
2464 .bankedChild();
2465 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2466 .mutex();
2467 InitReg(MISCREG_SCTLR_RST)
2468 .allPrivileges();
2469 InitReg(MISCREG_SEV_MAILBOX)
2470 .allPrivileges();
2471
2472 // AArch32 CP14 registers
2473 InitReg(MISCREG_DBGDIDR)
2474 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2475 InitReg(MISCREG_DBGDSCRint)
2476 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2477 InitReg(MISCREG_DBGDCCINT)
2478 .unimplemented()
2479 .allPrivileges();
2480 InitReg(MISCREG_DBGDTRTXint)
2481 .unimplemented()
2482 .allPrivileges();
2483 InitReg(MISCREG_DBGDTRRXint)
2484 .unimplemented()
2485 .allPrivileges();
2486 InitReg(MISCREG_DBGWFAR)
2487 .unimplemented()
2488 .allPrivileges();
2489 InitReg(MISCREG_DBGVCR)
2490 .unimplemented()
2491 .allPrivileges();
2492 InitReg(MISCREG_DBGDTRRXext)
2493 .unimplemented()
2494 .allPrivileges();
2495 InitReg(MISCREG_DBGDSCRext)
2496 .unimplemented()
2497 .warnNotFail()
2498 .allPrivileges();
2499 InitReg(MISCREG_DBGDTRTXext)
2500 .unimplemented()
2501 .allPrivileges();
2502 InitReg(MISCREG_DBGOSECCR)
2503 .unimplemented()
2504 .allPrivileges();
2505 InitReg(MISCREG_DBGBVR0)
2506 .unimplemented()
2507 .allPrivileges();
2508 InitReg(MISCREG_DBGBVR1)
2509 .unimplemented()
2510 .allPrivileges();
2511 InitReg(MISCREG_DBGBVR2)
2512 .unimplemented()
2513 .allPrivileges();
2514 InitReg(MISCREG_DBGBVR3)
2515 .unimplemented()
2516 .allPrivileges();
2517 InitReg(MISCREG_DBGBVR4)
2518 .unimplemented()
2519 .allPrivileges();
2520 InitReg(MISCREG_DBGBVR5)
2521 .unimplemented()
2522 .allPrivileges();
2523 InitReg(MISCREG_DBGBCR0)
2524 .unimplemented()
2525 .allPrivileges();
2526 InitReg(MISCREG_DBGBCR1)
2527 .unimplemented()
2528 .allPrivileges();
2529 InitReg(MISCREG_DBGBCR2)
2530 .unimplemented()
2531 .allPrivileges();
2532 InitReg(MISCREG_DBGBCR3)
2533 .unimplemented()
2534 .allPrivileges();
2535 InitReg(MISCREG_DBGBCR4)
2536 .unimplemented()
2537 .allPrivileges();
2538 InitReg(MISCREG_DBGBCR5)
2539 .unimplemented()
2540 .allPrivileges();
2541 InitReg(MISCREG_DBGWVR0)
2542 .unimplemented()
2543 .allPrivileges();
2544 InitReg(MISCREG_DBGWVR1)
2545 .unimplemented()
2546 .allPrivileges();
2547 InitReg(MISCREG_DBGWVR2)
2548 .unimplemented()
2549 .allPrivileges();
2550 InitReg(MISCREG_DBGWVR3)
2551 .unimplemented()
2552 .allPrivileges();
2553 InitReg(MISCREG_DBGWCR0)
2554 .unimplemented()
2555 .allPrivileges();
2556 InitReg(MISCREG_DBGWCR1)
2557 .unimplemented()
2558 .allPrivileges();
2559 InitReg(MISCREG_DBGWCR2)
2560 .unimplemented()
2561 .allPrivileges();
2562 InitReg(MISCREG_DBGWCR3)
2563 .unimplemented()
2564 .allPrivileges();
2565 InitReg(MISCREG_DBGDRAR)
2566 .unimplemented()
2567 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2568 InitReg(MISCREG_DBGBXVR4)
2569 .unimplemented()
2570 .allPrivileges();
2571 InitReg(MISCREG_DBGBXVR5)
2572 .unimplemented()
2573 .allPrivileges();
2574 InitReg(MISCREG_DBGOSLAR)
2575 .unimplemented()
2576 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
2577 InitReg(MISCREG_DBGOSLSR)
2578 .unimplemented()
2579 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2580 InitReg(MISCREG_DBGOSDLR)
2581 .unimplemented()
2582 .allPrivileges();
2583 InitReg(MISCREG_DBGPRCR)
2584 .unimplemented()
2585 .allPrivileges();
2586 InitReg(MISCREG_DBGDSAR)
2587 .unimplemented()
2588 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2589 InitReg(MISCREG_DBGCLAIMSET)
2590 .unimplemented()
2591 .allPrivileges();
2592 InitReg(MISCREG_DBGCLAIMCLR)
2593 .unimplemented()
2594 .allPrivileges();
2595 InitReg(MISCREG_DBGAUTHSTATUS)
2596 .unimplemented()
2597 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2598 InitReg(MISCREG_DBGDEVID2)
2599 .unimplemented()
2600 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2601 InitReg(MISCREG_DBGDEVID1)
2602 .unimplemented()
2603 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2604 InitReg(MISCREG_DBGDEVID0)
2605 .unimplemented()
2606 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2607 InitReg(MISCREG_TEECR)
2608 .unimplemented()
2609 .allPrivileges();
2610 InitReg(MISCREG_JIDR)
2611 .allPrivileges();
2612 InitReg(MISCREG_TEEHBR)
2613 .allPrivileges();
2614 InitReg(MISCREG_JOSCR)
2615 .allPrivileges();
2616 InitReg(MISCREG_JMCR)
2617 .allPrivileges();
2618
2619 // AArch32 CP15 registers
2620 InitReg(MISCREG_MIDR)
2621 .allPrivileges().exceptUserMode().writes(0);
2622 InitReg(MISCREG_CTR)
2623 .allPrivileges().exceptUserMode().writes(0);
2624 InitReg(MISCREG_TCMTR)
2625 .allPrivileges().exceptUserMode().writes(0);
2626 InitReg(MISCREG_TLBTR)
2627 .allPrivileges().exceptUserMode().writes(0);
2628 InitReg(MISCREG_MPIDR)
2629 .allPrivileges().exceptUserMode().writes(0);
2630 InitReg(MISCREG_REVIDR)
2631 .unimplemented()
2632 .warnNotFail()
2633 .allPrivileges().exceptUserMode().writes(0);
2634 InitReg(MISCREG_ID_PFR0)
2635 .allPrivileges().exceptUserMode().writes(0);
2636 InitReg(MISCREG_ID_PFR1)
2637 .allPrivileges().exceptUserMode().writes(0);
2638 InitReg(MISCREG_ID_DFR0)
2639 .allPrivileges().exceptUserMode().writes(0);
2640 InitReg(MISCREG_ID_AFR0)
2641 .allPrivileges().exceptUserMode().writes(0);
2642 InitReg(MISCREG_ID_MMFR0)
2643 .allPrivileges().exceptUserMode().writes(0);
2644 InitReg(MISCREG_ID_MMFR1)
2645 .allPrivileges().exceptUserMode().writes(0);
2646 InitReg(MISCREG_ID_MMFR2)
2647 .allPrivileges().exceptUserMode().writes(0);
2648 InitReg(MISCREG_ID_MMFR3)
2649 .allPrivileges().exceptUserMode().writes(0);
2650 InitReg(MISCREG_ID_ISAR0)
2651 .allPrivileges().exceptUserMode().writes(0);
2652 InitReg(MISCREG_ID_ISAR1)
2653 .allPrivileges().exceptUserMode().writes(0);
2654 InitReg(MISCREG_ID_ISAR2)
2655 .allPrivileges().exceptUserMode().writes(0);
2656 InitReg(MISCREG_ID_ISAR3)
2657 .allPrivileges().exceptUserMode().writes(0);
2658 InitReg(MISCREG_ID_ISAR4)
2659 .allPrivileges().exceptUserMode().writes(0);
2660 InitReg(MISCREG_ID_ISAR5)
2661 .allPrivileges().exceptUserMode().writes(0);
2662 InitReg(MISCREG_CCSIDR)
2663 .allPrivileges().exceptUserMode().writes(0);
2664 InitReg(MISCREG_CLIDR)
2665 .allPrivileges().exceptUserMode().writes(0);
2666 InitReg(MISCREG_AIDR)
2667 .allPrivileges().exceptUserMode().writes(0);
2668 InitReg(MISCREG_CSSELR)
2669 .banked();
2670 InitReg(MISCREG_CSSELR_NS)
2671 .bankedChild()
2672 .nonSecure().exceptUserMode();
2673 InitReg(MISCREG_CSSELR_S)
2674 .bankedChild()
2675 .secure().exceptUserMode();
2676 InitReg(MISCREG_VPIDR)
2677 .hyp().monNonSecure();
2678 InitReg(MISCREG_VMPIDR)
2679 .hyp().monNonSecure();
2680 InitReg(MISCREG_SCTLR)
2681 .banked();
2682 InitReg(MISCREG_SCTLR_NS)
2683 .bankedChild()
2684 .nonSecure().exceptUserMode();
2685 InitReg(MISCREG_SCTLR_S)
2686 .bankedChild()
2687 .secure().exceptUserMode();
2688 InitReg(MISCREG_ACTLR)
2689 .banked();
2690 InitReg(MISCREG_ACTLR_NS)
2691 .bankedChild()
2692 .nonSecure().exceptUserMode();
2693 InitReg(MISCREG_ACTLR_S)
2694 .bankedChild()
2695 .secure().exceptUserMode();
2696 InitReg(MISCREG_CPACR)
2697 .allPrivileges().exceptUserMode();
2698 InitReg(MISCREG_SCR)
2699 .mon().secure().exceptUserMode()
2700 .res0(0xff40) // [31:16], [6]
2701 .res1(0x0030); // [5:4]
2702 InitReg(MISCREG_SDER)
2703 .mon();
2704 InitReg(MISCREG_NSACR)
2705 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2706 InitReg(MISCREG_HSCTLR)
2707 .hyp().monNonSecure();
2708 InitReg(MISCREG_HACTLR)
2709 .hyp().monNonSecure();
2710 InitReg(MISCREG_HCR)
2711 .hyp().monNonSecure();
2712 InitReg(MISCREG_HDCR)
2713 .hyp().monNonSecure();
2714 InitReg(MISCREG_HCPTR)
2715 .hyp().monNonSecure();
2716 InitReg(MISCREG_HSTR)
2717 .hyp().monNonSecure();
2718 InitReg(MISCREG_HACR)
2719 .unimplemented()
2720 .warnNotFail()
2721 .hyp().monNonSecure();
2722 InitReg(MISCREG_TTBR0)
2723 .banked();
2724 InitReg(MISCREG_TTBR0_NS)
2725 .bankedChild()
2726 .nonSecure().exceptUserMode();
2727 InitReg(MISCREG_TTBR0_S)
2728 .bankedChild()
2729 .secure().exceptUserMode();
2730 InitReg(MISCREG_TTBR1)
2731 .banked();
2732 InitReg(MISCREG_TTBR1_NS)
2733 .bankedChild()
2734 .nonSecure().exceptUserMode();
2735 InitReg(MISCREG_TTBR1_S)
2736 .bankedChild()
2737 .secure().exceptUserMode();
2738 InitReg(MISCREG_TTBCR)
2739 .banked();
2740 InitReg(MISCREG_TTBCR_NS)
2741 .bankedChild()
2742 .nonSecure().exceptUserMode();
2743 InitReg(MISCREG_TTBCR_S)
2744 .bankedChild()
2745 .secure().exceptUserMode();
2746 InitReg(MISCREG_HTCR)
2747 .hyp().monNonSecure();
2748 InitReg(MISCREG_VTCR)
2749 .hyp().monNonSecure();
2750 InitReg(MISCREG_DACR)
2751 .banked();
2752 InitReg(MISCREG_DACR_NS)
2753 .bankedChild()
2754 .nonSecure().exceptUserMode();
2755 InitReg(MISCREG_DACR_S)
2756 .bankedChild()
2757 .secure().exceptUserMode();
2758 InitReg(MISCREG_DFSR)
2759 .banked();
2760 InitReg(MISCREG_DFSR_NS)
2761 .bankedChild()
2762 .nonSecure().exceptUserMode();
2763 InitReg(MISCREG_DFSR_S)
2764 .bankedChild()
2765 .secure().exceptUserMode();
2766 InitReg(MISCREG_IFSR)
2767 .banked();
2768 InitReg(MISCREG_IFSR_NS)
2769 .bankedChild()
2770 .nonSecure().exceptUserMode();
2771 InitReg(MISCREG_IFSR_S)
2772 .bankedChild()
2773 .secure().exceptUserMode();
2774 InitReg(MISCREG_ADFSR)
2775 .unimplemented()
2776 .warnNotFail()
2777 .banked();
2778 InitReg(MISCREG_ADFSR_NS)
2779 .unimplemented()
2780 .warnNotFail()
2781 .bankedChild()
2782 .nonSecure().exceptUserMode();
2783 InitReg(MISCREG_ADFSR_S)
2784 .unimplemented()
2785 .warnNotFail()
2786 .bankedChild()
2787 .secure().exceptUserMode();
2788 InitReg(MISCREG_AIFSR)
2789 .unimplemented()
2790 .warnNotFail()
2791 .banked();
2792 InitReg(MISCREG_AIFSR_NS)
2793 .unimplemented()
2794 .warnNotFail()
2795 .bankedChild()
2796 .nonSecure().exceptUserMode();
2797 InitReg(MISCREG_AIFSR_S)
2798 .unimplemented()
2799 .warnNotFail()
2800 .bankedChild()
2801 .secure().exceptUserMode();
2802 InitReg(MISCREG_HADFSR)
2803 .hyp().monNonSecure();
2804 InitReg(MISCREG_HAIFSR)
2805 .hyp().monNonSecure();
2806 InitReg(MISCREG_HSR)
2807 .hyp().monNonSecure();
2808 InitReg(MISCREG_DFAR)
2809 .banked();
2810 InitReg(MISCREG_DFAR_NS)
2811 .bankedChild()
2812 .nonSecure().exceptUserMode();
2813 InitReg(MISCREG_DFAR_S)
2814 .bankedChild()
2815 .secure().exceptUserMode();
2816 InitReg(MISCREG_IFAR)
2817 .banked();
2818 InitReg(MISCREG_IFAR_NS)
2819 .bankedChild()
2820 .nonSecure().exceptUserMode();
2821 InitReg(MISCREG_IFAR_S)
2822 .bankedChild()
2823 .secure().exceptUserMode();
2824 InitReg(MISCREG_HDFAR)
2825 .hyp().monNonSecure();
2826 InitReg(MISCREG_HIFAR)
2827 .hyp().monNonSecure();
2828 InitReg(MISCREG_HPFAR)
2829 .hyp().monNonSecure();
2830 InitReg(MISCREG_ICIALLUIS)
2831 .unimplemented()
2832 .warnNotFail()
2833 .writes(1).exceptUserMode();
2834 InitReg(MISCREG_BPIALLIS)
2835 .unimplemented()
2836 .warnNotFail()
2837 .writes(1).exceptUserMode();
2838 InitReg(MISCREG_PAR)
2839 .banked();
2840 InitReg(MISCREG_PAR_NS)
2841 .bankedChild()
2842 .nonSecure().exceptUserMode();
2843 InitReg(MISCREG_PAR_S)
2844 .bankedChild()
2845 .secure().exceptUserMode();
2846 InitReg(MISCREG_ICIALLU)
2847 .writes(1).exceptUserMode();
2848 InitReg(MISCREG_ICIMVAU)
2849 .unimplemented()
2850 .warnNotFail()
2851 .writes(1).exceptUserMode();
2852 InitReg(MISCREG_CP15ISB)
2853 .writes(1);
2854 InitReg(MISCREG_BPIALL)
2855 .unimplemented()
2856 .warnNotFail()
2857 .writes(1).exceptUserMode();
2858 InitReg(MISCREG_BPIMVA)
2859 .unimplemented()
2860 .warnNotFail()
2861 .writes(1).exceptUserMode();
2862 InitReg(MISCREG_DCIMVAC)
2863 .unimplemented()
2864 .warnNotFail()
2865 .writes(1).exceptUserMode();
2866 InitReg(MISCREG_DCISW)
2867 .unimplemented()
2868 .warnNotFail()
2869 .writes(1).exceptUserMode();
2870 InitReg(MISCREG_ATS1CPR)
2871 .writes(1).exceptUserMode();
2872 InitReg(MISCREG_ATS1CPW)
2873 .writes(1).exceptUserMode();
2874 InitReg(MISCREG_ATS1CUR)
2875 .writes(1).exceptUserMode();
2876 InitReg(MISCREG_ATS1CUW)
2877 .writes(1).exceptUserMode();
2878 InitReg(MISCREG_ATS12NSOPR)
2879 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2880 InitReg(MISCREG_ATS12NSOPW)
2881 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2882 InitReg(MISCREG_ATS12NSOUR)
2883 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2884 InitReg(MISCREG_ATS12NSOUW)
2885 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2886 InitReg(MISCREG_DCCMVAC)
2887 .writes(1).exceptUserMode();
2888 InitReg(MISCREG_DCCSW)
2889 .unimplemented()
2890 .warnNotFail()
2891 .writes(1).exceptUserMode();
2892 InitReg(MISCREG_CP15DSB)
2893 .writes(1);
2894 InitReg(MISCREG_CP15DMB)
2895 .writes(1);
2896 InitReg(MISCREG_DCCMVAU)
2897 .unimplemented()
2898 .warnNotFail()
2899 .writes(1).exceptUserMode();
2900 InitReg(MISCREG_DCCIMVAC)
2901 .unimplemented()
2902 .warnNotFail()
2903 .writes(1).exceptUserMode();
2904 InitReg(MISCREG_DCCISW)
2905 .unimplemented()
2906 .warnNotFail()
2907 .writes(1).exceptUserMode();
2908 InitReg(MISCREG_ATS1HR)
2909 .monNonSecureWrite().hypWrite();
2910 InitReg(MISCREG_ATS1HW)
2911 .monNonSecureWrite().hypWrite();
2912 InitReg(MISCREG_TLBIALLIS)
2913 .writes(1).exceptUserMode();
2914 InitReg(MISCREG_TLBIMVAIS)
2915 .writes(1).exceptUserMode();
2916 InitReg(MISCREG_TLBIASIDIS)
2917 .writes(1).exceptUserMode();
2918 InitReg(MISCREG_TLBIMVAAIS)
2919 .writes(1).exceptUserMode();
2920 InitReg(MISCREG_TLBIMVALIS)
2921 .writes(1).exceptUserMode();
2922 InitReg(MISCREG_TLBIMVAALIS)
2923 .writes(1).exceptUserMode();
2924 InitReg(MISCREG_ITLBIALL)
2925 .writes(1).exceptUserMode();
2926 InitReg(MISCREG_ITLBIMVA)
2927 .writes(1).exceptUserMode();
2928 InitReg(MISCREG_ITLBIASID)
2929 .writes(1).exceptUserMode();
2930 InitReg(MISCREG_DTLBIALL)
2931 .writes(1).exceptUserMode();
2932 InitReg(MISCREG_DTLBIMVA)
2933 .writes(1).exceptUserMode();
2934 InitReg(MISCREG_DTLBIASID)
2935 .writes(1).exceptUserMode();
2936 InitReg(MISCREG_TLBIALL)
2937 .writes(1).exceptUserMode();
2938 InitReg(MISCREG_TLBIMVA)
2939 .writes(1).exceptUserMode();
2940 InitReg(MISCREG_TLBIASID)
2941 .writes(1).exceptUserMode();
2942 InitReg(MISCREG_TLBIMVAA)
2943 .writes(1).exceptUserMode();
2944 InitReg(MISCREG_TLBIMVAL)
2945 .writes(1).exceptUserMode();
2946 InitReg(MISCREG_TLBIMVAAL)
2947 .writes(1).exceptUserMode();
2948 InitReg(MISCREG_TLBIIPAS2IS)

~~2935~~ .unimplemented()

2949 .monNonSecureWrite().hypWrite();
2950 InitReg(MISCREG_TLBIIPAS2LIS)

~~2938~~ .unimplemented()

2951 .monNonSecureWrite().hypWrite();
2952 InitReg(MISCREG_TLBIALLHIS)
2953 .monNonSecureWrite().hypWrite();
2954 InitReg(MISCREG_TLBIMVAHIS)
2955 .monNonSecureWrite().hypWrite();
2956 InitReg(MISCREG_TLBIALLNSNHIS)
2957 .monNonSecureWrite().hypWrite();
2958 InitReg(MISCREG_TLBIMVALHIS)
2959 .monNonSecureWrite().hypWrite();
2960 InitReg(MISCREG_TLBIIPAS2)

~~2949~~ .unimplemented()

2961 .monNonSecureWrite().hypWrite();
2962 InitReg(MISCREG_TLBIIPAS2L)

~~2952~~ .unimplemented()

2963 .monNonSecureWrite().hypWrite();
2964 InitReg(MISCREG_TLBIALLH)
2965 .monNonSecureWrite().hypWrite();
2966 InitReg(MISCREG_TLBIMVAH)
2967 .monNonSecureWrite().hypWrite();
2968 InitReg(MISCREG_TLBIALLNSNH)
2969 .monNonSecureWrite().hypWrite();
2970 InitReg(MISCREG_TLBIMVALH)
2971 .monNonSecureWrite().hypWrite();
2972 InitReg(MISCREG_PMCR)
2973 .allPrivileges();
2974 InitReg(MISCREG_PMCNTENSET)
2975 .allPrivileges();
2976 InitReg(MISCREG_PMCNTENCLR)
2977 .allPrivileges();
2978 InitReg(MISCREG_PMOVSR)
2979 .allPrivileges();
2980 InitReg(MISCREG_PMSWINC)
2981 .allPrivileges();
2982 InitReg(MISCREG_PMSELR)
2983 .allPrivileges();
2984 InitReg(MISCREG_PMCEID0)
2985 .allPrivileges();
2986 InitReg(MISCREG_PMCEID1)
2987 .allPrivileges();
2988 InitReg(MISCREG_PMCCNTR)
2989 .allPrivileges();
2990 InitReg(MISCREG_PMXEVTYPER)
2991 .allPrivileges();
2992 InitReg(MISCREG_PMCCFILTR)
2993 .allPrivileges();
2994 InitReg(MISCREG_PMXEVCNTR)
2995 .allPrivileges();
2996 InitReg(MISCREG_PMUSERENR)
2997 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
2998 InitReg(MISCREG_PMINTENSET)
2999 .allPrivileges().exceptUserMode();
3000 InitReg(MISCREG_PMINTENCLR)
3001 .allPrivileges().exceptUserMode();
3002 InitReg(MISCREG_PMOVSSET)
3003 .unimplemented()
3004 .allPrivileges();
3005 InitReg(MISCREG_L2CTLR)
3006 .allPrivileges().exceptUserMode();
3007 InitReg(MISCREG_L2ECTLR)
3008 .unimplemented()
3009 .allPrivileges().exceptUserMode();
3010 InitReg(MISCREG_PRRR)
3011 .banked();
3012 InitReg(MISCREG_PRRR_NS)
3013 .bankedChild()
3014 .nonSecure().exceptUserMode();
3015 InitReg(MISCREG_PRRR_S)
3016 .bankedChild()
3017 .secure().exceptUserMode();
3018 InitReg(MISCREG_MAIR0)
3019 .banked();
3020 InitReg(MISCREG_MAIR0_NS)
3021 .bankedChild()
3022 .nonSecure().exceptUserMode();
3023 InitReg(MISCREG_MAIR0_S)
3024 .bankedChild()
3025 .secure().exceptUserMode();
3026 InitReg(MISCREG_NMRR)
3027 .banked();
3028 InitReg(MISCREG_NMRR_NS)
3029 .bankedChild()
3030 .nonSecure().exceptUserMode();
3031 InitReg(MISCREG_NMRR_S)
3032 .bankedChild()
3033 .secure().exceptUserMode();
3034 InitReg(MISCREG_MAIR1)
3035 .banked();
3036 InitReg(MISCREG_MAIR1_NS)
3037 .bankedChild()
3038 .nonSecure().exceptUserMode();
3039 InitReg(MISCREG_MAIR1_S)
3040 .bankedChild()
3041 .secure().exceptUserMode();
3042 InitReg(MISCREG_AMAIR0)
3043 .banked();
3044 InitReg(MISCREG_AMAIR0_NS)
3045 .bankedChild()
3046 .nonSecure().exceptUserMode();
3047 InitReg(MISCREG_AMAIR0_S)
3048 .bankedChild()
3049 .secure().exceptUserMode();
3050 InitReg(MISCREG_AMAIR1)
3051 .banked();
3052 InitReg(MISCREG_AMAIR1_NS)
3053 .bankedChild()
3054 .nonSecure().exceptUserMode();
3055 InitReg(MISCREG_AMAIR1_S)
3056 .bankedChild()
3057 .secure().exceptUserMode();
3058 InitReg(MISCREG_HMAIR0)
3059 .hyp().monNonSecure();
3060 InitReg(MISCREG_HMAIR1)
3061 .hyp().monNonSecure();
3062 InitReg(MISCREG_HAMAIR0)
3063 .unimplemented()
3064 .warnNotFail()
3065 .hyp().monNonSecure();
3066 InitReg(MISCREG_HAMAIR1)
3067 .unimplemented()
3068 .warnNotFail()
3069 .hyp().monNonSecure();
3070 InitReg(MISCREG_VBAR)
3071 .banked();
3072 InitReg(MISCREG_VBAR_NS)
3073 .bankedChild()
3074 .nonSecure().exceptUserMode();
3075 InitReg(MISCREG_VBAR_S)
3076 .bankedChild()
3077 .secure().exceptUserMode();
3078 InitReg(MISCREG_MVBAR)
3079 .mon().secure().exceptUserMode();
3080 InitReg(MISCREG_RMR)
3081 .unimplemented()
3082 .mon().secure().exceptUserMode();
3083 InitReg(MISCREG_ISR)
3084 .allPrivileges().exceptUserMode().writes(0);
3085 InitReg(MISCREG_HVBAR)
3086 .hyp().monNonSecure();
3087 InitReg(MISCREG_FCSEIDR)
3088 .unimplemented()
3089 .warnNotFail()
3090 .allPrivileges().exceptUserMode();
3091 InitReg(MISCREG_CONTEXTIDR)
3092 .banked();
3093 InitReg(MISCREG_CONTEXTIDR_NS)
3094 .bankedChild()
3095 .nonSecure().exceptUserMode();
3096 InitReg(MISCREG_CONTEXTIDR_S)
3097 .bankedChild()
3098 .secure().exceptUserMode();
3099 InitReg(MISCREG_TPIDRURW)
3100 .banked();
3101 InitReg(MISCREG_TPIDRURW_NS)
3102 .bankedChild()
3103 .allPrivileges().monSecure(0).privSecure(0);
3104 InitReg(MISCREG_TPIDRURW_S)
3105 .bankedChild()
3106 .secure();
3107 InitReg(MISCREG_TPIDRURO)
3108 .banked();
3109 InitReg(MISCREG_TPIDRURO_NS)
3110 .bankedChild()
3111 .allPrivileges().secure(0).userNonSecureWrite(0).userSecureRead(1);
3112 InitReg(MISCREG_TPIDRURO_S)
3113 .bankedChild()
3114 .secure().userSecureWrite(0);
3115 InitReg(MISCREG_TPIDRPRW)
3116 .banked();
3117 InitReg(MISCREG_TPIDRPRW_NS)
3118 .bankedChild()
3119 .nonSecure().exceptUserMode();
3120 InitReg(MISCREG_TPIDRPRW_S)
3121 .bankedChild()
3122 .secure().exceptUserMode();
3123 InitReg(MISCREG_HTPIDR)
3124 .hyp().monNonSecure();
3125 InitReg(MISCREG_CNTFRQ)
3126 .unverifiable()
3127 .reads(1).mon();
3128 InitReg(MISCREG_CNTKCTL)
3129 .allPrivileges().exceptUserMode();
3130 InitReg(MISCREG_CNTP_TVAL)
3131 .banked();
3132 InitReg(MISCREG_CNTP_TVAL_NS)
3133 .bankedChild()
3134 .allPrivileges().monSecure(0).privSecure(0);
3135 InitReg(MISCREG_CNTP_TVAL_S)
3136 .unimplemented()
3137 .bankedChild()
3138 .secure().user(1);
3139 InitReg(MISCREG_CNTP_CTL)
3140 .banked();
3141 InitReg(MISCREG_CNTP_CTL_NS)
3142 .bankedChild()
3143 .allPrivileges().monSecure(0).privSecure(0);
3144 InitReg(MISCREG_CNTP_CTL_S)
3145 .unimplemented()
3146 .bankedChild()
3147 .secure().user(1);
3148 InitReg(MISCREG_CNTV_TVAL)
3149 .allPrivileges();
3150 InitReg(MISCREG_CNTV_CTL)
3151 .allPrivileges();
3152 InitReg(MISCREG_CNTHCTL)
3153 .unimplemented()
3154 .hypWrite().monNonSecureRead();
3155 InitReg(MISCREG_CNTHP_TVAL)
3156 .unimplemented()
3157 .hypWrite().monNonSecureRead();
3158 InitReg(MISCREG_CNTHP_CTL)
3159 .unimplemented()
3160 .hypWrite().monNonSecureRead();
3161 InitReg(MISCREG_IL1DATA0)
3162 .unimplemented()
3163 .allPrivileges().exceptUserMode();
3164 InitReg(MISCREG_IL1DATA1)
3165 .unimplemented()
3166 .allPrivileges().exceptUserMode();
3167 InitReg(MISCREG_IL1DATA2)
3168 .unimplemented()
3169 .allPrivileges().exceptUserMode();
3170 InitReg(MISCREG_IL1DATA3)
3171 .unimplemented()
3172 .allPrivileges().exceptUserMode();
3173 InitReg(MISCREG_DL1DATA0)
3174 .unimplemented()
3175 .allPrivileges().exceptUserMode();
3176 InitReg(MISCREG_DL1DATA1)
3177 .unimplemented()
3178 .allPrivileges().exceptUserMode();
3179 InitReg(MISCREG_DL1DATA2)
3180 .unimplemented()
3181 .allPrivileges().exceptUserMode();
3182 InitReg(MISCREG_DL1DATA3)
3183 .unimplemented()
3184 .allPrivileges().exceptUserMode();
3185 InitReg(MISCREG_DL1DATA4)
3186 .unimplemented()
3187 .allPrivileges().exceptUserMode();
3188 InitReg(MISCREG_RAMINDEX)
3189 .unimplemented()
3190 .writes(1).exceptUserMode();
3191 InitReg(MISCREG_L2ACTLR)
3192 .unimplemented()
3193 .allPrivileges().exceptUserMode();
3194 InitReg(MISCREG_CBAR)
3195 .unimplemented()
3196 .allPrivileges().exceptUserMode().writes(0);
3197 InitReg(MISCREG_HTTBR)
3198 .hyp().monNonSecure();
3199 InitReg(MISCREG_VTTBR)
3200 .hyp().monNonSecure();
3201 InitReg(MISCREG_CNTPCT)
3202 .reads(1);
3203 InitReg(MISCREG_CNTVCT)
3204 .unverifiable()
3205 .reads(1);
3206 InitReg(MISCREG_CNTP_CVAL)
3207 .banked();
3208 InitReg(MISCREG_CNTP_CVAL_NS)
3209 .bankedChild()
3210 .allPrivileges().monSecure(0).privSecure(0);
3211 InitReg(MISCREG_CNTP_CVAL_S)
3212 .unimplemented()
3213 .bankedChild()
3214 .secure().user(1);
3215 InitReg(MISCREG_CNTV_CVAL)
3216 .allPrivileges();
3217 InitReg(MISCREG_CNTVOFF)
3218 .hyp().monNonSecure();
3219 InitReg(MISCREG_CNTHP_CVAL)
3220 .unimplemented()
3221 .hypWrite().monNonSecureRead();
3222 InitReg(MISCREG_CPUMERRSR)
3223 .unimplemented()
3224 .allPrivileges().exceptUserMode();
3225 InitReg(MISCREG_L2MERRSR)
3226 .unimplemented()
3227 .warnNotFail()
3228 .allPrivileges().exceptUserMode();
3229
3230 // AArch64 registers (Op0=2);
3231 InitReg(MISCREG_MDCCINT_EL1)
3232 .allPrivileges();
3233 InitReg(MISCREG_OSDTRRX_EL1)
3234 .allPrivileges()
3235 .mapsTo(MISCREG_DBGDTRRXext);
3236 InitReg(MISCREG_MDSCR_EL1)
3237 .allPrivileges()
3238 .mapsTo(MISCREG_DBGDSCRext);
3239 InitReg(MISCREG_OSDTRTX_EL1)
3240 .allPrivileges()
3241 .mapsTo(MISCREG_DBGDTRTXext);
3242 InitReg(MISCREG_OSECCR_EL1)
3243 .allPrivileges()
3244 .mapsTo(MISCREG_DBGOSECCR);
3245 InitReg(MISCREG_DBGBVR0_EL1)
3246 .allPrivileges()
3247 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3248 InitReg(MISCREG_DBGBVR1_EL1)
3249 .allPrivileges()
3250 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3251 InitReg(MISCREG_DBGBVR2_EL1)
3252 .allPrivileges()
3253 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3254 InitReg(MISCREG_DBGBVR3_EL1)
3255 .allPrivileges()
3256 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3257 InitReg(MISCREG_DBGBVR4_EL1)
3258 .allPrivileges()
3259 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3260 InitReg(MISCREG_DBGBVR5_EL1)
3261 .allPrivileges()
3262 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3263 InitReg(MISCREG_DBGBCR0_EL1)
3264 .allPrivileges()
3265 .mapsTo(MISCREG_DBGBCR0);
3266 InitReg(MISCREG_DBGBCR1_EL1)
3267 .allPrivileges()
3268 .mapsTo(MISCREG_DBGBCR1);
3269 InitReg(MISCREG_DBGBCR2_EL1)
3270 .allPrivileges()
3271 .mapsTo(MISCREG_DBGBCR2);
3272 InitReg(MISCREG_DBGBCR3_EL1)
3273 .allPrivileges()
3274 .mapsTo(MISCREG_DBGBCR3);
3275 InitReg(MISCREG_DBGBCR4_EL1)
3276 .allPrivileges()
3277 .mapsTo(MISCREG_DBGBCR4);
3278 InitReg(MISCREG_DBGBCR5_EL1)
3279 .allPrivileges()
3280 .mapsTo(MISCREG_DBGBCR5);
3281 InitReg(MISCREG_DBGWVR0_EL1)
3282 .allPrivileges()
3283 .mapsTo(MISCREG_DBGWVR0);
3284 InitReg(MISCREG_DBGWVR1_EL1)
3285 .allPrivileges()
3286 .mapsTo(MISCREG_DBGWVR1);
3287 InitReg(MISCREG_DBGWVR2_EL1)
3288 .allPrivileges()
3289 .mapsTo(MISCREG_DBGWVR2);
3290 InitReg(MISCREG_DBGWVR3_EL1)
3291 .allPrivileges()
3292 .mapsTo(MISCREG_DBGWVR3);
3293 InitReg(MISCREG_DBGWCR0_EL1)
3294 .allPrivileges()
3295 .mapsTo(MISCREG_DBGWCR0);
3296 InitReg(MISCREG_DBGWCR1_EL1)
3297 .allPrivileges()
3298 .mapsTo(MISCREG_DBGWCR1);
3299 InitReg(MISCREG_DBGWCR2_EL1)
3300 .allPrivileges()
3301 .mapsTo(MISCREG_DBGWCR2);
3302 InitReg(MISCREG_DBGWCR3_EL1)
3303 .allPrivileges()
3304 .mapsTo(MISCREG_DBGWCR3);
3305 InitReg(MISCREG_MDCCSR_EL0)
3306 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3307 .mapsTo(MISCREG_DBGDSCRint);
3308 InitReg(MISCREG_MDDTR_EL0)
3309 .allPrivileges();
3310 InitReg(MISCREG_MDDTRTX_EL0)
3311 .allPrivileges();
3312 InitReg(MISCREG_MDDTRRX_EL0)
3313 .allPrivileges();
3314 InitReg(MISCREG_DBGVCR32_EL2)
3315 .allPrivileges()
3316 .mapsTo(MISCREG_DBGVCR);
3317 InitReg(MISCREG_MDRAR_EL1)
3318 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3319 .mapsTo(MISCREG_DBGDRAR);
3320 InitReg(MISCREG_OSLAR_EL1)
3321 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3322 .mapsTo(MISCREG_DBGOSLAR);
3323 InitReg(MISCREG_OSLSR_EL1)
3324 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3325 .mapsTo(MISCREG_DBGOSLSR);
3326 InitReg(MISCREG_OSDLR_EL1)
3327 .allPrivileges()
3328 .mapsTo(MISCREG_DBGOSDLR);
3329 InitReg(MISCREG_DBGPRCR_EL1)
3330 .allPrivileges()
3331 .mapsTo(MISCREG_DBGPRCR);
3332 InitReg(MISCREG_DBGCLAIMSET_EL1)
3333 .allPrivileges()
3334 .mapsTo(MISCREG_DBGCLAIMSET);
3335 InitReg(MISCREG_DBGCLAIMCLR_EL1)
3336 .allPrivileges()
3337 .mapsTo(MISCREG_DBGCLAIMCLR);
3338 InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3339 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3340 .mapsTo(MISCREG_DBGAUTHSTATUS);
3341 InitReg(MISCREG_TEECR32_EL1);
3342 InitReg(MISCREG_TEEHBR32_EL1);
3343
3344 // AArch64 registers (Op0=1,3);
3345 InitReg(MISCREG_MIDR_EL1)
3346 .allPrivileges().exceptUserMode().writes(0);
3347 InitReg(MISCREG_MPIDR_EL1)
3348 .allPrivileges().exceptUserMode().writes(0);
3349 InitReg(MISCREG_REVIDR_EL1)
3350 .allPrivileges().exceptUserMode().writes(0);
3351 InitReg(MISCREG_ID_PFR0_EL1)
3352 .allPrivileges().exceptUserMode().writes(0);
3353 InitReg(MISCREG_ID_PFR1_EL1)
3354 .allPrivileges().exceptUserMode().writes(0);
3355 InitReg(MISCREG_ID_DFR0_EL1)
3356 .allPrivileges().exceptUserMode().writes(0)
3357 .mapsTo(MISCREG_ID_DFR0);
3358 InitReg(MISCREG_ID_AFR0_EL1)
3359 .allPrivileges().exceptUserMode().writes(0);
3360 InitReg(MISCREG_ID_MMFR0_EL1)
3361 .allPrivileges().exceptUserMode().writes(0);
3362 InitReg(MISCREG_ID_MMFR1_EL1)
3363 .allPrivileges().exceptUserMode().writes(0);
3364 InitReg(MISCREG_ID_MMFR2_EL1)
3365 .allPrivileges().exceptUserMode().writes(0);
3366 InitReg(MISCREG_ID_MMFR3_EL1)
3367 .allPrivileges().exceptUserMode().writes(0);
3368 InitReg(MISCREG_ID_ISAR0_EL1)
3369 .allPrivileges().exceptUserMode().writes(0);
3370 InitReg(MISCREG_ID_ISAR1_EL1)
3371 .allPrivileges().exceptUserMode().writes(0);
3372 InitReg(MISCREG_ID_ISAR2_EL1)
3373 .allPrivileges().exceptUserMode().writes(0);
3374 InitReg(MISCREG_ID_ISAR3_EL1)
3375 .allPrivileges().exceptUserMode().writes(0);
3376 InitReg(MISCREG_ID_ISAR4_EL1)
3377 .allPrivileges().exceptUserMode().writes(0);
3378 InitReg(MISCREG_ID_ISAR5_EL1)
3379 .allPrivileges().exceptUserMode().writes(0);
3380 InitReg(MISCREG_MVFR0_EL1)
3381 .allPrivileges().exceptUserMode().writes(0);
3382 InitReg(MISCREG_MVFR1_EL1)
3383 .allPrivileges().exceptUserMode().writes(0);
3384 InitReg(MISCREG_MVFR2_EL1)
3385 .allPrivileges().exceptUserMode().writes(0);
3386 InitReg(MISCREG_ID_AA64PFR0_EL1)
3387 .allPrivileges().exceptUserMode().writes(0);
3388 InitReg(MISCREG_ID_AA64PFR1_EL1)
3389 .allPrivileges().exceptUserMode().writes(0);
3390 InitReg(MISCREG_ID_AA64DFR0_EL1)
3391 .allPrivileges().exceptUserMode().writes(0);
3392 InitReg(MISCREG_ID_AA64DFR1_EL1)
3393 .allPrivileges().exceptUserMode().writes(0);
3394 InitReg(MISCREG_ID_AA64AFR0_EL1)
3395 .allPrivileges().exceptUserMode().writes(0);
3396 InitReg(MISCREG_ID_AA64AFR1_EL1)
3397 .allPrivileges().exceptUserMode().writes(0);
3398 InitReg(MISCREG_ID_AA64ISAR0_EL1)
3399 .allPrivileges().exceptUserMode().writes(0);
3400 InitReg(MISCREG_ID_AA64ISAR1_EL1)
3401 .allPrivileges().exceptUserMode().writes(0);
3402 InitReg(MISCREG_ID_AA64MMFR0_EL1)
3403 .allPrivileges().exceptUserMode().writes(0);
3404 InitReg(MISCREG_ID_AA64MMFR1_EL1)
3405 .allPrivileges().exceptUserMode().writes(0);
3406 InitReg(MISCREG_CCSIDR_EL1)
3407 .allPrivileges().exceptUserMode().writes(0);
3408 InitReg(MISCREG_CLIDR_EL1)
3409 .allPrivileges().exceptUserMode().writes(0);
3410 InitReg(MISCREG_AIDR_EL1)
3411 .allPrivileges().exceptUserMode().writes(0);
3412 InitReg(MISCREG_CSSELR_EL1)
3413 .allPrivileges().exceptUserMode()
3414 .mapsTo(MISCREG_CSSELR_NS);
3415 InitReg(MISCREG_CTR_EL0)
3416 .reads(1);
3417 InitReg(MISCREG_DCZID_EL0)
3418 .reads(1);
3419 InitReg(MISCREG_VPIDR_EL2)
3420 .hyp().mon()
3421 .mapsTo(MISCREG_VPIDR);
3422 InitReg(MISCREG_VMPIDR_EL2)
3423 .hyp().mon()
3424 .mapsTo(MISCREG_VMPIDR);
3425 InitReg(MISCREG_SCTLR_EL1)
3426 .allPrivileges().exceptUserMode()
3427 .mapsTo(MISCREG_SCTLR_NS);
3428 InitReg(MISCREG_ACTLR_EL1)
3429 .allPrivileges().exceptUserMode()
3430 .mapsTo(MISCREG_ACTLR_NS);
3431 InitReg(MISCREG_CPACR_EL1)
3432 .allPrivileges().exceptUserMode()
3433 .mapsTo(MISCREG_CPACR);
3434 InitReg(MISCREG_SCTLR_EL2)
3435 .hyp().mon()
3436 .mapsTo(MISCREG_HSCTLR);
3437 InitReg(MISCREG_ACTLR_EL2)
3438 .hyp().mon()
3439 .mapsTo(MISCREG_HACTLR);
3440 InitReg(MISCREG_HCR_EL2)
3441 .hyp().mon()
3442 .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
3443 InitReg(MISCREG_MDCR_EL2)
3444 .hyp().mon()
3445 .mapsTo(MISCREG_HDCR);
3446 InitReg(MISCREG_CPTR_EL2)
3447 .hyp().mon()
3448 .mapsTo(MISCREG_HCPTR);
3449 InitReg(MISCREG_HSTR_EL2)
3450 .hyp().mon()
3451 .mapsTo(MISCREG_HSTR);
3452 InitReg(MISCREG_HACR_EL2)
3453 .hyp().mon()
3454 .mapsTo(MISCREG_HACR);
3455 InitReg(MISCREG_SCTLR_EL3)
3456 .mon();
3457 InitReg(MISCREG_ACTLR_EL3)
3458 .mon();
3459 InitReg(MISCREG_SCR_EL3)
3460 .mon()
3461 .mapsTo(MISCREG_SCR); // NAM D7-2005
3462 InitReg(MISCREG_SDER32_EL3)
3463 .mon()
3464 .mapsTo(MISCREG_SDER);
3465 InitReg(MISCREG_CPTR_EL3)
3466 .mon();
3467 InitReg(MISCREG_MDCR_EL3)
3468 .mon();
3469 InitReg(MISCREG_TTBR0_EL1)
3470 .allPrivileges().exceptUserMode()
3471 .mapsTo(MISCREG_TTBR0_NS);
3472 InitReg(MISCREG_TTBR1_EL1)
3473 .allPrivileges().exceptUserMode()
3474 .mapsTo(MISCREG_TTBR1_NS);
3475 InitReg(MISCREG_TCR_EL1)
3476 .allPrivileges().exceptUserMode()
3477 .mapsTo(MISCREG_TTBCR_NS);
3478 InitReg(MISCREG_TTBR0_EL2)
3479 .hyp().mon()
3480 .mapsTo(MISCREG_HTTBR);
3481 InitReg(MISCREG_TCR_EL2)
3482 .hyp().mon()
3483 .mapsTo(MISCREG_HTCR);
3484 InitReg(MISCREG_VTTBR_EL2)
3485 .hyp().mon()
3486 .mapsTo(MISCREG_VTTBR);
3487 InitReg(MISCREG_VTCR_EL2)
3488 .hyp().mon()
3489 .mapsTo(MISCREG_VTCR);
3490 InitReg(MISCREG_TTBR0_EL3)
3491 .mon();
3492 InitReg(MISCREG_TCR_EL3)
3493 .mon();
3494 InitReg(MISCREG_DACR32_EL2)
3495 .hyp().mon()
3496 .mapsTo(MISCREG_DACR_NS);
3497 InitReg(MISCREG_SPSR_EL1)
3498 .allPrivileges().exceptUserMode()
3499 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
3500 InitReg(MISCREG_ELR_EL1)
3501 .allPrivileges().exceptUserMode();
3502 InitReg(MISCREG_SP_EL0)
3503 .allPrivileges().exceptUserMode();
3504 InitReg(MISCREG_SPSEL)
3505 .allPrivileges().exceptUserMode();
3506 InitReg(MISCREG_CURRENTEL)
3507 .allPrivileges().exceptUserMode().writes(0);
3508 InitReg(MISCREG_NZCV)
3509 .allPrivileges();
3510 InitReg(MISCREG_DAIF)
3511 .allPrivileges();
3512 InitReg(MISCREG_FPCR)
3513 .allPrivileges();
3514 InitReg(MISCREG_FPSR)
3515 .allPrivileges();
3516 InitReg(MISCREG_DSPSR_EL0)
3517 .allPrivileges();
3518 InitReg(MISCREG_DLR_EL0)
3519 .allPrivileges();
3520 InitReg(MISCREG_SPSR_EL2)
3521 .hyp().mon()
3522 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
3523 InitReg(MISCREG_ELR_EL2)
3524 .hyp().mon();
3525 InitReg(MISCREG_SP_EL1)
3526 .hyp().mon();
3527 InitReg(MISCREG_SPSR_IRQ_AA64)
3528 .hyp().mon();
3529 InitReg(MISCREG_SPSR_ABT_AA64)
3530 .hyp().mon();
3531 InitReg(MISCREG_SPSR_UND_AA64)
3532 .hyp().mon();
3533 InitReg(MISCREG_SPSR_FIQ_AA64)
3534 .hyp().mon();
3535 InitReg(MISCREG_SPSR_EL3)
3536 .mon()
3537 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
3538 InitReg(MISCREG_ELR_EL3)
3539 .mon();
3540 InitReg(MISCREG_SP_EL2)
3541 .mon();
3542 InitReg(MISCREG_AFSR0_EL1)
3543 .allPrivileges().exceptUserMode()
3544 .mapsTo(MISCREG_ADFSR_NS);
3545 InitReg(MISCREG_AFSR1_EL1)
3546 .allPrivileges().exceptUserMode()
3547 .mapsTo(MISCREG_AIFSR_NS);
3548 InitReg(MISCREG_ESR_EL1)
3549 .allPrivileges().exceptUserMode();
3550 InitReg(MISCREG_IFSR32_EL2)
3551 .hyp().mon()
3552 .mapsTo(MISCREG_IFSR_NS);
3553 InitReg(MISCREG_AFSR0_EL2)
3554 .hyp().mon()
3555 .mapsTo(MISCREG_HADFSR);
3556 InitReg(MISCREG_AFSR1_EL2)
3557 .hyp().mon()
3558 .mapsTo(MISCREG_HAIFSR);
3559 InitReg(MISCREG_ESR_EL2)
3560 .hyp().mon()
3561 .mapsTo(MISCREG_HSR);
3562 InitReg(MISCREG_FPEXC32_EL2)
3563 .hyp().mon();
3564 InitReg(MISCREG_AFSR0_EL3)
3565 .mon();
3566 InitReg(MISCREG_AFSR1_EL3)
3567 .mon();
3568 InitReg(MISCREG_ESR_EL3)
3569 .mon();
3570 InitReg(MISCREG_FAR_EL1)
3571 .allPrivileges().exceptUserMode()
3572 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
3573 InitReg(MISCREG_FAR_EL2)
3574 .hyp().mon()
3575 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
3576 InitReg(MISCREG_HPFAR_EL2)
3577 .hyp().mon()
3578 .mapsTo(MISCREG_HPFAR);
3579 InitReg(MISCREG_FAR_EL3)
3580 .mon();
3581 InitReg(MISCREG_IC_IALLUIS)
3582 .warnNotFail()
3583 .writes(1).exceptUserMode();
3584 InitReg(MISCREG_PAR_EL1)
3585 .allPrivileges().exceptUserMode()
3586 .mapsTo(MISCREG_PAR_NS);
3587 InitReg(MISCREG_IC_IALLU)
3588 .warnNotFail()
3589 .writes(1).exceptUserMode();
3590 InitReg(MISCREG_DC_IVAC_Xt)
3591 .warnNotFail()
3592 .writes(1).exceptUserMode();
3593 InitReg(MISCREG_DC_ISW_Xt)
3594 .warnNotFail()
3595 .writes(1).exceptUserMode();
3596 InitReg(MISCREG_AT_S1E1R_Xt)
3597 .writes(1).exceptUserMode();
3598 InitReg(MISCREG_AT_S1E1W_Xt)
3599 .writes(1).exceptUserMode();
3600 InitReg(MISCREG_AT_S1E0R_Xt)
3601 .writes(1).exceptUserMode();
3602 InitReg(MISCREG_AT_S1E0W_Xt)
3603 .writes(1).exceptUserMode();
3604 InitReg(MISCREG_DC_CSW_Xt)
3605 .warnNotFail()
3606 .writes(1).exceptUserMode();
3607 InitReg(MISCREG_DC_CISW_Xt)
3608 .warnNotFail()
3609 .writes(1).exceptUserMode();
3610 InitReg(MISCREG_DC_ZVA_Xt)
3611 .warnNotFail()
3612 .writes(1).userSecureWrite(0);
3613 InitReg(MISCREG_IC_IVAU_Xt)
3614 .writes(1);
3615 InitReg(MISCREG_DC_CVAC_Xt)
3616 .warnNotFail()
3617 .writes(1);
3618 InitReg(MISCREG_DC_CVAU_Xt)
3619 .warnNotFail()
3620 .writes(1);
3621 InitReg(MISCREG_DC_CIVAC_Xt)
3622 .warnNotFail()
3623 .writes(1);
3624 InitReg(MISCREG_AT_S1E2R_Xt)
3625 .monNonSecureWrite().hypWrite();
3626 InitReg(MISCREG_AT_S1E2W_Xt)
3627 .monNonSecureWrite().hypWrite();
3628 InitReg(MISCREG_AT_S12E1R_Xt)
3629 .hypWrite().monSecureWrite().monNonSecureWrite();
3630 InitReg(MISCREG_AT_S12E1W_Xt)
3631 .hypWrite().monSecureWrite().monNonSecureWrite();
3632 InitReg(MISCREG_AT_S12E0R_Xt)
3633 .hypWrite().monSecureWrite().monNonSecureWrite();
3634 InitReg(MISCREG_AT_S12E0W_Xt)
3635 .hypWrite().monSecureWrite().monNonSecureWrite();
3636 InitReg(MISCREG_AT_S1E3R_Xt)
3637 .monSecureWrite().monNonSecureWrite();
3638 InitReg(MISCREG_AT_S1E3W_Xt)
3639 .monSecureWrite().monNonSecureWrite();
3640 InitReg(MISCREG_TLBI_VMALLE1IS)
3641 .writes(1).exceptUserMode();
3642 InitReg(MISCREG_TLBI_VAE1IS_Xt)
3643 .writes(1).exceptUserMode();
3644 InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
3645 .writes(1).exceptUserMode();
3646 InitReg(MISCREG_TLBI_VAAE1IS_Xt)
3647 .writes(1).exceptUserMode();
3648 InitReg(MISCREG_TLBI_VALE1IS_Xt)
3649 .writes(1).exceptUserMode();
3650 InitReg(MISCREG_TLBI_VAALE1IS_Xt)
3651 .writes(1).exceptUserMode();
3652 InitReg(MISCREG_TLBI_VMALLE1)
3653 .writes(1).exceptUserMode();
3654 InitReg(MISCREG_TLBI_VAE1_Xt)
3655 .writes(1).exceptUserMode();
3656 InitReg(MISCREG_TLBI_ASIDE1_Xt)
3657 .writes(1).exceptUserMode();
3658 InitReg(MISCREG_TLBI_VAAE1_Xt)
3659 .writes(1).exceptUserMode();
3660 InitReg(MISCREG_TLBI_VALE1_Xt)
3661 .writes(1).exceptUserMode();
3662 InitReg(MISCREG_TLBI_VAALE1_Xt)
3663 .writes(1).exceptUserMode();
3664 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
3665 .hypWrite().monSecureWrite().monNonSecureWrite();
3666 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
3667 .hypWrite().monSecureWrite().monNonSecureWrite();
3668 InitReg(MISCREG_TLBI_ALLE2IS)
3669 .monNonSecureWrite().hypWrite();
3670 InitReg(MISCREG_TLBI_VAE2IS_Xt)
3671 .monNonSecureWrite().hypWrite();
3672 InitReg(MISCREG_TLBI_ALLE1IS)
3673 .hypWrite().monSecureWrite().monNonSecureWrite();
3674 InitReg(MISCREG_TLBI_VALE2IS_Xt)
3675 .monNonSecureWrite().hypWrite();
3676 InitReg(MISCREG_TLBI_VMALLS12E1IS)
3677 .hypWrite().monSecureWrite().monNonSecureWrite();
3678 InitReg(MISCREG_TLBI_IPAS2E1_Xt)
3679 .hypWrite().monSecureWrite().monNonSecureWrite();
3680 InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
3681 .hypWrite().monSecureWrite().monNonSecureWrite();
3682 InitReg(MISCREG_TLBI_ALLE2)
3683 .monNonSecureWrite().hypWrite();
3684 InitReg(MISCREG_TLBI_VAE2_Xt)
3685 .monNonSecureWrite().hypWrite();
3686 InitReg(MISCREG_TLBI_ALLE1)
3687 .hypWrite().monSecureWrite().monNonSecureWrite();
3688 InitReg(MISCREG_TLBI_VALE2_Xt)
3689 .monNonSecureWrite().hypWrite();
3690 InitReg(MISCREG_TLBI_VMALLS12E1)
3691 .hypWrite().monSecureWrite().monNonSecureWrite();
3692 InitReg(MISCREG_TLBI_ALLE3IS)
3693 .monSecureWrite().monNonSecureWrite();
3694 InitReg(MISCREG_TLBI_VAE3IS_Xt)
3695 .monSecureWrite().monNonSecureWrite();
3696 InitReg(MISCREG_TLBI_VALE3IS_Xt)
3697 .monSecureWrite().monNonSecureWrite();
3698 InitReg(MISCREG_TLBI_ALLE3)
3699 .monSecureWrite().monNonSecureWrite();
3700 InitReg(MISCREG_TLBI_VAE3_Xt)
3701 .monSecureWrite().monNonSecureWrite();
3702 InitReg(MISCREG_TLBI_VALE3_Xt)
3703 .monSecureWrite().monNonSecureWrite();
3704 InitReg(MISCREG_PMINTENSET_EL1)
3705 .allPrivileges().exceptUserMode()
3706 .mapsTo(MISCREG_PMINTENSET);
3707 InitReg(MISCREG_PMINTENCLR_EL1)
3708 .allPrivileges().exceptUserMode()
3709 .mapsTo(MISCREG_PMINTENCLR);
3710 InitReg(MISCREG_PMCR_EL0)
3711 .allPrivileges()
3712 .mapsTo(MISCREG_PMCR);
3713 InitReg(MISCREG_PMCNTENSET_EL0)
3714 .allPrivileges()
3715 .mapsTo(MISCREG_PMCNTENSET);
3716 InitReg(MISCREG_PMCNTENCLR_EL0)
3717 .allPrivileges()
3718 .mapsTo(MISCREG_PMCNTENCLR);
3719 InitReg(MISCREG_PMOVSCLR_EL0)
3720 .allPrivileges();
3721// .mapsTo(MISCREG_PMOVSCLR);
3722 InitReg(MISCREG_PMSWINC_EL0)
3723 .writes(1).user()
3724 .mapsTo(MISCREG_PMSWINC);
3725 InitReg(MISCREG_PMSELR_EL0)
3726 .allPrivileges()
3727 .mapsTo(MISCREG_PMSELR);
3728 InitReg(MISCREG_PMCEID0_EL0)
3729 .reads(1).user()
3730 .mapsTo(MISCREG_PMCEID0);
3731 InitReg(MISCREG_PMCEID1_EL0)
3732 .reads(1).user()
3733 .mapsTo(MISCREG_PMCEID1);
3734 InitReg(MISCREG_PMCCNTR_EL0)
3735 .allPrivileges()
3736 .mapsTo(MISCREG_PMCCNTR);
3737 InitReg(MISCREG_PMXEVTYPER_EL0)
3738 .allPrivileges()
3739 .mapsTo(MISCREG_PMXEVTYPER);
3740 InitReg(MISCREG_PMCCFILTR_EL0)
3741 .allPrivileges();
3742 InitReg(MISCREG_PMXEVCNTR_EL0)
3743 .allPrivileges()
3744 .mapsTo(MISCREG_PMXEVCNTR);
3745 InitReg(MISCREG_PMUSERENR_EL0)
3746 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3747 .mapsTo(MISCREG_PMUSERENR);
3748 InitReg(MISCREG_PMOVSSET_EL0)
3749 .allPrivileges()
3750 .mapsTo(MISCREG_PMOVSSET);
3751 InitReg(MISCREG_MAIR_EL1)
3752 .allPrivileges().exceptUserMode()
3753 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
3754 InitReg(MISCREG_AMAIR_EL1)
3755 .allPrivileges().exceptUserMode()
3756 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
3757 InitReg(MISCREG_MAIR_EL2)
3758 .hyp().mon()
3759 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
3760 InitReg(MISCREG_AMAIR_EL2)
3761 .hyp().mon()
3762 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
3763 InitReg(MISCREG_MAIR_EL3)
3764 .mon();
3765 InitReg(MISCREG_AMAIR_EL3)
3766 .mon();
3767 InitReg(MISCREG_L2CTLR_EL1)
3768 .allPrivileges().exceptUserMode();
3769 InitReg(MISCREG_L2ECTLR_EL1)
3770 .allPrivileges().exceptUserMode();
3771 InitReg(MISCREG_VBAR_EL1)
3772 .allPrivileges().exceptUserMode()
3773 .mapsTo(MISCREG_VBAR_NS);
3774 InitReg(MISCREG_RVBAR_EL1)
3775 .allPrivileges().exceptUserMode().writes(0);
3776 InitReg(MISCREG_ISR_EL1)
3777 .allPrivileges().exceptUserMode().writes(0);
3778 InitReg(MISCREG_VBAR_EL2)
3779 .hyp().mon()
3780 .mapsTo(MISCREG_HVBAR);
3781 InitReg(MISCREG_RVBAR_EL2)
3782 .mon().hyp().writes(0);
3783 InitReg(MISCREG_VBAR_EL3)
3784 .mon();
3785 InitReg(MISCREG_RVBAR_EL3)
3786 .mon().writes(0);
3787 InitReg(MISCREG_RMR_EL3)
3788 .mon();
3789 InitReg(MISCREG_CONTEXTIDR_EL1)
3790 .allPrivileges().exceptUserMode()
3791 .mapsTo(MISCREG_CONTEXTIDR_NS);
3792 InitReg(MISCREG_TPIDR_EL1)
3793 .allPrivileges().exceptUserMode()
3794 .mapsTo(MISCREG_TPIDRPRW_NS);
3795 InitReg(MISCREG_TPIDR_EL0)
3796 .allPrivileges()
3797 .mapsTo(MISCREG_TPIDRURW_NS);
3798 InitReg(MISCREG_TPIDRRO_EL0)
3799 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3800 .mapsTo(MISCREG_TPIDRURO_NS);
3801 InitReg(MISCREG_TPIDR_EL2)
3802 .hyp().mon()
3803 .mapsTo(MISCREG_HTPIDR);
3804 InitReg(MISCREG_TPIDR_EL3)
3805 .mon();
3806 InitReg(MISCREG_CNTKCTL_EL1)
3807 .allPrivileges().exceptUserMode()
3808 .mapsTo(MISCREG_CNTKCTL);
3809 InitReg(MISCREG_CNTFRQ_EL0)
3810 .reads(1).mon()
3811 .mapsTo(MISCREG_CNTFRQ);
3812 InitReg(MISCREG_CNTPCT_EL0)
3813 .reads(1)
3814 .mapsTo(MISCREG_CNTPCT); /* 64b */
3815 InitReg(MISCREG_CNTVCT_EL0)
3816 .unverifiable()
3817 .reads(1)
3818 .mapsTo(MISCREG_CNTVCT); /* 64b */
3819 InitReg(MISCREG_CNTP_TVAL_EL0)
3820 .allPrivileges()
3821 .mapsTo(MISCREG_CNTP_TVAL_NS);
3822 InitReg(MISCREG_CNTP_CTL_EL0)
3823 .allPrivileges()
3824 .mapsTo(MISCREG_CNTP_CTL_NS);
3825 InitReg(MISCREG_CNTP_CVAL_EL0)
3826 .allPrivileges()
3827 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
3828 InitReg(MISCREG_CNTV_TVAL_EL0)
3829 .allPrivileges()
3830 .mapsTo(MISCREG_CNTV_TVAL);
3831 InitReg(MISCREG_CNTV_CTL_EL0)
3832 .allPrivileges()
3833 .mapsTo(MISCREG_CNTV_CTL);
3834 InitReg(MISCREG_CNTV_CVAL_EL0)
3835 .allPrivileges()
3836 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
3837 InitReg(MISCREG_PMEVCNTR0_EL0)
3838 .allPrivileges();
3839// .mapsTo(MISCREG_PMEVCNTR0);
3840 InitReg(MISCREG_PMEVCNTR1_EL0)
3841 .allPrivileges();
3842// .mapsTo(MISCREG_PMEVCNTR1);
3843 InitReg(MISCREG_PMEVCNTR2_EL0)
3844 .allPrivileges();
3845// .mapsTo(MISCREG_PMEVCNTR2);
3846 InitReg(MISCREG_PMEVCNTR3_EL0)
3847 .allPrivileges();
3848// .mapsTo(MISCREG_PMEVCNTR3);
3849 InitReg(MISCREG_PMEVCNTR4_EL0)
3850 .allPrivileges();
3851// .mapsTo(MISCREG_PMEVCNTR4);
3852 InitReg(MISCREG_PMEVCNTR5_EL0)
3853 .allPrivileges();
3854// .mapsTo(MISCREG_PMEVCNTR5);
3855 InitReg(MISCREG_PMEVTYPER0_EL0)
3856 .allPrivileges();
3857// .mapsTo(MISCREG_PMEVTYPER0);
3858 InitReg(MISCREG_PMEVTYPER1_EL0)
3859 .allPrivileges();
3860// .mapsTo(MISCREG_PMEVTYPER1);
3861 InitReg(MISCREG_PMEVTYPER2_EL0)
3862 .allPrivileges();
3863// .mapsTo(MISCREG_PMEVTYPER2);
3864 InitReg(MISCREG_PMEVTYPER3_EL0)
3865 .allPrivileges();
3866// .mapsTo(MISCREG_PMEVTYPER3);
3867 InitReg(MISCREG_PMEVTYPER4_EL0)
3868 .allPrivileges();
3869// .mapsTo(MISCREG_PMEVTYPER4);
3870 InitReg(MISCREG_PMEVTYPER5_EL0)
3871 .allPrivileges();
3872// .mapsTo(MISCREG_PMEVTYPER5);
3873 InitReg(MISCREG_CNTVOFF_EL2)
3874 .hyp().mon()
3875 .mapsTo(MISCREG_CNTVOFF); /* 64b */
3876 InitReg(MISCREG_CNTHCTL_EL2)
3877 .unimplemented()
3878 .warnNotFail()
3879 .mon().monNonSecureWrite(0).hypWrite()
3880 .mapsTo(MISCREG_CNTHCTL);
3881 InitReg(MISCREG_CNTHP_TVAL_EL2)
3882 .unimplemented()
3883 .mon().monNonSecureWrite(0).hypWrite()
3884 .mapsTo(MISCREG_CNTHP_TVAL);
3885 InitReg(MISCREG_CNTHP_CTL_EL2)
3886 .unimplemented()
3887 .mon().monNonSecureWrite(0).hypWrite()
3888 .mapsTo(MISCREG_CNTHP_CTL);
3889 InitReg(MISCREG_CNTHP_CVAL_EL2)
3890 .unimplemented()
3891 .mon().monNonSecureWrite(0).hypWrite()
3892 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
3893 InitReg(MISCREG_CNTPS_TVAL_EL1)
3894 .unimplemented()
3895 .mon().monNonSecureWrite(0).hypWrite();
3896 InitReg(MISCREG_CNTPS_CTL_EL1)
3897 .unimplemented()
3898 .mon().monNonSecureWrite(0).hypWrite();
3899 InitReg(MISCREG_CNTPS_CVAL_EL1)
3900 .unimplemented()
3901 .mon().monNonSecureWrite(0).hypWrite();
3902 InitReg(MISCREG_IL1DATA0_EL1)
3903 .allPrivileges().exceptUserMode();
3904 InitReg(MISCREG_IL1DATA1_EL1)
3905 .allPrivileges().exceptUserMode();
3906 InitReg(MISCREG_IL1DATA2_EL1)
3907 .allPrivileges().exceptUserMode();
3908 InitReg(MISCREG_IL1DATA3_EL1)
3909 .allPrivileges().exceptUserMode();
3910 InitReg(MISCREG_DL1DATA0_EL1)
3911 .allPrivileges().exceptUserMode();
3912 InitReg(MISCREG_DL1DATA1_EL1)
3913 .allPrivileges().exceptUserMode();
3914 InitReg(MISCREG_DL1DATA2_EL1)
3915 .allPrivileges().exceptUserMode();
3916 InitReg(MISCREG_DL1DATA3_EL1)
3917 .allPrivileges().exceptUserMode();
3918 InitReg(MISCREG_DL1DATA4_EL1)
3919 .allPrivileges().exceptUserMode();
3920 InitReg(MISCREG_L2ACTLR_EL1)
3921 .allPrivileges().exceptUserMode();
3922 InitReg(MISCREG_CPUACTLR_EL1)
3923 .allPrivileges().exceptUserMode();
3924 InitReg(MISCREG_CPUECTLR_EL1)
3925 .allPrivileges().exceptUserMode();
3926 InitReg(MISCREG_CPUMERRSR_EL1)
3927 .allPrivileges().exceptUserMode();
3928 InitReg(MISCREG_L2MERRSR_EL1)
3929 .unimplemented()
3930 .warnNotFail()
3931 .allPrivileges().exceptUserMode();
3932 InitReg(MISCREG_CBAR_EL1)
3933 .allPrivileges().exceptUserMode().writes(0);
3934 InitReg(MISCREG_CONTEXTIDR_EL2)
3935 .mon().hyp();
3936
3937 // Dummy registers
3938 InitReg(MISCREG_NOP)
3939 .allPrivileges();
3940 InitReg(MISCREG_RAZ)
3941 .allPrivileges().exceptUserMode().writes(0);
3942 InitReg(MISCREG_CP14_UNIMPL)
3943 .unimplemented()
3944 .warnNotFail();
3945 InitReg(MISCREG_CP15_UNIMPL)
3946 .unimplemented()
3947 .warnNotFail();
3948 InitReg(MISCREG_A64_UNIMPL)
3949 .unimplemented()
3950 .warnNotFail();
3951 InitReg(MISCREG_UNKNOWN);
3952
3953 // Register mappings for some unimplemented registers:
3954 // ESR_EL1 -> DFSR
3955 // RMR_EL1 -> RMR
3956 // RMR_EL2 -> HRMR
3957 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
3958 // DBGDTRRX_EL0 -> DBGDTRRXint
3959 // DBGDTRTX_EL0 -> DBGDTRRXint
3960 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
3961
3962 completed = true;
3963}
3964
3965} // namespace ArmISA