1/* 2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 273 unchanged lines hidden (view full) --- 282 return MISCREG_VTCR; 283 } 284 break; 285 case 3: 286 if (opc1 == 0 && crm == 0 && opc2 == 0) { 287 return MISCREG_DACR; 288 } 289 break; |
290 case 4: 291 if (opc1 == 0 && crm == 6 && opc2 == 0) { 292 return MISCREG_ICC_PMR; 293 } 294 break; |
295 case 5: 296 if (opc1 == 0) { 297 if (crm == 0) { 298 if (opc2 == 0) { 299 return MISCREG_DFSR; 300 } else if (opc2 == 1) { 301 return MISCREG_IFSR; 302 } --- 365 unchanged lines hidden (view full) --- 668 return MISCREG_VBAR; 669 } else if (opc2 == 1) { 670 return MISCREG_MVBAR; 671 } 672 } else if (crm == 1) { 673 if (opc2 == 0) { 674 return MISCREG_ISR; 675 } |
676 } else if (crm == 8) { 677 switch (opc2) { 678 case 0: 679 return MISCREG_ICC_IAR0; 680 case 1: 681 return MISCREG_ICC_EOIR0; 682 case 2: 683 return MISCREG_ICC_HPPIR0; 684 case 3: 685 return MISCREG_ICC_BPR0; 686 case 4: 687 return MISCREG_ICC_AP0R0; 688 case 5: 689 return MISCREG_ICC_AP0R1; 690 case 6: 691 return MISCREG_ICC_AP0R2; 692 case 7: 693 return MISCREG_ICC_AP0R3; 694 } 695 } else if (crm == 9) { 696 switch (opc2) { 697 case 0: 698 return MISCREG_ICC_AP1R0; 699 case 1: 700 return MISCREG_ICC_AP1R1; 701 case 2: 702 return MISCREG_ICC_AP1R2; 703 case 3: 704 return MISCREG_ICC_AP1R3; 705 } 706 } else if (crm == 11) { 707 switch (opc2) { 708 case 1: 709 return MISCREG_ICC_DIR; 710 case 3: 711 return MISCREG_ICC_RPR; 712 } 713 } else if (crm == 12) { 714 switch (opc2) { 715 case 0: 716 return MISCREG_ICC_IAR1; 717 case 1: 718 return MISCREG_ICC_EOIR1; 719 case 2: 720 return MISCREG_ICC_HPPIR1; 721 case 3: 722 return MISCREG_ICC_BPR1; 723 case 4: 724 return MISCREG_ICC_CTLR; 725 case 5: 726 return MISCREG_ICC_SRE; 727 case 6: 728 return MISCREG_ICC_IGRPEN0; 729 case 7: 730 return MISCREG_ICC_IGRPEN1; 731 } |
732 } 733 } else if (opc1 == 4) { |
734 if (crm == 0 && opc2 == 0) { |
735 return MISCREG_HVBAR; |
736 } else if (crm == 8) { 737 switch (opc2) { 738 case 0: 739 return MISCREG_ICH_AP0R0; 740 case 1: 741 return MISCREG_ICH_AP0R1; 742 case 2: 743 return MISCREG_ICH_AP0R2; 744 case 3: 745 return MISCREG_ICH_AP0R3; 746 } 747 } else if (crm == 9) { 748 switch (opc2) { 749 case 0: 750 return MISCREG_ICH_AP1R0; 751 case 1: 752 return MISCREG_ICH_AP1R1; 753 case 2: 754 return MISCREG_ICH_AP1R2; 755 case 3: 756 return MISCREG_ICH_AP1R3; 757 case 5: 758 return MISCREG_ICC_HSRE; 759 } 760 } else if (crm == 11) { 761 switch (opc2) { 762 case 0: 763 return MISCREG_ICH_HCR; 764 case 1: 765 return MISCREG_ICH_VTR; 766 case 2: 767 return MISCREG_ICH_MISR; 768 case 3: 769 return MISCREG_ICH_EISR; 770 case 5: 771 return MISCREG_ICH_ELRSR; 772 case 7: 773 return MISCREG_ICH_VMCR; 774 } 775 } else if (crm == 12) { 776 switch (opc2) { 777 case 0: 778 return MISCREG_ICH_LR0; 779 case 1: 780 return MISCREG_ICH_LR1; 781 case 2: 782 return MISCREG_ICH_LR2; 783 case 3: 784 return MISCREG_ICH_LR3; 785 case 4: 786 return MISCREG_ICH_LR4; 787 case 5: 788 return MISCREG_ICH_LR5; 789 case 6: 790 return MISCREG_ICH_LR6; 791 case 7: 792 return MISCREG_ICH_LR7; 793 } 794 } else if (crm == 13) { 795 switch (opc2) { 796 case 0: 797 return MISCREG_ICH_LR8; 798 case 1: 799 return MISCREG_ICH_LR9; 800 case 2: 801 return MISCREG_ICH_LR10; 802 case 3: 803 return MISCREG_ICH_LR11; 804 case 4: 805 return MISCREG_ICH_LR12; 806 case 5: 807 return MISCREG_ICH_LR13; 808 case 6: 809 return MISCREG_ICH_LR14; 810 case 7: 811 return MISCREG_ICH_LR15; 812 } 813 } else if (crm == 14) { 814 switch (opc2) { 815 case 0: 816 return MISCREG_ICH_LRC0; 817 case 1: 818 return MISCREG_ICH_LRC1; 819 case 2: 820 return MISCREG_ICH_LRC2; 821 case 3: 822 return MISCREG_ICH_LRC3; 823 case 4: 824 return MISCREG_ICH_LRC4; 825 case 5: 826 return MISCREG_ICH_LRC5; 827 case 6: 828 return MISCREG_ICH_LRC6; 829 case 7: 830 return MISCREG_ICH_LRC7; 831 } 832 } else if (crm == 15) { 833 switch (opc2) { 834 case 0: 835 return MISCREG_ICH_LRC8; 836 case 1: 837 return MISCREG_ICH_LRC9; 838 case 2: 839 return MISCREG_ICH_LRC10; 840 case 3: 841 return MISCREG_ICH_LRC11; 842 case 4: 843 return MISCREG_ICH_LRC12; 844 case 5: 845 return MISCREG_ICH_LRC13; 846 case 6: 847 return MISCREG_ICH_LRC14; 848 case 7: 849 return MISCREG_ICH_LRC15; 850 } 851 } 852 } else if (opc1 == 6) { 853 if (crm == 12) { 854 switch (opc2) { 855 case 4: 856 return MISCREG_ICC_MCTLR; 857 case 5: 858 return MISCREG_ICC_MSRE; 859 case 7: 860 return MISCREG_ICC_MGRPEN1; 861 } 862 } |
863 } 864 break; 865 case 13: 866 if (opc1 == 0) { 867 if (crm == 0) { 868 switch (opc2) { 869 case 0: 870 return MISCREG_FCSEIDR; --- 1078 unchanged lines hidden (view full) --- 1949 case 2: 1950 switch (op2) { 1951 case 0: 1952 return MISCREG_SPSEL; 1953 case 2: 1954 return MISCREG_CURRENTEL; 1955 } 1956 break; |
1957 case 6: 1958 switch (op2) { 1959 case 0: 1960 return MISCREG_ICC_PMR_EL1; 1961 } 1962 break; |
1963 } 1964 break; 1965 case 3: 1966 switch (crm) { 1967 case 2: 1968 switch (op2) { 1969 case 0: 1970 return MISCREG_NZCV; --- 363 unchanged lines hidden (view full) --- 2334 case 1: 2335 switch (op2) { 2336 case 0: 2337 return MISCREG_ISR_EL1; 2338 case 1: 2339 return MISCREG_DISR_EL1; 2340 } 2341 break; |
2342 case 8: 2343 switch (op2) { 2344 case 0: 2345 return MISCREG_ICC_IAR0_EL1; 2346 case 1: 2347 return MISCREG_ICC_EOIR0_EL1; 2348 case 2: 2349 return MISCREG_ICC_HPPIR0_EL1; 2350 case 3: 2351 return MISCREG_ICC_BPR0_EL1; 2352 case 4: 2353 return MISCREG_ICC_AP0R0_EL1; 2354 case 5: 2355 return MISCREG_ICC_AP0R1_EL1; 2356 case 6: 2357 return MISCREG_ICC_AP0R2_EL1; 2358 case 7: 2359 return MISCREG_ICC_AP0R3_EL1; 2360 } 2361 break; 2362 case 9: 2363 switch (op2) { 2364 case 0: 2365 return MISCREG_ICC_AP1R0_EL1; 2366 case 1: 2367 return MISCREG_ICC_AP1R1_EL1; 2368 case 2: 2369 return MISCREG_ICC_AP1R2_EL1; 2370 case 3: 2371 return MISCREG_ICC_AP1R3_EL1; 2372 } 2373 break; 2374 case 11: 2375 switch (op2) { 2376 case 1: 2377 return MISCREG_ICC_DIR_EL1; 2378 case 3: 2379 return MISCREG_ICC_RPR_EL1; 2380 case 5: 2381 return MISCREG_ICC_SGI1R_EL1; 2382 case 6: 2383 return MISCREG_ICC_ASGI1R_EL1; 2384 case 7: 2385 return MISCREG_ICC_SGI0R_EL1; 2386 } 2387 break; 2388 case 12: 2389 switch (op2) { 2390 case 0: 2391 return MISCREG_ICC_IAR1_EL1; 2392 case 1: 2393 return MISCREG_ICC_EOIR1_EL1; 2394 case 2: 2395 return MISCREG_ICC_HPPIR1_EL1; 2396 case 3: 2397 return MISCREG_ICC_BPR1_EL1; 2398 case 4: 2399 return MISCREG_ICC_CTLR_EL1; 2400 case 5: 2401 return MISCREG_ICC_SRE_EL1; 2402 case 6: 2403 return MISCREG_ICC_IGRPEN0_EL1; 2404 case 7: 2405 return MISCREG_ICC_IGRPEN1_EL1; 2406 } 2407 break; |
2408 } 2409 break; 2410 case 4: 2411 switch (crm) { 2412 case 0: 2413 switch (op2) { 2414 case 0: 2415 return MISCREG_VBAR_EL2; 2416 case 1: 2417 return MISCREG_RVBAR_EL2; 2418 } 2419 break; 2420 case 1: 2421 switch (op2) { 2422 case 1: 2423 return MISCREG_VDISR_EL2; 2424 } 2425 break; |
2426 case 8: 2427 switch (op2) { 2428 case 0: 2429 return MISCREG_ICH_AP0R0_EL2; 2430 case 1: 2431 return MISCREG_ICH_AP0R1_EL2; 2432 case 2: 2433 return MISCREG_ICH_AP0R2_EL2; 2434 case 3: 2435 return MISCREG_ICH_AP0R3_EL2; 2436 } 2437 break; 2438 case 9: 2439 switch (op2) { 2440 case 0: 2441 return MISCREG_ICH_AP1R0_EL2; 2442 case 1: 2443 return MISCREG_ICH_AP1R1_EL2; 2444 case 2: 2445 return MISCREG_ICH_AP1R2_EL2; 2446 case 3: 2447 return MISCREG_ICH_AP1R3_EL2; 2448 case 5: 2449 return MISCREG_ICC_SRE_EL2; 2450 } 2451 break; 2452 case 11: 2453 switch (op2) { 2454 case 0: 2455 return MISCREG_ICH_HCR_EL2; 2456 case 1: 2457 return MISCREG_ICH_VTR_EL2; 2458 case 2: 2459 return MISCREG_ICH_MISR_EL2; 2460 case 3: 2461 return MISCREG_ICH_EISR_EL2; 2462 case 5: 2463 return MISCREG_ICH_ELRSR_EL2; 2464 case 7: 2465 return MISCREG_ICH_VMCR_EL2; 2466 } 2467 break; 2468 case 12: 2469 switch (op2) { 2470 case 0: 2471 return MISCREG_ICH_LR0_EL2; 2472 case 1: 2473 return MISCREG_ICH_LR1_EL2; 2474 case 2: 2475 return MISCREG_ICH_LR2_EL2; 2476 case 3: 2477 return MISCREG_ICH_LR3_EL2; 2478 case 4: 2479 return MISCREG_ICH_LR4_EL2; 2480 case 5: 2481 return MISCREG_ICH_LR5_EL2; 2482 case 6: 2483 return MISCREG_ICH_LR6_EL2; 2484 case 7: 2485 return MISCREG_ICH_LR7_EL2; 2486 } 2487 break; 2488 case 13: 2489 switch (op2) { 2490 case 0: 2491 return MISCREG_ICH_LR8_EL2; 2492 case 1: 2493 return MISCREG_ICH_LR9_EL2; 2494 case 2: 2495 return MISCREG_ICH_LR10_EL2; 2496 case 3: 2497 return MISCREG_ICH_LR11_EL2; 2498 case 4: 2499 return MISCREG_ICH_LR12_EL2; 2500 case 5: 2501 return MISCREG_ICH_LR13_EL2; 2502 case 6: 2503 return MISCREG_ICH_LR14_EL2; 2504 case 7: 2505 return MISCREG_ICH_LR15_EL2; 2506 } 2507 break; |
2508 } 2509 break; 2510 case 6: 2511 switch (crm) { 2512 case 0: 2513 switch (op2) { 2514 case 0: 2515 return MISCREG_VBAR_EL3; 2516 case 1: 2517 return MISCREG_RVBAR_EL3; 2518 case 2: 2519 return MISCREG_RMR_EL3; 2520 } 2521 break; |
2522 case 12: 2523 switch (op2) { 2524 case 4: 2525 return MISCREG_ICC_CTLR_EL3; 2526 case 5: 2527 return MISCREG_ICC_SRE_EL3; 2528 case 7: 2529 return MISCREG_ICC_IGRPEN1_EL3; 2530 } 2531 break; |
2532 } 2533 break; 2534 } 2535 break; 2536 case 13: 2537 switch (op1) { 2538 case 0: 2539 switch (crm) { --- 1901 unchanged lines hidden (view full) --- 4441 InitReg(MISCREG_L2MERRSR_EL1) 4442 .unimplemented() 4443 .warnNotFail() 4444 .allPrivileges().exceptUserMode(); 4445 InitReg(MISCREG_CBAR_EL1) 4446 .allPrivileges().exceptUserMode().writes(0); 4447 InitReg(MISCREG_CONTEXTIDR_EL2) 4448 .mon().hyp(); |
4449 4450 // GICv3 AArch64 4451 InitReg(MISCREG_ICC_PMR_EL1) 4452 .res0(0xffffff00) // [31:8] 4453 .allPrivileges().exceptUserMode() 4454 .mapsTo(MISCREG_ICC_PMR); 4455 InitReg(MISCREG_ICC_IAR0_EL1) 4456 .allPrivileges().exceptUserMode().writes(0) 4457 .mapsTo(MISCREG_ICC_IAR0); 4458 InitReg(MISCREG_ICC_EOIR0_EL1) 4459 .allPrivileges().exceptUserMode().reads(0) 4460 .mapsTo(MISCREG_ICC_EOIR0); 4461 InitReg(MISCREG_ICC_HPPIR0_EL1) 4462 .allPrivileges().exceptUserMode().writes(0) 4463 .mapsTo(MISCREG_ICC_HPPIR0); 4464 InitReg(MISCREG_ICC_BPR0_EL1) 4465 .res0(0xfffffff8) // [31:3] 4466 .allPrivileges().exceptUserMode() 4467 .mapsTo(MISCREG_ICC_BPR0); 4468 InitReg(MISCREG_ICC_AP0R0_EL1) 4469 .allPrivileges().exceptUserMode() 4470 .mapsTo(MISCREG_ICC_AP0R0); 4471 InitReg(MISCREG_ICC_AP0R1_EL1) 4472 .allPrivileges().exceptUserMode() 4473 .mapsTo(MISCREG_ICC_AP0R1); 4474 InitReg(MISCREG_ICC_AP0R2_EL1) 4475 .allPrivileges().exceptUserMode() 4476 .mapsTo(MISCREG_ICC_AP0R2); 4477 InitReg(MISCREG_ICC_AP0R3_EL1) 4478 .allPrivileges().exceptUserMode() 4479 .mapsTo(MISCREG_ICC_AP0R3); 4480 InitReg(MISCREG_ICC_AP1R0_EL1) 4481 .banked() 4482 .mapsTo(MISCREG_ICC_AP1R0); 4483 InitReg(MISCREG_ICC_AP1R0_EL1_NS) 4484 .bankedChild() 4485 .allPrivileges().exceptUserMode() 4486 .mapsTo(MISCREG_ICC_AP1R0_NS); 4487 InitReg(MISCREG_ICC_AP1R0_EL1_S) 4488 .bankedChild() 4489 .allPrivileges().exceptUserMode() 4490 .mapsTo(MISCREG_ICC_AP1R0_S); 4491 InitReg(MISCREG_ICC_AP1R1_EL1) 4492 .banked() 4493 .mapsTo(MISCREG_ICC_AP1R1); 4494 InitReg(MISCREG_ICC_AP1R1_EL1_NS) 4495 .bankedChild() 4496 .allPrivileges().exceptUserMode() 4497 .mapsTo(MISCREG_ICC_AP1R1_NS); 4498 InitReg(MISCREG_ICC_AP1R1_EL1_S) 4499 .bankedChild() 4500 .allPrivileges().exceptUserMode() 4501 .mapsTo(MISCREG_ICC_AP1R1_S); 4502 InitReg(MISCREG_ICC_AP1R2_EL1) 4503 .banked() 4504 .mapsTo(MISCREG_ICC_AP1R2); 4505 InitReg(MISCREG_ICC_AP1R2_EL1_NS) 4506 .bankedChild() 4507 .allPrivileges().exceptUserMode() 4508 .mapsTo(MISCREG_ICC_AP1R2_NS); 4509 InitReg(MISCREG_ICC_AP1R2_EL1_S) 4510 .bankedChild() 4511 .allPrivileges().exceptUserMode() 4512 .mapsTo(MISCREG_ICC_AP1R2_S); 4513 InitReg(MISCREG_ICC_AP1R3_EL1) 4514 .banked() 4515 .mapsTo(MISCREG_ICC_AP1R3); 4516 InitReg(MISCREG_ICC_AP1R3_EL1_NS) 4517 .bankedChild() 4518 .allPrivileges().exceptUserMode() 4519 .mapsTo(MISCREG_ICC_AP1R3_NS); 4520 InitReg(MISCREG_ICC_AP1R3_EL1_S) 4521 .bankedChild() 4522 .allPrivileges().exceptUserMode() 4523 .mapsTo(MISCREG_ICC_AP1R3_S); 4524 InitReg(MISCREG_ICC_DIR_EL1) 4525 .res0(0xFF000000) // [31:24] 4526 .allPrivileges().exceptUserMode().reads(0) 4527 .mapsTo(MISCREG_ICC_DIR); 4528 InitReg(MISCREG_ICC_RPR_EL1) 4529 .allPrivileges().exceptUserMode().writes(0) 4530 .mapsTo(MISCREG_ICC_RPR); 4531 InitReg(MISCREG_ICC_SGI1R_EL1) 4532 .allPrivileges().exceptUserMode().reads(0) 4533 .mapsTo(MISCREG_ICC_SGI1R); 4534 InitReg(MISCREG_ICC_ASGI1R_EL1) 4535 .allPrivileges().exceptUserMode().reads(0) 4536 .mapsTo(MISCREG_ICC_ASGI1R); 4537 InitReg(MISCREG_ICC_SGI0R_EL1) 4538 .allPrivileges().exceptUserMode().reads(0) 4539 .mapsTo(MISCREG_ICC_SGI0R); 4540 InitReg(MISCREG_ICC_IAR1_EL1) 4541 .allPrivileges().exceptUserMode().writes(0) 4542 .mapsTo(MISCREG_ICC_IAR1); 4543 InitReg(MISCREG_ICC_EOIR1_EL1) 4544 .res0(0xFF000000) // [31:24] 4545 .allPrivileges().exceptUserMode().reads(0) 4546 .mapsTo(MISCREG_ICC_EOIR1); 4547 InitReg(MISCREG_ICC_HPPIR1_EL1) 4548 .allPrivileges().exceptUserMode().writes(0) 4549 .mapsTo(MISCREG_ICC_HPPIR1); 4550 InitReg(MISCREG_ICC_BPR1_EL1) 4551 .banked() 4552 .mapsTo(MISCREG_ICC_BPR1); 4553 InitReg(MISCREG_ICC_BPR1_EL1_NS) 4554 .bankedChild() 4555 .res0(0xfffffff8) // [31:3] 4556 .allPrivileges().exceptUserMode() 4557 .mapsTo(MISCREG_ICC_BPR1_NS); 4558 InitReg(MISCREG_ICC_BPR1_EL1_S) 4559 .bankedChild() 4560 .res0(0xfffffff8) // [31:3] 4561 .secure().exceptUserMode() 4562 .mapsTo(MISCREG_ICC_BPR1_S); 4563 InitReg(MISCREG_ICC_CTLR_EL1) 4564 .banked() 4565 .mapsTo(MISCREG_ICC_CTLR); 4566 InitReg(MISCREG_ICC_CTLR_EL1_NS) 4567 .bankedChild() 4568 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2] 4569 .allPrivileges().exceptUserMode() 4570 .mapsTo(MISCREG_ICC_CTLR_NS); 4571 InitReg(MISCREG_ICC_CTLR_EL1_S) 4572 .bankedChild() 4573 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2] 4574 .secure().exceptUserMode() 4575 .mapsTo(MISCREG_ICC_CTLR_S); 4576 InitReg(MISCREG_ICC_SRE_EL1) 4577 .banked() 4578 .mapsTo(MISCREG_ICC_SRE); 4579 InitReg(MISCREG_ICC_SRE_EL1_NS) 4580 .bankedChild() 4581 .res0(0xFFFFFFF8) // [31:3] 4582 .allPrivileges().exceptUserMode() 4583 .mapsTo(MISCREG_ICC_SRE_NS); 4584 InitReg(MISCREG_ICC_SRE_EL1_S) 4585 .bankedChild() 4586 .res0(0xFFFFFFF8) // [31:3] 4587 .secure().exceptUserMode() 4588 .mapsTo(MISCREG_ICC_SRE_S); 4589 InitReg(MISCREG_ICC_IGRPEN0_EL1) 4590 .res0(0xFFFFFFFE) // [31:1] 4591 .allPrivileges().exceptUserMode() 4592 .mapsTo(MISCREG_ICC_IGRPEN0); 4593 InitReg(MISCREG_ICC_IGRPEN1_EL1) 4594 .banked() 4595 .mapsTo(MISCREG_ICC_IGRPEN1); 4596 InitReg(MISCREG_ICC_IGRPEN1_EL1_NS) 4597 .bankedChild() 4598 .res0(0xFFFFFFFE) // [31:1] 4599 .allPrivileges().exceptUserMode() 4600 .mapsTo(MISCREG_ICC_IGRPEN1_NS); 4601 InitReg(MISCREG_ICC_IGRPEN1_EL1_S) 4602 .bankedChild() 4603 .res0(0xFFFFFFFE) // [31:1] 4604 .secure().exceptUserMode() 4605 .mapsTo(MISCREG_ICC_IGRPEN1_S); 4606 InitReg(MISCREG_ICC_SRE_EL2) 4607 .hyp().mon() 4608 .mapsTo(MISCREG_ICC_HSRE); 4609 InitReg(MISCREG_ICC_CTLR_EL3) 4610 .allPrivileges().exceptUserMode() 4611 .mapsTo(MISCREG_ICC_MCTLR); 4612 InitReg(MISCREG_ICC_SRE_EL3) 4613 .allPrivileges().exceptUserMode() 4614 .mapsTo(MISCREG_ICC_MSRE); 4615 InitReg(MISCREG_ICC_IGRPEN1_EL3) 4616 .allPrivileges().exceptUserMode() 4617 .mapsTo(MISCREG_ICC_MGRPEN1); 4618 4619 InitReg(MISCREG_ICH_AP0R0_EL2) 4620 .hyp().mon() 4621 .mapsTo(MISCREG_ICH_AP0R0); 4622 InitReg(MISCREG_ICH_AP0R1_EL2) 4623 .hyp().mon() 4624 .unimplemented() 4625 .mapsTo(MISCREG_ICH_AP0R1); 4626 InitReg(MISCREG_ICH_AP0R2_EL2) 4627 .hyp().mon() 4628 .unimplemented() 4629 .mapsTo(MISCREG_ICH_AP0R2); 4630 InitReg(MISCREG_ICH_AP0R3_EL2) 4631 .hyp().mon() 4632 .unimplemented() 4633 .mapsTo(MISCREG_ICH_AP0R3); 4634 InitReg(MISCREG_ICH_AP1R0_EL2) 4635 .hyp().mon() 4636 .mapsTo(MISCREG_ICH_AP1R0); 4637 InitReg(MISCREG_ICH_AP1R1_EL2) 4638 .hyp().mon() 4639 .unimplemented() 4640 .mapsTo(MISCREG_ICH_AP1R1); 4641 InitReg(MISCREG_ICH_AP1R2_EL2) 4642 .hyp().mon() 4643 .unimplemented() 4644 .mapsTo(MISCREG_ICH_AP1R2); 4645 InitReg(MISCREG_ICH_AP1R3_EL2) 4646 .hyp().mon() 4647 .unimplemented() 4648 .mapsTo(MISCREG_ICH_AP1R3); 4649 InitReg(MISCREG_ICH_HCR_EL2) 4650 .hyp().mon() 4651 .mapsTo(MISCREG_ICH_HCR); 4652 InitReg(MISCREG_ICH_VTR_EL2) 4653 .hyp().mon().writes(0) 4654 .mapsTo(MISCREG_ICH_VTR); 4655 InitReg(MISCREG_ICH_MISR_EL2) 4656 .hyp().mon().writes(0) 4657 .mapsTo(MISCREG_ICH_MISR); 4658 InitReg(MISCREG_ICH_EISR_EL2) 4659 .hyp().mon().writes(0) 4660 .mapsTo(MISCREG_ICH_EISR); 4661 InitReg(MISCREG_ICH_ELRSR_EL2) 4662 .hyp().mon().writes(0) 4663 .mapsTo(MISCREG_ICH_ELRSR); 4664 InitReg(MISCREG_ICH_VMCR_EL2) 4665 .hyp().mon() 4666 .mapsTo(MISCREG_ICH_VMCR); 4667 InitReg(MISCREG_ICH_LR0_EL2) 4668 .hyp().mon() 4669 .allPrivileges().exceptUserMode(); 4670 InitReg(MISCREG_ICH_LR1_EL2) 4671 .hyp().mon() 4672 .allPrivileges().exceptUserMode(); 4673 InitReg(MISCREG_ICH_LR2_EL2) 4674 .hyp().mon() 4675 .allPrivileges().exceptUserMode(); 4676 InitReg(MISCREG_ICH_LR3_EL2) 4677 .hyp().mon() 4678 .allPrivileges().exceptUserMode(); 4679 InitReg(MISCREG_ICH_LR4_EL2) 4680 .hyp().mon() 4681 .allPrivileges().exceptUserMode(); 4682 InitReg(MISCREG_ICH_LR5_EL2) 4683 .hyp().mon() 4684 .allPrivileges().exceptUserMode(); 4685 InitReg(MISCREG_ICH_LR6_EL2) 4686 .hyp().mon() 4687 .allPrivileges().exceptUserMode(); 4688 InitReg(MISCREG_ICH_LR7_EL2) 4689 .hyp().mon() 4690 .allPrivileges().exceptUserMode(); 4691 InitReg(MISCREG_ICH_LR8_EL2) 4692 .hyp().mon() 4693 .allPrivileges().exceptUserMode(); 4694 InitReg(MISCREG_ICH_LR9_EL2) 4695 .hyp().mon() 4696 .allPrivileges().exceptUserMode(); 4697 InitReg(MISCREG_ICH_LR10_EL2) 4698 .hyp().mon() 4699 .allPrivileges().exceptUserMode(); 4700 InitReg(MISCREG_ICH_LR11_EL2) 4701 .hyp().mon() 4702 .allPrivileges().exceptUserMode(); 4703 InitReg(MISCREG_ICH_LR12_EL2) 4704 .hyp().mon() 4705 .allPrivileges().exceptUserMode(); 4706 InitReg(MISCREG_ICH_LR13_EL2) 4707 .hyp().mon() 4708 .allPrivileges().exceptUserMode(); 4709 InitReg(MISCREG_ICH_LR14_EL2) 4710 .hyp().mon() 4711 .allPrivileges().exceptUserMode(); 4712 InitReg(MISCREG_ICH_LR15_EL2) 4713 .hyp().mon() 4714 .allPrivileges().exceptUserMode(); 4715 4716 // GICv3 AArch32 4717 InitReg(MISCREG_ICC_AP0R0) 4718 .allPrivileges().exceptUserMode(); 4719 InitReg(MISCREG_ICC_AP0R1) 4720 .allPrivileges().exceptUserMode(); 4721 InitReg(MISCREG_ICC_AP0R2) 4722 .allPrivileges().exceptUserMode(); 4723 InitReg(MISCREG_ICC_AP0R3) 4724 .allPrivileges().exceptUserMode(); 4725 InitReg(MISCREG_ICC_AP1R0) 4726 .allPrivileges().exceptUserMode(); 4727 InitReg(MISCREG_ICC_AP1R0_NS) 4728 .allPrivileges().exceptUserMode(); 4729 InitReg(MISCREG_ICC_AP1R0_S) 4730 .allPrivileges().exceptUserMode(); 4731 InitReg(MISCREG_ICC_AP1R1) 4732 .allPrivileges().exceptUserMode(); 4733 InitReg(MISCREG_ICC_AP1R1_NS) 4734 .allPrivileges().exceptUserMode(); 4735 InitReg(MISCREG_ICC_AP1R1_S) 4736 .allPrivileges().exceptUserMode(); 4737 InitReg(MISCREG_ICC_AP1R2) 4738 .allPrivileges().exceptUserMode(); 4739 InitReg(MISCREG_ICC_AP1R2_NS) 4740 .allPrivileges().exceptUserMode(); 4741 InitReg(MISCREG_ICC_AP1R2_S) 4742 .allPrivileges().exceptUserMode(); 4743 InitReg(MISCREG_ICC_AP1R3) 4744 .allPrivileges().exceptUserMode(); 4745 InitReg(MISCREG_ICC_AP1R3_NS) 4746 .allPrivileges().exceptUserMode(); 4747 InitReg(MISCREG_ICC_AP1R3_S) 4748 .allPrivileges().exceptUserMode(); 4749 InitReg(MISCREG_ICC_ASGI1R) 4750 .allPrivileges().exceptUserMode().reads(0); 4751 InitReg(MISCREG_ICC_BPR0) 4752 .allPrivileges().exceptUserMode(); 4753 InitReg(MISCREG_ICC_BPR1) 4754 .allPrivileges().exceptUserMode(); 4755 InitReg(MISCREG_ICC_BPR1_NS) 4756 .allPrivileges().exceptUserMode(); 4757 InitReg(MISCREG_ICC_BPR1_S) 4758 .allPrivileges().exceptUserMode(); 4759 InitReg(MISCREG_ICC_CTLR) 4760 .allPrivileges().exceptUserMode(); 4761 InitReg(MISCREG_ICC_CTLR_NS) 4762 .allPrivileges().exceptUserMode(); 4763 InitReg(MISCREG_ICC_CTLR_S) 4764 .allPrivileges().exceptUserMode(); 4765 InitReg(MISCREG_ICC_DIR) 4766 .allPrivileges().exceptUserMode().reads(0); 4767 InitReg(MISCREG_ICC_EOIR0) 4768 .allPrivileges().exceptUserMode().reads(0); 4769 InitReg(MISCREG_ICC_EOIR1) 4770 .allPrivileges().exceptUserMode().reads(0); 4771 InitReg(MISCREG_ICC_HPPIR0) 4772 .allPrivileges().exceptUserMode().writes(0); 4773 InitReg(MISCREG_ICC_HPPIR1) 4774 .allPrivileges().exceptUserMode().writes(0); 4775 InitReg(MISCREG_ICC_HSRE) 4776 .allPrivileges().exceptUserMode(); 4777 InitReg(MISCREG_ICC_IAR0) 4778 .allPrivileges().exceptUserMode().writes(0); 4779 InitReg(MISCREG_ICC_IAR1) 4780 .allPrivileges().exceptUserMode().writes(0); 4781 InitReg(MISCREG_ICC_IGRPEN0) 4782 .allPrivileges().exceptUserMode(); 4783 InitReg(MISCREG_ICC_IGRPEN1) 4784 .allPrivileges().exceptUserMode(); 4785 InitReg(MISCREG_ICC_IGRPEN1_NS) 4786 .allPrivileges().exceptUserMode(); 4787 InitReg(MISCREG_ICC_IGRPEN1_S) 4788 .allPrivileges().exceptUserMode(); 4789 InitReg(MISCREG_ICC_MCTLR) 4790 .allPrivileges().exceptUserMode(); 4791 InitReg(MISCREG_ICC_MGRPEN1) 4792 .allPrivileges().exceptUserMode(); 4793 InitReg(MISCREG_ICC_MSRE) 4794 .allPrivileges().exceptUserMode(); 4795 InitReg(MISCREG_ICC_PMR) 4796 .allPrivileges().exceptUserMode(); 4797 InitReg(MISCREG_ICC_RPR) 4798 .allPrivileges().exceptUserMode().writes(0); 4799 InitReg(MISCREG_ICC_SGI0R) 4800 .allPrivileges().exceptUserMode().reads(0); 4801 InitReg(MISCREG_ICC_SGI1R) 4802 .allPrivileges().exceptUserMode().reads(0); 4803 InitReg(MISCREG_ICC_SRE) 4804 .allPrivileges().exceptUserMode(); 4805 InitReg(MISCREG_ICC_SRE_NS) 4806 .allPrivileges().exceptUserMode(); 4807 InitReg(MISCREG_ICC_SRE_S) 4808 .allPrivileges().exceptUserMode(); 4809 4810 InitReg(MISCREG_ICH_AP0R0) 4811 .hyp().mon(); 4812 InitReg(MISCREG_ICH_AP0R1) 4813 .hyp().mon(); 4814 InitReg(MISCREG_ICH_AP0R2) 4815 .hyp().mon(); 4816 InitReg(MISCREG_ICH_AP0R3) 4817 .hyp().mon(); 4818 InitReg(MISCREG_ICH_AP1R0) 4819 .hyp().mon(); 4820 InitReg(MISCREG_ICH_AP1R1) 4821 .hyp().mon(); 4822 InitReg(MISCREG_ICH_AP1R2) 4823 .hyp().mon(); 4824 InitReg(MISCREG_ICH_AP1R3) 4825 .hyp().mon(); 4826 InitReg(MISCREG_ICH_HCR) 4827 .hyp().mon(); 4828 InitReg(MISCREG_ICH_VTR) 4829 .hyp().mon().writes(0); 4830 InitReg(MISCREG_ICH_MISR) 4831 .hyp().mon().writes(0); 4832 InitReg(MISCREG_ICH_EISR) 4833 .hyp().mon().writes(0); 4834 InitReg(MISCREG_ICH_ELRSR) 4835 .hyp().mon().writes(0); 4836 InitReg(MISCREG_ICH_VMCR) 4837 .hyp().mon(); 4838 InitReg(MISCREG_ICH_LR0) 4839 .hyp().mon(); 4840 InitReg(MISCREG_ICH_LR1) 4841 .hyp().mon(); 4842 InitReg(MISCREG_ICH_LR2) 4843 .hyp().mon(); 4844 InitReg(MISCREG_ICH_LR3) 4845 .hyp().mon(); 4846 InitReg(MISCREG_ICH_LR4) 4847 .hyp().mon(); 4848 InitReg(MISCREG_ICH_LR5) 4849 .hyp().mon(); 4850 InitReg(MISCREG_ICH_LR6) 4851 .hyp().mon(); 4852 InitReg(MISCREG_ICH_LR7) 4853 .hyp().mon(); 4854 InitReg(MISCREG_ICH_LR8) 4855 .hyp().mon(); 4856 InitReg(MISCREG_ICH_LR9) 4857 .hyp().mon(); 4858 InitReg(MISCREG_ICH_LR10) 4859 .hyp().mon(); 4860 InitReg(MISCREG_ICH_LR11) 4861 .hyp().mon(); 4862 InitReg(MISCREG_ICH_LR12) 4863 .hyp().mon(); 4864 InitReg(MISCREG_ICH_LR13) 4865 .hyp().mon(); 4866 InitReg(MISCREG_ICH_LR14) 4867 .hyp().mon(); 4868 InitReg(MISCREG_ICH_LR15) 4869 .hyp().mon(); 4870 InitReg(MISCREG_ICH_LRC0) 4871 .mapsTo(MISCREG_ICH_LR0) 4872 .hyp().mon(); 4873 InitReg(MISCREG_ICH_LRC1) 4874 .mapsTo(MISCREG_ICH_LR1) 4875 .hyp().mon(); 4876 InitReg(MISCREG_ICH_LRC2) 4877 .mapsTo(MISCREG_ICH_LR2) 4878 .hyp().mon(); 4879 InitReg(MISCREG_ICH_LRC3) 4880 .mapsTo(MISCREG_ICH_LR3) 4881 .hyp().mon(); 4882 InitReg(MISCREG_ICH_LRC4) 4883 .mapsTo(MISCREG_ICH_LR4) 4884 .hyp().mon(); 4885 InitReg(MISCREG_ICH_LRC5) 4886 .mapsTo(MISCREG_ICH_LR5) 4887 .hyp().mon(); 4888 InitReg(MISCREG_ICH_LRC6) 4889 .mapsTo(MISCREG_ICH_LR6) 4890 .hyp().mon(); 4891 InitReg(MISCREG_ICH_LRC7) 4892 .mapsTo(MISCREG_ICH_LR7) 4893 .hyp().mon(); 4894 InitReg(MISCREG_ICH_LRC8) 4895 .mapsTo(MISCREG_ICH_LR8) 4896 .hyp().mon(); 4897 InitReg(MISCREG_ICH_LRC9) 4898 .mapsTo(MISCREG_ICH_LR9) 4899 .hyp().mon(); 4900 InitReg(MISCREG_ICH_LRC10) 4901 .mapsTo(MISCREG_ICH_LR10) 4902 .hyp().mon(); 4903 InitReg(MISCREG_ICH_LRC11) 4904 .mapsTo(MISCREG_ICH_LR11) 4905 .hyp().mon(); 4906 InitReg(MISCREG_ICH_LRC12) 4907 .mapsTo(MISCREG_ICH_LR12) 4908 .hyp().mon(); 4909 InitReg(MISCREG_ICH_LRC13) 4910 .mapsTo(MISCREG_ICH_LR13) 4911 .hyp().mon(); 4912 InitReg(MISCREG_ICH_LRC14) 4913 .mapsTo(MISCREG_ICH_LR14) 4914 .hyp().mon(); 4915 InitReg(MISCREG_ICH_LRC15) 4916 .mapsTo(MISCREG_ICH_LR15) 4917 .hyp().mon(); 4918 |
4919 InitReg(MISCREG_CNTHV_CTL_EL2) 4920 .mon().hyp(); 4921 InitReg(MISCREG_CNTHV_CVAL_EL2) 4922 .mon().hyp(); 4923 InitReg(MISCREG_CNTHV_TVAL_EL2) 4924 .mon().hyp(); 4925 4926 // Dummy registers --- 63 unchanged lines hidden --- |