1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/miscregs.hh"
43#include "base/misc.hh"
44
45namespace ArmISA
46{
47
48MiscRegIndex
49decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
50{
51 switch(crn) {
52 case 0:
53 switch (opc2) {
54 case 0:
55 switch (crm) {
56 case 0:
57 return MISCREG_DBGDIDR;
58 case 1:
59 return MISCREG_DBGDSCR_INT;
60 default:
61 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
62 crn, opc1, crm, opc2);
63 return NUM_MISCREGS;
64 }
65 default:
66 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
67 crn, opc1, crm, opc2);
68 return NUM_MISCREGS;
69 }
70 default:
71 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
72 crn, opc1, crm, opc2);
73 return NUM_MISCREGS;
74 }
75
76}
77
78MiscRegIndex
79decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
80{
81 switch (crn) {
82 case 0:
83 switch (opc1) {
84 case 0:
85 switch (crm) {
86 case 0:
87 switch (opc2) {
88 case 1:
89 return MISCREG_CTR;
90 case 2:
91 return MISCREG_TCMTR;
92 case 3:
93 return MISCREG_TLBTR;
94 case 5:
95 return MISCREG_MPIDR;
96 default:
97 return MISCREG_MIDR;
98 }
99 break;
100 case 1:
101 switch (opc2) {
102 case 0:
103 return MISCREG_ID_PFR0;
104 case 1:
105 return MISCREG_ID_PFR1;
106 case 2:
107 return MISCREG_ID_DFR0;
108 case 3:
109 return MISCREG_ID_AFR0;
110 case 4:
111 return MISCREG_ID_MMFR0;
112 case 5:
113 return MISCREG_ID_MMFR1;
114 case 6:
115 return MISCREG_ID_MMFR2;
116 case 7:
117 return MISCREG_ID_MMFR3;
118 }
119 break;
120 case 2:
121 switch (opc2) {
122 case 0:
123 return MISCREG_ID_ISAR0;
124 case 1:
125 return MISCREG_ID_ISAR1;
126 case 2:
127 return MISCREG_ID_ISAR2;
128 case 3:
129 return MISCREG_ID_ISAR3;
130 case 4:
131 return MISCREG_ID_ISAR4;
132 case 5:
133 return MISCREG_ID_ISAR5;
134 case 6:
135 case 7:
136 return MISCREG_RAZ; // read as zero
137 }
138 break;
139 default:
140 return MISCREG_RAZ; // read as zero
141 }
142 break;
143 case 1:
144 if (crm == 0) {
145 switch (opc2) {
146 case 0:
147 return MISCREG_CCSIDR;
148 case 1:
149 return MISCREG_CLIDR;
150 case 7:
151 return MISCREG_AIDR;
152 }
153 }
154 break;
155 case 2:
156 if (crm == 0 && opc2 == 0) {
157 return MISCREG_CSSELR;
158 }
159 break;
160 }
161 break;
162 case 1:
163 if (opc1 == 0) {
164 if (crm == 0) {
165 switch (opc2) {
166 case 0:
167 return MISCREG_SCTLR;
168 case 1:
169 return MISCREG_ACTLR;
170 case 0x2:
171 return MISCREG_CPACR;
172 }
173 } else if (crm == 1) {
174 switch (opc2) {
175 case 0:
176 return MISCREG_SCR;
177 case 1:
178 return MISCREG_SDER;
179 case 2:
180 return MISCREG_NSACR;
181 }
182 }
183 }
184 break;
185 case 2:
186 if (opc1 == 0 && crm == 0) {
187 switch (opc2) {
188 case 0:
189 return MISCREG_TTBR0;
190 case 1:
191 return MISCREG_TTBR1;
192 case 2:
193 return MISCREG_TTBCR;
194 }
195 }
196 break;
197 case 3:
198 if (opc1 == 0 && crm == 0 && opc2 == 0) {
199 return MISCREG_DACR;
200 }
201 break;
202 case 5:
203 if (opc1 == 0) {
204 if (crm == 0) {
205 if (opc2 == 0) {
206 return MISCREG_DFSR;
207 } else if (opc2 == 1) {
208 return MISCREG_IFSR;
209 }
210 } else if (crm == 1) {
211 if (opc2 == 0) {
212 return MISCREG_ADFSR;
213 } else if (opc2 == 1) {
214 return MISCREG_AIFSR;
215 }
216 }
217 }
218 break;
219 case 6:
220 if (opc1 == 0 && crm == 0) {
221 switch (opc2) {
222 case 0:
223 return MISCREG_DFAR;
224 case 2:
225 return MISCREG_IFAR;
226 }
227 }
228 break;
229 case 7:
230 if (opc1 == 0) {
231 switch (crm) {
232 case 0:
233 if (opc2 == 4) {
234 return MISCREG_NOP;
235 }
236 break;
237 case 1:
238 switch (opc2) {
239 case 0:
240 return MISCREG_ICIALLUIS;
241 case 6:
242 return MISCREG_BPIALLIS;
243 }
244 break;
245 case 4:
246 if (opc2 == 0) {
247 return MISCREG_PAR;
248 }
249 break;
250 case 5:
251 switch (opc2) {
252 case 0:
253 return MISCREG_ICIALLU;
254 case 1:
255 return MISCREG_ICIMVAU;
256 case 4:
257 return MISCREG_CP15ISB;
258 case 6:
259 return MISCREG_BPIALL;
260 case 7:
261 return MISCREG_BPIMVA;
262 }
263 break;
264 case 6:
265 if (opc2 == 1) {
266 return MISCREG_DCIMVAC;
267 } else if (opc2 == 2) {
268 return MISCREG_DCISW;
269 }
270 break;
271 case 8:
272 switch (opc2) {
273 case 0:
274 return MISCREG_V2PCWPR;
275 case 1:
276 return MISCREG_V2PCWPW;
277 case 2:
278 return MISCREG_V2PCWUR;
279 case 3:
280 return MISCREG_V2PCWUW;
281 case 4:
282 return MISCREG_V2POWPR;
283 case 5:
284 return MISCREG_V2POWPW;
285 case 6:
286 return MISCREG_V2POWUR;
287 case 7:
288 return MISCREG_V2POWUW;
289 }
290 break;
291 case 10:
292 switch (opc2) {
293 case 1:
294 return MISCREG_DCCMVAC;
295 case 2:
296 return MISCREG_MCCSW;
297 case 4:
298 return MISCREG_CP15DSB;
299 case 5:
300 return MISCREG_CP15DMB;
301 }
302 break;
303 case 11:
304 if (opc2 == 1) {
305 return MISCREG_DCCMVAU;
306 }
307 break;
308 case 13:
309 if (opc2 == 1) {
310 return MISCREG_NOP;
311 }
312 break;
313 case 14:
314 if (opc2 == 1) {
315 return MISCREG_DCCIMVAC;
316 } else if (opc2 == 2) {
317 return MISCREG_DCCISW;
318 }
319 break;
320 }
321 }
322 break;
323 case 8:
324 if (opc1 == 0) {
325 switch (crm) {
326 case 3:
327 switch (opc2) {
328 case 0:
329 return MISCREG_TLBIALLIS;
330 case 1:
331 return MISCREG_TLBIMVAIS;
332 case 2:
333 return MISCREG_TLBIASIDIS;
334 case 3:
335 return MISCREG_TLBIMVAAIS;
336 }
337 break;
338 case 5:
339 switch (opc2) {
340 case 0:
341 return MISCREG_ITLBIALL;
342 case 1:
343 return MISCREG_ITLBIMVA;
344 case 2:
345 return MISCREG_ITLBIASID;
346 }
347 break;
348 case 6:
349 switch (opc2) {
350 case 0:
351 return MISCREG_DTLBIALL;
352 case 1:
353 return MISCREG_DTLBIMVA;
354 case 2:
355 return MISCREG_DTLBIASID;
356 }
357 break;
358 case 7:
359 switch (opc2) {
360 case 0:
361 return MISCREG_TLBIALL;
362 case 1:
363 return MISCREG_TLBIMVA;
364 case 2:
365 return MISCREG_TLBIASID;
366 case 3:
367 return MISCREG_TLBIMVAA;
368 }
369 break;
370 }
371 }
372 break;
373 case 9:
374 if (opc1 == 0) {
375 switch (crm) {
376 case 12:
377 switch (opc2) {
378 case 0:
379 return MISCREG_PMCR;
380 case 1:
381 return MISCREG_PMCNTENSET;
382 case 2:
383 return MISCREG_PMCNTENCLR;
384 case 3:
385 return MISCREG_PMOVSR;
386 case 4:
387 return MISCREG_PMSWINC;
388 case 5:
389 return MISCREG_PMSELR;
390 case 6:
391 return MISCREG_PMCEID0;
392 case 7:
393 return MISCREG_PMCEID1;
394 }
| 1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/miscregs.hh"
43#include "base/misc.hh"
44
45namespace ArmISA
46{
47
48MiscRegIndex
49decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
50{
51 switch(crn) {
52 case 0:
53 switch (opc2) {
54 case 0:
55 switch (crm) {
56 case 0:
57 return MISCREG_DBGDIDR;
58 case 1:
59 return MISCREG_DBGDSCR_INT;
60 default:
61 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
62 crn, opc1, crm, opc2);
63 return NUM_MISCREGS;
64 }
65 default:
66 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
67 crn, opc1, crm, opc2);
68 return NUM_MISCREGS;
69 }
70 default:
71 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
72 crn, opc1, crm, opc2);
73 return NUM_MISCREGS;
74 }
75
76}
77
78MiscRegIndex
79decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
80{
81 switch (crn) {
82 case 0:
83 switch (opc1) {
84 case 0:
85 switch (crm) {
86 case 0:
87 switch (opc2) {
88 case 1:
89 return MISCREG_CTR;
90 case 2:
91 return MISCREG_TCMTR;
92 case 3:
93 return MISCREG_TLBTR;
94 case 5:
95 return MISCREG_MPIDR;
96 default:
97 return MISCREG_MIDR;
98 }
99 break;
100 case 1:
101 switch (opc2) {
102 case 0:
103 return MISCREG_ID_PFR0;
104 case 1:
105 return MISCREG_ID_PFR1;
106 case 2:
107 return MISCREG_ID_DFR0;
108 case 3:
109 return MISCREG_ID_AFR0;
110 case 4:
111 return MISCREG_ID_MMFR0;
112 case 5:
113 return MISCREG_ID_MMFR1;
114 case 6:
115 return MISCREG_ID_MMFR2;
116 case 7:
117 return MISCREG_ID_MMFR3;
118 }
119 break;
120 case 2:
121 switch (opc2) {
122 case 0:
123 return MISCREG_ID_ISAR0;
124 case 1:
125 return MISCREG_ID_ISAR1;
126 case 2:
127 return MISCREG_ID_ISAR2;
128 case 3:
129 return MISCREG_ID_ISAR3;
130 case 4:
131 return MISCREG_ID_ISAR4;
132 case 5:
133 return MISCREG_ID_ISAR5;
134 case 6:
135 case 7:
136 return MISCREG_RAZ; // read as zero
137 }
138 break;
139 default:
140 return MISCREG_RAZ; // read as zero
141 }
142 break;
143 case 1:
144 if (crm == 0) {
145 switch (opc2) {
146 case 0:
147 return MISCREG_CCSIDR;
148 case 1:
149 return MISCREG_CLIDR;
150 case 7:
151 return MISCREG_AIDR;
152 }
153 }
154 break;
155 case 2:
156 if (crm == 0 && opc2 == 0) {
157 return MISCREG_CSSELR;
158 }
159 break;
160 }
161 break;
162 case 1:
163 if (opc1 == 0) {
164 if (crm == 0) {
165 switch (opc2) {
166 case 0:
167 return MISCREG_SCTLR;
168 case 1:
169 return MISCREG_ACTLR;
170 case 0x2:
171 return MISCREG_CPACR;
172 }
173 } else if (crm == 1) {
174 switch (opc2) {
175 case 0:
176 return MISCREG_SCR;
177 case 1:
178 return MISCREG_SDER;
179 case 2:
180 return MISCREG_NSACR;
181 }
182 }
183 }
184 break;
185 case 2:
186 if (opc1 == 0 && crm == 0) {
187 switch (opc2) {
188 case 0:
189 return MISCREG_TTBR0;
190 case 1:
191 return MISCREG_TTBR1;
192 case 2:
193 return MISCREG_TTBCR;
194 }
195 }
196 break;
197 case 3:
198 if (opc1 == 0 && crm == 0 && opc2 == 0) {
199 return MISCREG_DACR;
200 }
201 break;
202 case 5:
203 if (opc1 == 0) {
204 if (crm == 0) {
205 if (opc2 == 0) {
206 return MISCREG_DFSR;
207 } else if (opc2 == 1) {
208 return MISCREG_IFSR;
209 }
210 } else if (crm == 1) {
211 if (opc2 == 0) {
212 return MISCREG_ADFSR;
213 } else if (opc2 == 1) {
214 return MISCREG_AIFSR;
215 }
216 }
217 }
218 break;
219 case 6:
220 if (opc1 == 0 && crm == 0) {
221 switch (opc2) {
222 case 0:
223 return MISCREG_DFAR;
224 case 2:
225 return MISCREG_IFAR;
226 }
227 }
228 break;
229 case 7:
230 if (opc1 == 0) {
231 switch (crm) {
232 case 0:
233 if (opc2 == 4) {
234 return MISCREG_NOP;
235 }
236 break;
237 case 1:
238 switch (opc2) {
239 case 0:
240 return MISCREG_ICIALLUIS;
241 case 6:
242 return MISCREG_BPIALLIS;
243 }
244 break;
245 case 4:
246 if (opc2 == 0) {
247 return MISCREG_PAR;
248 }
249 break;
250 case 5:
251 switch (opc2) {
252 case 0:
253 return MISCREG_ICIALLU;
254 case 1:
255 return MISCREG_ICIMVAU;
256 case 4:
257 return MISCREG_CP15ISB;
258 case 6:
259 return MISCREG_BPIALL;
260 case 7:
261 return MISCREG_BPIMVA;
262 }
263 break;
264 case 6:
265 if (opc2 == 1) {
266 return MISCREG_DCIMVAC;
267 } else if (opc2 == 2) {
268 return MISCREG_DCISW;
269 }
270 break;
271 case 8:
272 switch (opc2) {
273 case 0:
274 return MISCREG_V2PCWPR;
275 case 1:
276 return MISCREG_V2PCWPW;
277 case 2:
278 return MISCREG_V2PCWUR;
279 case 3:
280 return MISCREG_V2PCWUW;
281 case 4:
282 return MISCREG_V2POWPR;
283 case 5:
284 return MISCREG_V2POWPW;
285 case 6:
286 return MISCREG_V2POWUR;
287 case 7:
288 return MISCREG_V2POWUW;
289 }
290 break;
291 case 10:
292 switch (opc2) {
293 case 1:
294 return MISCREG_DCCMVAC;
295 case 2:
296 return MISCREG_MCCSW;
297 case 4:
298 return MISCREG_CP15DSB;
299 case 5:
300 return MISCREG_CP15DMB;
301 }
302 break;
303 case 11:
304 if (opc2 == 1) {
305 return MISCREG_DCCMVAU;
306 }
307 break;
308 case 13:
309 if (opc2 == 1) {
310 return MISCREG_NOP;
311 }
312 break;
313 case 14:
314 if (opc2 == 1) {
315 return MISCREG_DCCIMVAC;
316 } else if (opc2 == 2) {
317 return MISCREG_DCCISW;
318 }
319 break;
320 }
321 }
322 break;
323 case 8:
324 if (opc1 == 0) {
325 switch (crm) {
326 case 3:
327 switch (opc2) {
328 case 0:
329 return MISCREG_TLBIALLIS;
330 case 1:
331 return MISCREG_TLBIMVAIS;
332 case 2:
333 return MISCREG_TLBIASIDIS;
334 case 3:
335 return MISCREG_TLBIMVAAIS;
336 }
337 break;
338 case 5:
339 switch (opc2) {
340 case 0:
341 return MISCREG_ITLBIALL;
342 case 1:
343 return MISCREG_ITLBIMVA;
344 case 2:
345 return MISCREG_ITLBIASID;
346 }
347 break;
348 case 6:
349 switch (opc2) {
350 case 0:
351 return MISCREG_DTLBIALL;
352 case 1:
353 return MISCREG_DTLBIMVA;
354 case 2:
355 return MISCREG_DTLBIASID;
356 }
357 break;
358 case 7:
359 switch (opc2) {
360 case 0:
361 return MISCREG_TLBIALL;
362 case 1:
363 return MISCREG_TLBIMVA;
364 case 2:
365 return MISCREG_TLBIASID;
366 case 3:
367 return MISCREG_TLBIMVAA;
368 }
369 break;
370 }
371 }
372 break;
373 case 9:
374 if (opc1 == 0) {
375 switch (crm) {
376 case 12:
377 switch (opc2) {
378 case 0:
379 return MISCREG_PMCR;
380 case 1:
381 return MISCREG_PMCNTENSET;
382 case 2:
383 return MISCREG_PMCNTENCLR;
384 case 3:
385 return MISCREG_PMOVSR;
386 case 4:
387 return MISCREG_PMSWINC;
388 case 5:
389 return MISCREG_PMSELR;
390 case 6:
391 return MISCREG_PMCEID0;
392 case 7:
393 return MISCREG_PMCEID1;
394 }
|
425 default:
426 return MISCREG_L2LATENCY;
427 }
428 }
429 //Reserved for Branch Predictor, Cache and TCM operations
430 break;
431 case 10:
432 if (opc1 == 0) {
433 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
434 if (crm == 2) { // TEX Remap Registers
435 if (opc2 == 0) {
436 return MISCREG_PRRR;
437 } else if (opc2 == 1) {
438 return MISCREG_NMRR;
439 }
440 }
441 }
442 break;
443 case 11:
444 if (opc1 <=7) {
445 switch (crm) {
446 case 0:
447 case 1:
448 case 2:
449 case 3:
450 case 4:
451 case 5:
452 case 6:
453 case 7:
454 case 8:
455 case 15:
456 // Reserved for DMA operations for TCM access
457 break;
458 }
459 }
460 break;
461 case 12:
462 if (opc1 == 0) {
463 if (crm == 0) {
464 if (opc2 == 0) {
465 return MISCREG_VBAR;
466 } else if (opc2 == 1) {
467 return MISCREG_MVBAR;
468 }
469 } else if (crm == 1) {
470 if (opc2 == 0) {
471 return MISCREG_ISR;
472 }
473 }
474 }
475 break;
476 case 13:
477 if (opc1 == 0) {
478 if (crm == 0) {
479 switch (opc2) {
480 case 0:
481 return MISCREG_FCEIDR;
482 case 1:
483 return MISCREG_CONTEXTIDR;
484 case 2:
485 return MISCREG_TPIDRURW;
486 case 3:
487 return MISCREG_TPIDRURO;
488 case 4:
489 return MISCREG_TPIDRPRW;
490 }
491 }
492 }
493 break;
494 case 15:
495 // Implementation defined
496 return MISCREG_CRN15;
497 }
498 // Unrecognized register
499 return NUM_MISCREGS;
500}
501
502}
| 429 default:
430 return MISCREG_L2LATENCY;
431 }
432 }
433 //Reserved for Branch Predictor, Cache and TCM operations
434 break;
435 case 10:
436 if (opc1 == 0) {
437 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
438 if (crm == 2) { // TEX Remap Registers
439 if (opc2 == 0) {
440 return MISCREG_PRRR;
441 } else if (opc2 == 1) {
442 return MISCREG_NMRR;
443 }
444 }
445 }
446 break;
447 case 11:
448 if (opc1 <=7) {
449 switch (crm) {
450 case 0:
451 case 1:
452 case 2:
453 case 3:
454 case 4:
455 case 5:
456 case 6:
457 case 7:
458 case 8:
459 case 15:
460 // Reserved for DMA operations for TCM access
461 break;
462 }
463 }
464 break;
465 case 12:
466 if (opc1 == 0) {
467 if (crm == 0) {
468 if (opc2 == 0) {
469 return MISCREG_VBAR;
470 } else if (opc2 == 1) {
471 return MISCREG_MVBAR;
472 }
473 } else if (crm == 1) {
474 if (opc2 == 0) {
475 return MISCREG_ISR;
476 }
477 }
478 }
479 break;
480 case 13:
481 if (opc1 == 0) {
482 if (crm == 0) {
483 switch (opc2) {
484 case 0:
485 return MISCREG_FCEIDR;
486 case 1:
487 return MISCREG_CONTEXTIDR;
488 case 2:
489 return MISCREG_TPIDRURW;
490 case 3:
491 return MISCREG_TPIDRURO;
492 case 4:
493 return MISCREG_TPIDRPRW;
494 }
495 }
496 }
497 break;
498 case 15:
499 // Implementation defined
500 return MISCREG_CRN15;
501 }
502 // Unrecognized register
503 return NUM_MISCREGS;
504}
505
506}
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