miscregs.cc (7583:665d71561298) miscregs.cc (7853:69aae4379062)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/miscregs.hh"
43#include "base/misc.hh"
44
45namespace ArmISA
46{
47
48MiscRegIndex
49decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
50{
51 switch (crn) {
52 case 0:
53 switch (opc1) {
54 case 0:
55 switch (crm) {
56 case 0:
57 switch (opc2) {
58 case 1:
59 return MISCREG_CTR;
60 case 2:
61 return MISCREG_TCMTR;
62 case 3:
63 return MISCREG_TLBTR;
64 case 5:
65 return MISCREG_MPIDR;
66 default:
67 return MISCREG_MIDR;
68 }
69 break;
70 case 1:
71 switch (opc2) {
72 case 0:
73 return MISCREG_ID_PFR0;
74 case 1:
75 return MISCREG_ID_PFR1;
76 case 2:
77 return MISCREG_ID_DFR0;
78 case 3:
79 return MISCREG_ID_AFR0;
80 case 4:
81 return MISCREG_ID_MMFR0;
82 case 5:
83 return MISCREG_ID_MMFR1;
84 case 6:
85 return MISCREG_ID_MMFR2;
86 case 7:
87 return MISCREG_ID_MMFR3;
88 }
89 break;
90 case 2:
91 switch (opc2) {
92 case 0:
93 return MISCREG_ID_ISAR0;
94 case 1:
95 return MISCREG_ID_ISAR1;
96 case 2:
97 return MISCREG_ID_ISAR2;
98 case 3:
99 return MISCREG_ID_ISAR3;
100 case 4:
101 return MISCREG_ID_ISAR4;
102 case 5:
103 return MISCREG_ID_ISAR5;
104 case 6:
105 case 7:
106 return MISCREG_RAZ; // read as zero
107 }
108 break;
109 default:
110 return MISCREG_RAZ; // read as zero
111 }
112 break;
113 case 1:
114 if (crm == 0) {
115 switch (opc2) {
116 case 0:
117 return MISCREG_CCSIDR;
118 case 1:
119 return MISCREG_CLIDR;
120 case 7:
121 return MISCREG_AIDR;
122 }
123 }
124 break;
125 case 2:
126 if (crm == 0 && opc2 == 0) {
127 return MISCREG_CSSELR;
128 }
129 break;
130 }
131 break;
132 case 1:
133 if (opc1 == 0) {
134 if (crm == 0) {
135 switch (opc2) {
136 case 0:
137 return MISCREG_SCTLR;
138 case 1:
139 return MISCREG_ACTLR;
140 case 0x2:
141 return MISCREG_CPACR;
142 }
143 } else if (crm == 1) {
144 switch (opc2) {
145 case 0:
146 return MISCREG_SCR;
147 case 1:
148 return MISCREG_SDER;
149 case 2:
150 return MISCREG_NSACR;
151 }
152 }
153 }
154 break;
155 case 2:
156 if (opc1 == 0 && crm == 0) {
157 switch (opc2) {
158 case 0:
159 return MISCREG_TTBR0;
160 case 1:
161 return MISCREG_TTBR1;
162 case 2:
163 return MISCREG_TTBCR;
164 }
165 }
166 break;
167 case 3:
168 if (opc1 == 0 && crm == 0 && opc2 == 0) {
169 return MISCREG_DACR;
170 }
171 break;
172 case 5:
173 if (opc1 == 0) {
174 if (crm == 0) {
175 if (opc2 == 0) {
176 return MISCREG_DFSR;
177 } else if (opc2 == 1) {
178 return MISCREG_IFSR;
179 }
180 } else if (crm == 1) {
181 if (opc2 == 0) {
182 return MISCREG_ADFSR;
183 } else if (opc2 == 1) {
184 return MISCREG_AIFSR;
185 }
186 }
187 }
188 break;
189 case 6:
190 if (opc1 == 0 && crm == 0) {
191 switch (opc2) {
192 case 0:
193 return MISCREG_DFAR;
194 case 2:
195 return MISCREG_IFAR;
196 }
197 }
198 break;
199 case 7:
200 if (opc1 == 0) {
201 switch (crm) {
202 case 0:
203 if (opc2 == 4) {
204 return MISCREG_NOP;
205 }
206 break;
207 case 1:
208 switch (opc2) {
209 case 0:
210 return MISCREG_ICIALLUIS;
211 case 6:
212 return MISCREG_BPIALLIS;
213 }
214 break;
215 case 4:
216 if (opc2 == 0) {
217 return MISCREG_PAR;
218 }
219 break;
220 case 5:
221 switch (opc2) {
222 case 0:
223 return MISCREG_ICIALLU;
224 case 1:
225 return MISCREG_ICIMVAU;
226 case 4:
227 return MISCREG_CP15ISB;
228 case 6:
229 return MISCREG_BPIALL;
230 case 7:
231 return MISCREG_BPIMVA;
232 }
233 break;
234 case 6:
235 if (opc2 == 1) {
236 return MISCREG_DCIMVAC;
237 } else if (opc2 == 2) {
238 return MISCREG_DCISW;
239 }
240 break;
241 case 8:
242 switch (opc2) {
243 case 0:
244 return MISCREG_V2PCWPR;
245 case 1:
246 return MISCREG_V2PCWPW;
247 case 2:
248 return MISCREG_V2PCWUR;
249 case 3:
250 return MISCREG_V2PCWUW;
251 case 4:
252 return MISCREG_V2POWPR;
253 case 5:
254 return MISCREG_V2POWPW;
255 case 6:
256 return MISCREG_V2POWUR;
257 case 7:
258 return MISCREG_V2POWUW;
259 }
260 break;
261 case 10:
262 switch (opc2) {
263 case 1:
264 return MISCREG_DCCMVAC;
265 case 2:
266 return MISCREG_MCCSW;
267 case 4:
268 return MISCREG_CP15DSB;
269 case 5:
270 return MISCREG_CP15DMB;
271 }
272 break;
273 case 11:
274 if (opc2 == 1) {
275 return MISCREG_DCCMVAU;
276 }
277 break;
278 case 13:
279 if (opc2 == 1) {
280 return MISCREG_NOP;
281 }
282 break;
283 case 14:
284 if (opc2 == 1) {
285 return MISCREG_DCCIMVAC;
286 } else if (opc2 == 2) {
287 return MISCREG_DCCISW;
288 }
289 break;
290 }
291 }
292 break;
293 case 8:
294 if (opc1 == 0) {
295 switch (crm) {
296 case 3:
297 switch (opc2) {
298 case 0:
299 return MISCREG_TLBIALLIS;
300 case 1:
301 return MISCREG_TLBIMVAIS;
302 case 2:
303 return MISCREG_TLBIASIDIS;
304 case 3:
305 return MISCREG_TLBIMVAAIS;
306 }
307 break;
308 case 5:
309 switch (opc2) {
310 case 0:
311 return MISCREG_ITLBIALL;
312 case 1:
313 return MISCREG_ITLBIMVA;
314 case 2:
315 return MISCREG_ITLBIASID;
316 }
317 break;
318 case 6:
319 switch (opc2) {
320 case 0:
321 return MISCREG_DTLBIALL;
322 case 1:
323 return MISCREG_DTLBIMVA;
324 case 2:
325 return MISCREG_DTLBIASID;
326 }
327 break;
328 case 7:
329 switch (opc2) {
330 case 0:
331 return MISCREG_TLBIALL;
332 case 1:
333 return MISCREG_TLBIMVA;
334 case 2:
335 return MISCREG_TLBIASID;
336 case 3:
337 return MISCREG_TLBIMVAA;
338 }
339 break;
340 }
341 }
342 break;
343 case 9:
344 if (opc1 == 0) {
345 switch (crm) {
346 case 12:
347 switch (opc2) {
348 case 0:
349 return MISCREG_PMCR;
350 case 1:
351 return MISCREG_PMCNTENSET;
352 case 2:
353 return MISCREG_PMCNTENCLR;
354 case 3:
355 return MISCREG_PMOVSR;
356 case 4:
357 return MISCREG_PMSWINC;
358 case 5:
359 return MISCREG_PMSELR;
360 case 6:
361 return MISCREG_PMCEID0;
362 case 7:
363 return MISCREG_PMCEID1;
364 }
365 case 13:
366 switch (opc2) {
367 case 0:
368 return MISCREG_PMCCNTR;
369 case 1:
370 return MISCREG_PMC_OTHER;
371 case 2:
372 return MISCREG_PMXEVCNTR;
373 }
374 case 14:
375 switch (opc2) {
376 case 0:
377 return MISCREG_PMUSERENR;
378 case 1:
379 return MISCREG_PMINTENSET;
380 case 2:
381 return MISCREG_PMINTENCLR;
382 }
383 }
384 }
385 //Reserved for Branch Predictor, Cache and TCM operations
386 break;
387 case 10:
388 if (opc1 == 0) {
389 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
390 if (crm == 2) { // TEX Remap Registers
391 if (opc2 == 0) {
392 return MISCREG_PRRR;
393 } else if (opc2 == 1) {
394 return MISCREG_NMRR;
395 }
396 }
397 }
398 break;
399 case 11:
400 if (opc1 >= 0 && opc1 <=7) {
401 switch (crm) {
402 case 0:
403 case 1:
404 case 2:
405 case 3:
406 case 4:
407 case 5:
408 case 6:
409 case 7:
410 case 8:
411 case 15:
412 // Reserved for DMA operations for TCM access
413 break;
414 }
415 }
416 break;
417 case 12:
418 if (opc1 == 0) {
419 if (crm == 0) {
420 if (opc2 == 0) {
421 return MISCREG_VBAR;
422 } else if (opc2 == 1) {
423 return MISCREG_MVBAR;
424 }
425 } else if (crm == 1) {
426 if (opc2 == 0) {
427 return MISCREG_ISR;
428 }
429 }
430 }
431 break;
432 case 13:
433 if (opc1 == 0) {
434 if (crm == 0) {
435 switch (opc2) {
436 case 0:
437 return MISCREG_FCEIDR;
438 case 1:
439 return MISCREG_CONTEXTIDR;
440 case 2:
441 return MISCREG_TPIDRURW;
442 case 3:
443 return MISCREG_TPIDRURO;
444 case 4:
445 return MISCREG_TPIDRPRW;
446 }
447 }
448 }
449 break;
450 case 15:
451 // Implementation defined
452 break;
453 }
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 */
40
41#include "arch/arm/isa.hh"
42#include "arch/arm/miscregs.hh"
43#include "base/misc.hh"
44
45namespace ArmISA
46{
47
48MiscRegIndex
49decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
50{
51 switch (crn) {
52 case 0:
53 switch (opc1) {
54 case 0:
55 switch (crm) {
56 case 0:
57 switch (opc2) {
58 case 1:
59 return MISCREG_CTR;
60 case 2:
61 return MISCREG_TCMTR;
62 case 3:
63 return MISCREG_TLBTR;
64 case 5:
65 return MISCREG_MPIDR;
66 default:
67 return MISCREG_MIDR;
68 }
69 break;
70 case 1:
71 switch (opc2) {
72 case 0:
73 return MISCREG_ID_PFR0;
74 case 1:
75 return MISCREG_ID_PFR1;
76 case 2:
77 return MISCREG_ID_DFR0;
78 case 3:
79 return MISCREG_ID_AFR0;
80 case 4:
81 return MISCREG_ID_MMFR0;
82 case 5:
83 return MISCREG_ID_MMFR1;
84 case 6:
85 return MISCREG_ID_MMFR2;
86 case 7:
87 return MISCREG_ID_MMFR3;
88 }
89 break;
90 case 2:
91 switch (opc2) {
92 case 0:
93 return MISCREG_ID_ISAR0;
94 case 1:
95 return MISCREG_ID_ISAR1;
96 case 2:
97 return MISCREG_ID_ISAR2;
98 case 3:
99 return MISCREG_ID_ISAR3;
100 case 4:
101 return MISCREG_ID_ISAR4;
102 case 5:
103 return MISCREG_ID_ISAR5;
104 case 6:
105 case 7:
106 return MISCREG_RAZ; // read as zero
107 }
108 break;
109 default:
110 return MISCREG_RAZ; // read as zero
111 }
112 break;
113 case 1:
114 if (crm == 0) {
115 switch (opc2) {
116 case 0:
117 return MISCREG_CCSIDR;
118 case 1:
119 return MISCREG_CLIDR;
120 case 7:
121 return MISCREG_AIDR;
122 }
123 }
124 break;
125 case 2:
126 if (crm == 0 && opc2 == 0) {
127 return MISCREG_CSSELR;
128 }
129 break;
130 }
131 break;
132 case 1:
133 if (opc1 == 0) {
134 if (crm == 0) {
135 switch (opc2) {
136 case 0:
137 return MISCREG_SCTLR;
138 case 1:
139 return MISCREG_ACTLR;
140 case 0x2:
141 return MISCREG_CPACR;
142 }
143 } else if (crm == 1) {
144 switch (opc2) {
145 case 0:
146 return MISCREG_SCR;
147 case 1:
148 return MISCREG_SDER;
149 case 2:
150 return MISCREG_NSACR;
151 }
152 }
153 }
154 break;
155 case 2:
156 if (opc1 == 0 && crm == 0) {
157 switch (opc2) {
158 case 0:
159 return MISCREG_TTBR0;
160 case 1:
161 return MISCREG_TTBR1;
162 case 2:
163 return MISCREG_TTBCR;
164 }
165 }
166 break;
167 case 3:
168 if (opc1 == 0 && crm == 0 && opc2 == 0) {
169 return MISCREG_DACR;
170 }
171 break;
172 case 5:
173 if (opc1 == 0) {
174 if (crm == 0) {
175 if (opc2 == 0) {
176 return MISCREG_DFSR;
177 } else if (opc2 == 1) {
178 return MISCREG_IFSR;
179 }
180 } else if (crm == 1) {
181 if (opc2 == 0) {
182 return MISCREG_ADFSR;
183 } else if (opc2 == 1) {
184 return MISCREG_AIFSR;
185 }
186 }
187 }
188 break;
189 case 6:
190 if (opc1 == 0 && crm == 0) {
191 switch (opc2) {
192 case 0:
193 return MISCREG_DFAR;
194 case 2:
195 return MISCREG_IFAR;
196 }
197 }
198 break;
199 case 7:
200 if (opc1 == 0) {
201 switch (crm) {
202 case 0:
203 if (opc2 == 4) {
204 return MISCREG_NOP;
205 }
206 break;
207 case 1:
208 switch (opc2) {
209 case 0:
210 return MISCREG_ICIALLUIS;
211 case 6:
212 return MISCREG_BPIALLIS;
213 }
214 break;
215 case 4:
216 if (opc2 == 0) {
217 return MISCREG_PAR;
218 }
219 break;
220 case 5:
221 switch (opc2) {
222 case 0:
223 return MISCREG_ICIALLU;
224 case 1:
225 return MISCREG_ICIMVAU;
226 case 4:
227 return MISCREG_CP15ISB;
228 case 6:
229 return MISCREG_BPIALL;
230 case 7:
231 return MISCREG_BPIMVA;
232 }
233 break;
234 case 6:
235 if (opc2 == 1) {
236 return MISCREG_DCIMVAC;
237 } else if (opc2 == 2) {
238 return MISCREG_DCISW;
239 }
240 break;
241 case 8:
242 switch (opc2) {
243 case 0:
244 return MISCREG_V2PCWPR;
245 case 1:
246 return MISCREG_V2PCWPW;
247 case 2:
248 return MISCREG_V2PCWUR;
249 case 3:
250 return MISCREG_V2PCWUW;
251 case 4:
252 return MISCREG_V2POWPR;
253 case 5:
254 return MISCREG_V2POWPW;
255 case 6:
256 return MISCREG_V2POWUR;
257 case 7:
258 return MISCREG_V2POWUW;
259 }
260 break;
261 case 10:
262 switch (opc2) {
263 case 1:
264 return MISCREG_DCCMVAC;
265 case 2:
266 return MISCREG_MCCSW;
267 case 4:
268 return MISCREG_CP15DSB;
269 case 5:
270 return MISCREG_CP15DMB;
271 }
272 break;
273 case 11:
274 if (opc2 == 1) {
275 return MISCREG_DCCMVAU;
276 }
277 break;
278 case 13:
279 if (opc2 == 1) {
280 return MISCREG_NOP;
281 }
282 break;
283 case 14:
284 if (opc2 == 1) {
285 return MISCREG_DCCIMVAC;
286 } else if (opc2 == 2) {
287 return MISCREG_DCCISW;
288 }
289 break;
290 }
291 }
292 break;
293 case 8:
294 if (opc1 == 0) {
295 switch (crm) {
296 case 3:
297 switch (opc2) {
298 case 0:
299 return MISCREG_TLBIALLIS;
300 case 1:
301 return MISCREG_TLBIMVAIS;
302 case 2:
303 return MISCREG_TLBIASIDIS;
304 case 3:
305 return MISCREG_TLBIMVAAIS;
306 }
307 break;
308 case 5:
309 switch (opc2) {
310 case 0:
311 return MISCREG_ITLBIALL;
312 case 1:
313 return MISCREG_ITLBIMVA;
314 case 2:
315 return MISCREG_ITLBIASID;
316 }
317 break;
318 case 6:
319 switch (opc2) {
320 case 0:
321 return MISCREG_DTLBIALL;
322 case 1:
323 return MISCREG_DTLBIMVA;
324 case 2:
325 return MISCREG_DTLBIASID;
326 }
327 break;
328 case 7:
329 switch (opc2) {
330 case 0:
331 return MISCREG_TLBIALL;
332 case 1:
333 return MISCREG_TLBIMVA;
334 case 2:
335 return MISCREG_TLBIASID;
336 case 3:
337 return MISCREG_TLBIMVAA;
338 }
339 break;
340 }
341 }
342 break;
343 case 9:
344 if (opc1 == 0) {
345 switch (crm) {
346 case 12:
347 switch (opc2) {
348 case 0:
349 return MISCREG_PMCR;
350 case 1:
351 return MISCREG_PMCNTENSET;
352 case 2:
353 return MISCREG_PMCNTENCLR;
354 case 3:
355 return MISCREG_PMOVSR;
356 case 4:
357 return MISCREG_PMSWINC;
358 case 5:
359 return MISCREG_PMSELR;
360 case 6:
361 return MISCREG_PMCEID0;
362 case 7:
363 return MISCREG_PMCEID1;
364 }
365 case 13:
366 switch (opc2) {
367 case 0:
368 return MISCREG_PMCCNTR;
369 case 1:
370 return MISCREG_PMC_OTHER;
371 case 2:
372 return MISCREG_PMXEVCNTR;
373 }
374 case 14:
375 switch (opc2) {
376 case 0:
377 return MISCREG_PMUSERENR;
378 case 1:
379 return MISCREG_PMINTENSET;
380 case 2:
381 return MISCREG_PMINTENCLR;
382 }
383 }
384 }
385 //Reserved for Branch Predictor, Cache and TCM operations
386 break;
387 case 10:
388 if (opc1 == 0) {
389 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
390 if (crm == 2) { // TEX Remap Registers
391 if (opc2 == 0) {
392 return MISCREG_PRRR;
393 } else if (opc2 == 1) {
394 return MISCREG_NMRR;
395 }
396 }
397 }
398 break;
399 case 11:
400 if (opc1 >= 0 && opc1 <=7) {
401 switch (crm) {
402 case 0:
403 case 1:
404 case 2:
405 case 3:
406 case 4:
407 case 5:
408 case 6:
409 case 7:
410 case 8:
411 case 15:
412 // Reserved for DMA operations for TCM access
413 break;
414 }
415 }
416 break;
417 case 12:
418 if (opc1 == 0) {
419 if (crm == 0) {
420 if (opc2 == 0) {
421 return MISCREG_VBAR;
422 } else if (opc2 == 1) {
423 return MISCREG_MVBAR;
424 }
425 } else if (crm == 1) {
426 if (opc2 == 0) {
427 return MISCREG_ISR;
428 }
429 }
430 }
431 break;
432 case 13:
433 if (opc1 == 0) {
434 if (crm == 0) {
435 switch (opc2) {
436 case 0:
437 return MISCREG_FCEIDR;
438 case 1:
439 return MISCREG_CONTEXTIDR;
440 case 2:
441 return MISCREG_TPIDRURW;
442 case 3:
443 return MISCREG_TPIDRURO;
444 case 4:
445 return MISCREG_TPIDRPRW;
446 }
447 }
448 }
449 break;
450 case 15:
451 // Implementation defined
452 break;
453 }
454 warn("Unknown miscreg: CRn: %d Opc1: %d CRm: %d opc2: %d\n",
455 crn, opc1, crm, opc2);
456 // Unrecognized register
457 return NUM_MISCREGS;
458}
459
460};
454 // Unrecognized register
455 return NUM_MISCREGS;
456}
457
458};