miscregs.cc (14244:6c2e687fe41f) miscregs.cc (14245:0c0a6fd47628)
1/*
2 * Copyright (c) 2010-2013, 2015-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 * Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include <tuple>
45
46#include "arch/arm/isa.hh"
47#include "base/logging.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51namespace ArmISA
52{
53
54MiscRegIndex
55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56{
57 switch(crn) {
58 case 0:
59 switch (opc1) {
60 case 0:
61 switch (opc2) {
62 case 0:
63 switch (crm) {
64 case 0:
65 return MISCREG_DBGDIDR;
66 case 1:
67 return MISCREG_DBGDSCRint;
68 }
69 break;
70 }
71 break;
72 case 7:
73 switch (opc2) {
74 case 0:
75 switch (crm) {
76 case 0:
77 return MISCREG_JIDR;
78 }
79 break;
80 }
81 break;
82 }
83 break;
84 case 1:
85 switch (opc1) {
86 case 6:
87 switch (crm) {
88 case 0:
89 switch (opc2) {
90 case 0:
91 return MISCREG_TEEHBR;
92 }
93 break;
94 }
95 break;
96 case 7:
97 switch (crm) {
98 case 0:
99 switch (opc2) {
100 case 0:
101 return MISCREG_JOSCR;
102 }
103 break;
104 }
105 break;
106 }
107 break;
108 case 2:
109 switch (opc1) {
110 case 7:
111 switch (crm) {
112 case 0:
113 switch (opc2) {
114 case 0:
115 return MISCREG_JMCR;
116 }
117 break;
118 }
119 break;
120 }
121 break;
122 }
123 // If we get here then it must be a register that we haven't implemented
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn, opc1, crm, opc2);
126 return MISCREG_CP14_UNIMPL;
127}
128
129using namespace std;
130
131MiscRegIndex
132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133{
134 switch (crn) {
135 case 0:
136 switch (opc1) {
137 case 0:
138 switch (crm) {
139 case 0:
140 switch (opc2) {
141 case 1:
142 return MISCREG_CTR;
143 case 2:
144 return MISCREG_TCMTR;
145 case 3:
146 return MISCREG_TLBTR;
147 case 5:
148 return MISCREG_MPIDR;
149 case 6:
150 return MISCREG_REVIDR;
151 default:
152 return MISCREG_MIDR;
153 }
154 break;
155 case 1:
156 switch (opc2) {
157 case 0:
158 return MISCREG_ID_PFR0;
159 case 1:
160 return MISCREG_ID_PFR1;
161 case 2:
162 return MISCREG_ID_DFR0;
163 case 3:
164 return MISCREG_ID_AFR0;
165 case 4:
166 return MISCREG_ID_MMFR0;
167 case 5:
168 return MISCREG_ID_MMFR1;
169 case 6:
170 return MISCREG_ID_MMFR2;
171 case 7:
172 return MISCREG_ID_MMFR3;
173 }
174 break;
175 case 2:
176 switch (opc2) {
177 case 0:
178 return MISCREG_ID_ISAR0;
179 case 1:
180 return MISCREG_ID_ISAR1;
181 case 2:
182 return MISCREG_ID_ISAR2;
183 case 3:
184 return MISCREG_ID_ISAR3;
185 case 4:
186 return MISCREG_ID_ISAR4;
187 case 5:
188 return MISCREG_ID_ISAR5;
189 case 6:
190 case 7:
191 return MISCREG_RAZ; // read as zero
192 }
193 break;
194 default:
195 return MISCREG_RAZ; // read as zero
196 }
197 break;
198 case 1:
199 if (crm == 0) {
200 switch (opc2) {
201 case 0:
202 return MISCREG_CCSIDR;
203 case 1:
204 return MISCREG_CLIDR;
205 case 7:
206 return MISCREG_AIDR;
207 }
208 }
209 break;
210 case 2:
211 if (crm == 0 && opc2 == 0) {
212 return MISCREG_CSSELR;
213 }
214 break;
215 case 4:
216 if (crm == 0) {
217 if (opc2 == 0)
218 return MISCREG_VPIDR;
219 else if (opc2 == 5)
220 return MISCREG_VMPIDR;
221 }
222 break;
223 }
224 break;
225 case 1:
226 if (opc1 == 0) {
227 if (crm == 0) {
228 switch (opc2) {
229 case 0:
230 return MISCREG_SCTLR;
231 case 1:
232 return MISCREG_ACTLR;
233 case 0x2:
234 return MISCREG_CPACR;
235 }
236 } else if (crm == 1) {
237 switch (opc2) {
238 case 0:
239 return MISCREG_SCR;
240 case 1:
241 return MISCREG_SDER;
242 case 2:
243 return MISCREG_NSACR;
244 }
245 }
246 } else if (opc1 == 4) {
247 if (crm == 0) {
248 if (opc2 == 0)
249 return MISCREG_HSCTLR;
250 else if (opc2 == 1)
251 return MISCREG_HACTLR;
252 } else if (crm == 1) {
253 switch (opc2) {
254 case 0:
255 return MISCREG_HCR;
256 case 1:
257 return MISCREG_HDCR;
258 case 2:
259 return MISCREG_HCPTR;
260 case 3:
261 return MISCREG_HSTR;
262 case 7:
263 return MISCREG_HACR;
264 }
265 }
266 }
267 break;
268 case 2:
269 if (opc1 == 0 && crm == 0) {
270 switch (opc2) {
271 case 0:
272 return MISCREG_TTBR0;
273 case 1:
274 return MISCREG_TTBR1;
275 case 2:
276 return MISCREG_TTBCR;
277 }
278 } else if (opc1 == 4) {
279 if (crm == 0 && opc2 == 2)
280 return MISCREG_HTCR;
281 else if (crm == 1 && opc2 == 2)
282 return MISCREG_VTCR;
283 }
284 break;
285 case 3:
286 if (opc1 == 0 && crm == 0 && opc2 == 0) {
287 return MISCREG_DACR;
288 }
289 break;
290 case 4:
291 if (opc1 == 0 && crm == 6 && opc2 == 0) {
292 return MISCREG_ICC_PMR;
293 }
294 break;
295 case 5:
296 if (opc1 == 0) {
297 if (crm == 0) {
298 if (opc2 == 0) {
299 return MISCREG_DFSR;
300 } else if (opc2 == 1) {
301 return MISCREG_IFSR;
302 }
303 } else if (crm == 1) {
304 if (opc2 == 0) {
305 return MISCREG_ADFSR;
306 } else if (opc2 == 1) {
307 return MISCREG_AIFSR;
308 }
309 }
310 } else if (opc1 == 4) {
311 if (crm == 1) {
312 if (opc2 == 0)
313 return MISCREG_HADFSR;
314 else if (opc2 == 1)
315 return MISCREG_HAIFSR;
316 } else if (crm == 2 && opc2 == 0) {
317 return MISCREG_HSR;
318 }
319 }
320 break;
321 case 6:
322 if (opc1 == 0 && crm == 0) {
323 switch (opc2) {
324 case 0:
325 return MISCREG_DFAR;
326 case 2:
327 return MISCREG_IFAR;
328 }
329 } else if (opc1 == 4 && crm == 0) {
330 switch (opc2) {
331 case 0:
332 return MISCREG_HDFAR;
333 case 2:
334 return MISCREG_HIFAR;
335 case 4:
336 return MISCREG_HPFAR;
337 }
338 }
339 break;
340 case 7:
341 if (opc1 == 0) {
342 switch (crm) {
343 case 0:
344 if (opc2 == 4) {
345 return MISCREG_NOP;
346 }
347 break;
348 case 1:
349 switch (opc2) {
350 case 0:
351 return MISCREG_ICIALLUIS;
352 case 6:
353 return MISCREG_BPIALLIS;
354 }
355 break;
356 case 4:
357 if (opc2 == 0) {
358 return MISCREG_PAR;
359 }
360 break;
361 case 5:
362 switch (opc2) {
363 case 0:
364 return MISCREG_ICIALLU;
365 case 1:
366 return MISCREG_ICIMVAU;
367 case 4:
368 return MISCREG_CP15ISB;
369 case 6:
370 return MISCREG_BPIALL;
371 case 7:
372 return MISCREG_BPIMVA;
373 }
374 break;
375 case 6:
376 if (opc2 == 1) {
377 return MISCREG_DCIMVAC;
378 } else if (opc2 == 2) {
379 return MISCREG_DCISW;
380 }
381 break;
382 case 8:
383 switch (opc2) {
384 case 0:
385 return MISCREG_ATS1CPR;
386 case 1:
387 return MISCREG_ATS1CPW;
388 case 2:
389 return MISCREG_ATS1CUR;
390 case 3:
391 return MISCREG_ATS1CUW;
392 case 4:
393 return MISCREG_ATS12NSOPR;
394 case 5:
395 return MISCREG_ATS12NSOPW;
396 case 6:
397 return MISCREG_ATS12NSOUR;
398 case 7:
399 return MISCREG_ATS12NSOUW;
400 }
401 break;
402 case 10:
403 switch (opc2) {
404 case 1:
405 return MISCREG_DCCMVAC;
406 case 2:
407 return MISCREG_DCCSW;
408 case 4:
409 return MISCREG_CP15DSB;
410 case 5:
411 return MISCREG_CP15DMB;
412 }
413 break;
414 case 11:
415 if (opc2 == 1) {
416 return MISCREG_DCCMVAU;
417 }
418 break;
419 case 13:
420 if (opc2 == 1) {
421 return MISCREG_NOP;
422 }
423 break;
424 case 14:
425 if (opc2 == 1) {
426 return MISCREG_DCCIMVAC;
427 } else if (opc2 == 2) {
428 return MISCREG_DCCISW;
429 }
430 break;
431 }
432 } else if (opc1 == 4 && crm == 8) {
433 if (opc2 == 0)
434 return MISCREG_ATS1HR;
435 else if (opc2 == 1)
436 return MISCREG_ATS1HW;
437 }
438 break;
439 case 8:
440 if (opc1 == 0) {
441 switch (crm) {
442 case 3:
443 switch (opc2) {
444 case 0:
445 return MISCREG_TLBIALLIS;
446 case 1:
447 return MISCREG_TLBIMVAIS;
448 case 2:
449 return MISCREG_TLBIASIDIS;
450 case 3:
451 return MISCREG_TLBIMVAAIS;
452 case 5:
453 return MISCREG_TLBIMVALIS;
454 case 7:
455 return MISCREG_TLBIMVAALIS;
456 }
457 break;
458 case 5:
459 switch (opc2) {
460 case 0:
461 return MISCREG_ITLBIALL;
462 case 1:
463 return MISCREG_ITLBIMVA;
464 case 2:
465 return MISCREG_ITLBIASID;
466 }
467 break;
468 case 6:
469 switch (opc2) {
470 case 0:
471 return MISCREG_DTLBIALL;
472 case 1:
473 return MISCREG_DTLBIMVA;
474 case 2:
475 return MISCREG_DTLBIASID;
476 }
477 break;
478 case 7:
479 switch (opc2) {
480 case 0:
481 return MISCREG_TLBIALL;
482 case 1:
483 return MISCREG_TLBIMVA;
484 case 2:
485 return MISCREG_TLBIASID;
486 case 3:
487 return MISCREG_TLBIMVAA;
488 case 5:
489 return MISCREG_TLBIMVAL;
490 case 7:
491 return MISCREG_TLBIMVAAL;
492 }
493 break;
494 }
495 } else if (opc1 == 4) {
496 if (crm == 0) {
497 switch (opc2) {
498 case 1:
499 return MISCREG_TLBIIPAS2IS;
500 case 5:
501 return MISCREG_TLBIIPAS2LIS;
502 }
503 } else if (crm == 3) {
504 switch (opc2) {
505 case 0:
506 return MISCREG_TLBIALLHIS;
507 case 1:
508 return MISCREG_TLBIMVAHIS;
509 case 4:
510 return MISCREG_TLBIALLNSNHIS;
511 case 5:
512 return MISCREG_TLBIMVALHIS;
513 }
514 } else if (crm == 4) {
515 switch (opc2) {
516 case 1:
517 return MISCREG_TLBIIPAS2;
518 case 5:
519 return MISCREG_TLBIIPAS2L;
520 }
521 } else if (crm == 7) {
522 switch (opc2) {
523 case 0:
524 return MISCREG_TLBIALLH;
525 case 1:
526 return MISCREG_TLBIMVAH;
527 case 4:
528 return MISCREG_TLBIALLNSNH;
529 case 5:
530 return MISCREG_TLBIMVALH;
531 }
532 }
533 }
534 break;
535 case 9:
536 // Every cop register with CRn = 9 and CRm in
537 // {0-2}, {5-8} is implementation defined regardless
538 // of opc1 and opc2.
539 switch (crm) {
540 case 0:
541 case 1:
542 case 2:
543 case 5:
544 case 6:
545 case 7:
546 case 8:
547 return MISCREG_IMPDEF_UNIMPL;
548 }
549 if (opc1 == 0) {
550 switch (crm) {
551 case 12:
552 switch (opc2) {
553 case 0:
554 return MISCREG_PMCR;
555 case 1:
556 return MISCREG_PMCNTENSET;
557 case 2:
558 return MISCREG_PMCNTENCLR;
559 case 3:
560 return MISCREG_PMOVSR;
561 case 4:
562 return MISCREG_PMSWINC;
563 case 5:
564 return MISCREG_PMSELR;
565 case 6:
566 return MISCREG_PMCEID0;
567 case 7:
568 return MISCREG_PMCEID1;
569 }
570 break;
571 case 13:
572 switch (opc2) {
573 case 0:
574 return MISCREG_PMCCNTR;
575 case 1:
576 // Selector is PMSELR.SEL
577 return MISCREG_PMXEVTYPER_PMCCFILTR;
578 case 2:
579 return MISCREG_PMXEVCNTR;
580 }
581 break;
582 case 14:
583 switch (opc2) {
584 case 0:
585 return MISCREG_PMUSERENR;
586 case 1:
587 return MISCREG_PMINTENSET;
588 case 2:
589 return MISCREG_PMINTENCLR;
590 case 3:
591 return MISCREG_PMOVSSET;
592 }
593 break;
594 }
595 } else if (opc1 == 1) {
596 switch (crm) {
597 case 0:
598 switch (opc2) {
599 case 2: // L2CTLR, L2 Control Register
600 return MISCREG_L2CTLR;
601 case 3:
602 return MISCREG_L2ECTLR;
603 }
604 break;
605 break;
606 }
607 }
608 break;
609 case 10:
610 if (opc1 == 0) {
611 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
612 if (crm < 2) {
613 return MISCREG_IMPDEF_UNIMPL;
614 } else if (crm == 2) { // TEX Remap Registers
615 if (opc2 == 0) {
616 // Selector is TTBCR.EAE
617 return MISCREG_PRRR_MAIR0;
618 } else if (opc2 == 1) {
619 // Selector is TTBCR.EAE
620 return MISCREG_NMRR_MAIR1;
621 }
622 } else if (crm == 3) {
623 if (opc2 == 0) {
624 return MISCREG_AMAIR0;
625 } else if (opc2 == 1) {
626 return MISCREG_AMAIR1;
627 }
628 }
629 } else if (opc1 == 4) {
630 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
631 if (crm == 2) {
632 if (opc2 == 0)
633 return MISCREG_HMAIR0;
634 else if (opc2 == 1)
635 return MISCREG_HMAIR1;
636 } else if (crm == 3) {
637 if (opc2 == 0)
638 return MISCREG_HAMAIR0;
639 else if (opc2 == 1)
640 return MISCREG_HAMAIR1;
641 }
642 }
643 break;
644 case 11:
645 if (opc1 <=7) {
646 switch (crm) {
647 case 0:
648 case 1:
649 case 2:
650 case 3:
651 case 4:
652 case 5:
653 case 6:
654 case 7:
655 case 8:
656 case 15:
657 // Reserved for DMA operations for TCM access
658 return MISCREG_IMPDEF_UNIMPL;
659 default:
660 break;
661 }
662 }
663 break;
664 case 12:
665 if (opc1 == 0) {
666 if (crm == 0) {
667 if (opc2 == 0) {
668 return MISCREG_VBAR;
669 } else if (opc2 == 1) {
670 return MISCREG_MVBAR;
671 }
672 } else if (crm == 1) {
673 if (opc2 == 0) {
674 return MISCREG_ISR;
675 }
676 } else if (crm == 8) {
677 switch (opc2) {
678 case 0:
679 return MISCREG_ICC_IAR0;
680 case 1:
681 return MISCREG_ICC_EOIR0;
682 case 2:
683 return MISCREG_ICC_HPPIR0;
684 case 3:
685 return MISCREG_ICC_BPR0;
686 case 4:
687 return MISCREG_ICC_AP0R0;
688 case 5:
689 return MISCREG_ICC_AP0R1;
690 case 6:
691 return MISCREG_ICC_AP0R2;
692 case 7:
693 return MISCREG_ICC_AP0R3;
694 }
695 } else if (crm == 9) {
696 switch (opc2) {
697 case 0:
698 return MISCREG_ICC_AP1R0;
699 case 1:
700 return MISCREG_ICC_AP1R1;
701 case 2:
702 return MISCREG_ICC_AP1R2;
703 case 3:
704 return MISCREG_ICC_AP1R3;
705 }
706 } else if (crm == 11) {
707 switch (opc2) {
708 case 1:
709 return MISCREG_ICC_DIR;
710 case 3:
711 return MISCREG_ICC_RPR;
712 }
713 } else if (crm == 12) {
714 switch (opc2) {
715 case 0:
716 return MISCREG_ICC_IAR1;
717 case 1:
718 return MISCREG_ICC_EOIR1;
719 case 2:
720 return MISCREG_ICC_HPPIR1;
721 case 3:
722 return MISCREG_ICC_BPR1;
723 case 4:
724 return MISCREG_ICC_CTLR;
725 case 5:
726 return MISCREG_ICC_SRE;
727 case 6:
728 return MISCREG_ICC_IGRPEN0;
729 case 7:
730 return MISCREG_ICC_IGRPEN1;
731 }
732 }
733 } else if (opc1 == 4) {
734 if (crm == 0 && opc2 == 0) {
735 return MISCREG_HVBAR;
736 } else if (crm == 8) {
737 switch (opc2) {
738 case 0:
739 return MISCREG_ICH_AP0R0;
740 case 1:
741 return MISCREG_ICH_AP0R1;
742 case 2:
743 return MISCREG_ICH_AP0R2;
744 case 3:
745 return MISCREG_ICH_AP0R3;
746 }
747 } else if (crm == 9) {
748 switch (opc2) {
749 case 0:
750 return MISCREG_ICH_AP1R0;
751 case 1:
752 return MISCREG_ICH_AP1R1;
753 case 2:
754 return MISCREG_ICH_AP1R2;
755 case 3:
756 return MISCREG_ICH_AP1R3;
757 case 5:
758 return MISCREG_ICC_HSRE;
759 }
760 } else if (crm == 11) {
761 switch (opc2) {
762 case 0:
763 return MISCREG_ICH_HCR;
764 case 1:
765 return MISCREG_ICH_VTR;
766 case 2:
767 return MISCREG_ICH_MISR;
768 case 3:
769 return MISCREG_ICH_EISR;
770 case 5:
771 return MISCREG_ICH_ELRSR;
772 case 7:
773 return MISCREG_ICH_VMCR;
774 }
775 } else if (crm == 12) {
776 switch (opc2) {
777 case 0:
778 return MISCREG_ICH_LR0;
779 case 1:
780 return MISCREG_ICH_LR1;
781 case 2:
782 return MISCREG_ICH_LR2;
783 case 3:
784 return MISCREG_ICH_LR3;
785 case 4:
786 return MISCREG_ICH_LR4;
787 case 5:
788 return MISCREG_ICH_LR5;
789 case 6:
790 return MISCREG_ICH_LR6;
791 case 7:
792 return MISCREG_ICH_LR7;
793 }
794 } else if (crm == 13) {
795 switch (opc2) {
796 case 0:
797 return MISCREG_ICH_LR8;
798 case 1:
799 return MISCREG_ICH_LR9;
800 case 2:
801 return MISCREG_ICH_LR10;
802 case 3:
803 return MISCREG_ICH_LR11;
804 case 4:
805 return MISCREG_ICH_LR12;
806 case 5:
807 return MISCREG_ICH_LR13;
808 case 6:
809 return MISCREG_ICH_LR14;
810 case 7:
811 return MISCREG_ICH_LR15;
812 }
813 } else if (crm == 14) {
814 switch (opc2) {
815 case 0:
816 return MISCREG_ICH_LRC0;
817 case 1:
818 return MISCREG_ICH_LRC1;
819 case 2:
820 return MISCREG_ICH_LRC2;
821 case 3:
822 return MISCREG_ICH_LRC3;
823 case 4:
824 return MISCREG_ICH_LRC4;
825 case 5:
826 return MISCREG_ICH_LRC5;
827 case 6:
828 return MISCREG_ICH_LRC6;
829 case 7:
830 return MISCREG_ICH_LRC7;
831 }
832 } else if (crm == 15) {
833 switch (opc2) {
834 case 0:
835 return MISCREG_ICH_LRC8;
836 case 1:
837 return MISCREG_ICH_LRC9;
838 case 2:
839 return MISCREG_ICH_LRC10;
840 case 3:
841 return MISCREG_ICH_LRC11;
842 case 4:
843 return MISCREG_ICH_LRC12;
844 case 5:
845 return MISCREG_ICH_LRC13;
846 case 6:
847 return MISCREG_ICH_LRC14;
848 case 7:
849 return MISCREG_ICH_LRC15;
850 }
851 }
852 } else if (opc1 == 6) {
853 if (crm == 12) {
854 switch (opc2) {
855 case 4:
856 return MISCREG_ICC_MCTLR;
857 case 5:
858 return MISCREG_ICC_MSRE;
859 case 7:
860 return MISCREG_ICC_MGRPEN1;
861 }
862 }
863 }
864 break;
865 case 13:
866 if (opc1 == 0) {
867 if (crm == 0) {
868 switch (opc2) {
869 case 0:
870 return MISCREG_FCSEIDR;
871 case 1:
872 return MISCREG_CONTEXTIDR;
873 case 2:
874 return MISCREG_TPIDRURW;
875 case 3:
876 return MISCREG_TPIDRURO;
877 case 4:
878 return MISCREG_TPIDRPRW;
879 }
880 }
881 } else if (opc1 == 4) {
882 if (crm == 0 && opc2 == 2)
883 return MISCREG_HTPIDR;
884 }
885 break;
886 case 14:
887 if (opc1 == 0) {
888 switch (crm) {
889 case 0:
890 if (opc2 == 0)
891 return MISCREG_CNTFRQ;
892 break;
893 case 1:
894 if (opc2 == 0)
895 return MISCREG_CNTKCTL;
896 break;
897 case 2:
898 if (opc2 == 0)
899 return MISCREG_CNTP_TVAL;
900 else if (opc2 == 1)
901 return MISCREG_CNTP_CTL;
902 break;
903 case 3:
904 if (opc2 == 0)
905 return MISCREG_CNTV_TVAL;
906 else if (opc2 == 1)
907 return MISCREG_CNTV_CTL;
908 break;
909 }
910 } else if (opc1 == 4) {
911 if (crm == 1 && opc2 == 0) {
912 return MISCREG_CNTHCTL;
913 } else if (crm == 2) {
914 if (opc2 == 0)
915 return MISCREG_CNTHP_TVAL;
916 else if (opc2 == 1)
917 return MISCREG_CNTHP_CTL;
918 }
919 }
920 break;
921 case 15:
922 // Implementation defined
923 return MISCREG_IMPDEF_UNIMPL;
924 }
925 // Unrecognized register
926 return MISCREG_CP15_UNIMPL;
927}
928
929MiscRegIndex
930decodeCP15Reg64(unsigned crm, unsigned opc1)
931{
932 switch (crm) {
933 case 2:
934 switch (opc1) {
935 case 0:
936 return MISCREG_TTBR0;
937 case 1:
938 return MISCREG_TTBR1;
939 case 4:
940 return MISCREG_HTTBR;
941 case 6:
942 return MISCREG_VTTBR;
943 }
944 break;
945 case 7:
946 if (opc1 == 0)
947 return MISCREG_PAR;
948 break;
949 case 14:
950 switch (opc1) {
951 case 0:
952 return MISCREG_CNTPCT;
953 case 1:
954 return MISCREG_CNTVCT;
955 case 2:
956 return MISCREG_CNTP_CVAL;
957 case 3:
958 return MISCREG_CNTV_CVAL;
959 case 4:
960 return MISCREG_CNTVOFF;
961 case 6:
962 return MISCREG_CNTHP_CVAL;
963 }
964 break;
965 case 12:
966 switch (opc1) {
967 case 0:
968 return MISCREG_ICC_SGI1R;
969 case 1:
970 return MISCREG_ICC_ASGI1R;
971 case 2:
972 return MISCREG_ICC_SGI0R;
973 default:
974 break;
975 }
976 break;
977 case 15:
978 if (opc1 == 0)
979 return MISCREG_CPUMERRSR;
980 else if (opc1 == 1)
981 return MISCREG_L2MERRSR;
982 break;
983 }
984 // Unrecognized register
985 return MISCREG_CP15_UNIMPL;
986}
987
988std::tuple<bool, bool>
989canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
990{
991 bool secure = !scr.ns;
992 bool canRead = false;
993 bool undefined = false;
994
995 switch (cpsr.mode) {
996 case MODE_USER:
997 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
998 miscRegInfo[reg][MISCREG_USR_NS_RD];
999 break;
1000 case MODE_FIQ:
1001 case MODE_IRQ:
1002 case MODE_SVC:
1003 case MODE_ABORT:
1004 case MODE_UNDEFINED:
1005 case MODE_SYSTEM:
1006 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1007 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1008 break;
1009 case MODE_MON:
1010 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1011 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1012 break;
1013 case MODE_HYP:
1014 canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1015 break;
1016 default:
1017 undefined = true;
1018 }
1019 // can't do permissions checkes on the root of a banked pair of regs
1020 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1021 return std::make_tuple(canRead, undefined);
1022}
1023
1024std::tuple<bool, bool>
1025canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
1026{
1027 bool secure = !scr.ns;
1028 bool canWrite = false;
1029 bool undefined = false;
1030
1031 switch (cpsr.mode) {
1032 case MODE_USER:
1033 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1034 miscRegInfo[reg][MISCREG_USR_NS_WR];
1035 break;
1036 case MODE_FIQ:
1037 case MODE_IRQ:
1038 case MODE_SVC:
1039 case MODE_ABORT:
1040 case MODE_UNDEFINED:
1041 case MODE_SYSTEM:
1042 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1043 miscRegInfo[reg][MISCREG_PRI_NS_WR];
1044 break;
1045 case MODE_MON:
1046 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1047 miscRegInfo[reg][MISCREG_MON_NS1_WR];
1048 break;
1049 case MODE_HYP:
1050 canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
1051 break;
1052 default:
1053 undefined = true;
1054 }
1055 // can't do permissions checkes on the root of a banked pair of regs
1056 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1057 return std::make_tuple(canWrite, undefined);
1058}
1059
1060int
1061snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
1062{
1063 SCR scr = tc->readMiscReg(MISCREG_SCR);
1064 return snsBankedIndex(reg, tc, scr.ns);
1065}
1066
1067int
1068snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
1069{
1070 int reg_as_int = static_cast<int>(reg);
1071 if (miscRegInfo[reg][MISCREG_BANKED]) {
1072 reg_as_int += (ArmSystem::haveSecurity(tc) &&
1073 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
1074 }
1075 return reg_as_int;
1076}
1077
1078int
1079snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
1080{
1081 SCR scr = tc->readMiscReg(MISCREG_SCR);
1082 return tc->getIsaPtr()->snsBankedIndex64(reg, scr.ns);
1083}
1084
1085/**
1086 * If the reg is a child reg of a banked set, then the parent is the last
1087 * banked one in the list. This is messy, and the wish is to eventually have
1088 * the bitmap replaced with a better data structure. the preUnflatten function
1089 * initializes a lookup table to speed up the search for these banked
1090 * registers.
1091 */
1092
1093int unflattenResultMiscReg[NUM_MISCREGS];
1094
1095void
1096preUnflattenMiscReg()
1097{
1098 int reg = -1;
1099 for (int i = 0 ; i < NUM_MISCREGS; i++){
1100 if (miscRegInfo[i][MISCREG_BANKED])
1101 reg = i;
1102 if (miscRegInfo[i][MISCREG_BANKED_CHILD])
1103 unflattenResultMiscReg[i] = reg;
1104 else
1105 unflattenResultMiscReg[i] = i;
1106 // if this assert fails, no parent was found, and something is broken
1107 assert(unflattenResultMiscReg[i] > -1);
1108 }
1109}
1110
1111int
1112unflattenMiscReg(int reg)
1113{
1114 return unflattenResultMiscReg[reg];
1115}
1116
1117bool
1118canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1119{
1120 // Check for SP_EL0 access while SPSEL == 0
1121 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1122 return false;
1123
1124 // Check for RVBAR access
1125 if (reg == MISCREG_RVBAR_EL1) {
1126 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1127 if (highest_el == EL2 || highest_el == EL3)
1128 return false;
1129 }
1130 if (reg == MISCREG_RVBAR_EL2) {
1131 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1132 if (highest_el == EL3)
1133 return false;
1134 }
1135
1136 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1137
1138 switch (currEL(cpsr)) {
1139 case EL0:
1140 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1141 miscRegInfo[reg][MISCREG_USR_NS_RD];
1142 case EL1:
1143 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1144 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1145 case EL2:
1146 return miscRegInfo[reg][MISCREG_HYP_RD];
1147 case EL3:
1148 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1149 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1150 default:
1151 panic("Invalid exception level");
1152 }
1153}
1154
1155bool
1156canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1157{
1158 // Check for SP_EL0 access while SPSEL == 0
1159 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1160 return false;
1161 ExceptionLevel el = currEL(cpsr);
1162 if (reg == MISCREG_DAIF) {
1163 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1164 if (el == EL0 && !sctlr.uma)
1165 return false;
1166 }
1167 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
1168 // In syscall-emulation mode, this test is skipped and DCZVA is always
1169 // allowed at EL0
1170 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1171 if (el == EL0 && !sctlr.dze)
1172 return false;
1173 }
1174 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
1175 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1176 if (el == EL0 && !sctlr.uci)
1177 return false;
1178 }
1179
1180 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1181
1182 switch (el) {
1183 case EL0:
1184 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1185 miscRegInfo[reg][MISCREG_USR_NS_WR];
1186 case EL1:
1187 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1188 miscRegInfo[reg][MISCREG_PRI_NS_WR];
1189 case EL2:
1190 return miscRegInfo[reg][MISCREG_HYP_WR];
1191 case EL3:
1192 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1193 miscRegInfo[reg][MISCREG_MON_NS1_WR];
1194 default:
1195 panic("Invalid exception level");
1196 }
1197}
1198
1199MiscRegIndex
1200decodeAArch64SysReg(unsigned op0, unsigned op1,
1201 unsigned crn, unsigned crm,
1202 unsigned op2)
1203{
1204 switch (op0) {
1205 case 1:
1206 switch (crn) {
1207 case 7:
1208 switch (op1) {
1209 case 0:
1210 switch (crm) {
1211 case 1:
1212 switch (op2) {
1213 case 0:
1214 return MISCREG_IC_IALLUIS;
1215 }
1216 break;
1217 case 5:
1218 switch (op2) {
1219 case 0:
1220 return MISCREG_IC_IALLU;
1221 }
1222 break;
1223 case 6:
1224 switch (op2) {
1225 case 1:
1226 return MISCREG_DC_IVAC_Xt;
1227 case 2:
1228 return MISCREG_DC_ISW_Xt;
1229 }
1230 break;
1231 case 8:
1232 switch (op2) {
1233 case 0:
1234 return MISCREG_AT_S1E1R_Xt;
1235 case 1:
1236 return MISCREG_AT_S1E1W_Xt;
1237 case 2:
1238 return MISCREG_AT_S1E0R_Xt;
1239 case 3:
1240 return MISCREG_AT_S1E0W_Xt;
1241 }
1242 break;
1243 case 10:
1244 switch (op2) {
1245 case 2:
1246 return MISCREG_DC_CSW_Xt;
1247 }
1248 break;
1249 case 14:
1250 switch (op2) {
1251 case 2:
1252 return MISCREG_DC_CISW_Xt;
1253 }
1254 break;
1255 }
1256 break;
1257 case 3:
1258 switch (crm) {
1259 case 4:
1260 switch (op2) {
1261 case 1:
1262 return MISCREG_DC_ZVA_Xt;
1263 }
1264 break;
1265 case 5:
1266 switch (op2) {
1267 case 1:
1268 return MISCREG_IC_IVAU_Xt;
1269 }
1270 break;
1271 case 10:
1272 switch (op2) {
1273 case 1:
1274 return MISCREG_DC_CVAC_Xt;
1275 }
1276 break;
1277 case 11:
1278 switch (op2) {
1279 case 1:
1280 return MISCREG_DC_CVAU_Xt;
1281 }
1282 break;
1283 case 14:
1284 switch (op2) {
1285 case 1:
1286 return MISCREG_DC_CIVAC_Xt;
1287 }
1288 break;
1289 }
1290 break;
1291 case 4:
1292 switch (crm) {
1293 case 8:
1294 switch (op2) {
1295 case 0:
1296 return MISCREG_AT_S1E2R_Xt;
1297 case 1:
1298 return MISCREG_AT_S1E2W_Xt;
1299 case 4:
1300 return MISCREG_AT_S12E1R_Xt;
1301 case 5:
1302 return MISCREG_AT_S12E1W_Xt;
1303 case 6:
1304 return MISCREG_AT_S12E0R_Xt;
1305 case 7:
1306 return MISCREG_AT_S12E0W_Xt;
1307 }
1308 break;
1309 }
1310 break;
1311 case 6:
1312 switch (crm) {
1313 case 8:
1314 switch (op2) {
1315 case 0:
1316 return MISCREG_AT_S1E3R_Xt;
1317 case 1:
1318 return MISCREG_AT_S1E3W_Xt;
1319 }
1320 break;
1321 }
1322 break;
1323 }
1324 break;
1325 case 8:
1326 switch (op1) {
1327 case 0:
1328 switch (crm) {
1329 case 3:
1330 switch (op2) {
1331 case 0:
1332 return MISCREG_TLBI_VMALLE1IS;
1333 case 1:
1334 return MISCREG_TLBI_VAE1IS_Xt;
1335 case 2:
1336 return MISCREG_TLBI_ASIDE1IS_Xt;
1337 case 3:
1338 return MISCREG_TLBI_VAAE1IS_Xt;
1339 case 5:
1340 return MISCREG_TLBI_VALE1IS_Xt;
1341 case 7:
1342 return MISCREG_TLBI_VAALE1IS_Xt;
1343 }
1344 break;
1345 case 7:
1346 switch (op2) {
1347 case 0:
1348 return MISCREG_TLBI_VMALLE1;
1349 case 1:
1350 return MISCREG_TLBI_VAE1_Xt;
1351 case 2:
1352 return MISCREG_TLBI_ASIDE1_Xt;
1353 case 3:
1354 return MISCREG_TLBI_VAAE1_Xt;
1355 case 5:
1356 return MISCREG_TLBI_VALE1_Xt;
1357 case 7:
1358 return MISCREG_TLBI_VAALE1_Xt;
1359 }
1360 break;
1361 }
1362 break;
1363 case 4:
1364 switch (crm) {
1365 case 0:
1366 switch (op2) {
1367 case 1:
1368 return MISCREG_TLBI_IPAS2E1IS_Xt;
1369 case 5:
1370 return MISCREG_TLBI_IPAS2LE1IS_Xt;
1371 }
1372 break;
1373 case 3:
1374 switch (op2) {
1375 case 0:
1376 return MISCREG_TLBI_ALLE2IS;
1377 case 1:
1378 return MISCREG_TLBI_VAE2IS_Xt;
1379 case 4:
1380 return MISCREG_TLBI_ALLE1IS;
1381 case 5:
1382 return MISCREG_TLBI_VALE2IS_Xt;
1383 case 6:
1384 return MISCREG_TLBI_VMALLS12E1IS;
1385 }
1386 break;
1387 case 4:
1388 switch (op2) {
1389 case 1:
1390 return MISCREG_TLBI_IPAS2E1_Xt;
1391 case 5:
1392 return MISCREG_TLBI_IPAS2LE1_Xt;
1393 }
1394 break;
1395 case 7:
1396 switch (op2) {
1397 case 0:
1398 return MISCREG_TLBI_ALLE2;
1399 case 1:
1400 return MISCREG_TLBI_VAE2_Xt;
1401 case 4:
1402 return MISCREG_TLBI_ALLE1;
1403 case 5:
1404 return MISCREG_TLBI_VALE2_Xt;
1405 case 6:
1406 return MISCREG_TLBI_VMALLS12E1;
1407 }
1408 break;
1409 }
1410 break;
1411 case 6:
1412 switch (crm) {
1413 case 3:
1414 switch (op2) {
1415 case 0:
1416 return MISCREG_TLBI_ALLE3IS;
1417 case 1:
1418 return MISCREG_TLBI_VAE3IS_Xt;
1419 case 5:
1420 return MISCREG_TLBI_VALE3IS_Xt;
1421 }
1422 break;
1423 case 7:
1424 switch (op2) {
1425 case 0:
1426 return MISCREG_TLBI_ALLE3;
1427 case 1:
1428 return MISCREG_TLBI_VAE3_Xt;
1429 case 5:
1430 return MISCREG_TLBI_VALE3_Xt;
1431 }
1432 break;
1433 }
1434 break;
1435 }
1436 break;
1437 case 11:
1438 case 15:
1439 // SYS Instruction with CRn = { 11, 15 }
1440 // (Trappable by HCR_EL2.TIDCP)
1441 return MISCREG_IMPDEF_UNIMPL;
1442 }
1443 break;
1444 case 2:
1445 switch (crn) {
1446 case 0:
1447 switch (op1) {
1448 case 0:
1449 switch (crm) {
1450 case 0:
1451 switch (op2) {
1452 case 2:
1453 return MISCREG_OSDTRRX_EL1;
1454 case 4:
1455 return MISCREG_DBGBVR0_EL1;
1456 case 5:
1457 return MISCREG_DBGBCR0_EL1;
1458 case 6:
1459 return MISCREG_DBGWVR0_EL1;
1460 case 7:
1461 return MISCREG_DBGWCR0_EL1;
1462 }
1463 break;
1464 case 1:
1465 switch (op2) {
1466 case 4:
1467 return MISCREG_DBGBVR1_EL1;
1468 case 5:
1469 return MISCREG_DBGBCR1_EL1;
1470 case 6:
1471 return MISCREG_DBGWVR1_EL1;
1472 case 7:
1473 return MISCREG_DBGWCR1_EL1;
1474 }
1475 break;
1476 case 2:
1477 switch (op2) {
1478 case 0:
1479 return MISCREG_MDCCINT_EL1;
1480 case 2:
1481 return MISCREG_MDSCR_EL1;
1482 case 4:
1483 return MISCREG_DBGBVR2_EL1;
1484 case 5:
1485 return MISCREG_DBGBCR2_EL1;
1486 case 6:
1487 return MISCREG_DBGWVR2_EL1;
1488 case 7:
1489 return MISCREG_DBGWCR2_EL1;
1490 }
1491 break;
1492 case 3:
1493 switch (op2) {
1494 case 2:
1495 return MISCREG_OSDTRTX_EL1;
1496 case 4:
1497 return MISCREG_DBGBVR3_EL1;
1498 case 5:
1499 return MISCREG_DBGBCR3_EL1;
1500 case 6:
1501 return MISCREG_DBGWVR3_EL1;
1502 case 7:
1503 return MISCREG_DBGWCR3_EL1;
1504 }
1505 break;
1506 case 4:
1507 switch (op2) {
1508 case 4:
1509 return MISCREG_DBGBVR4_EL1;
1510 case 5:
1511 return MISCREG_DBGBCR4_EL1;
1512 }
1513 break;
1514 case 5:
1515 switch (op2) {
1516 case 4:
1517 return MISCREG_DBGBVR5_EL1;
1518 case 5:
1519 return MISCREG_DBGBCR5_EL1;
1520 }
1521 break;
1522 case 6:
1523 switch (op2) {
1524 case 2:
1525 return MISCREG_OSECCR_EL1;
1526 }
1527 break;
1528 }
1529 break;
1530 case 2:
1531 switch (crm) {
1532 case 0:
1533 switch (op2) {
1534 case 0:
1535 return MISCREG_TEECR32_EL1;
1536 }
1537 break;
1538 }
1539 break;
1540 case 3:
1541 switch (crm) {
1542 case 1:
1543 switch (op2) {
1544 case 0:
1545 return MISCREG_MDCCSR_EL0;
1546 }
1547 break;
1548 case 4:
1549 switch (op2) {
1550 case 0:
1551 return MISCREG_MDDTR_EL0;
1552 }
1553 break;
1554 case 5:
1555 switch (op2) {
1556 case 0:
1557 return MISCREG_MDDTRRX_EL0;
1558 }
1559 break;
1560 }
1561 break;
1562 case 4:
1563 switch (crm) {
1564 case 7:
1565 switch (op2) {
1566 case 0:
1567 return MISCREG_DBGVCR32_EL2;
1568 }
1569 break;
1570 }
1571 break;
1572 }
1573 break;
1574 case 1:
1575 switch (op1) {
1576 case 0:
1577 switch (crm) {
1578 case 0:
1579 switch (op2) {
1580 case 0:
1581 return MISCREG_MDRAR_EL1;
1582 case 4:
1583 return MISCREG_OSLAR_EL1;
1584 }
1585 break;
1586 case 1:
1587 switch (op2) {
1588 case 4:
1589 return MISCREG_OSLSR_EL1;
1590 }
1591 break;
1592 case 3:
1593 switch (op2) {
1594 case 4:
1595 return MISCREG_OSDLR_EL1;
1596 }
1597 break;
1598 case 4:
1599 switch (op2) {
1600 case 4:
1601 return MISCREG_DBGPRCR_EL1;
1602 }
1603 break;
1604 }
1605 break;
1606 case 2:
1607 switch (crm) {
1608 case 0:
1609 switch (op2) {
1610 case 0:
1611 return MISCREG_TEEHBR32_EL1;
1612 }
1613 break;
1614 }
1615 break;
1616 }
1617 break;
1618 case 7:
1619 switch (op1) {
1620 case 0:
1621 switch (crm) {
1622 case 8:
1623 switch (op2) {
1624 case 6:
1625 return MISCREG_DBGCLAIMSET_EL1;
1626 }
1627 break;
1628 case 9:
1629 switch (op2) {
1630 case 6:
1631 return MISCREG_DBGCLAIMCLR_EL1;
1632 }
1633 break;
1634 case 14:
1635 switch (op2) {
1636 case 6:
1637 return MISCREG_DBGAUTHSTATUS_EL1;
1638 }
1639 break;
1640 }
1641 break;
1642 }
1643 break;
1644 }
1645 break;
1646 case 3:
1647 switch (crn) {
1648 case 0:
1649 switch (op1) {
1650 case 0:
1651 switch (crm) {
1652 case 0:
1653 switch (op2) {
1654 case 0:
1655 return MISCREG_MIDR_EL1;
1656 case 5:
1657 return MISCREG_MPIDR_EL1;
1658 case 6:
1659 return MISCREG_REVIDR_EL1;
1660 }
1661 break;
1662 case 1:
1663 switch (op2) {
1664 case 0:
1665 return MISCREG_ID_PFR0_EL1;
1666 case 1:
1667 return MISCREG_ID_PFR1_EL1;
1668 case 2:
1669 return MISCREG_ID_DFR0_EL1;
1670 case 3:
1671 return MISCREG_ID_AFR0_EL1;
1672 case 4:
1673 return MISCREG_ID_MMFR0_EL1;
1674 case 5:
1675 return MISCREG_ID_MMFR1_EL1;
1676 case 6:
1677 return MISCREG_ID_MMFR2_EL1;
1678 case 7:
1679 return MISCREG_ID_MMFR3_EL1;
1680 }
1681 break;
1682 case 2:
1683 switch (op2) {
1684 case 0:
1685 return MISCREG_ID_ISAR0_EL1;
1686 case 1:
1687 return MISCREG_ID_ISAR1_EL1;
1688 case 2:
1689 return MISCREG_ID_ISAR2_EL1;
1690 case 3:
1691 return MISCREG_ID_ISAR3_EL1;
1692 case 4:
1693 return MISCREG_ID_ISAR4_EL1;
1694 case 5:
1695 return MISCREG_ID_ISAR5_EL1;
1696 }
1697 break;
1698 case 3:
1699 switch (op2) {
1700 case 0:
1701 return MISCREG_MVFR0_EL1;
1702 case 1:
1703 return MISCREG_MVFR1_EL1;
1704 case 2:
1705 return MISCREG_MVFR2_EL1;
1706 case 3 ... 7:
1707 return MISCREG_RAZ;
1708 }
1709 break;
1710 case 4:
1711 switch (op2) {
1712 case 0:
1713 return MISCREG_ID_AA64PFR0_EL1;
1714 case 1:
1715 return MISCREG_ID_AA64PFR1_EL1;
1716 case 2 ... 3:
1717 return MISCREG_RAZ;
1718 case 4:
1719 return MISCREG_ID_AA64ZFR0_EL1;
1720 case 5 ... 7:
1721 return MISCREG_RAZ;
1722 }
1723 break;
1724 case 5:
1725 switch (op2) {
1726 case 0:
1727 return MISCREG_ID_AA64DFR0_EL1;
1728 case 1:
1729 return MISCREG_ID_AA64DFR1_EL1;
1730 case 4:
1731 return MISCREG_ID_AA64AFR0_EL1;
1732 case 5:
1733 return MISCREG_ID_AA64AFR1_EL1;
1734 case 2:
1735 case 3:
1736 case 6:
1737 case 7:
1738 return MISCREG_RAZ;
1739 }
1740 break;
1741 case 6:
1742 switch (op2) {
1743 case 0:
1744 return MISCREG_ID_AA64ISAR0_EL1;
1745 case 1:
1746 return MISCREG_ID_AA64ISAR1_EL1;
1747 case 2 ... 7:
1748 return MISCREG_RAZ;
1749 }
1750 break;
1751 case 7:
1752 switch (op2) {
1753 case 0:
1754 return MISCREG_ID_AA64MMFR0_EL1;
1755 case 1:
1756 return MISCREG_ID_AA64MMFR1_EL1;
1757 case 2:
1758 return MISCREG_ID_AA64MMFR2_EL1;
1759 case 3 ... 7:
1760 return MISCREG_RAZ;
1761 }
1762 break;
1763 }
1764 break;
1765 case 1:
1766 switch (crm) {
1767 case 0:
1768 switch (op2) {
1769 case 0:
1770 return MISCREG_CCSIDR_EL1;
1771 case 1:
1772 return MISCREG_CLIDR_EL1;
1773 case 7:
1774 return MISCREG_AIDR_EL1;
1775 }
1776 break;
1777 }
1778 break;
1779 case 2:
1780 switch (crm) {
1781 case 0:
1782 switch (op2) {
1783 case 0:
1784 return MISCREG_CSSELR_EL1;
1785 }
1786 break;
1787 }
1788 break;
1789 case 3:
1790 switch (crm) {
1791 case 0:
1792 switch (op2) {
1793 case 1:
1794 return MISCREG_CTR_EL0;
1795 case 7:
1796 return MISCREG_DCZID_EL0;
1797 }
1798 break;
1799 }
1800 break;
1801 case 4:
1802 switch (crm) {
1803 case 0:
1804 switch (op2) {
1805 case 0:
1806 return MISCREG_VPIDR_EL2;
1807 case 5:
1808 return MISCREG_VMPIDR_EL2;
1809 }
1810 break;
1811 }
1812 break;
1813 }
1814 break;
1815 case 1:
1816 switch (op1) {
1817 case 0:
1818 switch (crm) {
1819 case 0:
1820 switch (op2) {
1821 case 0:
1822 return MISCREG_SCTLR_EL1;
1823 case 1:
1824 return MISCREG_ACTLR_EL1;
1825 case 2:
1826 return MISCREG_CPACR_EL1;
1827 }
1828 break;
1829 case 2:
1830 switch (op2) {
1831 case 0:
1832 return MISCREG_ZCR_EL1;
1833 }
1834 break;
1835 }
1836 break;
1837 case 4:
1838 switch (crm) {
1839 case 0:
1840 switch (op2) {
1841 case 0:
1842 return MISCREG_SCTLR_EL2;
1843 case 1:
1844 return MISCREG_ACTLR_EL2;
1845 }
1846 break;
1847 case 1:
1848 switch (op2) {
1849 case 0:
1850 return MISCREG_HCR_EL2;
1851 case 1:
1852 return MISCREG_MDCR_EL2;
1853 case 2:
1854 return MISCREG_CPTR_EL2;
1855 case 3:
1856 return MISCREG_HSTR_EL2;
1857 case 7:
1858 return MISCREG_HACR_EL2;
1859 }
1860 break;
1861 case 2:
1862 switch (op2) {
1863 case 0:
1864 return MISCREG_ZCR_EL2;
1865 }
1866 break;
1867 }
1868 break;
1869 case 5:
1870 switch (crm) {
1871 case 2:
1872 switch (op2) {
1873 case 0:
1874 return MISCREG_ZCR_EL12;
1875 }
1876 break;
1877 }
1878 break;
1879 case 6:
1880 switch (crm) {
1881 case 0:
1882 switch (op2) {
1883 case 0:
1884 return MISCREG_SCTLR_EL3;
1885 case 1:
1886 return MISCREG_ACTLR_EL3;
1887 }
1888 break;
1889 case 1:
1890 switch (op2) {
1891 case 0:
1892 return MISCREG_SCR_EL3;
1893 case 1:
1894 return MISCREG_SDER32_EL3;
1895 case 2:
1896 return MISCREG_CPTR_EL3;
1897 }
1898 break;
1899 case 2:
1900 switch (op2) {
1901 case 0:
1902 return MISCREG_ZCR_EL3;
1903 }
1904 break;
1905 case 3:
1906 switch (op2) {
1907 case 1:
1908 return MISCREG_MDCR_EL3;
1909 }
1910 break;
1911 }
1912 break;
1913 }
1914 break;
1915 case 2:
1916 switch (op1) {
1917 case 0:
1918 switch (crm) {
1919 case 0:
1920 switch (op2) {
1921 case 0:
1922 return MISCREG_TTBR0_EL1;
1923 case 1:
1924 return MISCREG_TTBR1_EL1;
1925 case 2:
1926 return MISCREG_TCR_EL1;
1927 }
1928 break;
1929 }
1930 break;
1931 case 4:
1932 switch (crm) {
1933 case 0:
1934 switch (op2) {
1935 case 0:
1936 return MISCREG_TTBR0_EL2;
1937 case 1:
1938 return MISCREG_TTBR1_EL2;
1939 case 2:
1940 return MISCREG_TCR_EL2;
1941 }
1942 break;
1943 case 1:
1944 switch (op2) {
1945 case 0:
1946 return MISCREG_VTTBR_EL2;
1947 case 2:
1948 return MISCREG_VTCR_EL2;
1949 }
1950 break;
1951 }
1952 break;
1953 case 6:
1954 switch (crm) {
1955 case 0:
1956 switch (op2) {
1957 case 0:
1958 return MISCREG_TTBR0_EL3;
1959 case 2:
1960 return MISCREG_TCR_EL3;
1961 }
1962 break;
1963 }
1964 break;
1965 }
1966 break;
1967 case 3:
1968 switch (op1) {
1969 case 4:
1970 switch (crm) {
1971 case 0:
1972 switch (op2) {
1973 case 0:
1974 return MISCREG_DACR32_EL2;
1975 }
1976 break;
1977 }
1978 break;
1979 }
1980 break;
1981 case 4:
1982 switch (op1) {
1983 case 0:
1984 switch (crm) {
1985 case 0:
1986 switch (op2) {
1987 case 0:
1988 return MISCREG_SPSR_EL1;
1989 case 1:
1990 return MISCREG_ELR_EL1;
1991 }
1992 break;
1993 case 1:
1994 switch (op2) {
1995 case 0:
1996 return MISCREG_SP_EL0;
1997 }
1998 break;
1999 case 2:
2000 switch (op2) {
2001 case 0:
2002 return MISCREG_SPSEL;
2003 case 2:
2004 return MISCREG_CURRENTEL;
2005 case 3:
2006 return MISCREG_PAN;
2007 }
2008 break;
2009 case 6:
2010 switch (op2) {
2011 case 0:
2012 return MISCREG_ICC_PMR_EL1;
2013 }
2014 break;
2015 }
2016 break;
2017 case 3:
2018 switch (crm) {
2019 case 2:
2020 switch (op2) {
2021 case 0:
2022 return MISCREG_NZCV;
2023 case 1:
2024 return MISCREG_DAIF;
2025 }
2026 break;
2027 case 4:
2028 switch (op2) {
2029 case 0:
2030 return MISCREG_FPCR;
2031 case 1:
2032 return MISCREG_FPSR;
2033 }
2034 break;
2035 case 5:
2036 switch (op2) {
2037 case 0:
2038 return MISCREG_DSPSR_EL0;
2039 case 1:
2040 return MISCREG_DLR_EL0;
2041 }
2042 break;
2043 }
2044 break;
2045 case 4:
2046 switch (crm) {
2047 case 0:
2048 switch (op2) {
2049 case 0:
2050 return MISCREG_SPSR_EL2;
2051 case 1:
2052 return MISCREG_ELR_EL2;
2053 }
2054 break;
2055 case 1:
2056 switch (op2) {
2057 case 0:
2058 return MISCREG_SP_EL1;
2059 }
2060 break;
2061 case 3:
2062 switch (op2) {
2063 case 0:
2064 return MISCREG_SPSR_IRQ_AA64;
2065 case 1:
2066 return MISCREG_SPSR_ABT_AA64;
2067 case 2:
2068 return MISCREG_SPSR_UND_AA64;
2069 case 3:
2070 return MISCREG_SPSR_FIQ_AA64;
2071 }
2072 break;
2073 }
2074 break;
2075 case 6:
2076 switch (crm) {
2077 case 0:
2078 switch (op2) {
2079 case 0:
2080 return MISCREG_SPSR_EL3;
2081 case 1:
2082 return MISCREG_ELR_EL3;
2083 }
2084 break;
2085 case 1:
2086 switch (op2) {
2087 case 0:
2088 return MISCREG_SP_EL2;
2089 }
2090 break;
2091 }
2092 break;
2093 }
2094 break;
2095 case 5:
2096 switch (op1) {
2097 case 0:
2098 switch (crm) {
2099 case 1:
2100 switch (op2) {
2101 case 0:
2102 return MISCREG_AFSR0_EL1;
2103 case 1:
2104 return MISCREG_AFSR1_EL1;
2105 }
2106 break;
2107 case 2:
2108 switch (op2) {
2109 case 0:
2110 return MISCREG_ESR_EL1;
2111 }
2112 break;
2113 case 3:
2114 switch (op2) {
2115 case 0:
2116 return MISCREG_ERRIDR_EL1;
2117 case 1:
2118 return MISCREG_ERRSELR_EL1;
2119 }
2120 break;
2121 case 4:
2122 switch (op2) {
2123 case 0:
2124 return MISCREG_ERXFR_EL1;
2125 case 1:
2126 return MISCREG_ERXCTLR_EL1;
2127 case 2:
2128 return MISCREG_ERXSTATUS_EL1;
2129 case 3:
2130 return MISCREG_ERXADDR_EL1;
2131 }
2132 break;
2133 case 5:
2134 switch (op2) {
2135 case 0:
2136 return MISCREG_ERXMISC0_EL1;
2137 case 1:
2138 return MISCREG_ERXMISC1_EL1;
2139 }
2140 break;
2141 }
2142 break;
2143 case 4:
2144 switch (crm) {
2145 case 0:
2146 switch (op2) {
2147 case 1:
2148 return MISCREG_IFSR32_EL2;
2149 }
2150 break;
2151 case 1:
2152 switch (op2) {
2153 case 0:
2154 return MISCREG_AFSR0_EL2;
2155 case 1:
2156 return MISCREG_AFSR1_EL2;
2157 }
2158 break;
2159 case 2:
2160 switch (op2) {
2161 case 0:
2162 return MISCREG_ESR_EL2;
2163 case 3:
2164 return MISCREG_VSESR_EL2;
2165 }
2166 break;
2167 case 3:
2168 switch (op2) {
2169 case 0:
2170 return MISCREG_FPEXC32_EL2;
2171 }
2172 break;
2173 }
2174 break;
2175 case 6:
2176 switch (crm) {
2177 case 1:
2178 switch (op2) {
2179 case 0:
2180 return MISCREG_AFSR0_EL3;
2181 case 1:
2182 return MISCREG_AFSR1_EL3;
2183 }
2184 break;
2185 case 2:
2186 switch (op2) {
2187 case 0:
2188 return MISCREG_ESR_EL3;
2189 }
2190 break;
2191 }
2192 break;
2193 }
2194 break;
2195 case 6:
2196 switch (op1) {
2197 case 0:
2198 switch (crm) {
2199 case 0:
2200 switch (op2) {
2201 case 0:
2202 return MISCREG_FAR_EL1;
2203 }
2204 break;
2205 }
2206 break;
2207 case 4:
2208 switch (crm) {
2209 case 0:
2210 switch (op2) {
2211 case 0:
2212 return MISCREG_FAR_EL2;
2213 case 4:
2214 return MISCREG_HPFAR_EL2;
2215 }
2216 break;
2217 }
2218 break;
2219 case 6:
2220 switch (crm) {
2221 case 0:
2222 switch (op2) {
2223 case 0:
2224 return MISCREG_FAR_EL3;
2225 }
2226 break;
2227 }
2228 break;
2229 }
2230 break;
2231 case 7:
2232 switch (op1) {
2233 case 0:
2234 switch (crm) {
2235 case 4:
2236 switch (op2) {
2237 case 0:
2238 return MISCREG_PAR_EL1;
2239 }
2240 break;
2241 }
2242 break;
2243 }
2244 break;
2245 case 9:
2246 switch (op1) {
2247 case 0:
2248 switch (crm) {
2249 case 14:
2250 switch (op2) {
2251 case 1:
2252 return MISCREG_PMINTENSET_EL1;
2253 case 2:
2254 return MISCREG_PMINTENCLR_EL1;
2255 }
2256 break;
2257 }
2258 break;
2259 case 3:
2260 switch (crm) {
2261 case 12:
2262 switch (op2) {
2263 case 0:
2264 return MISCREG_PMCR_EL0;
2265 case 1:
2266 return MISCREG_PMCNTENSET_EL0;
2267 case 2:
2268 return MISCREG_PMCNTENCLR_EL0;
2269 case 3:
2270 return MISCREG_PMOVSCLR_EL0;
2271 case 4:
2272 return MISCREG_PMSWINC_EL0;
2273 case 5:
2274 return MISCREG_PMSELR_EL0;
2275 case 6:
2276 return MISCREG_PMCEID0_EL0;
2277 case 7:
2278 return MISCREG_PMCEID1_EL0;
2279 }
2280 break;
2281 case 13:
2282 switch (op2) {
2283 case 0:
2284 return MISCREG_PMCCNTR_EL0;
2285 case 1:
2286 return MISCREG_PMXEVTYPER_EL0;
2287 case 2:
2288 return MISCREG_PMXEVCNTR_EL0;
2289 }
2290 break;
2291 case 14:
2292 switch (op2) {
2293 case 0:
2294 return MISCREG_PMUSERENR_EL0;
2295 case 3:
2296 return MISCREG_PMOVSSET_EL0;
2297 }
2298 break;
2299 }
2300 break;
2301 }
2302 break;
2303 case 10:
2304 switch (op1) {
2305 case 0:
2306 switch (crm) {
2307 case 2:
2308 switch (op2) {
2309 case 0:
2310 return MISCREG_MAIR_EL1;
2311 }
2312 break;
2313 case 3:
2314 switch (op2) {
2315 case 0:
2316 return MISCREG_AMAIR_EL1;
2317 }
2318 break;
2319 }
2320 break;
2321 case 4:
2322 switch (crm) {
2323 case 2:
2324 switch (op2) {
2325 case 0:
2326 return MISCREG_MAIR_EL2;
2327 }
2328 break;
2329 case 3:
2330 switch (op2) {
2331 case 0:
2332 return MISCREG_AMAIR_EL2;
2333 }
2334 break;
2335 }
2336 break;
2337 case 6:
2338 switch (crm) {
2339 case 2:
2340 switch (op2) {
2341 case 0:
2342 return MISCREG_MAIR_EL3;
2343 }
2344 break;
2345 case 3:
2346 switch (op2) {
2347 case 0:
2348 return MISCREG_AMAIR_EL3;
2349 }
2350 break;
2351 }
2352 break;
2353 }
2354 break;
2355 case 11:
2356 switch (op1) {
2357 case 1:
2358 switch (crm) {
2359 case 0:
2360 switch (op2) {
2361 case 2:
2362 return MISCREG_L2CTLR_EL1;
2363 case 3:
2364 return MISCREG_L2ECTLR_EL1;
2365 }
2366 break;
2367 }
2368 M5_FALLTHROUGH;
2369 default:
2370 // S3_<op1>_11_<Cm>_<op2>
2371 return MISCREG_IMPDEF_UNIMPL;
2372 }
2373 M5_UNREACHABLE;
2374 case 12:
2375 switch (op1) {
2376 case 0:
2377 switch (crm) {
2378 case 0:
2379 switch (op2) {
2380 case 0:
2381 return MISCREG_VBAR_EL1;
2382 case 1:
2383 return MISCREG_RVBAR_EL1;
2384 }
2385 break;
2386 case 1:
2387 switch (op2) {
2388 case 0:
2389 return MISCREG_ISR_EL1;
2390 case 1:
2391 return MISCREG_DISR_EL1;
2392 }
2393 break;
2394 case 8:
2395 switch (op2) {
2396 case 0:
2397 return MISCREG_ICC_IAR0_EL1;
2398 case 1:
2399 return MISCREG_ICC_EOIR0_EL1;
2400 case 2:
2401 return MISCREG_ICC_HPPIR0_EL1;
2402 case 3:
2403 return MISCREG_ICC_BPR0_EL1;
2404 case 4:
2405 return MISCREG_ICC_AP0R0_EL1;
2406 case 5:
2407 return MISCREG_ICC_AP0R1_EL1;
2408 case 6:
2409 return MISCREG_ICC_AP0R2_EL1;
2410 case 7:
2411 return MISCREG_ICC_AP0R3_EL1;
2412 }
2413 break;
2414 case 9:
2415 switch (op2) {
2416 case 0:
2417 return MISCREG_ICC_AP1R0_EL1;
2418 case 1:
2419 return MISCREG_ICC_AP1R1_EL1;
2420 case 2:
2421 return MISCREG_ICC_AP1R2_EL1;
2422 case 3:
2423 return MISCREG_ICC_AP1R3_EL1;
2424 }
2425 break;
2426 case 11:
2427 switch (op2) {
2428 case 1:
2429 return MISCREG_ICC_DIR_EL1;
2430 case 3:
2431 return MISCREG_ICC_RPR_EL1;
2432 case 5:
2433 return MISCREG_ICC_SGI1R_EL1;
2434 case 6:
2435 return MISCREG_ICC_ASGI1R_EL1;
2436 case 7:
2437 return MISCREG_ICC_SGI0R_EL1;
2438 }
2439 break;
2440 case 12:
2441 switch (op2) {
2442 case 0:
2443 return MISCREG_ICC_IAR1_EL1;
2444 case 1:
2445 return MISCREG_ICC_EOIR1_EL1;
2446 case 2:
2447 return MISCREG_ICC_HPPIR1_EL1;
2448 case 3:
2449 return MISCREG_ICC_BPR1_EL1;
2450 case 4:
2451 return MISCREG_ICC_CTLR_EL1;
2452 case 5:
2453 return MISCREG_ICC_SRE_EL1;
2454 case 6:
2455 return MISCREG_ICC_IGRPEN0_EL1;
2456 case 7:
2457 return MISCREG_ICC_IGRPEN1_EL1;
2458 }
2459 break;
2460 }
2461 break;
2462 case 4:
2463 switch (crm) {
2464 case 0:
2465 switch (op2) {
2466 case 0:
2467 return MISCREG_VBAR_EL2;
2468 case 1:
2469 return MISCREG_RVBAR_EL2;
2470 }
2471 break;
2472 case 1:
2473 switch (op2) {
2474 case 1:
2475 return MISCREG_VDISR_EL2;
2476 }
2477 break;
2478 case 8:
2479 switch (op2) {
2480 case 0:
2481 return MISCREG_ICH_AP0R0_EL2;
2482 case 1:
2483 return MISCREG_ICH_AP0R1_EL2;
2484 case 2:
2485 return MISCREG_ICH_AP0R2_EL2;
2486 case 3:
2487 return MISCREG_ICH_AP0R3_EL2;
2488 }
2489 break;
2490 case 9:
2491 switch (op2) {
2492 case 0:
2493 return MISCREG_ICH_AP1R0_EL2;
2494 case 1:
2495 return MISCREG_ICH_AP1R1_EL2;
2496 case 2:
2497 return MISCREG_ICH_AP1R2_EL2;
2498 case 3:
2499 return MISCREG_ICH_AP1R3_EL2;
2500 case 5:
2501 return MISCREG_ICC_SRE_EL2;
2502 }
2503 break;
2504 case 11:
2505 switch (op2) {
2506 case 0:
2507 return MISCREG_ICH_HCR_EL2;
2508 case 1:
2509 return MISCREG_ICH_VTR_EL2;
2510 case 2:
2511 return MISCREG_ICH_MISR_EL2;
2512 case 3:
2513 return MISCREG_ICH_EISR_EL2;
2514 case 5:
2515 return MISCREG_ICH_ELRSR_EL2;
2516 case 7:
2517 return MISCREG_ICH_VMCR_EL2;
2518 }
2519 break;
2520 case 12:
2521 switch (op2) {
2522 case 0:
2523 return MISCREG_ICH_LR0_EL2;
2524 case 1:
2525 return MISCREG_ICH_LR1_EL2;
2526 case 2:
2527 return MISCREG_ICH_LR2_EL2;
2528 case 3:
2529 return MISCREG_ICH_LR3_EL2;
2530 case 4:
2531 return MISCREG_ICH_LR4_EL2;
2532 case 5:
2533 return MISCREG_ICH_LR5_EL2;
2534 case 6:
2535 return MISCREG_ICH_LR6_EL2;
2536 case 7:
2537 return MISCREG_ICH_LR7_EL2;
2538 }
2539 break;
2540 case 13:
2541 switch (op2) {
2542 case 0:
2543 return MISCREG_ICH_LR8_EL2;
2544 case 1:
2545 return MISCREG_ICH_LR9_EL2;
2546 case 2:
2547 return MISCREG_ICH_LR10_EL2;
2548 case 3:
2549 return MISCREG_ICH_LR11_EL2;
2550 case 4:
2551 return MISCREG_ICH_LR12_EL2;
2552 case 5:
2553 return MISCREG_ICH_LR13_EL2;
2554 case 6:
2555 return MISCREG_ICH_LR14_EL2;
2556 case 7:
2557 return MISCREG_ICH_LR15_EL2;
2558 }
2559 break;
2560 }
2561 break;
2562 case 6:
2563 switch (crm) {
2564 case 0:
2565 switch (op2) {
2566 case 0:
2567 return MISCREG_VBAR_EL3;
2568 case 1:
2569 return MISCREG_RVBAR_EL3;
2570 case 2:
2571 return MISCREG_RMR_EL3;
2572 }
2573 break;
2574 case 12:
2575 switch (op2) {
2576 case 4:
2577 return MISCREG_ICC_CTLR_EL3;
2578 case 5:
2579 return MISCREG_ICC_SRE_EL3;
2580 case 7:
2581 return MISCREG_ICC_IGRPEN1_EL3;
2582 }
2583 break;
2584 }
2585 break;
2586 }
2587 break;
2588 case 13:
2589 switch (op1) {
2590 case 0:
2591 switch (crm) {
2592 case 0:
2593 switch (op2) {
2594 case 1:
2595 return MISCREG_CONTEXTIDR_EL1;
2596 case 4:
2597 return MISCREG_TPIDR_EL1;
2598 }
2599 break;
2600 }
2601 break;
2602 case 3:
2603 switch (crm) {
2604 case 0:
2605 switch (op2) {
2606 case 2:
2607 return MISCREG_TPIDR_EL0;
2608 case 3:
2609 return MISCREG_TPIDRRO_EL0;
2610 }
2611 break;
2612 }
2613 break;
2614 case 4:
2615 switch (crm) {
2616 case 0:
2617 switch (op2) {
2618 case 1:
2619 return MISCREG_CONTEXTIDR_EL2;
2620 case 2:
2621 return MISCREG_TPIDR_EL2;
2622 }
2623 break;
2624 }
2625 break;
2626 case 6:
2627 switch (crm) {
2628 case 0:
2629 switch (op2) {
2630 case 2:
2631 return MISCREG_TPIDR_EL3;
2632 }
2633 break;
2634 }
2635 break;
2636 }
2637 break;
2638 case 14:
2639 switch (op1) {
2640 case 0:
2641 switch (crm) {
2642 case 1:
2643 switch (op2) {
2644 case 0:
2645 return MISCREG_CNTKCTL_EL1;
2646 }
2647 break;
2648 }
2649 break;
2650 case 3:
2651 switch (crm) {
2652 case 0:
2653 switch (op2) {
2654 case 0:
2655 return MISCREG_CNTFRQ_EL0;
2656 case 1:
2657 return MISCREG_CNTPCT_EL0;
2658 case 2:
2659 return MISCREG_CNTVCT_EL0;
2660 }
2661 break;
2662 case 2:
2663 switch (op2) {
2664 case 0:
2665 return MISCREG_CNTP_TVAL_EL0;
2666 case 1:
2667 return MISCREG_CNTP_CTL_EL0;
2668 case 2:
2669 return MISCREG_CNTP_CVAL_EL0;
2670 }
2671 break;
2672 case 3:
2673 switch (op2) {
2674 case 0:
2675 return MISCREG_CNTV_TVAL_EL0;
2676 case 1:
2677 return MISCREG_CNTV_CTL_EL0;
2678 case 2:
2679 return MISCREG_CNTV_CVAL_EL0;
2680 }
2681 break;
2682 case 8:
2683 switch (op2) {
2684 case 0:
2685 return MISCREG_PMEVCNTR0_EL0;
2686 case 1:
2687 return MISCREG_PMEVCNTR1_EL0;
2688 case 2:
2689 return MISCREG_PMEVCNTR2_EL0;
2690 case 3:
2691 return MISCREG_PMEVCNTR3_EL0;
2692 case 4:
2693 return MISCREG_PMEVCNTR4_EL0;
2694 case 5:
2695 return MISCREG_PMEVCNTR5_EL0;
2696 }
2697 break;
2698 case 12:
2699 switch (op2) {
2700 case 0:
2701 return MISCREG_PMEVTYPER0_EL0;
2702 case 1:
2703 return MISCREG_PMEVTYPER1_EL0;
2704 case 2:
2705 return MISCREG_PMEVTYPER2_EL0;
2706 case 3:
2707 return MISCREG_PMEVTYPER3_EL0;
2708 case 4:
2709 return MISCREG_PMEVTYPER4_EL0;
2710 case 5:
2711 return MISCREG_PMEVTYPER5_EL0;
2712 }
2713 break;
2714 case 15:
2715 switch (op2) {
2716 case 7:
2717 return MISCREG_PMCCFILTR_EL0;
2718 }
2719 }
2720 break;
2721 case 4:
2722 switch (crm) {
2723 case 0:
2724 switch (op2) {
2725 case 3:
2726 return MISCREG_CNTVOFF_EL2;
2727 }
2728 break;
2729 case 1:
2730 switch (op2) {
2731 case 0:
2732 return MISCREG_CNTHCTL_EL2;
2733 }
2734 break;
2735 case 2:
2736 switch (op2) {
2737 case 0:
2738 return MISCREG_CNTHP_TVAL_EL2;
2739 case 1:
2740 return MISCREG_CNTHP_CTL_EL2;
2741 case 2:
2742 return MISCREG_CNTHP_CVAL_EL2;
2743 }
2744 break;
2745 case 3:
2746 switch (op2) {
2747 case 0:
2748 return MISCREG_CNTHV_TVAL_EL2;
2749 case 1:
2750 return MISCREG_CNTHV_CTL_EL2;
2751 case 2:
2752 return MISCREG_CNTHV_CVAL_EL2;
2753 }
2754 break;
2755 }
2756 break;
2757 case 7:
2758 switch (crm) {
2759 case 2:
2760 switch (op2) {
2761 case 0:
2762 return MISCREG_CNTPS_TVAL_EL1;
2763 case 1:
2764 return MISCREG_CNTPS_CTL_EL1;
2765 case 2:
2766 return MISCREG_CNTPS_CVAL_EL1;
2767 }
2768 break;
2769 }
2770 break;
2771 }
2772 break;
2773 case 15:
2774 switch (op1) {
2775 case 0:
2776 switch (crm) {
2777 case 0:
2778 switch (op2) {
2779 case 0:
2780 return MISCREG_IL1DATA0_EL1;
2781 case 1:
2782 return MISCREG_IL1DATA1_EL1;
2783 case 2:
2784 return MISCREG_IL1DATA2_EL1;
2785 case 3:
2786 return MISCREG_IL1DATA3_EL1;
2787 }
2788 break;
2789 case 1:
2790 switch (op2) {
2791 case 0:
2792 return MISCREG_DL1DATA0_EL1;
2793 case 1:
2794 return MISCREG_DL1DATA1_EL1;
2795 case 2:
2796 return MISCREG_DL1DATA2_EL1;
2797 case 3:
2798 return MISCREG_DL1DATA3_EL1;
2799 case 4:
2800 return MISCREG_DL1DATA4_EL1;
2801 }
2802 break;
2803 }
2804 break;
2805 case 1:
2806 switch (crm) {
2807 case 0:
2808 switch (op2) {
2809 case 0:
2810 return MISCREG_L2ACTLR_EL1;
2811 }
2812 break;
2813 case 2:
2814 switch (op2) {
2815 case 0:
2816 return MISCREG_CPUACTLR_EL1;
2817 case 1:
2818 return MISCREG_CPUECTLR_EL1;
2819 case 2:
2820 return MISCREG_CPUMERRSR_EL1;
2821 case 3:
2822 return MISCREG_L2MERRSR_EL1;
2823 }
2824 break;
2825 case 3:
2826 switch (op2) {
2827 case 0:
2828 return MISCREG_CBAR_EL1;
2829
2830 }
2831 break;
2832 }
2833 break;
2834 }
2835 // S3_<op1>_15_<Cm>_<op2>
2836 return MISCREG_IMPDEF_UNIMPL;
2837 }
2838 break;
2839 }
2840
2841 return MISCREG_UNKNOWN;
2842}
2843
2844bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2845
2846void
2847ISA::initializeMiscRegMetadata()
2848{
2849 // the MiscReg metadata tables are shared across all instances of the
2850 // ISA object, so there's no need to initialize them multiple times.
2851 static bool completed = false;
2852 if (completed)
2853 return;
2854
2855 // This boolean variable specifies if the system is running in aarch32 at
2856 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2857 // is running in aarch64 (aarch32EL3 = false)
2858 bool aarch32EL3 = haveSecurity && !highestELIs64;
2859
2860 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2861 // unsupported
2862 bool SPAN = false;
2863
2864 // Implicit error synchronization event enable (Arm 8.2+), unsupported
2865 bool IESB = false;
2866
2867 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2868 // unsupported
2869 bool LSMAOE = false;
2870
2871 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2872 bool nTLSMD = false;
2873
2874 // Pointer authentication (Arm 8.3+), unsupported
2875 bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2876 bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2877 bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2878 bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2879
2880 /**
2881 * Some registers alias with others, and therefore need to be translated.
2882 * When two mapping registers are given, they are the 32b lower and
2883 * upper halves, respectively, of the 64b register being mapped.
2884 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2885 *
2886 * NAM = "not architecturally mandated",
2887 * from ARM DDI 0487A.i, template text
2888 * "AArch64 System register ___ can be mapped to
2889 * AArch32 System register ___, but this is not
2890 * architecturally mandated."
2891 */
2892
2893 InitReg(MISCREG_CPSR)
2894 .allPrivileges();
2895 InitReg(MISCREG_SPSR)
2896 .allPrivileges();
2897 InitReg(MISCREG_SPSR_FIQ)
2898 .allPrivileges();
2899 InitReg(MISCREG_SPSR_IRQ)
2900 .allPrivileges();
2901 InitReg(MISCREG_SPSR_SVC)
2902 .allPrivileges();
2903 InitReg(MISCREG_SPSR_MON)
2904 .allPrivileges();
2905 InitReg(MISCREG_SPSR_ABT)
2906 .allPrivileges();
2907 InitReg(MISCREG_SPSR_HYP)
2908 .allPrivileges();
2909 InitReg(MISCREG_SPSR_UND)
2910 .allPrivileges();
2911 InitReg(MISCREG_ELR_HYP)
2912 .allPrivileges();
2913 InitReg(MISCREG_FPSID)
2914 .allPrivileges();
2915 InitReg(MISCREG_FPSCR)
2916 .allPrivileges();
2917 InitReg(MISCREG_MVFR1)
2918 .allPrivileges();
2919 InitReg(MISCREG_MVFR0)
2920 .allPrivileges();
2921 InitReg(MISCREG_FPEXC)
2922 .allPrivileges();
2923
2924 // Helper registers
2925 InitReg(MISCREG_CPSR_MODE)
2926 .allPrivileges();
2927 InitReg(MISCREG_CPSR_Q)
2928 .allPrivileges();
2929 InitReg(MISCREG_FPSCR_EXC)
2930 .allPrivileges();
2931 InitReg(MISCREG_FPSCR_QC)
2932 .allPrivileges();
2933 InitReg(MISCREG_LOCKADDR)
2934 .allPrivileges();
2935 InitReg(MISCREG_LOCKFLAG)
2936 .allPrivileges();
2937 InitReg(MISCREG_PRRR_MAIR0)
2938 .mutex()
2939 .banked();
2940 InitReg(MISCREG_PRRR_MAIR0_NS)
2941 .mutex()
2942 .privSecure(!aarch32EL3)
2943 .bankedChild();
2944 InitReg(MISCREG_PRRR_MAIR0_S)
2945 .mutex()
2946 .bankedChild();
2947 InitReg(MISCREG_NMRR_MAIR1)
2948 .mutex()
2949 .banked();
2950 InitReg(MISCREG_NMRR_MAIR1_NS)
2951 .mutex()
2952 .privSecure(!aarch32EL3)
2953 .bankedChild();
2954 InitReg(MISCREG_NMRR_MAIR1_S)
2955 .mutex()
2956 .bankedChild();
2957 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2958 .mutex();
2959 InitReg(MISCREG_SCTLR_RST)
2960 .allPrivileges();
2961 InitReg(MISCREG_SEV_MAILBOX)
2962 .allPrivileges();
2963
2964 // AArch32 CP14 registers
2965 InitReg(MISCREG_DBGDIDR)
2966 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2967 InitReg(MISCREG_DBGDSCRint)
2968 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2969 InitReg(MISCREG_DBGDCCINT)
2970 .unimplemented()
2971 .allPrivileges();
2972 InitReg(MISCREG_DBGDTRTXint)
2973 .unimplemented()
2974 .allPrivileges();
2975 InitReg(MISCREG_DBGDTRRXint)
2976 .unimplemented()
2977 .allPrivileges();
2978 InitReg(MISCREG_DBGWFAR)
2979 .unimplemented()
2980 .allPrivileges();
2981 InitReg(MISCREG_DBGVCR)
2982 .unimplemented()
2983 .allPrivileges();
2984 InitReg(MISCREG_DBGDTRRXext)
2985 .unimplemented()
2986 .allPrivileges();
2987 InitReg(MISCREG_DBGDSCRext)
2988 .unimplemented()
2989 .warnNotFail()
2990 .allPrivileges();
2991 InitReg(MISCREG_DBGDTRTXext)
2992 .unimplemented()
2993 .allPrivileges();
2994 InitReg(MISCREG_DBGOSECCR)
2995 .unimplemented()
2996 .allPrivileges();
2997 InitReg(MISCREG_DBGBVR0)
2998 .unimplemented()
2999 .allPrivileges();
3000 InitReg(MISCREG_DBGBVR1)
3001 .unimplemented()
3002 .allPrivileges();
3003 InitReg(MISCREG_DBGBVR2)
3004 .unimplemented()
3005 .allPrivileges();
3006 InitReg(MISCREG_DBGBVR3)
3007 .unimplemented()
3008 .allPrivileges();
3009 InitReg(MISCREG_DBGBVR4)
3010 .unimplemented()
3011 .allPrivileges();
3012 InitReg(MISCREG_DBGBVR5)
3013 .unimplemented()
3014 .allPrivileges();
3015 InitReg(MISCREG_DBGBCR0)
3016 .unimplemented()
3017 .allPrivileges();
3018 InitReg(MISCREG_DBGBCR1)
3019 .unimplemented()
3020 .allPrivileges();
3021 InitReg(MISCREG_DBGBCR2)
3022 .unimplemented()
3023 .allPrivileges();
3024 InitReg(MISCREG_DBGBCR3)
3025 .unimplemented()
3026 .allPrivileges();
3027 InitReg(MISCREG_DBGBCR4)
3028 .unimplemented()
3029 .allPrivileges();
3030 InitReg(MISCREG_DBGBCR5)
3031 .unimplemented()
3032 .allPrivileges();
3033 InitReg(MISCREG_DBGWVR0)
3034 .unimplemented()
3035 .allPrivileges();
3036 InitReg(MISCREG_DBGWVR1)
3037 .unimplemented()
3038 .allPrivileges();
3039 InitReg(MISCREG_DBGWVR2)
3040 .unimplemented()
3041 .allPrivileges();
3042 InitReg(MISCREG_DBGWVR3)
3043 .unimplemented()
3044 .allPrivileges();
3045 InitReg(MISCREG_DBGWCR0)
3046 .unimplemented()
3047 .allPrivileges();
3048 InitReg(MISCREG_DBGWCR1)
3049 .unimplemented()
3050 .allPrivileges();
3051 InitReg(MISCREG_DBGWCR2)
3052 .unimplemented()
3053 .allPrivileges();
3054 InitReg(MISCREG_DBGWCR3)
3055 .unimplemented()
3056 .allPrivileges();
3057 InitReg(MISCREG_DBGDRAR)
3058 .unimplemented()
3059 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3060 InitReg(MISCREG_DBGBXVR4)
3061 .unimplemented()
3062 .allPrivileges();
3063 InitReg(MISCREG_DBGBXVR5)
3064 .unimplemented()
3065 .allPrivileges();
3066 InitReg(MISCREG_DBGOSLAR)
3067 .unimplemented()
3068 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3069 InitReg(MISCREG_DBGOSLSR)
3070 .unimplemented()
3071 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3072 InitReg(MISCREG_DBGOSDLR)
3073 .unimplemented()
3074 .allPrivileges();
3075 InitReg(MISCREG_DBGPRCR)
3076 .unimplemented()
3077 .allPrivileges();
3078 InitReg(MISCREG_DBGDSAR)
3079 .unimplemented()
3080 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3081 InitReg(MISCREG_DBGCLAIMSET)
3082 .unimplemented()
3083 .allPrivileges();
3084 InitReg(MISCREG_DBGCLAIMCLR)
3085 .unimplemented()
3086 .allPrivileges();
3087 InitReg(MISCREG_DBGAUTHSTATUS)
3088 .unimplemented()
3089 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3090 InitReg(MISCREG_DBGDEVID2)
3091 .unimplemented()
3092 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3093 InitReg(MISCREG_DBGDEVID1)
3094 .unimplemented()
3095 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3096 InitReg(MISCREG_DBGDEVID0)
3097 .unimplemented()
3098 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3099 InitReg(MISCREG_TEECR)
3100 .unimplemented()
3101 .allPrivileges();
3102 InitReg(MISCREG_JIDR)
3103 .allPrivileges();
3104 InitReg(MISCREG_TEEHBR)
3105 .allPrivileges();
3106 InitReg(MISCREG_JOSCR)
3107 .allPrivileges();
3108 InitReg(MISCREG_JMCR)
3109 .allPrivileges();
3110
3111 // AArch32 CP15 registers
3112 InitReg(MISCREG_MIDR)
3113 .allPrivileges().exceptUserMode().writes(0);
3114 InitReg(MISCREG_CTR)
3115 .allPrivileges().exceptUserMode().writes(0);
3116 InitReg(MISCREG_TCMTR)
3117 .allPrivileges().exceptUserMode().writes(0);
3118 InitReg(MISCREG_TLBTR)
3119 .allPrivileges().exceptUserMode().writes(0);
3120 InitReg(MISCREG_MPIDR)
3121 .allPrivileges().exceptUserMode().writes(0);
3122 InitReg(MISCREG_REVIDR)
3123 .unimplemented()
3124 .warnNotFail()
3125 .allPrivileges().exceptUserMode().writes(0);
3126 InitReg(MISCREG_ID_PFR0)
3127 .allPrivileges().exceptUserMode().writes(0);
3128 InitReg(MISCREG_ID_PFR1)
3129 .allPrivileges().exceptUserMode().writes(0);
3130 InitReg(MISCREG_ID_DFR0)
3131 .allPrivileges().exceptUserMode().writes(0);
3132 InitReg(MISCREG_ID_AFR0)
3133 .allPrivileges().exceptUserMode().writes(0);
3134 InitReg(MISCREG_ID_MMFR0)
3135 .allPrivileges().exceptUserMode().writes(0);
3136 InitReg(MISCREG_ID_MMFR1)
3137 .allPrivileges().exceptUserMode().writes(0);
3138 InitReg(MISCREG_ID_MMFR2)
3139 .allPrivileges().exceptUserMode().writes(0);
3140 InitReg(MISCREG_ID_MMFR3)
3141 .allPrivileges().exceptUserMode().writes(0);
3142 InitReg(MISCREG_ID_ISAR0)
3143 .allPrivileges().exceptUserMode().writes(0);
3144 InitReg(MISCREG_ID_ISAR1)
3145 .allPrivileges().exceptUserMode().writes(0);
3146 InitReg(MISCREG_ID_ISAR2)
3147 .allPrivileges().exceptUserMode().writes(0);
3148 InitReg(MISCREG_ID_ISAR3)
3149 .allPrivileges().exceptUserMode().writes(0);
3150 InitReg(MISCREG_ID_ISAR4)
3151 .allPrivileges().exceptUserMode().writes(0);
3152 InitReg(MISCREG_ID_ISAR5)
3153 .allPrivileges().exceptUserMode().writes(0);
3154 InitReg(MISCREG_CCSIDR)
3155 .allPrivileges().exceptUserMode().writes(0);
3156 InitReg(MISCREG_CLIDR)
3157 .allPrivileges().exceptUserMode().writes(0);
3158 InitReg(MISCREG_AIDR)
3159 .allPrivileges().exceptUserMode().writes(0);
3160 InitReg(MISCREG_CSSELR)
3161 .banked();
3162 InitReg(MISCREG_CSSELR_NS)
3163 .bankedChild()
3164 .privSecure(!aarch32EL3)
3165 .nonSecure().exceptUserMode();
3166 InitReg(MISCREG_CSSELR_S)
3167 .bankedChild()
3168 .secure().exceptUserMode();
3169 InitReg(MISCREG_VPIDR)
3170 .hyp().monNonSecure();
3171 InitReg(MISCREG_VMPIDR)
3172 .hyp().monNonSecure();
3173 InitReg(MISCREG_SCTLR)
3174 .banked()
3175 // readMiscRegNoEffect() uses this metadata
3176 // despite using children (below) as backing store
3177 .res0(0x8d22c600)
3178 .res1(0x00400800 | (SPAN ? 0 : 0x800000)
3179 | (LSMAOE ? 0 : 0x10)
3180 | (nTLSMD ? 0 : 0x8));
3181 InitReg(MISCREG_SCTLR_NS)
3182 .bankedChild()
3183 .privSecure(!aarch32EL3)
3184 .nonSecure().exceptUserMode();
3185 InitReg(MISCREG_SCTLR_S)
3186 .bankedChild()
3187 .secure().exceptUserMode();
3188 InitReg(MISCREG_ACTLR)
3189 .banked();
3190 InitReg(MISCREG_ACTLR_NS)
3191 .bankedChild()
3192 .privSecure(!aarch32EL3)
3193 .nonSecure().exceptUserMode();
3194 InitReg(MISCREG_ACTLR_S)
3195 .bankedChild()
3196 .secure().exceptUserMode();
3197 InitReg(MISCREG_CPACR)
3198 .allPrivileges().exceptUserMode();
3199 InitReg(MISCREG_SCR)
3200 .mon().secure().exceptUserMode()
3201 .res0(0xff40) // [31:16], [6]
3202 .res1(0x0030); // [5:4]
3203 InitReg(MISCREG_SDER)
3204 .mon();
3205 InitReg(MISCREG_NSACR)
3206 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3207 InitReg(MISCREG_HSCTLR)
3208 .hyp().monNonSecure()
3209 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3210 | (IESB ? 0 : 0x200000)
3211 | (EnDA ? 0 : 0x8000000)
3212 | (EnIB ? 0 : 0x40000000)
3213 | (EnIA ? 0 : 0x80000000))
3214 .res1(0x30c50830);
3215 InitReg(MISCREG_HACTLR)
3216 .hyp().monNonSecure();
3217 InitReg(MISCREG_HCR)
3218 .hyp().monNonSecure();
3219 InitReg(MISCREG_HDCR)
3220 .hyp().monNonSecure();
3221 InitReg(MISCREG_HCPTR)
3222 .hyp().monNonSecure();
3223 InitReg(MISCREG_HSTR)
3224 .hyp().monNonSecure();
3225 InitReg(MISCREG_HACR)
3226 .unimplemented()
3227 .warnNotFail()
3228 .hyp().monNonSecure();
3229 InitReg(MISCREG_TTBR0)
3230 .banked();
3231 InitReg(MISCREG_TTBR0_NS)
3232 .bankedChild()
3233 .privSecure(!aarch32EL3)
3234 .nonSecure().exceptUserMode();
3235 InitReg(MISCREG_TTBR0_S)
3236 .bankedChild()
3237 .secure().exceptUserMode();
3238 InitReg(MISCREG_TTBR1)
3239 .banked();
3240 InitReg(MISCREG_TTBR1_NS)
3241 .bankedChild()
3242 .privSecure(!aarch32EL3)
3243 .nonSecure().exceptUserMode();
3244 InitReg(MISCREG_TTBR1_S)
3245 .bankedChild()
3246 .secure().exceptUserMode();
3247 InitReg(MISCREG_TTBCR)
3248 .banked();
3249 InitReg(MISCREG_TTBCR_NS)
3250 .bankedChild()
3251 .privSecure(!aarch32EL3)
3252 .nonSecure().exceptUserMode();
3253 InitReg(MISCREG_TTBCR_S)
3254 .bankedChild()
3255 .secure().exceptUserMode();
3256 InitReg(MISCREG_HTCR)
3257 .hyp().monNonSecure();
3258 InitReg(MISCREG_VTCR)
3259 .hyp().monNonSecure();
3260 InitReg(MISCREG_DACR)
3261 .banked();
3262 InitReg(MISCREG_DACR_NS)
3263 .bankedChild()
3264 .privSecure(!aarch32EL3)
3265 .nonSecure().exceptUserMode();
3266 InitReg(MISCREG_DACR_S)
3267 .bankedChild()
3268 .secure().exceptUserMode();
3269 InitReg(MISCREG_DFSR)
3270 .banked();
3271 InitReg(MISCREG_DFSR_NS)
3272 .bankedChild()
3273 .privSecure(!aarch32EL3)
3274 .nonSecure().exceptUserMode();
3275 InitReg(MISCREG_DFSR_S)
3276 .bankedChild()
3277 .secure().exceptUserMode();
3278 InitReg(MISCREG_IFSR)
3279 .banked();
3280 InitReg(MISCREG_IFSR_NS)
3281 .bankedChild()
3282 .privSecure(!aarch32EL3)
3283 .nonSecure().exceptUserMode();
3284 InitReg(MISCREG_IFSR_S)
3285 .bankedChild()
3286 .secure().exceptUserMode();
3287 InitReg(MISCREG_ADFSR)
3288 .unimplemented()
3289 .warnNotFail()
3290 .banked();
3291 InitReg(MISCREG_ADFSR_NS)
3292 .unimplemented()
3293 .warnNotFail()
3294 .bankedChild()
3295 .privSecure(!aarch32EL3)
3296 .nonSecure().exceptUserMode();
3297 InitReg(MISCREG_ADFSR_S)
3298 .unimplemented()
3299 .warnNotFail()
3300 .bankedChild()
3301 .secure().exceptUserMode();
3302 InitReg(MISCREG_AIFSR)
3303 .unimplemented()
3304 .warnNotFail()
3305 .banked();
3306 InitReg(MISCREG_AIFSR_NS)
3307 .unimplemented()
3308 .warnNotFail()
3309 .bankedChild()
3310 .privSecure(!aarch32EL3)
3311 .nonSecure().exceptUserMode();
3312 InitReg(MISCREG_AIFSR_S)
3313 .unimplemented()
3314 .warnNotFail()
3315 .bankedChild()
3316 .secure().exceptUserMode();
3317 InitReg(MISCREG_HADFSR)
3318 .hyp().monNonSecure();
3319 InitReg(MISCREG_HAIFSR)
3320 .hyp().monNonSecure();
3321 InitReg(MISCREG_HSR)
3322 .hyp().monNonSecure();
3323 InitReg(MISCREG_DFAR)
3324 .banked();
3325 InitReg(MISCREG_DFAR_NS)
3326 .bankedChild()
3327 .privSecure(!aarch32EL3)
3328 .nonSecure().exceptUserMode();
3329 InitReg(MISCREG_DFAR_S)
3330 .bankedChild()
3331 .secure().exceptUserMode();
3332 InitReg(MISCREG_IFAR)
3333 .banked();
3334 InitReg(MISCREG_IFAR_NS)
3335 .bankedChild()
3336 .privSecure(!aarch32EL3)
3337 .nonSecure().exceptUserMode();
3338 InitReg(MISCREG_IFAR_S)
3339 .bankedChild()
3340 .secure().exceptUserMode();
3341 InitReg(MISCREG_HDFAR)
3342 .hyp().monNonSecure();
3343 InitReg(MISCREG_HIFAR)
3344 .hyp().monNonSecure();
3345 InitReg(MISCREG_HPFAR)
3346 .hyp().monNonSecure();
3347 InitReg(MISCREG_ICIALLUIS)
3348 .unimplemented()
3349 .warnNotFail()
3350 .writes(1).exceptUserMode();
3351 InitReg(MISCREG_BPIALLIS)
3352 .unimplemented()
3353 .warnNotFail()
3354 .writes(1).exceptUserMode();
3355 InitReg(MISCREG_PAR)
3356 .banked();
3357 InitReg(MISCREG_PAR_NS)
3358 .bankedChild()
3359 .privSecure(!aarch32EL3)
3360 .nonSecure().exceptUserMode();
3361 InitReg(MISCREG_PAR_S)
3362 .bankedChild()
3363 .secure().exceptUserMode();
3364 InitReg(MISCREG_ICIALLU)
3365 .writes(1).exceptUserMode();
3366 InitReg(MISCREG_ICIMVAU)
3367 .unimplemented()
3368 .warnNotFail()
3369 .writes(1).exceptUserMode();
3370 InitReg(MISCREG_CP15ISB)
3371 .writes(1);
3372 InitReg(MISCREG_BPIALL)
3373 .unimplemented()
3374 .warnNotFail()
3375 .writes(1).exceptUserMode();
3376 InitReg(MISCREG_BPIMVA)
3377 .unimplemented()
3378 .warnNotFail()
3379 .writes(1).exceptUserMode();
3380 InitReg(MISCREG_DCIMVAC)
3381 .unimplemented()
3382 .warnNotFail()
3383 .writes(1).exceptUserMode();
3384 InitReg(MISCREG_DCISW)
3385 .unimplemented()
3386 .warnNotFail()
3387 .writes(1).exceptUserMode();
3388 InitReg(MISCREG_ATS1CPR)
3389 .writes(1).exceptUserMode();
3390 InitReg(MISCREG_ATS1CPW)
3391 .writes(1).exceptUserMode();
3392 InitReg(MISCREG_ATS1CUR)
3393 .writes(1).exceptUserMode();
3394 InitReg(MISCREG_ATS1CUW)
3395 .writes(1).exceptUserMode();
3396 InitReg(MISCREG_ATS12NSOPR)
3397 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3398 InitReg(MISCREG_ATS12NSOPW)
3399 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3400 InitReg(MISCREG_ATS12NSOUR)
3401 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3402 InitReg(MISCREG_ATS12NSOUW)
3403 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3404 InitReg(MISCREG_DCCMVAC)
3405 .writes(1).exceptUserMode();
3406 InitReg(MISCREG_DCCSW)
3407 .unimplemented()
3408 .warnNotFail()
3409 .writes(1).exceptUserMode();
3410 InitReg(MISCREG_CP15DSB)
3411 .writes(1);
3412 InitReg(MISCREG_CP15DMB)
3413 .writes(1);
3414 InitReg(MISCREG_DCCMVAU)
3415 .unimplemented()
3416 .warnNotFail()
3417 .writes(1).exceptUserMode();
3418 InitReg(MISCREG_DCCIMVAC)
3419 .unimplemented()
3420 .warnNotFail()
3421 .writes(1).exceptUserMode();
3422 InitReg(MISCREG_DCCISW)
3423 .unimplemented()
3424 .warnNotFail()
3425 .writes(1).exceptUserMode();
3426 InitReg(MISCREG_ATS1HR)
3427 .monNonSecureWrite().hypWrite();
3428 InitReg(MISCREG_ATS1HW)
3429 .monNonSecureWrite().hypWrite();
3430 InitReg(MISCREG_TLBIALLIS)
3431 .writes(1).exceptUserMode();
3432 InitReg(MISCREG_TLBIMVAIS)
3433 .writes(1).exceptUserMode();
3434 InitReg(MISCREG_TLBIASIDIS)
3435 .writes(1).exceptUserMode();
3436 InitReg(MISCREG_TLBIMVAAIS)
3437 .writes(1).exceptUserMode();
3438 InitReg(MISCREG_TLBIMVALIS)
3439 .writes(1).exceptUserMode();
3440 InitReg(MISCREG_TLBIMVAALIS)
3441 .writes(1).exceptUserMode();
3442 InitReg(MISCREG_ITLBIALL)
3443 .writes(1).exceptUserMode();
3444 InitReg(MISCREG_ITLBIMVA)
3445 .writes(1).exceptUserMode();
3446 InitReg(MISCREG_ITLBIASID)
3447 .writes(1).exceptUserMode();
3448 InitReg(MISCREG_DTLBIALL)
3449 .writes(1).exceptUserMode();
3450 InitReg(MISCREG_DTLBIMVA)
3451 .writes(1).exceptUserMode();
3452 InitReg(MISCREG_DTLBIASID)
3453 .writes(1).exceptUserMode();
3454 InitReg(MISCREG_TLBIALL)
3455 .writes(1).exceptUserMode();
3456 InitReg(MISCREG_TLBIMVA)
3457 .writes(1).exceptUserMode();
3458 InitReg(MISCREG_TLBIASID)
3459 .writes(1).exceptUserMode();
3460 InitReg(MISCREG_TLBIMVAA)
3461 .writes(1).exceptUserMode();
3462 InitReg(MISCREG_TLBIMVAL)
3463 .writes(1).exceptUserMode();
3464 InitReg(MISCREG_TLBIMVAAL)
3465 .writes(1).exceptUserMode();
3466 InitReg(MISCREG_TLBIIPAS2IS)
3467 .monNonSecureWrite().hypWrite();
3468 InitReg(MISCREG_TLBIIPAS2LIS)
3469 .monNonSecureWrite().hypWrite();
3470 InitReg(MISCREG_TLBIALLHIS)
3471 .monNonSecureWrite().hypWrite();
3472 InitReg(MISCREG_TLBIMVAHIS)
3473 .monNonSecureWrite().hypWrite();
3474 InitReg(MISCREG_TLBIALLNSNHIS)
3475 .monNonSecureWrite().hypWrite();
3476 InitReg(MISCREG_TLBIMVALHIS)
3477 .monNonSecureWrite().hypWrite();
3478 InitReg(MISCREG_TLBIIPAS2)
3479 .monNonSecureWrite().hypWrite();
3480 InitReg(MISCREG_TLBIIPAS2L)
3481 .monNonSecureWrite().hypWrite();
3482 InitReg(MISCREG_TLBIALLH)
3483 .monNonSecureWrite().hypWrite();
3484 InitReg(MISCREG_TLBIMVAH)
3485 .monNonSecureWrite().hypWrite();
3486 InitReg(MISCREG_TLBIALLNSNH)
3487 .monNonSecureWrite().hypWrite();
3488 InitReg(MISCREG_TLBIMVALH)
3489 .monNonSecureWrite().hypWrite();
3490 InitReg(MISCREG_PMCR)
3491 .allPrivileges();
3492 InitReg(MISCREG_PMCNTENSET)
3493 .allPrivileges();
3494 InitReg(MISCREG_PMCNTENCLR)
3495 .allPrivileges();
3496 InitReg(MISCREG_PMOVSR)
3497 .allPrivileges();
3498 InitReg(MISCREG_PMSWINC)
3499 .allPrivileges();
3500 InitReg(MISCREG_PMSELR)
3501 .allPrivileges();
3502 InitReg(MISCREG_PMCEID0)
3503 .allPrivileges();
3504 InitReg(MISCREG_PMCEID1)
3505 .allPrivileges();
3506 InitReg(MISCREG_PMCCNTR)
3507 .allPrivileges();
3508 InitReg(MISCREG_PMXEVTYPER)
3509 .allPrivileges();
3510 InitReg(MISCREG_PMCCFILTR)
3511 .allPrivileges();
3512 InitReg(MISCREG_PMXEVCNTR)
3513 .allPrivileges();
3514 InitReg(MISCREG_PMUSERENR)
3515 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3516 InitReg(MISCREG_PMINTENSET)
3517 .allPrivileges().exceptUserMode();
3518 InitReg(MISCREG_PMINTENCLR)
3519 .allPrivileges().exceptUserMode();
3520 InitReg(MISCREG_PMOVSSET)
3521 .unimplemented()
3522 .allPrivileges();
3523 InitReg(MISCREG_L2CTLR)
3524 .allPrivileges().exceptUserMode();
3525 InitReg(MISCREG_L2ECTLR)
3526 .unimplemented()
3527 .allPrivileges().exceptUserMode();
3528 InitReg(MISCREG_PRRR)
3529 .banked();
3530 InitReg(MISCREG_PRRR_NS)
3531 .bankedChild()
3532 .privSecure(!aarch32EL3)
3533 .nonSecure().exceptUserMode();
3534 InitReg(MISCREG_PRRR_S)
3535 .bankedChild()
3536 .secure().exceptUserMode();
3537 InitReg(MISCREG_MAIR0)
3538 .banked();
3539 InitReg(MISCREG_MAIR0_NS)
3540 .bankedChild()
3541 .privSecure(!aarch32EL3)
3542 .nonSecure().exceptUserMode();
3543 InitReg(MISCREG_MAIR0_S)
3544 .bankedChild()
3545 .secure().exceptUserMode();
3546 InitReg(MISCREG_NMRR)
3547 .banked();
3548 InitReg(MISCREG_NMRR_NS)
3549 .bankedChild()
3550 .privSecure(!aarch32EL3)
3551 .nonSecure().exceptUserMode();
3552 InitReg(MISCREG_NMRR_S)
3553 .bankedChild()
3554 .secure().exceptUserMode();
3555 InitReg(MISCREG_MAIR1)
3556 .banked();
3557 InitReg(MISCREG_MAIR1_NS)
3558 .bankedChild()
3559 .privSecure(!aarch32EL3)
3560 .nonSecure().exceptUserMode();
3561 InitReg(MISCREG_MAIR1_S)
3562 .bankedChild()
3563 .secure().exceptUserMode();
3564 InitReg(MISCREG_AMAIR0)
3565 .banked();
3566 InitReg(MISCREG_AMAIR0_NS)
3567 .bankedChild()
3568 .privSecure(!aarch32EL3)
3569 .nonSecure().exceptUserMode();
3570 InitReg(MISCREG_AMAIR0_S)
3571 .bankedChild()
3572 .secure().exceptUserMode();
3573 InitReg(MISCREG_AMAIR1)
3574 .banked();
3575 InitReg(MISCREG_AMAIR1_NS)
3576 .bankedChild()
3577 .privSecure(!aarch32EL3)
3578 .nonSecure().exceptUserMode();
3579 InitReg(MISCREG_AMAIR1_S)
3580 .bankedChild()
3581 .secure().exceptUserMode();
3582 InitReg(MISCREG_HMAIR0)
3583 .hyp().monNonSecure();
3584 InitReg(MISCREG_HMAIR1)
3585 .hyp().monNonSecure();
3586 InitReg(MISCREG_HAMAIR0)
3587 .unimplemented()
3588 .warnNotFail()
3589 .hyp().monNonSecure();
3590 InitReg(MISCREG_HAMAIR1)
3591 .unimplemented()
3592 .warnNotFail()
3593 .hyp().monNonSecure();
3594 InitReg(MISCREG_VBAR)
3595 .banked();
3596 InitReg(MISCREG_VBAR_NS)
3597 .bankedChild()
3598 .privSecure(!aarch32EL3)
3599 .nonSecure().exceptUserMode();
3600 InitReg(MISCREG_VBAR_S)
3601 .bankedChild()
3602 .secure().exceptUserMode();
3603 InitReg(MISCREG_MVBAR)
3604 .mon().secure()
3605 .hypRead(FullSystem && system->highestEL() == EL2)
3606 .privRead(FullSystem && system->highestEL() == EL1)
3607 .exceptUserMode();
3608 InitReg(MISCREG_RMR)
3609 .unimplemented()
3610 .mon().secure().exceptUserMode();
3611 InitReg(MISCREG_ISR)
3612 .allPrivileges().exceptUserMode().writes(0);
3613 InitReg(MISCREG_HVBAR)
3614 .hyp().monNonSecure()
3615 .res0(0x1f);
3616 InitReg(MISCREG_FCSEIDR)
3617 .unimplemented()
3618 .warnNotFail()
3619 .allPrivileges().exceptUserMode();
3620 InitReg(MISCREG_CONTEXTIDR)
3621 .banked();
3622 InitReg(MISCREG_CONTEXTIDR_NS)
3623 .bankedChild()
3624 .privSecure(!aarch32EL3)
3625 .nonSecure().exceptUserMode();
3626 InitReg(MISCREG_CONTEXTIDR_S)
3627 .bankedChild()
3628 .secure().exceptUserMode();
3629 InitReg(MISCREG_TPIDRURW)
3630 .banked();
3631 InitReg(MISCREG_TPIDRURW_NS)
3632 .bankedChild()
3633 .allPrivileges()
3634 .privSecure(!aarch32EL3)
3635 .monSecure(0);
3636 InitReg(MISCREG_TPIDRURW_S)
3637 .bankedChild()
3638 .secure();
3639 InitReg(MISCREG_TPIDRURO)
3640 .banked();
3641 InitReg(MISCREG_TPIDRURO_NS)
3642 .bankedChild()
3643 .allPrivileges()
3644 .userNonSecureWrite(0).userSecureRead(1)
3645 .privSecure(!aarch32EL3)
3646 .monSecure(0);
3647 InitReg(MISCREG_TPIDRURO_S)
3648 .bankedChild()
3649 .secure().userSecureWrite(0);
3650 InitReg(MISCREG_TPIDRPRW)
3651 .banked();
3652 InitReg(MISCREG_TPIDRPRW_NS)
3653 .bankedChild()
3654 .nonSecure().exceptUserMode()
3655 .privSecure(!aarch32EL3);
3656 InitReg(MISCREG_TPIDRPRW_S)
3657 .bankedChild()
3658 .secure().exceptUserMode();
3659 InitReg(MISCREG_HTPIDR)
3660 .hyp().monNonSecure();
3661 InitReg(MISCREG_CNTFRQ)
3662 .unverifiable()
3663 .reads(1).mon();
3664 InitReg(MISCREG_CNTKCTL)
3665 .allPrivileges().exceptUserMode();
3666 InitReg(MISCREG_CNTP_TVAL)
3667 .banked();
3668 InitReg(MISCREG_CNTP_TVAL_NS)
3669 .bankedChild()
3670 .allPrivileges()
3671 .privSecure(!aarch32EL3)
3672 .monSecure(0);
3673 InitReg(MISCREG_CNTP_TVAL_S)
3674 .bankedChild()
3675 .secure().user(1);
3676 InitReg(MISCREG_CNTP_CTL)
3677 .banked();
3678 InitReg(MISCREG_CNTP_CTL_NS)
3679 .bankedChild()
3680 .allPrivileges()
3681 .privSecure(!aarch32EL3)
3682 .monSecure(0);
3683 InitReg(MISCREG_CNTP_CTL_S)
3684 .bankedChild()
3685 .secure().user(1);
3686 InitReg(MISCREG_CNTV_TVAL)
3687 .allPrivileges();
3688 InitReg(MISCREG_CNTV_CTL)
3689 .allPrivileges();
3690 InitReg(MISCREG_CNTHCTL)
3691 .hypWrite().monNonSecureRead();
3692 InitReg(MISCREG_CNTHP_TVAL)
3693 .hypWrite().monNonSecureRead();
3694 InitReg(MISCREG_CNTHP_CTL)
3695 .hypWrite().monNonSecureRead();
3696 InitReg(MISCREG_IL1DATA0)
3697 .unimplemented()
3698 .allPrivileges().exceptUserMode();
3699 InitReg(MISCREG_IL1DATA1)
3700 .unimplemented()
3701 .allPrivileges().exceptUserMode();
3702 InitReg(MISCREG_IL1DATA2)
3703 .unimplemented()
3704 .allPrivileges().exceptUserMode();
3705 InitReg(MISCREG_IL1DATA3)
3706 .unimplemented()
3707 .allPrivileges().exceptUserMode();
3708 InitReg(MISCREG_DL1DATA0)
3709 .unimplemented()
3710 .allPrivileges().exceptUserMode();
3711 InitReg(MISCREG_DL1DATA1)
3712 .unimplemented()
3713 .allPrivileges().exceptUserMode();
3714 InitReg(MISCREG_DL1DATA2)
3715 .unimplemented()
3716 .allPrivileges().exceptUserMode();
3717 InitReg(MISCREG_DL1DATA3)
3718 .unimplemented()
3719 .allPrivileges().exceptUserMode();
3720 InitReg(MISCREG_DL1DATA4)
3721 .unimplemented()
3722 .allPrivileges().exceptUserMode();
3723 InitReg(MISCREG_RAMINDEX)
3724 .unimplemented()
3725 .writes(1).exceptUserMode();
3726 InitReg(MISCREG_L2ACTLR)
3727 .unimplemented()
3728 .allPrivileges().exceptUserMode();
3729 InitReg(MISCREG_CBAR)
3730 .unimplemented()
3731 .allPrivileges().exceptUserMode().writes(0);
3732 InitReg(MISCREG_HTTBR)
3733 .hyp().monNonSecure();
3734 InitReg(MISCREG_VTTBR)
3735 .hyp().monNonSecure();
3736 InitReg(MISCREG_CNTPCT)
3737 .reads(1);
3738 InitReg(MISCREG_CNTVCT)
3739 .unverifiable()
3740 .reads(1);
3741 InitReg(MISCREG_CNTP_CVAL)
3742 .banked();
3743 InitReg(MISCREG_CNTP_CVAL_NS)
3744 .bankedChild()
3745 .allPrivileges()
3746 .privSecure(!aarch32EL3)
3747 .monSecure(0);
3748 InitReg(MISCREG_CNTP_CVAL_S)
3749 .bankedChild()
3750 .secure().user(1);
3751 InitReg(MISCREG_CNTV_CVAL)
3752 .allPrivileges();
3753 InitReg(MISCREG_CNTVOFF)
3754 .hyp().monNonSecure();
3755 InitReg(MISCREG_CNTHP_CVAL)
3756 .hypWrite().monNonSecureRead();
3757 InitReg(MISCREG_CPUMERRSR)
3758 .unimplemented()
3759 .allPrivileges().exceptUserMode();
3760 InitReg(MISCREG_L2MERRSR)
3761 .unimplemented()
3762 .warnNotFail()
3763 .allPrivileges().exceptUserMode();
3764
3765 // AArch64 registers (Op0=2);
3766 InitReg(MISCREG_MDCCINT_EL1)
3767 .allPrivileges();
3768 InitReg(MISCREG_OSDTRRX_EL1)
3769 .allPrivileges()
3770 .mapsTo(MISCREG_DBGDTRRXext);
3771 InitReg(MISCREG_MDSCR_EL1)
3772 .allPrivileges()
3773 .mapsTo(MISCREG_DBGDSCRext);
3774 InitReg(MISCREG_OSDTRTX_EL1)
3775 .allPrivileges()
3776 .mapsTo(MISCREG_DBGDTRTXext);
3777 InitReg(MISCREG_OSECCR_EL1)
3778 .allPrivileges()
3779 .mapsTo(MISCREG_DBGOSECCR);
3780 InitReg(MISCREG_DBGBVR0_EL1)
3781 .allPrivileges()
3782 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3783 InitReg(MISCREG_DBGBVR1_EL1)
3784 .allPrivileges()
3785 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3786 InitReg(MISCREG_DBGBVR2_EL1)
3787 .allPrivileges()
3788 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3789 InitReg(MISCREG_DBGBVR3_EL1)
3790 .allPrivileges()
3791 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3792 InitReg(MISCREG_DBGBVR4_EL1)
3793 .allPrivileges()
3794 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3795 InitReg(MISCREG_DBGBVR5_EL1)
3796 .allPrivileges()
3797 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3798 InitReg(MISCREG_DBGBCR0_EL1)
3799 .allPrivileges()
3800 .mapsTo(MISCREG_DBGBCR0);
3801 InitReg(MISCREG_DBGBCR1_EL1)
3802 .allPrivileges()
3803 .mapsTo(MISCREG_DBGBCR1);
3804 InitReg(MISCREG_DBGBCR2_EL1)
3805 .allPrivileges()
3806 .mapsTo(MISCREG_DBGBCR2);
3807 InitReg(MISCREG_DBGBCR3_EL1)
3808 .allPrivileges()
3809 .mapsTo(MISCREG_DBGBCR3);
3810 InitReg(MISCREG_DBGBCR4_EL1)
3811 .allPrivileges()
3812 .mapsTo(MISCREG_DBGBCR4);
3813 InitReg(MISCREG_DBGBCR5_EL1)
3814 .allPrivileges()
3815 .mapsTo(MISCREG_DBGBCR5);
3816 InitReg(MISCREG_DBGWVR0_EL1)
3817 .allPrivileges()
3818 .mapsTo(MISCREG_DBGWVR0);
3819 InitReg(MISCREG_DBGWVR1_EL1)
3820 .allPrivileges()
3821 .mapsTo(MISCREG_DBGWVR1);
3822 InitReg(MISCREG_DBGWVR2_EL1)
3823 .allPrivileges()
3824 .mapsTo(MISCREG_DBGWVR2);
3825 InitReg(MISCREG_DBGWVR3_EL1)
3826 .allPrivileges()
3827 .mapsTo(MISCREG_DBGWVR3);
3828 InitReg(MISCREG_DBGWCR0_EL1)
3829 .allPrivileges()
3830 .mapsTo(MISCREG_DBGWCR0);
3831 InitReg(MISCREG_DBGWCR1_EL1)
3832 .allPrivileges()
3833 .mapsTo(MISCREG_DBGWCR1);
3834 InitReg(MISCREG_DBGWCR2_EL1)
3835 .allPrivileges()
3836 .mapsTo(MISCREG_DBGWCR2);
3837 InitReg(MISCREG_DBGWCR3_EL1)
3838 .allPrivileges()
3839 .mapsTo(MISCREG_DBGWCR3);
3840 InitReg(MISCREG_MDCCSR_EL0)
3841 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3842 .mapsTo(MISCREG_DBGDSCRint);
3843 InitReg(MISCREG_MDDTR_EL0)
3844 .allPrivileges();
3845 InitReg(MISCREG_MDDTRTX_EL0)
3846 .allPrivileges();
3847 InitReg(MISCREG_MDDTRRX_EL0)
3848 .allPrivileges();
3849 InitReg(MISCREG_DBGVCR32_EL2)
3850 .allPrivileges()
3851 .mapsTo(MISCREG_DBGVCR);
3852 InitReg(MISCREG_MDRAR_EL1)
3853 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3854 .mapsTo(MISCREG_DBGDRAR);
3855 InitReg(MISCREG_OSLAR_EL1)
3856 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3857 .mapsTo(MISCREG_DBGOSLAR);
3858 InitReg(MISCREG_OSLSR_EL1)
3859 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3860 .mapsTo(MISCREG_DBGOSLSR);
3861 InitReg(MISCREG_OSDLR_EL1)
3862 .allPrivileges()
3863 .mapsTo(MISCREG_DBGOSDLR);
3864 InitReg(MISCREG_DBGPRCR_EL1)
3865 .allPrivileges()
3866 .mapsTo(MISCREG_DBGPRCR);
3867 InitReg(MISCREG_DBGCLAIMSET_EL1)
3868 .allPrivileges()
3869 .mapsTo(MISCREG_DBGCLAIMSET);
3870 InitReg(MISCREG_DBGCLAIMCLR_EL1)
3871 .allPrivileges()
3872 .mapsTo(MISCREG_DBGCLAIMCLR);
3873 InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3874 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3875 .mapsTo(MISCREG_DBGAUTHSTATUS);
3876 InitReg(MISCREG_TEECR32_EL1);
3877 InitReg(MISCREG_TEEHBR32_EL1);
3878
3879 // AArch64 registers (Op0=1,3);
3880 InitReg(MISCREG_MIDR_EL1)
3881 .allPrivileges().exceptUserMode().writes(0);
3882 InitReg(MISCREG_MPIDR_EL1)
3883 .allPrivileges().exceptUserMode().writes(0);
3884 InitReg(MISCREG_REVIDR_EL1)
3885 .allPrivileges().exceptUserMode().writes(0);
3886 InitReg(MISCREG_ID_PFR0_EL1)
3887 .allPrivileges().exceptUserMode().writes(0)
3888 .mapsTo(MISCREG_ID_PFR0);
3889 InitReg(MISCREG_ID_PFR1_EL1)
3890 .allPrivileges().exceptUserMode().writes(0)
3891 .mapsTo(MISCREG_ID_PFR1);
3892 InitReg(MISCREG_ID_DFR0_EL1)
3893 .allPrivileges().exceptUserMode().writes(0)
3894 .mapsTo(MISCREG_ID_DFR0);
3895 InitReg(MISCREG_ID_AFR0_EL1)
3896 .allPrivileges().exceptUserMode().writes(0)
3897 .mapsTo(MISCREG_ID_AFR0);
3898 InitReg(MISCREG_ID_MMFR0_EL1)
3899 .allPrivileges().exceptUserMode().writes(0)
3900 .mapsTo(MISCREG_ID_MMFR0);
3901 InitReg(MISCREG_ID_MMFR1_EL1)
3902 .allPrivileges().exceptUserMode().writes(0)
3903 .mapsTo(MISCREG_ID_MMFR1);
3904 InitReg(MISCREG_ID_MMFR2_EL1)
3905 .allPrivileges().exceptUserMode().writes(0)
3906 .mapsTo(MISCREG_ID_MMFR2);
3907 InitReg(MISCREG_ID_MMFR3_EL1)
3908 .allPrivileges().exceptUserMode().writes(0)
3909 .mapsTo(MISCREG_ID_MMFR3);
3910 InitReg(MISCREG_ID_ISAR0_EL1)
3911 .allPrivileges().exceptUserMode().writes(0)
3912 .mapsTo(MISCREG_ID_ISAR0);
3913 InitReg(MISCREG_ID_ISAR1_EL1)
3914 .allPrivileges().exceptUserMode().writes(0)
3915 .mapsTo(MISCREG_ID_ISAR1);
3916 InitReg(MISCREG_ID_ISAR2_EL1)
3917 .allPrivileges().exceptUserMode().writes(0)
3918 .mapsTo(MISCREG_ID_ISAR2);
3919 InitReg(MISCREG_ID_ISAR3_EL1)
3920 .allPrivileges().exceptUserMode().writes(0)
3921 .mapsTo(MISCREG_ID_ISAR3);
3922 InitReg(MISCREG_ID_ISAR4_EL1)
3923 .allPrivileges().exceptUserMode().writes(0)
3924 .mapsTo(MISCREG_ID_ISAR4);
3925 InitReg(MISCREG_ID_ISAR5_EL1)
3926 .allPrivileges().exceptUserMode().writes(0)
3927 .mapsTo(MISCREG_ID_ISAR5);
3928 InitReg(MISCREG_MVFR0_EL1)
3929 .allPrivileges().exceptUserMode().writes(0);
3930 InitReg(MISCREG_MVFR1_EL1)
3931 .allPrivileges().exceptUserMode().writes(0);
3932 InitReg(MISCREG_MVFR2_EL1)
3933 .allPrivileges().exceptUserMode().writes(0);
3934 InitReg(MISCREG_ID_AA64PFR0_EL1)
3935 .allPrivileges().exceptUserMode().writes(0);
3936 InitReg(MISCREG_ID_AA64PFR1_EL1)
3937 .allPrivileges().exceptUserMode().writes(0);
3938 InitReg(MISCREG_ID_AA64DFR0_EL1)
3939 .allPrivileges().exceptUserMode().writes(0);
3940 InitReg(MISCREG_ID_AA64DFR1_EL1)
3941 .allPrivileges().exceptUserMode().writes(0);
3942 InitReg(MISCREG_ID_AA64AFR0_EL1)
3943 .allPrivileges().exceptUserMode().writes(0);
3944 InitReg(MISCREG_ID_AA64AFR1_EL1)
3945 .allPrivileges().exceptUserMode().writes(0);
3946 InitReg(MISCREG_ID_AA64ISAR0_EL1)
3947 .allPrivileges().exceptUserMode().writes(0);
3948 InitReg(MISCREG_ID_AA64ISAR1_EL1)
3949 .allPrivileges().exceptUserMode().writes(0);
3950 InitReg(MISCREG_ID_AA64MMFR0_EL1)
3951 .allPrivileges().exceptUserMode().writes(0);
3952 InitReg(MISCREG_ID_AA64MMFR1_EL1)
3953 .allPrivileges().exceptUserMode().writes(0);
3954 InitReg(MISCREG_ID_AA64MMFR2_EL1)
3955 .allPrivileges().exceptUserMode().writes(0);
3956 InitReg(MISCREG_CCSIDR_EL1)
3957 .allPrivileges().exceptUserMode().writes(0);
3958 InitReg(MISCREG_CLIDR_EL1)
3959 .allPrivileges().exceptUserMode().writes(0);
3960 InitReg(MISCREG_AIDR_EL1)
3961 .allPrivileges().exceptUserMode().writes(0);
3962 InitReg(MISCREG_CSSELR_EL1)
3963 .allPrivileges().exceptUserMode()
3964 .mapsTo(MISCREG_CSSELR_NS);
3965 InitReg(MISCREG_CTR_EL0)
3966 .reads(1);
3967 InitReg(MISCREG_DCZID_EL0)
3968 .reads(1);
3969 InitReg(MISCREG_VPIDR_EL2)
3970 .hyp().mon()
3971 .mapsTo(MISCREG_VPIDR);
3972 InitReg(MISCREG_VMPIDR_EL2)
3973 .hyp().mon()
3974 .mapsTo(MISCREG_VMPIDR);
3975 InitReg(MISCREG_SCTLR_EL1)
3976 .allPrivileges().exceptUserMode()
3977 .res0( 0x20440 | (EnDB ? 0 : 0x2000)
3978 | (IESB ? 0 : 0x200000)
3979 | (EnDA ? 0 : 0x8000000)
3980 | (EnIB ? 0 : 0x40000000)
3981 | (EnIA ? 0 : 0x80000000))
3982 .res1(0x500800 | (SPAN ? 0 : 0x800000)
3983 | (nTLSMD ? 0 : 0x8000000)
3984 | (LSMAOE ? 0 : 0x10000000))
3985 .mapsTo(MISCREG_SCTLR_NS);
3986 InitReg(MISCREG_ACTLR_EL1)
3987 .allPrivileges().exceptUserMode()
3988 .mapsTo(MISCREG_ACTLR_NS);
3989 InitReg(MISCREG_CPACR_EL1)
3990 .allPrivileges().exceptUserMode()
3991 .mapsTo(MISCREG_CPACR);
3992 InitReg(MISCREG_SCTLR_EL2)
3993 .hyp().mon()
3994 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3995 | (IESB ? 0 : 0x200000)
3996 | (EnDA ? 0 : 0x8000000)
3997 | (EnIB ? 0 : 0x40000000)
3998 | (EnIA ? 0 : 0x80000000))
3999 .res1(0x30c50830)
4000 .mapsTo(MISCREG_HSCTLR);
4001 InitReg(MISCREG_ACTLR_EL2)
4002 .hyp().mon()
4003 .mapsTo(MISCREG_HACTLR);
4004 InitReg(MISCREG_HCR_EL2)
4005 .hyp().mon()
4006 .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
4007 InitReg(MISCREG_MDCR_EL2)
4008 .hyp().mon()
4009 .mapsTo(MISCREG_HDCR);
4010 InitReg(MISCREG_CPTR_EL2)
4011 .hyp().mon()
4012 .mapsTo(MISCREG_HCPTR);
4013 InitReg(MISCREG_HSTR_EL2)
4014 .hyp().mon()
4015 .mapsTo(MISCREG_HSTR);
4016 InitReg(MISCREG_HACR_EL2)
4017 .hyp().mon()
4018 .mapsTo(MISCREG_HACR);
4019 InitReg(MISCREG_SCTLR_EL3)
4020 .mon()
4021 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4022 | (IESB ? 0 : 0x200000)
4023 | (EnDA ? 0 : 0x8000000)
4024 | (EnIB ? 0 : 0x40000000)
4025 | (EnIA ? 0 : 0x80000000))
4026 .res1(0x30c50830);
4027 InitReg(MISCREG_ACTLR_EL3)
4028 .mon();
4029 InitReg(MISCREG_SCR_EL3)
4030 .mon()
4031 .mapsTo(MISCREG_SCR); // NAM D7-2005
4032 InitReg(MISCREG_SDER32_EL3)
4033 .mon()
4034 .mapsTo(MISCREG_SDER);
4035 InitReg(MISCREG_CPTR_EL3)
4036 .mon();
4037 InitReg(MISCREG_MDCR_EL3)
4038 .mon();
4039 InitReg(MISCREG_TTBR0_EL1)
4040 .allPrivileges().exceptUserMode()
4041 .mapsTo(MISCREG_TTBR0_NS);
4042 InitReg(MISCREG_TTBR1_EL1)
4043 .allPrivileges().exceptUserMode()
4044 .mapsTo(MISCREG_TTBR1_NS);
4045 InitReg(MISCREG_TCR_EL1)
4046 .allPrivileges().exceptUserMode()
4047 .mapsTo(MISCREG_TTBCR_NS);
4048 InitReg(MISCREG_TTBR0_EL2)
4049 .hyp().mon()
4050 .mapsTo(MISCREG_HTTBR);
4051 InitReg(MISCREG_TTBR1_EL2)
4052 .hyp().mon();
4053 InitReg(MISCREG_TCR_EL2)
4054 .hyp().mon()
4055 .mapsTo(MISCREG_HTCR);
4056 InitReg(MISCREG_VTTBR_EL2)
4057 .hyp().mon()
4058 .mapsTo(MISCREG_VTTBR);
4059 InitReg(MISCREG_VTCR_EL2)
4060 .hyp().mon()
4061 .mapsTo(MISCREG_VTCR);
4062 InitReg(MISCREG_TTBR0_EL3)
4063 .mon();
4064 InitReg(MISCREG_TCR_EL3)
4065 .mon();
4066 InitReg(MISCREG_DACR32_EL2)
4067 .hyp().mon()
4068 .mapsTo(MISCREG_DACR_NS);
4069 InitReg(MISCREG_SPSR_EL1)
4070 .allPrivileges().exceptUserMode()
4071 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
4072 InitReg(MISCREG_ELR_EL1)
4073 .allPrivileges().exceptUserMode();
4074 InitReg(MISCREG_SP_EL0)
4075 .allPrivileges().exceptUserMode();
4076 InitReg(MISCREG_SPSEL)
4077 .allPrivileges().exceptUserMode();
4078 InitReg(MISCREG_CURRENTEL)
4079 .allPrivileges().exceptUserMode().writes(0);
4080 InitReg(MISCREG_PAN)
4081 .allPrivileges().exceptUserMode()
4082 .implemented(havePAN);
4083 InitReg(MISCREG_NZCV)
4084 .allPrivileges();
4085 InitReg(MISCREG_DAIF)
4086 .allPrivileges();
4087 InitReg(MISCREG_FPCR)
4088 .allPrivileges();
4089 InitReg(MISCREG_FPSR)
4090 .allPrivileges();
4091 InitReg(MISCREG_DSPSR_EL0)
4092 .allPrivileges();
4093 InitReg(MISCREG_DLR_EL0)
4094 .allPrivileges();
4095 InitReg(MISCREG_SPSR_EL2)
4096 .hyp().mon()
4097 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
4098 InitReg(MISCREG_ELR_EL2)
4099 .hyp().mon();
4100 InitReg(MISCREG_SP_EL1)
4101 .hyp().mon();
4102 InitReg(MISCREG_SPSR_IRQ_AA64)
4103 .hyp().mon();
4104 InitReg(MISCREG_SPSR_ABT_AA64)
4105 .hyp().mon();
4106 InitReg(MISCREG_SPSR_UND_AA64)
4107 .hyp().mon();
4108 InitReg(MISCREG_SPSR_FIQ_AA64)
4109 .hyp().mon();
4110 InitReg(MISCREG_SPSR_EL3)
4111 .mon()
4112 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
4113 InitReg(MISCREG_ELR_EL3)
4114 .mon();
4115 InitReg(MISCREG_SP_EL2)
4116 .mon();
4117 InitReg(MISCREG_AFSR0_EL1)
4118 .allPrivileges().exceptUserMode()
4119 .mapsTo(MISCREG_ADFSR_NS);
4120 InitReg(MISCREG_AFSR1_EL1)
4121 .allPrivileges().exceptUserMode()
4122 .mapsTo(MISCREG_AIFSR_NS);
4123 InitReg(MISCREG_ESR_EL1)
4124 .allPrivileges().exceptUserMode();
4125 InitReg(MISCREG_IFSR32_EL2)
4126 .hyp().mon()
4127 .mapsTo(MISCREG_IFSR_NS);
4128 InitReg(MISCREG_AFSR0_EL2)
4129 .hyp().mon()
4130 .mapsTo(MISCREG_HADFSR);
4131 InitReg(MISCREG_AFSR1_EL2)
4132 .hyp().mon()
4133 .mapsTo(MISCREG_HAIFSR);
4134 InitReg(MISCREG_ESR_EL2)
4135 .hyp().mon()
4136 .mapsTo(MISCREG_HSR);
4137 InitReg(MISCREG_FPEXC32_EL2)
4138 .hyp().mon().mapsTo(MISCREG_FPEXC);
4139 InitReg(MISCREG_AFSR0_EL3)
4140 .mon();
4141 InitReg(MISCREG_AFSR1_EL3)
4142 .mon();
4143 InitReg(MISCREG_ESR_EL3)
4144 .mon();
4145 InitReg(MISCREG_FAR_EL1)
4146 .allPrivileges().exceptUserMode()
4147 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
4148 InitReg(MISCREG_FAR_EL2)
4149 .hyp().mon()
4150 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
4151 InitReg(MISCREG_HPFAR_EL2)
4152 .hyp().mon()
4153 .mapsTo(MISCREG_HPFAR);
4154 InitReg(MISCREG_FAR_EL3)
4155 .mon();
4156 InitReg(MISCREG_IC_IALLUIS)
4157 .warnNotFail()
4158 .writes(1).exceptUserMode();
4159 InitReg(MISCREG_PAR_EL1)
4160 .allPrivileges().exceptUserMode()
4161 .mapsTo(MISCREG_PAR_NS);
4162 InitReg(MISCREG_IC_IALLU)
4163 .warnNotFail()
4164 .writes(1).exceptUserMode();
4165 InitReg(MISCREG_DC_IVAC_Xt)
4166 .warnNotFail()
4167 .writes(1).exceptUserMode();
4168 InitReg(MISCREG_DC_ISW_Xt)
4169 .warnNotFail()
4170 .writes(1).exceptUserMode();
4171 InitReg(MISCREG_AT_S1E1R_Xt)
4172 .writes(1).exceptUserMode();
4173 InitReg(MISCREG_AT_S1E1W_Xt)
4174 .writes(1).exceptUserMode();
4175 InitReg(MISCREG_AT_S1E0R_Xt)
4176 .writes(1).exceptUserMode();
4177 InitReg(MISCREG_AT_S1E0W_Xt)
4178 .writes(1).exceptUserMode();
4179 InitReg(MISCREG_DC_CSW_Xt)
4180 .warnNotFail()
4181 .writes(1).exceptUserMode();
4182 InitReg(MISCREG_DC_CISW_Xt)
4183 .warnNotFail()
4184 .writes(1).exceptUserMode();
4185 InitReg(MISCREG_DC_ZVA_Xt)
4186 .warnNotFail()
4187 .writes(1).userSecureWrite(0);
4188 InitReg(MISCREG_IC_IVAU_Xt)
4189 .writes(1);
4190 InitReg(MISCREG_DC_CVAC_Xt)
4191 .warnNotFail()
4192 .writes(1);
4193 InitReg(MISCREG_DC_CVAU_Xt)
4194 .warnNotFail()
4195 .writes(1);
4196 InitReg(MISCREG_DC_CIVAC_Xt)
4197 .warnNotFail()
4198 .writes(1);
4199 InitReg(MISCREG_AT_S1E2R_Xt)
4200 .monNonSecureWrite().hypWrite();
4201 InitReg(MISCREG_AT_S1E2W_Xt)
4202 .monNonSecureWrite().hypWrite();
4203 InitReg(MISCREG_AT_S12E1R_Xt)
4204 .hypWrite().monSecureWrite().monNonSecureWrite();
4205 InitReg(MISCREG_AT_S12E1W_Xt)
4206 .hypWrite().monSecureWrite().monNonSecureWrite();
4207 InitReg(MISCREG_AT_S12E0R_Xt)
4208 .hypWrite().monSecureWrite().monNonSecureWrite();
4209 InitReg(MISCREG_AT_S12E0W_Xt)
4210 .hypWrite().monSecureWrite().monNonSecureWrite();
4211 InitReg(MISCREG_AT_S1E3R_Xt)
4212 .monSecureWrite().monNonSecureWrite();
4213 InitReg(MISCREG_AT_S1E3W_Xt)
4214 .monSecureWrite().monNonSecureWrite();
4215 InitReg(MISCREG_TLBI_VMALLE1IS)
4216 .writes(1).exceptUserMode();
4217 InitReg(MISCREG_TLBI_VAE1IS_Xt)
4218 .writes(1).exceptUserMode();
4219 InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
4220 .writes(1).exceptUserMode();
4221 InitReg(MISCREG_TLBI_VAAE1IS_Xt)
4222 .writes(1).exceptUserMode();
4223 InitReg(MISCREG_TLBI_VALE1IS_Xt)
4224 .writes(1).exceptUserMode();
4225 InitReg(MISCREG_TLBI_VAALE1IS_Xt)
4226 .writes(1).exceptUserMode();
4227 InitReg(MISCREG_TLBI_VMALLE1)
4228 .writes(1).exceptUserMode();
4229 InitReg(MISCREG_TLBI_VAE1_Xt)
4230 .writes(1).exceptUserMode();
4231 InitReg(MISCREG_TLBI_ASIDE1_Xt)
4232 .writes(1).exceptUserMode();
4233 InitReg(MISCREG_TLBI_VAAE1_Xt)
4234 .writes(1).exceptUserMode();
4235 InitReg(MISCREG_TLBI_VALE1_Xt)
4236 .writes(1).exceptUserMode();
4237 InitReg(MISCREG_TLBI_VAALE1_Xt)
4238 .writes(1).exceptUserMode();
4239 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
4240 .hypWrite().monSecureWrite().monNonSecureWrite();
4241 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
4242 .hypWrite().monSecureWrite().monNonSecureWrite();
4243 InitReg(MISCREG_TLBI_ALLE2IS)
4244 .monNonSecureWrite().hypWrite();
4245 InitReg(MISCREG_TLBI_VAE2IS_Xt)
4246 .monNonSecureWrite().hypWrite();
4247 InitReg(MISCREG_TLBI_ALLE1IS)
4248 .hypWrite().monSecureWrite().monNonSecureWrite();
4249 InitReg(MISCREG_TLBI_VALE2IS_Xt)
4250 .monNonSecureWrite().hypWrite();
4251 InitReg(MISCREG_TLBI_VMALLS12E1IS)
4252 .hypWrite().monSecureWrite().monNonSecureWrite();
4253 InitReg(MISCREG_TLBI_IPAS2E1_Xt)
4254 .hypWrite().monSecureWrite().monNonSecureWrite();
4255 InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
4256 .hypWrite().monSecureWrite().monNonSecureWrite();
4257 InitReg(MISCREG_TLBI_ALLE2)
4258 .monNonSecureWrite().hypWrite();
4259 InitReg(MISCREG_TLBI_VAE2_Xt)
4260 .monNonSecureWrite().hypWrite();
4261 InitReg(MISCREG_TLBI_ALLE1)
4262 .hypWrite().monSecureWrite().monNonSecureWrite();
4263 InitReg(MISCREG_TLBI_VALE2_Xt)
4264 .monNonSecureWrite().hypWrite();
4265 InitReg(MISCREG_TLBI_VMALLS12E1)
4266 .hypWrite().monSecureWrite().monNonSecureWrite();
4267 InitReg(MISCREG_TLBI_ALLE3IS)
4268 .monSecureWrite().monNonSecureWrite();
4269 InitReg(MISCREG_TLBI_VAE3IS_Xt)
4270 .monSecureWrite().monNonSecureWrite();
4271 InitReg(MISCREG_TLBI_VALE3IS_Xt)
4272 .monSecureWrite().monNonSecureWrite();
4273 InitReg(MISCREG_TLBI_ALLE3)
4274 .monSecureWrite().monNonSecureWrite();
4275 InitReg(MISCREG_TLBI_VAE3_Xt)
4276 .monSecureWrite().monNonSecureWrite();
4277 InitReg(MISCREG_TLBI_VALE3_Xt)
4278 .monSecureWrite().monNonSecureWrite();
4279 InitReg(MISCREG_PMINTENSET_EL1)
4280 .allPrivileges().exceptUserMode()
4281 .mapsTo(MISCREG_PMINTENSET);
4282 InitReg(MISCREG_PMINTENCLR_EL1)
4283 .allPrivileges().exceptUserMode()
4284 .mapsTo(MISCREG_PMINTENCLR);
4285 InitReg(MISCREG_PMCR_EL0)
4286 .allPrivileges()
4287 .mapsTo(MISCREG_PMCR);
4288 InitReg(MISCREG_PMCNTENSET_EL0)
4289 .allPrivileges()
4290 .mapsTo(MISCREG_PMCNTENSET);
4291 InitReg(MISCREG_PMCNTENCLR_EL0)
4292 .allPrivileges()
4293 .mapsTo(MISCREG_PMCNTENCLR);
4294 InitReg(MISCREG_PMOVSCLR_EL0)
4295 .allPrivileges();
4296// .mapsTo(MISCREG_PMOVSCLR);
4297 InitReg(MISCREG_PMSWINC_EL0)
4298 .writes(1).user()
4299 .mapsTo(MISCREG_PMSWINC);
4300 InitReg(MISCREG_PMSELR_EL0)
4301 .allPrivileges()
4302 .mapsTo(MISCREG_PMSELR);
4303 InitReg(MISCREG_PMCEID0_EL0)
4304 .reads(1).user()
4305 .mapsTo(MISCREG_PMCEID0);
4306 InitReg(MISCREG_PMCEID1_EL0)
4307 .reads(1).user()
4308 .mapsTo(MISCREG_PMCEID1);
4309 InitReg(MISCREG_PMCCNTR_EL0)
4310 .allPrivileges()
4311 .mapsTo(MISCREG_PMCCNTR);
4312 InitReg(MISCREG_PMXEVTYPER_EL0)
4313 .allPrivileges()
4314 .mapsTo(MISCREG_PMXEVTYPER);
4315 InitReg(MISCREG_PMCCFILTR_EL0)
4316 .allPrivileges();
4317 InitReg(MISCREG_PMXEVCNTR_EL0)
4318 .allPrivileges()
4319 .mapsTo(MISCREG_PMXEVCNTR);
4320 InitReg(MISCREG_PMUSERENR_EL0)
4321 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4322 .mapsTo(MISCREG_PMUSERENR);
4323 InitReg(MISCREG_PMOVSSET_EL0)
4324 .allPrivileges()
4325 .mapsTo(MISCREG_PMOVSSET);
4326 InitReg(MISCREG_MAIR_EL1)
4327 .allPrivileges().exceptUserMode()
4328 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
4329 InitReg(MISCREG_AMAIR_EL1)
4330 .allPrivileges().exceptUserMode()
4331 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
4332 InitReg(MISCREG_MAIR_EL2)
4333 .hyp().mon()
4334 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
4335 InitReg(MISCREG_AMAIR_EL2)
4336 .hyp().mon()
4337 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
4338 InitReg(MISCREG_MAIR_EL3)
4339 .mon();
4340 InitReg(MISCREG_AMAIR_EL3)
4341 .mon();
4342 InitReg(MISCREG_L2CTLR_EL1)
4343 .allPrivileges().exceptUserMode();
4344 InitReg(MISCREG_L2ECTLR_EL1)
4345 .allPrivileges().exceptUserMode();
4346 InitReg(MISCREG_VBAR_EL1)
4347 .allPrivileges().exceptUserMode()
4348 .mapsTo(MISCREG_VBAR_NS);
4349 InitReg(MISCREG_RVBAR_EL1)
4350 .allPrivileges().exceptUserMode().writes(0);
4351 InitReg(MISCREG_ISR_EL1)
4352 .allPrivileges().exceptUserMode().writes(0);
4353 InitReg(MISCREG_VBAR_EL2)
4354 .hyp().mon()
4355 .res0(0x7ff)
4356 .mapsTo(MISCREG_HVBAR);
4357 InitReg(MISCREG_RVBAR_EL2)
4358 .mon().hyp().writes(0);
4359 InitReg(MISCREG_VBAR_EL3)
4360 .mon();
4361 InitReg(MISCREG_RVBAR_EL3)
4362 .mon().writes(0);
4363 InitReg(MISCREG_RMR_EL3)
4364 .mon();
4365 InitReg(MISCREG_CONTEXTIDR_EL1)
4366 .allPrivileges().exceptUserMode()
4367 .mapsTo(MISCREG_CONTEXTIDR_NS);
4368 InitReg(MISCREG_TPIDR_EL1)
4369 .allPrivileges().exceptUserMode()
4370 .mapsTo(MISCREG_TPIDRPRW_NS);
4371 InitReg(MISCREG_TPIDR_EL0)
4372 .allPrivileges()
4373 .mapsTo(MISCREG_TPIDRURW_NS);
4374 InitReg(MISCREG_TPIDRRO_EL0)
4375 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4376 .mapsTo(MISCREG_TPIDRURO_NS);
4377 InitReg(MISCREG_TPIDR_EL2)
4378 .hyp().mon()
4379 .mapsTo(MISCREG_HTPIDR);
4380 InitReg(MISCREG_TPIDR_EL3)
4381 .mon();
4382 InitReg(MISCREG_CNTKCTL_EL1)
4383 .allPrivileges().exceptUserMode()
4384 .mapsTo(MISCREG_CNTKCTL);
4385 InitReg(MISCREG_CNTFRQ_EL0)
4386 .reads(1).mon()
4387 .mapsTo(MISCREG_CNTFRQ);
4388 InitReg(MISCREG_CNTPCT_EL0)
4389 .reads(1)
4390 .mapsTo(MISCREG_CNTPCT); /* 64b */
4391 InitReg(MISCREG_CNTVCT_EL0)
4392 .unverifiable()
4393 .reads(1)
4394 .mapsTo(MISCREG_CNTVCT); /* 64b */
4395 InitReg(MISCREG_CNTP_TVAL_EL0)
4396 .allPrivileges()
4397 .mapsTo(MISCREG_CNTP_TVAL_NS);
4398 InitReg(MISCREG_CNTP_CTL_EL0)
4399 .allPrivileges()
4400 .mapsTo(MISCREG_CNTP_CTL_NS);
4401 InitReg(MISCREG_CNTP_CVAL_EL0)
4402 .allPrivileges()
4403 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
4404 InitReg(MISCREG_CNTV_TVAL_EL0)
4405 .allPrivileges()
4406 .mapsTo(MISCREG_CNTV_TVAL);
4407 InitReg(MISCREG_CNTV_CTL_EL0)
4408 .allPrivileges()
4409 .mapsTo(MISCREG_CNTV_CTL);
4410 InitReg(MISCREG_CNTV_CVAL_EL0)
4411 .allPrivileges()
4412 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
4413 InitReg(MISCREG_PMEVCNTR0_EL0)
4414 .allPrivileges();
4415// .mapsTo(MISCREG_PMEVCNTR0);
4416 InitReg(MISCREG_PMEVCNTR1_EL0)
4417 .allPrivileges();
4418// .mapsTo(MISCREG_PMEVCNTR1);
4419 InitReg(MISCREG_PMEVCNTR2_EL0)
4420 .allPrivileges();
4421// .mapsTo(MISCREG_PMEVCNTR2);
4422 InitReg(MISCREG_PMEVCNTR3_EL0)
4423 .allPrivileges();
4424// .mapsTo(MISCREG_PMEVCNTR3);
4425 InitReg(MISCREG_PMEVCNTR4_EL0)
4426 .allPrivileges();
4427// .mapsTo(MISCREG_PMEVCNTR4);
4428 InitReg(MISCREG_PMEVCNTR5_EL0)
4429 .allPrivileges();
4430// .mapsTo(MISCREG_PMEVCNTR5);
4431 InitReg(MISCREG_PMEVTYPER0_EL0)
4432 .allPrivileges();
4433// .mapsTo(MISCREG_PMEVTYPER0);
4434 InitReg(MISCREG_PMEVTYPER1_EL0)
4435 .allPrivileges();
4436// .mapsTo(MISCREG_PMEVTYPER1);
4437 InitReg(MISCREG_PMEVTYPER2_EL0)
4438 .allPrivileges();
4439// .mapsTo(MISCREG_PMEVTYPER2);
4440 InitReg(MISCREG_PMEVTYPER3_EL0)
4441 .allPrivileges();
4442// .mapsTo(MISCREG_PMEVTYPER3);
4443 InitReg(MISCREG_PMEVTYPER4_EL0)
4444 .allPrivileges();
4445// .mapsTo(MISCREG_PMEVTYPER4);
4446 InitReg(MISCREG_PMEVTYPER5_EL0)
4447 .allPrivileges();
4448// .mapsTo(MISCREG_PMEVTYPER5);
4449 InitReg(MISCREG_CNTVOFF_EL2)
4450 .hyp().mon()
4451 .mapsTo(MISCREG_CNTVOFF); /* 64b */
4452 InitReg(MISCREG_CNTHCTL_EL2)
4453 .mon().hyp()
4454 .mapsTo(MISCREG_CNTHCTL);
4455 InitReg(MISCREG_CNTHP_TVAL_EL2)
4456 .mon().hyp()
4457 .mapsTo(MISCREG_CNTHP_TVAL);
4458 InitReg(MISCREG_CNTHP_CTL_EL2)
4459 .mon().hyp()
4460 .mapsTo(MISCREG_CNTHP_CTL);
4461 InitReg(MISCREG_CNTHP_CVAL_EL2)
4462 .mon().hyp()
4463 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
4464 InitReg(MISCREG_CNTPS_TVAL_EL1)
4465 .mon().privSecure();
4466 InitReg(MISCREG_CNTPS_CTL_EL1)
4467 .mon().privSecure();
4468 InitReg(MISCREG_CNTPS_CVAL_EL1)
4469 .mon().privSecure();
4470 InitReg(MISCREG_IL1DATA0_EL1)
4471 .allPrivileges().exceptUserMode();
4472 InitReg(MISCREG_IL1DATA1_EL1)
4473 .allPrivileges().exceptUserMode();
4474 InitReg(MISCREG_IL1DATA2_EL1)
4475 .allPrivileges().exceptUserMode();
4476 InitReg(MISCREG_IL1DATA3_EL1)
4477 .allPrivileges().exceptUserMode();
4478 InitReg(MISCREG_DL1DATA0_EL1)
4479 .allPrivileges().exceptUserMode();
4480 InitReg(MISCREG_DL1DATA1_EL1)
4481 .allPrivileges().exceptUserMode();
4482 InitReg(MISCREG_DL1DATA2_EL1)
4483 .allPrivileges().exceptUserMode();
4484 InitReg(MISCREG_DL1DATA3_EL1)
4485 .allPrivileges().exceptUserMode();
4486 InitReg(MISCREG_DL1DATA4_EL1)
4487 .allPrivileges().exceptUserMode();
4488 InitReg(MISCREG_L2ACTLR_EL1)
4489 .allPrivileges().exceptUserMode();
4490 InitReg(MISCREG_CPUACTLR_EL1)
4491 .allPrivileges().exceptUserMode();
4492 InitReg(MISCREG_CPUECTLR_EL1)
4493 .allPrivileges().exceptUserMode();
4494 InitReg(MISCREG_CPUMERRSR_EL1)
4495 .allPrivileges().exceptUserMode();
4496 InitReg(MISCREG_L2MERRSR_EL1)
4497 .unimplemented()
4498 .warnNotFail()
4499 .allPrivileges().exceptUserMode();
4500 InitReg(MISCREG_CBAR_EL1)
4501 .allPrivileges().exceptUserMode().writes(0);
4502 InitReg(MISCREG_CONTEXTIDR_EL2)
4503 .mon().hyp();
4504
4505 // GICv3 AArch64
4506 InitReg(MISCREG_ICC_PMR_EL1)
4507 .res0(0xffffff00) // [31:8]
4508 .allPrivileges().exceptUserMode()
4509 .mapsTo(MISCREG_ICC_PMR);
4510 InitReg(MISCREG_ICC_IAR0_EL1)
4511 .allPrivileges().exceptUserMode().writes(0)
4512 .mapsTo(MISCREG_ICC_IAR0);
4513 InitReg(MISCREG_ICC_EOIR0_EL1)
4514 .allPrivileges().exceptUserMode().reads(0)
4515 .mapsTo(MISCREG_ICC_EOIR0);
4516 InitReg(MISCREG_ICC_HPPIR0_EL1)
4517 .allPrivileges().exceptUserMode().writes(0)
4518 .mapsTo(MISCREG_ICC_HPPIR0);
4519 InitReg(MISCREG_ICC_BPR0_EL1)
4520 .res0(0xfffffff8) // [31:3]
4521 .allPrivileges().exceptUserMode()
4522 .mapsTo(MISCREG_ICC_BPR0);
4523 InitReg(MISCREG_ICC_AP0R0_EL1)
4524 .allPrivileges().exceptUserMode()
4525 .mapsTo(MISCREG_ICC_AP0R0);
4526 InitReg(MISCREG_ICC_AP0R1_EL1)
4527 .allPrivileges().exceptUserMode()
4528 .mapsTo(MISCREG_ICC_AP0R1);
4529 InitReg(MISCREG_ICC_AP0R2_EL1)
4530 .allPrivileges().exceptUserMode()
4531 .mapsTo(MISCREG_ICC_AP0R2);
4532 InitReg(MISCREG_ICC_AP0R3_EL1)
4533 .allPrivileges().exceptUserMode()
4534 .mapsTo(MISCREG_ICC_AP0R3);
4535 InitReg(MISCREG_ICC_AP1R0_EL1)
4536 .banked()
4537 .mapsTo(MISCREG_ICC_AP1R0);
4538 InitReg(MISCREG_ICC_AP1R0_EL1_NS)
4539 .bankedChild()
4540 .allPrivileges().exceptUserMode()
4541 .mapsTo(MISCREG_ICC_AP1R0_NS);
4542 InitReg(MISCREG_ICC_AP1R0_EL1_S)
4543 .bankedChild()
4544 .allPrivileges().exceptUserMode()
4545 .mapsTo(MISCREG_ICC_AP1R0_S);
4546 InitReg(MISCREG_ICC_AP1R1_EL1)
4547 .banked()
4548 .mapsTo(MISCREG_ICC_AP1R1);
4549 InitReg(MISCREG_ICC_AP1R1_EL1_NS)
4550 .bankedChild()
4551 .allPrivileges().exceptUserMode()
4552 .mapsTo(MISCREG_ICC_AP1R1_NS);
4553 InitReg(MISCREG_ICC_AP1R1_EL1_S)
4554 .bankedChild()
4555 .allPrivileges().exceptUserMode()
4556 .mapsTo(MISCREG_ICC_AP1R1_S);
4557 InitReg(MISCREG_ICC_AP1R2_EL1)
4558 .banked()
4559 .mapsTo(MISCREG_ICC_AP1R2);
4560 InitReg(MISCREG_ICC_AP1R2_EL1_NS)
4561 .bankedChild()
4562 .allPrivileges().exceptUserMode()
4563 .mapsTo(MISCREG_ICC_AP1R2_NS);
4564 InitReg(MISCREG_ICC_AP1R2_EL1_S)
4565 .bankedChild()
4566 .allPrivileges().exceptUserMode()
4567 .mapsTo(MISCREG_ICC_AP1R2_S);
4568 InitReg(MISCREG_ICC_AP1R3_EL1)
4569 .banked()
4570 .mapsTo(MISCREG_ICC_AP1R3);
4571 InitReg(MISCREG_ICC_AP1R3_EL1_NS)
4572 .bankedChild()
4573 .allPrivileges().exceptUserMode()
4574 .mapsTo(MISCREG_ICC_AP1R3_NS);
4575 InitReg(MISCREG_ICC_AP1R3_EL1_S)
4576 .bankedChild()
4577 .allPrivileges().exceptUserMode()
4578 .mapsTo(MISCREG_ICC_AP1R3_S);
4579 InitReg(MISCREG_ICC_DIR_EL1)
4580 .res0(0xFF000000) // [31:24]
4581 .allPrivileges().exceptUserMode().reads(0)
4582 .mapsTo(MISCREG_ICC_DIR);
4583 InitReg(MISCREG_ICC_RPR_EL1)
4584 .allPrivileges().exceptUserMode().writes(0)
4585 .mapsTo(MISCREG_ICC_RPR);
4586 InitReg(MISCREG_ICC_SGI1R_EL1)
4587 .allPrivileges().exceptUserMode().reads(0)
4588 .mapsTo(MISCREG_ICC_SGI1R);
4589 InitReg(MISCREG_ICC_ASGI1R_EL1)
4590 .allPrivileges().exceptUserMode().reads(0)
4591 .mapsTo(MISCREG_ICC_ASGI1R);
4592 InitReg(MISCREG_ICC_SGI0R_EL1)
4593 .allPrivileges().exceptUserMode().reads(0)
4594 .mapsTo(MISCREG_ICC_SGI0R);
4595 InitReg(MISCREG_ICC_IAR1_EL1)
4596 .allPrivileges().exceptUserMode().writes(0)
4597 .mapsTo(MISCREG_ICC_IAR1);
4598 InitReg(MISCREG_ICC_EOIR1_EL1)
4599 .res0(0xFF000000) // [31:24]
4600 .allPrivileges().exceptUserMode().reads(0)
4601 .mapsTo(MISCREG_ICC_EOIR1);
4602 InitReg(MISCREG_ICC_HPPIR1_EL1)
4603 .allPrivileges().exceptUserMode().writes(0)
4604 .mapsTo(MISCREG_ICC_HPPIR1);
4605 InitReg(MISCREG_ICC_BPR1_EL1)
4606 .banked64()
4607 .mapsTo(MISCREG_ICC_BPR1);
4608 InitReg(MISCREG_ICC_BPR1_EL1_NS)
4609 .bankedChild()
4610 .res0(0xfffffff8) // [31:3]
4611 .allPrivileges().exceptUserMode()
4612 .mapsTo(MISCREG_ICC_BPR1_NS);
4613 InitReg(MISCREG_ICC_BPR1_EL1_S)
4614 .bankedChild()
4615 .res0(0xfffffff8) // [31:3]
4616 .secure().exceptUserMode()
4617 .mapsTo(MISCREG_ICC_BPR1_S);
4618 InitReg(MISCREG_ICC_CTLR_EL1)
1/*
2 * Copyright (c) 2010-2013, 2015-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 * Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include <tuple>
45
46#include "arch/arm/isa.hh"
47#include "base/logging.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51namespace ArmISA
52{
53
54MiscRegIndex
55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56{
57 switch(crn) {
58 case 0:
59 switch (opc1) {
60 case 0:
61 switch (opc2) {
62 case 0:
63 switch (crm) {
64 case 0:
65 return MISCREG_DBGDIDR;
66 case 1:
67 return MISCREG_DBGDSCRint;
68 }
69 break;
70 }
71 break;
72 case 7:
73 switch (opc2) {
74 case 0:
75 switch (crm) {
76 case 0:
77 return MISCREG_JIDR;
78 }
79 break;
80 }
81 break;
82 }
83 break;
84 case 1:
85 switch (opc1) {
86 case 6:
87 switch (crm) {
88 case 0:
89 switch (opc2) {
90 case 0:
91 return MISCREG_TEEHBR;
92 }
93 break;
94 }
95 break;
96 case 7:
97 switch (crm) {
98 case 0:
99 switch (opc2) {
100 case 0:
101 return MISCREG_JOSCR;
102 }
103 break;
104 }
105 break;
106 }
107 break;
108 case 2:
109 switch (opc1) {
110 case 7:
111 switch (crm) {
112 case 0:
113 switch (opc2) {
114 case 0:
115 return MISCREG_JMCR;
116 }
117 break;
118 }
119 break;
120 }
121 break;
122 }
123 // If we get here then it must be a register that we haven't implemented
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn, opc1, crm, opc2);
126 return MISCREG_CP14_UNIMPL;
127}
128
129using namespace std;
130
131MiscRegIndex
132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133{
134 switch (crn) {
135 case 0:
136 switch (opc1) {
137 case 0:
138 switch (crm) {
139 case 0:
140 switch (opc2) {
141 case 1:
142 return MISCREG_CTR;
143 case 2:
144 return MISCREG_TCMTR;
145 case 3:
146 return MISCREG_TLBTR;
147 case 5:
148 return MISCREG_MPIDR;
149 case 6:
150 return MISCREG_REVIDR;
151 default:
152 return MISCREG_MIDR;
153 }
154 break;
155 case 1:
156 switch (opc2) {
157 case 0:
158 return MISCREG_ID_PFR0;
159 case 1:
160 return MISCREG_ID_PFR1;
161 case 2:
162 return MISCREG_ID_DFR0;
163 case 3:
164 return MISCREG_ID_AFR0;
165 case 4:
166 return MISCREG_ID_MMFR0;
167 case 5:
168 return MISCREG_ID_MMFR1;
169 case 6:
170 return MISCREG_ID_MMFR2;
171 case 7:
172 return MISCREG_ID_MMFR3;
173 }
174 break;
175 case 2:
176 switch (opc2) {
177 case 0:
178 return MISCREG_ID_ISAR0;
179 case 1:
180 return MISCREG_ID_ISAR1;
181 case 2:
182 return MISCREG_ID_ISAR2;
183 case 3:
184 return MISCREG_ID_ISAR3;
185 case 4:
186 return MISCREG_ID_ISAR4;
187 case 5:
188 return MISCREG_ID_ISAR5;
189 case 6:
190 case 7:
191 return MISCREG_RAZ; // read as zero
192 }
193 break;
194 default:
195 return MISCREG_RAZ; // read as zero
196 }
197 break;
198 case 1:
199 if (crm == 0) {
200 switch (opc2) {
201 case 0:
202 return MISCREG_CCSIDR;
203 case 1:
204 return MISCREG_CLIDR;
205 case 7:
206 return MISCREG_AIDR;
207 }
208 }
209 break;
210 case 2:
211 if (crm == 0 && opc2 == 0) {
212 return MISCREG_CSSELR;
213 }
214 break;
215 case 4:
216 if (crm == 0) {
217 if (opc2 == 0)
218 return MISCREG_VPIDR;
219 else if (opc2 == 5)
220 return MISCREG_VMPIDR;
221 }
222 break;
223 }
224 break;
225 case 1:
226 if (opc1 == 0) {
227 if (crm == 0) {
228 switch (opc2) {
229 case 0:
230 return MISCREG_SCTLR;
231 case 1:
232 return MISCREG_ACTLR;
233 case 0x2:
234 return MISCREG_CPACR;
235 }
236 } else if (crm == 1) {
237 switch (opc2) {
238 case 0:
239 return MISCREG_SCR;
240 case 1:
241 return MISCREG_SDER;
242 case 2:
243 return MISCREG_NSACR;
244 }
245 }
246 } else if (opc1 == 4) {
247 if (crm == 0) {
248 if (opc2 == 0)
249 return MISCREG_HSCTLR;
250 else if (opc2 == 1)
251 return MISCREG_HACTLR;
252 } else if (crm == 1) {
253 switch (opc2) {
254 case 0:
255 return MISCREG_HCR;
256 case 1:
257 return MISCREG_HDCR;
258 case 2:
259 return MISCREG_HCPTR;
260 case 3:
261 return MISCREG_HSTR;
262 case 7:
263 return MISCREG_HACR;
264 }
265 }
266 }
267 break;
268 case 2:
269 if (opc1 == 0 && crm == 0) {
270 switch (opc2) {
271 case 0:
272 return MISCREG_TTBR0;
273 case 1:
274 return MISCREG_TTBR1;
275 case 2:
276 return MISCREG_TTBCR;
277 }
278 } else if (opc1 == 4) {
279 if (crm == 0 && opc2 == 2)
280 return MISCREG_HTCR;
281 else if (crm == 1 && opc2 == 2)
282 return MISCREG_VTCR;
283 }
284 break;
285 case 3:
286 if (opc1 == 0 && crm == 0 && opc2 == 0) {
287 return MISCREG_DACR;
288 }
289 break;
290 case 4:
291 if (opc1 == 0 && crm == 6 && opc2 == 0) {
292 return MISCREG_ICC_PMR;
293 }
294 break;
295 case 5:
296 if (opc1 == 0) {
297 if (crm == 0) {
298 if (opc2 == 0) {
299 return MISCREG_DFSR;
300 } else if (opc2 == 1) {
301 return MISCREG_IFSR;
302 }
303 } else if (crm == 1) {
304 if (opc2 == 0) {
305 return MISCREG_ADFSR;
306 } else if (opc2 == 1) {
307 return MISCREG_AIFSR;
308 }
309 }
310 } else if (opc1 == 4) {
311 if (crm == 1) {
312 if (opc2 == 0)
313 return MISCREG_HADFSR;
314 else if (opc2 == 1)
315 return MISCREG_HAIFSR;
316 } else if (crm == 2 && opc2 == 0) {
317 return MISCREG_HSR;
318 }
319 }
320 break;
321 case 6:
322 if (opc1 == 0 && crm == 0) {
323 switch (opc2) {
324 case 0:
325 return MISCREG_DFAR;
326 case 2:
327 return MISCREG_IFAR;
328 }
329 } else if (opc1 == 4 && crm == 0) {
330 switch (opc2) {
331 case 0:
332 return MISCREG_HDFAR;
333 case 2:
334 return MISCREG_HIFAR;
335 case 4:
336 return MISCREG_HPFAR;
337 }
338 }
339 break;
340 case 7:
341 if (opc1 == 0) {
342 switch (crm) {
343 case 0:
344 if (opc2 == 4) {
345 return MISCREG_NOP;
346 }
347 break;
348 case 1:
349 switch (opc2) {
350 case 0:
351 return MISCREG_ICIALLUIS;
352 case 6:
353 return MISCREG_BPIALLIS;
354 }
355 break;
356 case 4:
357 if (opc2 == 0) {
358 return MISCREG_PAR;
359 }
360 break;
361 case 5:
362 switch (opc2) {
363 case 0:
364 return MISCREG_ICIALLU;
365 case 1:
366 return MISCREG_ICIMVAU;
367 case 4:
368 return MISCREG_CP15ISB;
369 case 6:
370 return MISCREG_BPIALL;
371 case 7:
372 return MISCREG_BPIMVA;
373 }
374 break;
375 case 6:
376 if (opc2 == 1) {
377 return MISCREG_DCIMVAC;
378 } else if (opc2 == 2) {
379 return MISCREG_DCISW;
380 }
381 break;
382 case 8:
383 switch (opc2) {
384 case 0:
385 return MISCREG_ATS1CPR;
386 case 1:
387 return MISCREG_ATS1CPW;
388 case 2:
389 return MISCREG_ATS1CUR;
390 case 3:
391 return MISCREG_ATS1CUW;
392 case 4:
393 return MISCREG_ATS12NSOPR;
394 case 5:
395 return MISCREG_ATS12NSOPW;
396 case 6:
397 return MISCREG_ATS12NSOUR;
398 case 7:
399 return MISCREG_ATS12NSOUW;
400 }
401 break;
402 case 10:
403 switch (opc2) {
404 case 1:
405 return MISCREG_DCCMVAC;
406 case 2:
407 return MISCREG_DCCSW;
408 case 4:
409 return MISCREG_CP15DSB;
410 case 5:
411 return MISCREG_CP15DMB;
412 }
413 break;
414 case 11:
415 if (opc2 == 1) {
416 return MISCREG_DCCMVAU;
417 }
418 break;
419 case 13:
420 if (opc2 == 1) {
421 return MISCREG_NOP;
422 }
423 break;
424 case 14:
425 if (opc2 == 1) {
426 return MISCREG_DCCIMVAC;
427 } else if (opc2 == 2) {
428 return MISCREG_DCCISW;
429 }
430 break;
431 }
432 } else if (opc1 == 4 && crm == 8) {
433 if (opc2 == 0)
434 return MISCREG_ATS1HR;
435 else if (opc2 == 1)
436 return MISCREG_ATS1HW;
437 }
438 break;
439 case 8:
440 if (opc1 == 0) {
441 switch (crm) {
442 case 3:
443 switch (opc2) {
444 case 0:
445 return MISCREG_TLBIALLIS;
446 case 1:
447 return MISCREG_TLBIMVAIS;
448 case 2:
449 return MISCREG_TLBIASIDIS;
450 case 3:
451 return MISCREG_TLBIMVAAIS;
452 case 5:
453 return MISCREG_TLBIMVALIS;
454 case 7:
455 return MISCREG_TLBIMVAALIS;
456 }
457 break;
458 case 5:
459 switch (opc2) {
460 case 0:
461 return MISCREG_ITLBIALL;
462 case 1:
463 return MISCREG_ITLBIMVA;
464 case 2:
465 return MISCREG_ITLBIASID;
466 }
467 break;
468 case 6:
469 switch (opc2) {
470 case 0:
471 return MISCREG_DTLBIALL;
472 case 1:
473 return MISCREG_DTLBIMVA;
474 case 2:
475 return MISCREG_DTLBIASID;
476 }
477 break;
478 case 7:
479 switch (opc2) {
480 case 0:
481 return MISCREG_TLBIALL;
482 case 1:
483 return MISCREG_TLBIMVA;
484 case 2:
485 return MISCREG_TLBIASID;
486 case 3:
487 return MISCREG_TLBIMVAA;
488 case 5:
489 return MISCREG_TLBIMVAL;
490 case 7:
491 return MISCREG_TLBIMVAAL;
492 }
493 break;
494 }
495 } else if (opc1 == 4) {
496 if (crm == 0) {
497 switch (opc2) {
498 case 1:
499 return MISCREG_TLBIIPAS2IS;
500 case 5:
501 return MISCREG_TLBIIPAS2LIS;
502 }
503 } else if (crm == 3) {
504 switch (opc2) {
505 case 0:
506 return MISCREG_TLBIALLHIS;
507 case 1:
508 return MISCREG_TLBIMVAHIS;
509 case 4:
510 return MISCREG_TLBIALLNSNHIS;
511 case 5:
512 return MISCREG_TLBIMVALHIS;
513 }
514 } else if (crm == 4) {
515 switch (opc2) {
516 case 1:
517 return MISCREG_TLBIIPAS2;
518 case 5:
519 return MISCREG_TLBIIPAS2L;
520 }
521 } else if (crm == 7) {
522 switch (opc2) {
523 case 0:
524 return MISCREG_TLBIALLH;
525 case 1:
526 return MISCREG_TLBIMVAH;
527 case 4:
528 return MISCREG_TLBIALLNSNH;
529 case 5:
530 return MISCREG_TLBIMVALH;
531 }
532 }
533 }
534 break;
535 case 9:
536 // Every cop register with CRn = 9 and CRm in
537 // {0-2}, {5-8} is implementation defined regardless
538 // of opc1 and opc2.
539 switch (crm) {
540 case 0:
541 case 1:
542 case 2:
543 case 5:
544 case 6:
545 case 7:
546 case 8:
547 return MISCREG_IMPDEF_UNIMPL;
548 }
549 if (opc1 == 0) {
550 switch (crm) {
551 case 12:
552 switch (opc2) {
553 case 0:
554 return MISCREG_PMCR;
555 case 1:
556 return MISCREG_PMCNTENSET;
557 case 2:
558 return MISCREG_PMCNTENCLR;
559 case 3:
560 return MISCREG_PMOVSR;
561 case 4:
562 return MISCREG_PMSWINC;
563 case 5:
564 return MISCREG_PMSELR;
565 case 6:
566 return MISCREG_PMCEID0;
567 case 7:
568 return MISCREG_PMCEID1;
569 }
570 break;
571 case 13:
572 switch (opc2) {
573 case 0:
574 return MISCREG_PMCCNTR;
575 case 1:
576 // Selector is PMSELR.SEL
577 return MISCREG_PMXEVTYPER_PMCCFILTR;
578 case 2:
579 return MISCREG_PMXEVCNTR;
580 }
581 break;
582 case 14:
583 switch (opc2) {
584 case 0:
585 return MISCREG_PMUSERENR;
586 case 1:
587 return MISCREG_PMINTENSET;
588 case 2:
589 return MISCREG_PMINTENCLR;
590 case 3:
591 return MISCREG_PMOVSSET;
592 }
593 break;
594 }
595 } else if (opc1 == 1) {
596 switch (crm) {
597 case 0:
598 switch (opc2) {
599 case 2: // L2CTLR, L2 Control Register
600 return MISCREG_L2CTLR;
601 case 3:
602 return MISCREG_L2ECTLR;
603 }
604 break;
605 break;
606 }
607 }
608 break;
609 case 10:
610 if (opc1 == 0) {
611 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
612 if (crm < 2) {
613 return MISCREG_IMPDEF_UNIMPL;
614 } else if (crm == 2) { // TEX Remap Registers
615 if (opc2 == 0) {
616 // Selector is TTBCR.EAE
617 return MISCREG_PRRR_MAIR0;
618 } else if (opc2 == 1) {
619 // Selector is TTBCR.EAE
620 return MISCREG_NMRR_MAIR1;
621 }
622 } else if (crm == 3) {
623 if (opc2 == 0) {
624 return MISCREG_AMAIR0;
625 } else if (opc2 == 1) {
626 return MISCREG_AMAIR1;
627 }
628 }
629 } else if (opc1 == 4) {
630 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
631 if (crm == 2) {
632 if (opc2 == 0)
633 return MISCREG_HMAIR0;
634 else if (opc2 == 1)
635 return MISCREG_HMAIR1;
636 } else if (crm == 3) {
637 if (opc2 == 0)
638 return MISCREG_HAMAIR0;
639 else if (opc2 == 1)
640 return MISCREG_HAMAIR1;
641 }
642 }
643 break;
644 case 11:
645 if (opc1 <=7) {
646 switch (crm) {
647 case 0:
648 case 1:
649 case 2:
650 case 3:
651 case 4:
652 case 5:
653 case 6:
654 case 7:
655 case 8:
656 case 15:
657 // Reserved for DMA operations for TCM access
658 return MISCREG_IMPDEF_UNIMPL;
659 default:
660 break;
661 }
662 }
663 break;
664 case 12:
665 if (opc1 == 0) {
666 if (crm == 0) {
667 if (opc2 == 0) {
668 return MISCREG_VBAR;
669 } else if (opc2 == 1) {
670 return MISCREG_MVBAR;
671 }
672 } else if (crm == 1) {
673 if (opc2 == 0) {
674 return MISCREG_ISR;
675 }
676 } else if (crm == 8) {
677 switch (opc2) {
678 case 0:
679 return MISCREG_ICC_IAR0;
680 case 1:
681 return MISCREG_ICC_EOIR0;
682 case 2:
683 return MISCREG_ICC_HPPIR0;
684 case 3:
685 return MISCREG_ICC_BPR0;
686 case 4:
687 return MISCREG_ICC_AP0R0;
688 case 5:
689 return MISCREG_ICC_AP0R1;
690 case 6:
691 return MISCREG_ICC_AP0R2;
692 case 7:
693 return MISCREG_ICC_AP0R3;
694 }
695 } else if (crm == 9) {
696 switch (opc2) {
697 case 0:
698 return MISCREG_ICC_AP1R0;
699 case 1:
700 return MISCREG_ICC_AP1R1;
701 case 2:
702 return MISCREG_ICC_AP1R2;
703 case 3:
704 return MISCREG_ICC_AP1R3;
705 }
706 } else if (crm == 11) {
707 switch (opc2) {
708 case 1:
709 return MISCREG_ICC_DIR;
710 case 3:
711 return MISCREG_ICC_RPR;
712 }
713 } else if (crm == 12) {
714 switch (opc2) {
715 case 0:
716 return MISCREG_ICC_IAR1;
717 case 1:
718 return MISCREG_ICC_EOIR1;
719 case 2:
720 return MISCREG_ICC_HPPIR1;
721 case 3:
722 return MISCREG_ICC_BPR1;
723 case 4:
724 return MISCREG_ICC_CTLR;
725 case 5:
726 return MISCREG_ICC_SRE;
727 case 6:
728 return MISCREG_ICC_IGRPEN0;
729 case 7:
730 return MISCREG_ICC_IGRPEN1;
731 }
732 }
733 } else if (opc1 == 4) {
734 if (crm == 0 && opc2 == 0) {
735 return MISCREG_HVBAR;
736 } else if (crm == 8) {
737 switch (opc2) {
738 case 0:
739 return MISCREG_ICH_AP0R0;
740 case 1:
741 return MISCREG_ICH_AP0R1;
742 case 2:
743 return MISCREG_ICH_AP0R2;
744 case 3:
745 return MISCREG_ICH_AP0R3;
746 }
747 } else if (crm == 9) {
748 switch (opc2) {
749 case 0:
750 return MISCREG_ICH_AP1R0;
751 case 1:
752 return MISCREG_ICH_AP1R1;
753 case 2:
754 return MISCREG_ICH_AP1R2;
755 case 3:
756 return MISCREG_ICH_AP1R3;
757 case 5:
758 return MISCREG_ICC_HSRE;
759 }
760 } else if (crm == 11) {
761 switch (opc2) {
762 case 0:
763 return MISCREG_ICH_HCR;
764 case 1:
765 return MISCREG_ICH_VTR;
766 case 2:
767 return MISCREG_ICH_MISR;
768 case 3:
769 return MISCREG_ICH_EISR;
770 case 5:
771 return MISCREG_ICH_ELRSR;
772 case 7:
773 return MISCREG_ICH_VMCR;
774 }
775 } else if (crm == 12) {
776 switch (opc2) {
777 case 0:
778 return MISCREG_ICH_LR0;
779 case 1:
780 return MISCREG_ICH_LR1;
781 case 2:
782 return MISCREG_ICH_LR2;
783 case 3:
784 return MISCREG_ICH_LR3;
785 case 4:
786 return MISCREG_ICH_LR4;
787 case 5:
788 return MISCREG_ICH_LR5;
789 case 6:
790 return MISCREG_ICH_LR6;
791 case 7:
792 return MISCREG_ICH_LR7;
793 }
794 } else if (crm == 13) {
795 switch (opc2) {
796 case 0:
797 return MISCREG_ICH_LR8;
798 case 1:
799 return MISCREG_ICH_LR9;
800 case 2:
801 return MISCREG_ICH_LR10;
802 case 3:
803 return MISCREG_ICH_LR11;
804 case 4:
805 return MISCREG_ICH_LR12;
806 case 5:
807 return MISCREG_ICH_LR13;
808 case 6:
809 return MISCREG_ICH_LR14;
810 case 7:
811 return MISCREG_ICH_LR15;
812 }
813 } else if (crm == 14) {
814 switch (opc2) {
815 case 0:
816 return MISCREG_ICH_LRC0;
817 case 1:
818 return MISCREG_ICH_LRC1;
819 case 2:
820 return MISCREG_ICH_LRC2;
821 case 3:
822 return MISCREG_ICH_LRC3;
823 case 4:
824 return MISCREG_ICH_LRC4;
825 case 5:
826 return MISCREG_ICH_LRC5;
827 case 6:
828 return MISCREG_ICH_LRC6;
829 case 7:
830 return MISCREG_ICH_LRC7;
831 }
832 } else if (crm == 15) {
833 switch (opc2) {
834 case 0:
835 return MISCREG_ICH_LRC8;
836 case 1:
837 return MISCREG_ICH_LRC9;
838 case 2:
839 return MISCREG_ICH_LRC10;
840 case 3:
841 return MISCREG_ICH_LRC11;
842 case 4:
843 return MISCREG_ICH_LRC12;
844 case 5:
845 return MISCREG_ICH_LRC13;
846 case 6:
847 return MISCREG_ICH_LRC14;
848 case 7:
849 return MISCREG_ICH_LRC15;
850 }
851 }
852 } else if (opc1 == 6) {
853 if (crm == 12) {
854 switch (opc2) {
855 case 4:
856 return MISCREG_ICC_MCTLR;
857 case 5:
858 return MISCREG_ICC_MSRE;
859 case 7:
860 return MISCREG_ICC_MGRPEN1;
861 }
862 }
863 }
864 break;
865 case 13:
866 if (opc1 == 0) {
867 if (crm == 0) {
868 switch (opc2) {
869 case 0:
870 return MISCREG_FCSEIDR;
871 case 1:
872 return MISCREG_CONTEXTIDR;
873 case 2:
874 return MISCREG_TPIDRURW;
875 case 3:
876 return MISCREG_TPIDRURO;
877 case 4:
878 return MISCREG_TPIDRPRW;
879 }
880 }
881 } else if (opc1 == 4) {
882 if (crm == 0 && opc2 == 2)
883 return MISCREG_HTPIDR;
884 }
885 break;
886 case 14:
887 if (opc1 == 0) {
888 switch (crm) {
889 case 0:
890 if (opc2 == 0)
891 return MISCREG_CNTFRQ;
892 break;
893 case 1:
894 if (opc2 == 0)
895 return MISCREG_CNTKCTL;
896 break;
897 case 2:
898 if (opc2 == 0)
899 return MISCREG_CNTP_TVAL;
900 else if (opc2 == 1)
901 return MISCREG_CNTP_CTL;
902 break;
903 case 3:
904 if (opc2 == 0)
905 return MISCREG_CNTV_TVAL;
906 else if (opc2 == 1)
907 return MISCREG_CNTV_CTL;
908 break;
909 }
910 } else if (opc1 == 4) {
911 if (crm == 1 && opc2 == 0) {
912 return MISCREG_CNTHCTL;
913 } else if (crm == 2) {
914 if (opc2 == 0)
915 return MISCREG_CNTHP_TVAL;
916 else if (opc2 == 1)
917 return MISCREG_CNTHP_CTL;
918 }
919 }
920 break;
921 case 15:
922 // Implementation defined
923 return MISCREG_IMPDEF_UNIMPL;
924 }
925 // Unrecognized register
926 return MISCREG_CP15_UNIMPL;
927}
928
929MiscRegIndex
930decodeCP15Reg64(unsigned crm, unsigned opc1)
931{
932 switch (crm) {
933 case 2:
934 switch (opc1) {
935 case 0:
936 return MISCREG_TTBR0;
937 case 1:
938 return MISCREG_TTBR1;
939 case 4:
940 return MISCREG_HTTBR;
941 case 6:
942 return MISCREG_VTTBR;
943 }
944 break;
945 case 7:
946 if (opc1 == 0)
947 return MISCREG_PAR;
948 break;
949 case 14:
950 switch (opc1) {
951 case 0:
952 return MISCREG_CNTPCT;
953 case 1:
954 return MISCREG_CNTVCT;
955 case 2:
956 return MISCREG_CNTP_CVAL;
957 case 3:
958 return MISCREG_CNTV_CVAL;
959 case 4:
960 return MISCREG_CNTVOFF;
961 case 6:
962 return MISCREG_CNTHP_CVAL;
963 }
964 break;
965 case 12:
966 switch (opc1) {
967 case 0:
968 return MISCREG_ICC_SGI1R;
969 case 1:
970 return MISCREG_ICC_ASGI1R;
971 case 2:
972 return MISCREG_ICC_SGI0R;
973 default:
974 break;
975 }
976 break;
977 case 15:
978 if (opc1 == 0)
979 return MISCREG_CPUMERRSR;
980 else if (opc1 == 1)
981 return MISCREG_L2MERRSR;
982 break;
983 }
984 // Unrecognized register
985 return MISCREG_CP15_UNIMPL;
986}
987
988std::tuple<bool, bool>
989canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
990{
991 bool secure = !scr.ns;
992 bool canRead = false;
993 bool undefined = false;
994
995 switch (cpsr.mode) {
996 case MODE_USER:
997 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
998 miscRegInfo[reg][MISCREG_USR_NS_RD];
999 break;
1000 case MODE_FIQ:
1001 case MODE_IRQ:
1002 case MODE_SVC:
1003 case MODE_ABORT:
1004 case MODE_UNDEFINED:
1005 case MODE_SYSTEM:
1006 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1007 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1008 break;
1009 case MODE_MON:
1010 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1011 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1012 break;
1013 case MODE_HYP:
1014 canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1015 break;
1016 default:
1017 undefined = true;
1018 }
1019 // can't do permissions checkes on the root of a banked pair of regs
1020 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1021 return std::make_tuple(canRead, undefined);
1022}
1023
1024std::tuple<bool, bool>
1025canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
1026{
1027 bool secure = !scr.ns;
1028 bool canWrite = false;
1029 bool undefined = false;
1030
1031 switch (cpsr.mode) {
1032 case MODE_USER:
1033 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1034 miscRegInfo[reg][MISCREG_USR_NS_WR];
1035 break;
1036 case MODE_FIQ:
1037 case MODE_IRQ:
1038 case MODE_SVC:
1039 case MODE_ABORT:
1040 case MODE_UNDEFINED:
1041 case MODE_SYSTEM:
1042 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1043 miscRegInfo[reg][MISCREG_PRI_NS_WR];
1044 break;
1045 case MODE_MON:
1046 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1047 miscRegInfo[reg][MISCREG_MON_NS1_WR];
1048 break;
1049 case MODE_HYP:
1050 canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
1051 break;
1052 default:
1053 undefined = true;
1054 }
1055 // can't do permissions checkes on the root of a banked pair of regs
1056 assert(!miscRegInfo[reg][MISCREG_BANKED]);
1057 return std::make_tuple(canWrite, undefined);
1058}
1059
1060int
1061snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
1062{
1063 SCR scr = tc->readMiscReg(MISCREG_SCR);
1064 return snsBankedIndex(reg, tc, scr.ns);
1065}
1066
1067int
1068snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
1069{
1070 int reg_as_int = static_cast<int>(reg);
1071 if (miscRegInfo[reg][MISCREG_BANKED]) {
1072 reg_as_int += (ArmSystem::haveSecurity(tc) &&
1073 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
1074 }
1075 return reg_as_int;
1076}
1077
1078int
1079snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
1080{
1081 SCR scr = tc->readMiscReg(MISCREG_SCR);
1082 return tc->getIsaPtr()->snsBankedIndex64(reg, scr.ns);
1083}
1084
1085/**
1086 * If the reg is a child reg of a banked set, then the parent is the last
1087 * banked one in the list. This is messy, and the wish is to eventually have
1088 * the bitmap replaced with a better data structure. the preUnflatten function
1089 * initializes a lookup table to speed up the search for these banked
1090 * registers.
1091 */
1092
1093int unflattenResultMiscReg[NUM_MISCREGS];
1094
1095void
1096preUnflattenMiscReg()
1097{
1098 int reg = -1;
1099 for (int i = 0 ; i < NUM_MISCREGS; i++){
1100 if (miscRegInfo[i][MISCREG_BANKED])
1101 reg = i;
1102 if (miscRegInfo[i][MISCREG_BANKED_CHILD])
1103 unflattenResultMiscReg[i] = reg;
1104 else
1105 unflattenResultMiscReg[i] = i;
1106 // if this assert fails, no parent was found, and something is broken
1107 assert(unflattenResultMiscReg[i] > -1);
1108 }
1109}
1110
1111int
1112unflattenMiscReg(int reg)
1113{
1114 return unflattenResultMiscReg[reg];
1115}
1116
1117bool
1118canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1119{
1120 // Check for SP_EL0 access while SPSEL == 0
1121 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1122 return false;
1123
1124 // Check for RVBAR access
1125 if (reg == MISCREG_RVBAR_EL1) {
1126 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1127 if (highest_el == EL2 || highest_el == EL3)
1128 return false;
1129 }
1130 if (reg == MISCREG_RVBAR_EL2) {
1131 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1132 if (highest_el == EL3)
1133 return false;
1134 }
1135
1136 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1137
1138 switch (currEL(cpsr)) {
1139 case EL0:
1140 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1141 miscRegInfo[reg][MISCREG_USR_NS_RD];
1142 case EL1:
1143 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1144 miscRegInfo[reg][MISCREG_PRI_NS_RD];
1145 case EL2:
1146 return miscRegInfo[reg][MISCREG_HYP_RD];
1147 case EL3:
1148 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1149 miscRegInfo[reg][MISCREG_MON_NS1_RD];
1150 default:
1151 panic("Invalid exception level");
1152 }
1153}
1154
1155bool
1156canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1157{
1158 // Check for SP_EL0 access while SPSEL == 0
1159 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1160 return false;
1161 ExceptionLevel el = currEL(cpsr);
1162 if (reg == MISCREG_DAIF) {
1163 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1164 if (el == EL0 && !sctlr.uma)
1165 return false;
1166 }
1167 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
1168 // In syscall-emulation mode, this test is skipped and DCZVA is always
1169 // allowed at EL0
1170 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1171 if (el == EL0 && !sctlr.dze)
1172 return false;
1173 }
1174 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
1175 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1176 if (el == EL0 && !sctlr.uci)
1177 return false;
1178 }
1179
1180 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1181
1182 switch (el) {
1183 case EL0:
1184 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1185 miscRegInfo[reg][MISCREG_USR_NS_WR];
1186 case EL1:
1187 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1188 miscRegInfo[reg][MISCREG_PRI_NS_WR];
1189 case EL2:
1190 return miscRegInfo[reg][MISCREG_HYP_WR];
1191 case EL3:
1192 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1193 miscRegInfo[reg][MISCREG_MON_NS1_WR];
1194 default:
1195 panic("Invalid exception level");
1196 }
1197}
1198
1199MiscRegIndex
1200decodeAArch64SysReg(unsigned op0, unsigned op1,
1201 unsigned crn, unsigned crm,
1202 unsigned op2)
1203{
1204 switch (op0) {
1205 case 1:
1206 switch (crn) {
1207 case 7:
1208 switch (op1) {
1209 case 0:
1210 switch (crm) {
1211 case 1:
1212 switch (op2) {
1213 case 0:
1214 return MISCREG_IC_IALLUIS;
1215 }
1216 break;
1217 case 5:
1218 switch (op2) {
1219 case 0:
1220 return MISCREG_IC_IALLU;
1221 }
1222 break;
1223 case 6:
1224 switch (op2) {
1225 case 1:
1226 return MISCREG_DC_IVAC_Xt;
1227 case 2:
1228 return MISCREG_DC_ISW_Xt;
1229 }
1230 break;
1231 case 8:
1232 switch (op2) {
1233 case 0:
1234 return MISCREG_AT_S1E1R_Xt;
1235 case 1:
1236 return MISCREG_AT_S1E1W_Xt;
1237 case 2:
1238 return MISCREG_AT_S1E0R_Xt;
1239 case 3:
1240 return MISCREG_AT_S1E0W_Xt;
1241 }
1242 break;
1243 case 10:
1244 switch (op2) {
1245 case 2:
1246 return MISCREG_DC_CSW_Xt;
1247 }
1248 break;
1249 case 14:
1250 switch (op2) {
1251 case 2:
1252 return MISCREG_DC_CISW_Xt;
1253 }
1254 break;
1255 }
1256 break;
1257 case 3:
1258 switch (crm) {
1259 case 4:
1260 switch (op2) {
1261 case 1:
1262 return MISCREG_DC_ZVA_Xt;
1263 }
1264 break;
1265 case 5:
1266 switch (op2) {
1267 case 1:
1268 return MISCREG_IC_IVAU_Xt;
1269 }
1270 break;
1271 case 10:
1272 switch (op2) {
1273 case 1:
1274 return MISCREG_DC_CVAC_Xt;
1275 }
1276 break;
1277 case 11:
1278 switch (op2) {
1279 case 1:
1280 return MISCREG_DC_CVAU_Xt;
1281 }
1282 break;
1283 case 14:
1284 switch (op2) {
1285 case 1:
1286 return MISCREG_DC_CIVAC_Xt;
1287 }
1288 break;
1289 }
1290 break;
1291 case 4:
1292 switch (crm) {
1293 case 8:
1294 switch (op2) {
1295 case 0:
1296 return MISCREG_AT_S1E2R_Xt;
1297 case 1:
1298 return MISCREG_AT_S1E2W_Xt;
1299 case 4:
1300 return MISCREG_AT_S12E1R_Xt;
1301 case 5:
1302 return MISCREG_AT_S12E1W_Xt;
1303 case 6:
1304 return MISCREG_AT_S12E0R_Xt;
1305 case 7:
1306 return MISCREG_AT_S12E0W_Xt;
1307 }
1308 break;
1309 }
1310 break;
1311 case 6:
1312 switch (crm) {
1313 case 8:
1314 switch (op2) {
1315 case 0:
1316 return MISCREG_AT_S1E3R_Xt;
1317 case 1:
1318 return MISCREG_AT_S1E3W_Xt;
1319 }
1320 break;
1321 }
1322 break;
1323 }
1324 break;
1325 case 8:
1326 switch (op1) {
1327 case 0:
1328 switch (crm) {
1329 case 3:
1330 switch (op2) {
1331 case 0:
1332 return MISCREG_TLBI_VMALLE1IS;
1333 case 1:
1334 return MISCREG_TLBI_VAE1IS_Xt;
1335 case 2:
1336 return MISCREG_TLBI_ASIDE1IS_Xt;
1337 case 3:
1338 return MISCREG_TLBI_VAAE1IS_Xt;
1339 case 5:
1340 return MISCREG_TLBI_VALE1IS_Xt;
1341 case 7:
1342 return MISCREG_TLBI_VAALE1IS_Xt;
1343 }
1344 break;
1345 case 7:
1346 switch (op2) {
1347 case 0:
1348 return MISCREG_TLBI_VMALLE1;
1349 case 1:
1350 return MISCREG_TLBI_VAE1_Xt;
1351 case 2:
1352 return MISCREG_TLBI_ASIDE1_Xt;
1353 case 3:
1354 return MISCREG_TLBI_VAAE1_Xt;
1355 case 5:
1356 return MISCREG_TLBI_VALE1_Xt;
1357 case 7:
1358 return MISCREG_TLBI_VAALE1_Xt;
1359 }
1360 break;
1361 }
1362 break;
1363 case 4:
1364 switch (crm) {
1365 case 0:
1366 switch (op2) {
1367 case 1:
1368 return MISCREG_TLBI_IPAS2E1IS_Xt;
1369 case 5:
1370 return MISCREG_TLBI_IPAS2LE1IS_Xt;
1371 }
1372 break;
1373 case 3:
1374 switch (op2) {
1375 case 0:
1376 return MISCREG_TLBI_ALLE2IS;
1377 case 1:
1378 return MISCREG_TLBI_VAE2IS_Xt;
1379 case 4:
1380 return MISCREG_TLBI_ALLE1IS;
1381 case 5:
1382 return MISCREG_TLBI_VALE2IS_Xt;
1383 case 6:
1384 return MISCREG_TLBI_VMALLS12E1IS;
1385 }
1386 break;
1387 case 4:
1388 switch (op2) {
1389 case 1:
1390 return MISCREG_TLBI_IPAS2E1_Xt;
1391 case 5:
1392 return MISCREG_TLBI_IPAS2LE1_Xt;
1393 }
1394 break;
1395 case 7:
1396 switch (op2) {
1397 case 0:
1398 return MISCREG_TLBI_ALLE2;
1399 case 1:
1400 return MISCREG_TLBI_VAE2_Xt;
1401 case 4:
1402 return MISCREG_TLBI_ALLE1;
1403 case 5:
1404 return MISCREG_TLBI_VALE2_Xt;
1405 case 6:
1406 return MISCREG_TLBI_VMALLS12E1;
1407 }
1408 break;
1409 }
1410 break;
1411 case 6:
1412 switch (crm) {
1413 case 3:
1414 switch (op2) {
1415 case 0:
1416 return MISCREG_TLBI_ALLE3IS;
1417 case 1:
1418 return MISCREG_TLBI_VAE3IS_Xt;
1419 case 5:
1420 return MISCREG_TLBI_VALE3IS_Xt;
1421 }
1422 break;
1423 case 7:
1424 switch (op2) {
1425 case 0:
1426 return MISCREG_TLBI_ALLE3;
1427 case 1:
1428 return MISCREG_TLBI_VAE3_Xt;
1429 case 5:
1430 return MISCREG_TLBI_VALE3_Xt;
1431 }
1432 break;
1433 }
1434 break;
1435 }
1436 break;
1437 case 11:
1438 case 15:
1439 // SYS Instruction with CRn = { 11, 15 }
1440 // (Trappable by HCR_EL2.TIDCP)
1441 return MISCREG_IMPDEF_UNIMPL;
1442 }
1443 break;
1444 case 2:
1445 switch (crn) {
1446 case 0:
1447 switch (op1) {
1448 case 0:
1449 switch (crm) {
1450 case 0:
1451 switch (op2) {
1452 case 2:
1453 return MISCREG_OSDTRRX_EL1;
1454 case 4:
1455 return MISCREG_DBGBVR0_EL1;
1456 case 5:
1457 return MISCREG_DBGBCR0_EL1;
1458 case 6:
1459 return MISCREG_DBGWVR0_EL1;
1460 case 7:
1461 return MISCREG_DBGWCR0_EL1;
1462 }
1463 break;
1464 case 1:
1465 switch (op2) {
1466 case 4:
1467 return MISCREG_DBGBVR1_EL1;
1468 case 5:
1469 return MISCREG_DBGBCR1_EL1;
1470 case 6:
1471 return MISCREG_DBGWVR1_EL1;
1472 case 7:
1473 return MISCREG_DBGWCR1_EL1;
1474 }
1475 break;
1476 case 2:
1477 switch (op2) {
1478 case 0:
1479 return MISCREG_MDCCINT_EL1;
1480 case 2:
1481 return MISCREG_MDSCR_EL1;
1482 case 4:
1483 return MISCREG_DBGBVR2_EL1;
1484 case 5:
1485 return MISCREG_DBGBCR2_EL1;
1486 case 6:
1487 return MISCREG_DBGWVR2_EL1;
1488 case 7:
1489 return MISCREG_DBGWCR2_EL1;
1490 }
1491 break;
1492 case 3:
1493 switch (op2) {
1494 case 2:
1495 return MISCREG_OSDTRTX_EL1;
1496 case 4:
1497 return MISCREG_DBGBVR3_EL1;
1498 case 5:
1499 return MISCREG_DBGBCR3_EL1;
1500 case 6:
1501 return MISCREG_DBGWVR3_EL1;
1502 case 7:
1503 return MISCREG_DBGWCR3_EL1;
1504 }
1505 break;
1506 case 4:
1507 switch (op2) {
1508 case 4:
1509 return MISCREG_DBGBVR4_EL1;
1510 case 5:
1511 return MISCREG_DBGBCR4_EL1;
1512 }
1513 break;
1514 case 5:
1515 switch (op2) {
1516 case 4:
1517 return MISCREG_DBGBVR5_EL1;
1518 case 5:
1519 return MISCREG_DBGBCR5_EL1;
1520 }
1521 break;
1522 case 6:
1523 switch (op2) {
1524 case 2:
1525 return MISCREG_OSECCR_EL1;
1526 }
1527 break;
1528 }
1529 break;
1530 case 2:
1531 switch (crm) {
1532 case 0:
1533 switch (op2) {
1534 case 0:
1535 return MISCREG_TEECR32_EL1;
1536 }
1537 break;
1538 }
1539 break;
1540 case 3:
1541 switch (crm) {
1542 case 1:
1543 switch (op2) {
1544 case 0:
1545 return MISCREG_MDCCSR_EL0;
1546 }
1547 break;
1548 case 4:
1549 switch (op2) {
1550 case 0:
1551 return MISCREG_MDDTR_EL0;
1552 }
1553 break;
1554 case 5:
1555 switch (op2) {
1556 case 0:
1557 return MISCREG_MDDTRRX_EL0;
1558 }
1559 break;
1560 }
1561 break;
1562 case 4:
1563 switch (crm) {
1564 case 7:
1565 switch (op2) {
1566 case 0:
1567 return MISCREG_DBGVCR32_EL2;
1568 }
1569 break;
1570 }
1571 break;
1572 }
1573 break;
1574 case 1:
1575 switch (op1) {
1576 case 0:
1577 switch (crm) {
1578 case 0:
1579 switch (op2) {
1580 case 0:
1581 return MISCREG_MDRAR_EL1;
1582 case 4:
1583 return MISCREG_OSLAR_EL1;
1584 }
1585 break;
1586 case 1:
1587 switch (op2) {
1588 case 4:
1589 return MISCREG_OSLSR_EL1;
1590 }
1591 break;
1592 case 3:
1593 switch (op2) {
1594 case 4:
1595 return MISCREG_OSDLR_EL1;
1596 }
1597 break;
1598 case 4:
1599 switch (op2) {
1600 case 4:
1601 return MISCREG_DBGPRCR_EL1;
1602 }
1603 break;
1604 }
1605 break;
1606 case 2:
1607 switch (crm) {
1608 case 0:
1609 switch (op2) {
1610 case 0:
1611 return MISCREG_TEEHBR32_EL1;
1612 }
1613 break;
1614 }
1615 break;
1616 }
1617 break;
1618 case 7:
1619 switch (op1) {
1620 case 0:
1621 switch (crm) {
1622 case 8:
1623 switch (op2) {
1624 case 6:
1625 return MISCREG_DBGCLAIMSET_EL1;
1626 }
1627 break;
1628 case 9:
1629 switch (op2) {
1630 case 6:
1631 return MISCREG_DBGCLAIMCLR_EL1;
1632 }
1633 break;
1634 case 14:
1635 switch (op2) {
1636 case 6:
1637 return MISCREG_DBGAUTHSTATUS_EL1;
1638 }
1639 break;
1640 }
1641 break;
1642 }
1643 break;
1644 }
1645 break;
1646 case 3:
1647 switch (crn) {
1648 case 0:
1649 switch (op1) {
1650 case 0:
1651 switch (crm) {
1652 case 0:
1653 switch (op2) {
1654 case 0:
1655 return MISCREG_MIDR_EL1;
1656 case 5:
1657 return MISCREG_MPIDR_EL1;
1658 case 6:
1659 return MISCREG_REVIDR_EL1;
1660 }
1661 break;
1662 case 1:
1663 switch (op2) {
1664 case 0:
1665 return MISCREG_ID_PFR0_EL1;
1666 case 1:
1667 return MISCREG_ID_PFR1_EL1;
1668 case 2:
1669 return MISCREG_ID_DFR0_EL1;
1670 case 3:
1671 return MISCREG_ID_AFR0_EL1;
1672 case 4:
1673 return MISCREG_ID_MMFR0_EL1;
1674 case 5:
1675 return MISCREG_ID_MMFR1_EL1;
1676 case 6:
1677 return MISCREG_ID_MMFR2_EL1;
1678 case 7:
1679 return MISCREG_ID_MMFR3_EL1;
1680 }
1681 break;
1682 case 2:
1683 switch (op2) {
1684 case 0:
1685 return MISCREG_ID_ISAR0_EL1;
1686 case 1:
1687 return MISCREG_ID_ISAR1_EL1;
1688 case 2:
1689 return MISCREG_ID_ISAR2_EL1;
1690 case 3:
1691 return MISCREG_ID_ISAR3_EL1;
1692 case 4:
1693 return MISCREG_ID_ISAR4_EL1;
1694 case 5:
1695 return MISCREG_ID_ISAR5_EL1;
1696 }
1697 break;
1698 case 3:
1699 switch (op2) {
1700 case 0:
1701 return MISCREG_MVFR0_EL1;
1702 case 1:
1703 return MISCREG_MVFR1_EL1;
1704 case 2:
1705 return MISCREG_MVFR2_EL1;
1706 case 3 ... 7:
1707 return MISCREG_RAZ;
1708 }
1709 break;
1710 case 4:
1711 switch (op2) {
1712 case 0:
1713 return MISCREG_ID_AA64PFR0_EL1;
1714 case 1:
1715 return MISCREG_ID_AA64PFR1_EL1;
1716 case 2 ... 3:
1717 return MISCREG_RAZ;
1718 case 4:
1719 return MISCREG_ID_AA64ZFR0_EL1;
1720 case 5 ... 7:
1721 return MISCREG_RAZ;
1722 }
1723 break;
1724 case 5:
1725 switch (op2) {
1726 case 0:
1727 return MISCREG_ID_AA64DFR0_EL1;
1728 case 1:
1729 return MISCREG_ID_AA64DFR1_EL1;
1730 case 4:
1731 return MISCREG_ID_AA64AFR0_EL1;
1732 case 5:
1733 return MISCREG_ID_AA64AFR1_EL1;
1734 case 2:
1735 case 3:
1736 case 6:
1737 case 7:
1738 return MISCREG_RAZ;
1739 }
1740 break;
1741 case 6:
1742 switch (op2) {
1743 case 0:
1744 return MISCREG_ID_AA64ISAR0_EL1;
1745 case 1:
1746 return MISCREG_ID_AA64ISAR1_EL1;
1747 case 2 ... 7:
1748 return MISCREG_RAZ;
1749 }
1750 break;
1751 case 7:
1752 switch (op2) {
1753 case 0:
1754 return MISCREG_ID_AA64MMFR0_EL1;
1755 case 1:
1756 return MISCREG_ID_AA64MMFR1_EL1;
1757 case 2:
1758 return MISCREG_ID_AA64MMFR2_EL1;
1759 case 3 ... 7:
1760 return MISCREG_RAZ;
1761 }
1762 break;
1763 }
1764 break;
1765 case 1:
1766 switch (crm) {
1767 case 0:
1768 switch (op2) {
1769 case 0:
1770 return MISCREG_CCSIDR_EL1;
1771 case 1:
1772 return MISCREG_CLIDR_EL1;
1773 case 7:
1774 return MISCREG_AIDR_EL1;
1775 }
1776 break;
1777 }
1778 break;
1779 case 2:
1780 switch (crm) {
1781 case 0:
1782 switch (op2) {
1783 case 0:
1784 return MISCREG_CSSELR_EL1;
1785 }
1786 break;
1787 }
1788 break;
1789 case 3:
1790 switch (crm) {
1791 case 0:
1792 switch (op2) {
1793 case 1:
1794 return MISCREG_CTR_EL0;
1795 case 7:
1796 return MISCREG_DCZID_EL0;
1797 }
1798 break;
1799 }
1800 break;
1801 case 4:
1802 switch (crm) {
1803 case 0:
1804 switch (op2) {
1805 case 0:
1806 return MISCREG_VPIDR_EL2;
1807 case 5:
1808 return MISCREG_VMPIDR_EL2;
1809 }
1810 break;
1811 }
1812 break;
1813 }
1814 break;
1815 case 1:
1816 switch (op1) {
1817 case 0:
1818 switch (crm) {
1819 case 0:
1820 switch (op2) {
1821 case 0:
1822 return MISCREG_SCTLR_EL1;
1823 case 1:
1824 return MISCREG_ACTLR_EL1;
1825 case 2:
1826 return MISCREG_CPACR_EL1;
1827 }
1828 break;
1829 case 2:
1830 switch (op2) {
1831 case 0:
1832 return MISCREG_ZCR_EL1;
1833 }
1834 break;
1835 }
1836 break;
1837 case 4:
1838 switch (crm) {
1839 case 0:
1840 switch (op2) {
1841 case 0:
1842 return MISCREG_SCTLR_EL2;
1843 case 1:
1844 return MISCREG_ACTLR_EL2;
1845 }
1846 break;
1847 case 1:
1848 switch (op2) {
1849 case 0:
1850 return MISCREG_HCR_EL2;
1851 case 1:
1852 return MISCREG_MDCR_EL2;
1853 case 2:
1854 return MISCREG_CPTR_EL2;
1855 case 3:
1856 return MISCREG_HSTR_EL2;
1857 case 7:
1858 return MISCREG_HACR_EL2;
1859 }
1860 break;
1861 case 2:
1862 switch (op2) {
1863 case 0:
1864 return MISCREG_ZCR_EL2;
1865 }
1866 break;
1867 }
1868 break;
1869 case 5:
1870 switch (crm) {
1871 case 2:
1872 switch (op2) {
1873 case 0:
1874 return MISCREG_ZCR_EL12;
1875 }
1876 break;
1877 }
1878 break;
1879 case 6:
1880 switch (crm) {
1881 case 0:
1882 switch (op2) {
1883 case 0:
1884 return MISCREG_SCTLR_EL3;
1885 case 1:
1886 return MISCREG_ACTLR_EL3;
1887 }
1888 break;
1889 case 1:
1890 switch (op2) {
1891 case 0:
1892 return MISCREG_SCR_EL3;
1893 case 1:
1894 return MISCREG_SDER32_EL3;
1895 case 2:
1896 return MISCREG_CPTR_EL3;
1897 }
1898 break;
1899 case 2:
1900 switch (op2) {
1901 case 0:
1902 return MISCREG_ZCR_EL3;
1903 }
1904 break;
1905 case 3:
1906 switch (op2) {
1907 case 1:
1908 return MISCREG_MDCR_EL3;
1909 }
1910 break;
1911 }
1912 break;
1913 }
1914 break;
1915 case 2:
1916 switch (op1) {
1917 case 0:
1918 switch (crm) {
1919 case 0:
1920 switch (op2) {
1921 case 0:
1922 return MISCREG_TTBR0_EL1;
1923 case 1:
1924 return MISCREG_TTBR1_EL1;
1925 case 2:
1926 return MISCREG_TCR_EL1;
1927 }
1928 break;
1929 }
1930 break;
1931 case 4:
1932 switch (crm) {
1933 case 0:
1934 switch (op2) {
1935 case 0:
1936 return MISCREG_TTBR0_EL2;
1937 case 1:
1938 return MISCREG_TTBR1_EL2;
1939 case 2:
1940 return MISCREG_TCR_EL2;
1941 }
1942 break;
1943 case 1:
1944 switch (op2) {
1945 case 0:
1946 return MISCREG_VTTBR_EL2;
1947 case 2:
1948 return MISCREG_VTCR_EL2;
1949 }
1950 break;
1951 }
1952 break;
1953 case 6:
1954 switch (crm) {
1955 case 0:
1956 switch (op2) {
1957 case 0:
1958 return MISCREG_TTBR0_EL3;
1959 case 2:
1960 return MISCREG_TCR_EL3;
1961 }
1962 break;
1963 }
1964 break;
1965 }
1966 break;
1967 case 3:
1968 switch (op1) {
1969 case 4:
1970 switch (crm) {
1971 case 0:
1972 switch (op2) {
1973 case 0:
1974 return MISCREG_DACR32_EL2;
1975 }
1976 break;
1977 }
1978 break;
1979 }
1980 break;
1981 case 4:
1982 switch (op1) {
1983 case 0:
1984 switch (crm) {
1985 case 0:
1986 switch (op2) {
1987 case 0:
1988 return MISCREG_SPSR_EL1;
1989 case 1:
1990 return MISCREG_ELR_EL1;
1991 }
1992 break;
1993 case 1:
1994 switch (op2) {
1995 case 0:
1996 return MISCREG_SP_EL0;
1997 }
1998 break;
1999 case 2:
2000 switch (op2) {
2001 case 0:
2002 return MISCREG_SPSEL;
2003 case 2:
2004 return MISCREG_CURRENTEL;
2005 case 3:
2006 return MISCREG_PAN;
2007 }
2008 break;
2009 case 6:
2010 switch (op2) {
2011 case 0:
2012 return MISCREG_ICC_PMR_EL1;
2013 }
2014 break;
2015 }
2016 break;
2017 case 3:
2018 switch (crm) {
2019 case 2:
2020 switch (op2) {
2021 case 0:
2022 return MISCREG_NZCV;
2023 case 1:
2024 return MISCREG_DAIF;
2025 }
2026 break;
2027 case 4:
2028 switch (op2) {
2029 case 0:
2030 return MISCREG_FPCR;
2031 case 1:
2032 return MISCREG_FPSR;
2033 }
2034 break;
2035 case 5:
2036 switch (op2) {
2037 case 0:
2038 return MISCREG_DSPSR_EL0;
2039 case 1:
2040 return MISCREG_DLR_EL0;
2041 }
2042 break;
2043 }
2044 break;
2045 case 4:
2046 switch (crm) {
2047 case 0:
2048 switch (op2) {
2049 case 0:
2050 return MISCREG_SPSR_EL2;
2051 case 1:
2052 return MISCREG_ELR_EL2;
2053 }
2054 break;
2055 case 1:
2056 switch (op2) {
2057 case 0:
2058 return MISCREG_SP_EL1;
2059 }
2060 break;
2061 case 3:
2062 switch (op2) {
2063 case 0:
2064 return MISCREG_SPSR_IRQ_AA64;
2065 case 1:
2066 return MISCREG_SPSR_ABT_AA64;
2067 case 2:
2068 return MISCREG_SPSR_UND_AA64;
2069 case 3:
2070 return MISCREG_SPSR_FIQ_AA64;
2071 }
2072 break;
2073 }
2074 break;
2075 case 6:
2076 switch (crm) {
2077 case 0:
2078 switch (op2) {
2079 case 0:
2080 return MISCREG_SPSR_EL3;
2081 case 1:
2082 return MISCREG_ELR_EL3;
2083 }
2084 break;
2085 case 1:
2086 switch (op2) {
2087 case 0:
2088 return MISCREG_SP_EL2;
2089 }
2090 break;
2091 }
2092 break;
2093 }
2094 break;
2095 case 5:
2096 switch (op1) {
2097 case 0:
2098 switch (crm) {
2099 case 1:
2100 switch (op2) {
2101 case 0:
2102 return MISCREG_AFSR0_EL1;
2103 case 1:
2104 return MISCREG_AFSR1_EL1;
2105 }
2106 break;
2107 case 2:
2108 switch (op2) {
2109 case 0:
2110 return MISCREG_ESR_EL1;
2111 }
2112 break;
2113 case 3:
2114 switch (op2) {
2115 case 0:
2116 return MISCREG_ERRIDR_EL1;
2117 case 1:
2118 return MISCREG_ERRSELR_EL1;
2119 }
2120 break;
2121 case 4:
2122 switch (op2) {
2123 case 0:
2124 return MISCREG_ERXFR_EL1;
2125 case 1:
2126 return MISCREG_ERXCTLR_EL1;
2127 case 2:
2128 return MISCREG_ERXSTATUS_EL1;
2129 case 3:
2130 return MISCREG_ERXADDR_EL1;
2131 }
2132 break;
2133 case 5:
2134 switch (op2) {
2135 case 0:
2136 return MISCREG_ERXMISC0_EL1;
2137 case 1:
2138 return MISCREG_ERXMISC1_EL1;
2139 }
2140 break;
2141 }
2142 break;
2143 case 4:
2144 switch (crm) {
2145 case 0:
2146 switch (op2) {
2147 case 1:
2148 return MISCREG_IFSR32_EL2;
2149 }
2150 break;
2151 case 1:
2152 switch (op2) {
2153 case 0:
2154 return MISCREG_AFSR0_EL2;
2155 case 1:
2156 return MISCREG_AFSR1_EL2;
2157 }
2158 break;
2159 case 2:
2160 switch (op2) {
2161 case 0:
2162 return MISCREG_ESR_EL2;
2163 case 3:
2164 return MISCREG_VSESR_EL2;
2165 }
2166 break;
2167 case 3:
2168 switch (op2) {
2169 case 0:
2170 return MISCREG_FPEXC32_EL2;
2171 }
2172 break;
2173 }
2174 break;
2175 case 6:
2176 switch (crm) {
2177 case 1:
2178 switch (op2) {
2179 case 0:
2180 return MISCREG_AFSR0_EL3;
2181 case 1:
2182 return MISCREG_AFSR1_EL3;
2183 }
2184 break;
2185 case 2:
2186 switch (op2) {
2187 case 0:
2188 return MISCREG_ESR_EL3;
2189 }
2190 break;
2191 }
2192 break;
2193 }
2194 break;
2195 case 6:
2196 switch (op1) {
2197 case 0:
2198 switch (crm) {
2199 case 0:
2200 switch (op2) {
2201 case 0:
2202 return MISCREG_FAR_EL1;
2203 }
2204 break;
2205 }
2206 break;
2207 case 4:
2208 switch (crm) {
2209 case 0:
2210 switch (op2) {
2211 case 0:
2212 return MISCREG_FAR_EL2;
2213 case 4:
2214 return MISCREG_HPFAR_EL2;
2215 }
2216 break;
2217 }
2218 break;
2219 case 6:
2220 switch (crm) {
2221 case 0:
2222 switch (op2) {
2223 case 0:
2224 return MISCREG_FAR_EL3;
2225 }
2226 break;
2227 }
2228 break;
2229 }
2230 break;
2231 case 7:
2232 switch (op1) {
2233 case 0:
2234 switch (crm) {
2235 case 4:
2236 switch (op2) {
2237 case 0:
2238 return MISCREG_PAR_EL1;
2239 }
2240 break;
2241 }
2242 break;
2243 }
2244 break;
2245 case 9:
2246 switch (op1) {
2247 case 0:
2248 switch (crm) {
2249 case 14:
2250 switch (op2) {
2251 case 1:
2252 return MISCREG_PMINTENSET_EL1;
2253 case 2:
2254 return MISCREG_PMINTENCLR_EL1;
2255 }
2256 break;
2257 }
2258 break;
2259 case 3:
2260 switch (crm) {
2261 case 12:
2262 switch (op2) {
2263 case 0:
2264 return MISCREG_PMCR_EL0;
2265 case 1:
2266 return MISCREG_PMCNTENSET_EL0;
2267 case 2:
2268 return MISCREG_PMCNTENCLR_EL0;
2269 case 3:
2270 return MISCREG_PMOVSCLR_EL0;
2271 case 4:
2272 return MISCREG_PMSWINC_EL0;
2273 case 5:
2274 return MISCREG_PMSELR_EL0;
2275 case 6:
2276 return MISCREG_PMCEID0_EL0;
2277 case 7:
2278 return MISCREG_PMCEID1_EL0;
2279 }
2280 break;
2281 case 13:
2282 switch (op2) {
2283 case 0:
2284 return MISCREG_PMCCNTR_EL0;
2285 case 1:
2286 return MISCREG_PMXEVTYPER_EL0;
2287 case 2:
2288 return MISCREG_PMXEVCNTR_EL0;
2289 }
2290 break;
2291 case 14:
2292 switch (op2) {
2293 case 0:
2294 return MISCREG_PMUSERENR_EL0;
2295 case 3:
2296 return MISCREG_PMOVSSET_EL0;
2297 }
2298 break;
2299 }
2300 break;
2301 }
2302 break;
2303 case 10:
2304 switch (op1) {
2305 case 0:
2306 switch (crm) {
2307 case 2:
2308 switch (op2) {
2309 case 0:
2310 return MISCREG_MAIR_EL1;
2311 }
2312 break;
2313 case 3:
2314 switch (op2) {
2315 case 0:
2316 return MISCREG_AMAIR_EL1;
2317 }
2318 break;
2319 }
2320 break;
2321 case 4:
2322 switch (crm) {
2323 case 2:
2324 switch (op2) {
2325 case 0:
2326 return MISCREG_MAIR_EL2;
2327 }
2328 break;
2329 case 3:
2330 switch (op2) {
2331 case 0:
2332 return MISCREG_AMAIR_EL2;
2333 }
2334 break;
2335 }
2336 break;
2337 case 6:
2338 switch (crm) {
2339 case 2:
2340 switch (op2) {
2341 case 0:
2342 return MISCREG_MAIR_EL3;
2343 }
2344 break;
2345 case 3:
2346 switch (op2) {
2347 case 0:
2348 return MISCREG_AMAIR_EL3;
2349 }
2350 break;
2351 }
2352 break;
2353 }
2354 break;
2355 case 11:
2356 switch (op1) {
2357 case 1:
2358 switch (crm) {
2359 case 0:
2360 switch (op2) {
2361 case 2:
2362 return MISCREG_L2CTLR_EL1;
2363 case 3:
2364 return MISCREG_L2ECTLR_EL1;
2365 }
2366 break;
2367 }
2368 M5_FALLTHROUGH;
2369 default:
2370 // S3_<op1>_11_<Cm>_<op2>
2371 return MISCREG_IMPDEF_UNIMPL;
2372 }
2373 M5_UNREACHABLE;
2374 case 12:
2375 switch (op1) {
2376 case 0:
2377 switch (crm) {
2378 case 0:
2379 switch (op2) {
2380 case 0:
2381 return MISCREG_VBAR_EL1;
2382 case 1:
2383 return MISCREG_RVBAR_EL1;
2384 }
2385 break;
2386 case 1:
2387 switch (op2) {
2388 case 0:
2389 return MISCREG_ISR_EL1;
2390 case 1:
2391 return MISCREG_DISR_EL1;
2392 }
2393 break;
2394 case 8:
2395 switch (op2) {
2396 case 0:
2397 return MISCREG_ICC_IAR0_EL1;
2398 case 1:
2399 return MISCREG_ICC_EOIR0_EL1;
2400 case 2:
2401 return MISCREG_ICC_HPPIR0_EL1;
2402 case 3:
2403 return MISCREG_ICC_BPR0_EL1;
2404 case 4:
2405 return MISCREG_ICC_AP0R0_EL1;
2406 case 5:
2407 return MISCREG_ICC_AP0R1_EL1;
2408 case 6:
2409 return MISCREG_ICC_AP0R2_EL1;
2410 case 7:
2411 return MISCREG_ICC_AP0R3_EL1;
2412 }
2413 break;
2414 case 9:
2415 switch (op2) {
2416 case 0:
2417 return MISCREG_ICC_AP1R0_EL1;
2418 case 1:
2419 return MISCREG_ICC_AP1R1_EL1;
2420 case 2:
2421 return MISCREG_ICC_AP1R2_EL1;
2422 case 3:
2423 return MISCREG_ICC_AP1R3_EL1;
2424 }
2425 break;
2426 case 11:
2427 switch (op2) {
2428 case 1:
2429 return MISCREG_ICC_DIR_EL1;
2430 case 3:
2431 return MISCREG_ICC_RPR_EL1;
2432 case 5:
2433 return MISCREG_ICC_SGI1R_EL1;
2434 case 6:
2435 return MISCREG_ICC_ASGI1R_EL1;
2436 case 7:
2437 return MISCREG_ICC_SGI0R_EL1;
2438 }
2439 break;
2440 case 12:
2441 switch (op2) {
2442 case 0:
2443 return MISCREG_ICC_IAR1_EL1;
2444 case 1:
2445 return MISCREG_ICC_EOIR1_EL1;
2446 case 2:
2447 return MISCREG_ICC_HPPIR1_EL1;
2448 case 3:
2449 return MISCREG_ICC_BPR1_EL1;
2450 case 4:
2451 return MISCREG_ICC_CTLR_EL1;
2452 case 5:
2453 return MISCREG_ICC_SRE_EL1;
2454 case 6:
2455 return MISCREG_ICC_IGRPEN0_EL1;
2456 case 7:
2457 return MISCREG_ICC_IGRPEN1_EL1;
2458 }
2459 break;
2460 }
2461 break;
2462 case 4:
2463 switch (crm) {
2464 case 0:
2465 switch (op2) {
2466 case 0:
2467 return MISCREG_VBAR_EL2;
2468 case 1:
2469 return MISCREG_RVBAR_EL2;
2470 }
2471 break;
2472 case 1:
2473 switch (op2) {
2474 case 1:
2475 return MISCREG_VDISR_EL2;
2476 }
2477 break;
2478 case 8:
2479 switch (op2) {
2480 case 0:
2481 return MISCREG_ICH_AP0R0_EL2;
2482 case 1:
2483 return MISCREG_ICH_AP0R1_EL2;
2484 case 2:
2485 return MISCREG_ICH_AP0R2_EL2;
2486 case 3:
2487 return MISCREG_ICH_AP0R3_EL2;
2488 }
2489 break;
2490 case 9:
2491 switch (op2) {
2492 case 0:
2493 return MISCREG_ICH_AP1R0_EL2;
2494 case 1:
2495 return MISCREG_ICH_AP1R1_EL2;
2496 case 2:
2497 return MISCREG_ICH_AP1R2_EL2;
2498 case 3:
2499 return MISCREG_ICH_AP1R3_EL2;
2500 case 5:
2501 return MISCREG_ICC_SRE_EL2;
2502 }
2503 break;
2504 case 11:
2505 switch (op2) {
2506 case 0:
2507 return MISCREG_ICH_HCR_EL2;
2508 case 1:
2509 return MISCREG_ICH_VTR_EL2;
2510 case 2:
2511 return MISCREG_ICH_MISR_EL2;
2512 case 3:
2513 return MISCREG_ICH_EISR_EL2;
2514 case 5:
2515 return MISCREG_ICH_ELRSR_EL2;
2516 case 7:
2517 return MISCREG_ICH_VMCR_EL2;
2518 }
2519 break;
2520 case 12:
2521 switch (op2) {
2522 case 0:
2523 return MISCREG_ICH_LR0_EL2;
2524 case 1:
2525 return MISCREG_ICH_LR1_EL2;
2526 case 2:
2527 return MISCREG_ICH_LR2_EL2;
2528 case 3:
2529 return MISCREG_ICH_LR3_EL2;
2530 case 4:
2531 return MISCREG_ICH_LR4_EL2;
2532 case 5:
2533 return MISCREG_ICH_LR5_EL2;
2534 case 6:
2535 return MISCREG_ICH_LR6_EL2;
2536 case 7:
2537 return MISCREG_ICH_LR7_EL2;
2538 }
2539 break;
2540 case 13:
2541 switch (op2) {
2542 case 0:
2543 return MISCREG_ICH_LR8_EL2;
2544 case 1:
2545 return MISCREG_ICH_LR9_EL2;
2546 case 2:
2547 return MISCREG_ICH_LR10_EL2;
2548 case 3:
2549 return MISCREG_ICH_LR11_EL2;
2550 case 4:
2551 return MISCREG_ICH_LR12_EL2;
2552 case 5:
2553 return MISCREG_ICH_LR13_EL2;
2554 case 6:
2555 return MISCREG_ICH_LR14_EL2;
2556 case 7:
2557 return MISCREG_ICH_LR15_EL2;
2558 }
2559 break;
2560 }
2561 break;
2562 case 6:
2563 switch (crm) {
2564 case 0:
2565 switch (op2) {
2566 case 0:
2567 return MISCREG_VBAR_EL3;
2568 case 1:
2569 return MISCREG_RVBAR_EL3;
2570 case 2:
2571 return MISCREG_RMR_EL3;
2572 }
2573 break;
2574 case 12:
2575 switch (op2) {
2576 case 4:
2577 return MISCREG_ICC_CTLR_EL3;
2578 case 5:
2579 return MISCREG_ICC_SRE_EL3;
2580 case 7:
2581 return MISCREG_ICC_IGRPEN1_EL3;
2582 }
2583 break;
2584 }
2585 break;
2586 }
2587 break;
2588 case 13:
2589 switch (op1) {
2590 case 0:
2591 switch (crm) {
2592 case 0:
2593 switch (op2) {
2594 case 1:
2595 return MISCREG_CONTEXTIDR_EL1;
2596 case 4:
2597 return MISCREG_TPIDR_EL1;
2598 }
2599 break;
2600 }
2601 break;
2602 case 3:
2603 switch (crm) {
2604 case 0:
2605 switch (op2) {
2606 case 2:
2607 return MISCREG_TPIDR_EL0;
2608 case 3:
2609 return MISCREG_TPIDRRO_EL0;
2610 }
2611 break;
2612 }
2613 break;
2614 case 4:
2615 switch (crm) {
2616 case 0:
2617 switch (op2) {
2618 case 1:
2619 return MISCREG_CONTEXTIDR_EL2;
2620 case 2:
2621 return MISCREG_TPIDR_EL2;
2622 }
2623 break;
2624 }
2625 break;
2626 case 6:
2627 switch (crm) {
2628 case 0:
2629 switch (op2) {
2630 case 2:
2631 return MISCREG_TPIDR_EL3;
2632 }
2633 break;
2634 }
2635 break;
2636 }
2637 break;
2638 case 14:
2639 switch (op1) {
2640 case 0:
2641 switch (crm) {
2642 case 1:
2643 switch (op2) {
2644 case 0:
2645 return MISCREG_CNTKCTL_EL1;
2646 }
2647 break;
2648 }
2649 break;
2650 case 3:
2651 switch (crm) {
2652 case 0:
2653 switch (op2) {
2654 case 0:
2655 return MISCREG_CNTFRQ_EL0;
2656 case 1:
2657 return MISCREG_CNTPCT_EL0;
2658 case 2:
2659 return MISCREG_CNTVCT_EL0;
2660 }
2661 break;
2662 case 2:
2663 switch (op2) {
2664 case 0:
2665 return MISCREG_CNTP_TVAL_EL0;
2666 case 1:
2667 return MISCREG_CNTP_CTL_EL0;
2668 case 2:
2669 return MISCREG_CNTP_CVAL_EL0;
2670 }
2671 break;
2672 case 3:
2673 switch (op2) {
2674 case 0:
2675 return MISCREG_CNTV_TVAL_EL0;
2676 case 1:
2677 return MISCREG_CNTV_CTL_EL0;
2678 case 2:
2679 return MISCREG_CNTV_CVAL_EL0;
2680 }
2681 break;
2682 case 8:
2683 switch (op2) {
2684 case 0:
2685 return MISCREG_PMEVCNTR0_EL0;
2686 case 1:
2687 return MISCREG_PMEVCNTR1_EL0;
2688 case 2:
2689 return MISCREG_PMEVCNTR2_EL0;
2690 case 3:
2691 return MISCREG_PMEVCNTR3_EL0;
2692 case 4:
2693 return MISCREG_PMEVCNTR4_EL0;
2694 case 5:
2695 return MISCREG_PMEVCNTR5_EL0;
2696 }
2697 break;
2698 case 12:
2699 switch (op2) {
2700 case 0:
2701 return MISCREG_PMEVTYPER0_EL0;
2702 case 1:
2703 return MISCREG_PMEVTYPER1_EL0;
2704 case 2:
2705 return MISCREG_PMEVTYPER2_EL0;
2706 case 3:
2707 return MISCREG_PMEVTYPER3_EL0;
2708 case 4:
2709 return MISCREG_PMEVTYPER4_EL0;
2710 case 5:
2711 return MISCREG_PMEVTYPER5_EL0;
2712 }
2713 break;
2714 case 15:
2715 switch (op2) {
2716 case 7:
2717 return MISCREG_PMCCFILTR_EL0;
2718 }
2719 }
2720 break;
2721 case 4:
2722 switch (crm) {
2723 case 0:
2724 switch (op2) {
2725 case 3:
2726 return MISCREG_CNTVOFF_EL2;
2727 }
2728 break;
2729 case 1:
2730 switch (op2) {
2731 case 0:
2732 return MISCREG_CNTHCTL_EL2;
2733 }
2734 break;
2735 case 2:
2736 switch (op2) {
2737 case 0:
2738 return MISCREG_CNTHP_TVAL_EL2;
2739 case 1:
2740 return MISCREG_CNTHP_CTL_EL2;
2741 case 2:
2742 return MISCREG_CNTHP_CVAL_EL2;
2743 }
2744 break;
2745 case 3:
2746 switch (op2) {
2747 case 0:
2748 return MISCREG_CNTHV_TVAL_EL2;
2749 case 1:
2750 return MISCREG_CNTHV_CTL_EL2;
2751 case 2:
2752 return MISCREG_CNTHV_CVAL_EL2;
2753 }
2754 break;
2755 }
2756 break;
2757 case 7:
2758 switch (crm) {
2759 case 2:
2760 switch (op2) {
2761 case 0:
2762 return MISCREG_CNTPS_TVAL_EL1;
2763 case 1:
2764 return MISCREG_CNTPS_CTL_EL1;
2765 case 2:
2766 return MISCREG_CNTPS_CVAL_EL1;
2767 }
2768 break;
2769 }
2770 break;
2771 }
2772 break;
2773 case 15:
2774 switch (op1) {
2775 case 0:
2776 switch (crm) {
2777 case 0:
2778 switch (op2) {
2779 case 0:
2780 return MISCREG_IL1DATA0_EL1;
2781 case 1:
2782 return MISCREG_IL1DATA1_EL1;
2783 case 2:
2784 return MISCREG_IL1DATA2_EL1;
2785 case 3:
2786 return MISCREG_IL1DATA3_EL1;
2787 }
2788 break;
2789 case 1:
2790 switch (op2) {
2791 case 0:
2792 return MISCREG_DL1DATA0_EL1;
2793 case 1:
2794 return MISCREG_DL1DATA1_EL1;
2795 case 2:
2796 return MISCREG_DL1DATA2_EL1;
2797 case 3:
2798 return MISCREG_DL1DATA3_EL1;
2799 case 4:
2800 return MISCREG_DL1DATA4_EL1;
2801 }
2802 break;
2803 }
2804 break;
2805 case 1:
2806 switch (crm) {
2807 case 0:
2808 switch (op2) {
2809 case 0:
2810 return MISCREG_L2ACTLR_EL1;
2811 }
2812 break;
2813 case 2:
2814 switch (op2) {
2815 case 0:
2816 return MISCREG_CPUACTLR_EL1;
2817 case 1:
2818 return MISCREG_CPUECTLR_EL1;
2819 case 2:
2820 return MISCREG_CPUMERRSR_EL1;
2821 case 3:
2822 return MISCREG_L2MERRSR_EL1;
2823 }
2824 break;
2825 case 3:
2826 switch (op2) {
2827 case 0:
2828 return MISCREG_CBAR_EL1;
2829
2830 }
2831 break;
2832 }
2833 break;
2834 }
2835 // S3_<op1>_15_<Cm>_<op2>
2836 return MISCREG_IMPDEF_UNIMPL;
2837 }
2838 break;
2839 }
2840
2841 return MISCREG_UNKNOWN;
2842}
2843
2844bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2845
2846void
2847ISA::initializeMiscRegMetadata()
2848{
2849 // the MiscReg metadata tables are shared across all instances of the
2850 // ISA object, so there's no need to initialize them multiple times.
2851 static bool completed = false;
2852 if (completed)
2853 return;
2854
2855 // This boolean variable specifies if the system is running in aarch32 at
2856 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2857 // is running in aarch64 (aarch32EL3 = false)
2858 bool aarch32EL3 = haveSecurity && !highestELIs64;
2859
2860 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2861 // unsupported
2862 bool SPAN = false;
2863
2864 // Implicit error synchronization event enable (Arm 8.2+), unsupported
2865 bool IESB = false;
2866
2867 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2868 // unsupported
2869 bool LSMAOE = false;
2870
2871 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2872 bool nTLSMD = false;
2873
2874 // Pointer authentication (Arm 8.3+), unsupported
2875 bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2876 bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2877 bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2878 bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2879
2880 /**
2881 * Some registers alias with others, and therefore need to be translated.
2882 * When two mapping registers are given, they are the 32b lower and
2883 * upper halves, respectively, of the 64b register being mapped.
2884 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2885 *
2886 * NAM = "not architecturally mandated",
2887 * from ARM DDI 0487A.i, template text
2888 * "AArch64 System register ___ can be mapped to
2889 * AArch32 System register ___, but this is not
2890 * architecturally mandated."
2891 */
2892
2893 InitReg(MISCREG_CPSR)
2894 .allPrivileges();
2895 InitReg(MISCREG_SPSR)
2896 .allPrivileges();
2897 InitReg(MISCREG_SPSR_FIQ)
2898 .allPrivileges();
2899 InitReg(MISCREG_SPSR_IRQ)
2900 .allPrivileges();
2901 InitReg(MISCREG_SPSR_SVC)
2902 .allPrivileges();
2903 InitReg(MISCREG_SPSR_MON)
2904 .allPrivileges();
2905 InitReg(MISCREG_SPSR_ABT)
2906 .allPrivileges();
2907 InitReg(MISCREG_SPSR_HYP)
2908 .allPrivileges();
2909 InitReg(MISCREG_SPSR_UND)
2910 .allPrivileges();
2911 InitReg(MISCREG_ELR_HYP)
2912 .allPrivileges();
2913 InitReg(MISCREG_FPSID)
2914 .allPrivileges();
2915 InitReg(MISCREG_FPSCR)
2916 .allPrivileges();
2917 InitReg(MISCREG_MVFR1)
2918 .allPrivileges();
2919 InitReg(MISCREG_MVFR0)
2920 .allPrivileges();
2921 InitReg(MISCREG_FPEXC)
2922 .allPrivileges();
2923
2924 // Helper registers
2925 InitReg(MISCREG_CPSR_MODE)
2926 .allPrivileges();
2927 InitReg(MISCREG_CPSR_Q)
2928 .allPrivileges();
2929 InitReg(MISCREG_FPSCR_EXC)
2930 .allPrivileges();
2931 InitReg(MISCREG_FPSCR_QC)
2932 .allPrivileges();
2933 InitReg(MISCREG_LOCKADDR)
2934 .allPrivileges();
2935 InitReg(MISCREG_LOCKFLAG)
2936 .allPrivileges();
2937 InitReg(MISCREG_PRRR_MAIR0)
2938 .mutex()
2939 .banked();
2940 InitReg(MISCREG_PRRR_MAIR0_NS)
2941 .mutex()
2942 .privSecure(!aarch32EL3)
2943 .bankedChild();
2944 InitReg(MISCREG_PRRR_MAIR0_S)
2945 .mutex()
2946 .bankedChild();
2947 InitReg(MISCREG_NMRR_MAIR1)
2948 .mutex()
2949 .banked();
2950 InitReg(MISCREG_NMRR_MAIR1_NS)
2951 .mutex()
2952 .privSecure(!aarch32EL3)
2953 .bankedChild();
2954 InitReg(MISCREG_NMRR_MAIR1_S)
2955 .mutex()
2956 .bankedChild();
2957 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2958 .mutex();
2959 InitReg(MISCREG_SCTLR_RST)
2960 .allPrivileges();
2961 InitReg(MISCREG_SEV_MAILBOX)
2962 .allPrivileges();
2963
2964 // AArch32 CP14 registers
2965 InitReg(MISCREG_DBGDIDR)
2966 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2967 InitReg(MISCREG_DBGDSCRint)
2968 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2969 InitReg(MISCREG_DBGDCCINT)
2970 .unimplemented()
2971 .allPrivileges();
2972 InitReg(MISCREG_DBGDTRTXint)
2973 .unimplemented()
2974 .allPrivileges();
2975 InitReg(MISCREG_DBGDTRRXint)
2976 .unimplemented()
2977 .allPrivileges();
2978 InitReg(MISCREG_DBGWFAR)
2979 .unimplemented()
2980 .allPrivileges();
2981 InitReg(MISCREG_DBGVCR)
2982 .unimplemented()
2983 .allPrivileges();
2984 InitReg(MISCREG_DBGDTRRXext)
2985 .unimplemented()
2986 .allPrivileges();
2987 InitReg(MISCREG_DBGDSCRext)
2988 .unimplemented()
2989 .warnNotFail()
2990 .allPrivileges();
2991 InitReg(MISCREG_DBGDTRTXext)
2992 .unimplemented()
2993 .allPrivileges();
2994 InitReg(MISCREG_DBGOSECCR)
2995 .unimplemented()
2996 .allPrivileges();
2997 InitReg(MISCREG_DBGBVR0)
2998 .unimplemented()
2999 .allPrivileges();
3000 InitReg(MISCREG_DBGBVR1)
3001 .unimplemented()
3002 .allPrivileges();
3003 InitReg(MISCREG_DBGBVR2)
3004 .unimplemented()
3005 .allPrivileges();
3006 InitReg(MISCREG_DBGBVR3)
3007 .unimplemented()
3008 .allPrivileges();
3009 InitReg(MISCREG_DBGBVR4)
3010 .unimplemented()
3011 .allPrivileges();
3012 InitReg(MISCREG_DBGBVR5)
3013 .unimplemented()
3014 .allPrivileges();
3015 InitReg(MISCREG_DBGBCR0)
3016 .unimplemented()
3017 .allPrivileges();
3018 InitReg(MISCREG_DBGBCR1)
3019 .unimplemented()
3020 .allPrivileges();
3021 InitReg(MISCREG_DBGBCR2)
3022 .unimplemented()
3023 .allPrivileges();
3024 InitReg(MISCREG_DBGBCR3)
3025 .unimplemented()
3026 .allPrivileges();
3027 InitReg(MISCREG_DBGBCR4)
3028 .unimplemented()
3029 .allPrivileges();
3030 InitReg(MISCREG_DBGBCR5)
3031 .unimplemented()
3032 .allPrivileges();
3033 InitReg(MISCREG_DBGWVR0)
3034 .unimplemented()
3035 .allPrivileges();
3036 InitReg(MISCREG_DBGWVR1)
3037 .unimplemented()
3038 .allPrivileges();
3039 InitReg(MISCREG_DBGWVR2)
3040 .unimplemented()
3041 .allPrivileges();
3042 InitReg(MISCREG_DBGWVR3)
3043 .unimplemented()
3044 .allPrivileges();
3045 InitReg(MISCREG_DBGWCR0)
3046 .unimplemented()
3047 .allPrivileges();
3048 InitReg(MISCREG_DBGWCR1)
3049 .unimplemented()
3050 .allPrivileges();
3051 InitReg(MISCREG_DBGWCR2)
3052 .unimplemented()
3053 .allPrivileges();
3054 InitReg(MISCREG_DBGWCR3)
3055 .unimplemented()
3056 .allPrivileges();
3057 InitReg(MISCREG_DBGDRAR)
3058 .unimplemented()
3059 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3060 InitReg(MISCREG_DBGBXVR4)
3061 .unimplemented()
3062 .allPrivileges();
3063 InitReg(MISCREG_DBGBXVR5)
3064 .unimplemented()
3065 .allPrivileges();
3066 InitReg(MISCREG_DBGOSLAR)
3067 .unimplemented()
3068 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3069 InitReg(MISCREG_DBGOSLSR)
3070 .unimplemented()
3071 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3072 InitReg(MISCREG_DBGOSDLR)
3073 .unimplemented()
3074 .allPrivileges();
3075 InitReg(MISCREG_DBGPRCR)
3076 .unimplemented()
3077 .allPrivileges();
3078 InitReg(MISCREG_DBGDSAR)
3079 .unimplemented()
3080 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3081 InitReg(MISCREG_DBGCLAIMSET)
3082 .unimplemented()
3083 .allPrivileges();
3084 InitReg(MISCREG_DBGCLAIMCLR)
3085 .unimplemented()
3086 .allPrivileges();
3087 InitReg(MISCREG_DBGAUTHSTATUS)
3088 .unimplemented()
3089 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3090 InitReg(MISCREG_DBGDEVID2)
3091 .unimplemented()
3092 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3093 InitReg(MISCREG_DBGDEVID1)
3094 .unimplemented()
3095 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3096 InitReg(MISCREG_DBGDEVID0)
3097 .unimplemented()
3098 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3099 InitReg(MISCREG_TEECR)
3100 .unimplemented()
3101 .allPrivileges();
3102 InitReg(MISCREG_JIDR)
3103 .allPrivileges();
3104 InitReg(MISCREG_TEEHBR)
3105 .allPrivileges();
3106 InitReg(MISCREG_JOSCR)
3107 .allPrivileges();
3108 InitReg(MISCREG_JMCR)
3109 .allPrivileges();
3110
3111 // AArch32 CP15 registers
3112 InitReg(MISCREG_MIDR)
3113 .allPrivileges().exceptUserMode().writes(0);
3114 InitReg(MISCREG_CTR)
3115 .allPrivileges().exceptUserMode().writes(0);
3116 InitReg(MISCREG_TCMTR)
3117 .allPrivileges().exceptUserMode().writes(0);
3118 InitReg(MISCREG_TLBTR)
3119 .allPrivileges().exceptUserMode().writes(0);
3120 InitReg(MISCREG_MPIDR)
3121 .allPrivileges().exceptUserMode().writes(0);
3122 InitReg(MISCREG_REVIDR)
3123 .unimplemented()
3124 .warnNotFail()
3125 .allPrivileges().exceptUserMode().writes(0);
3126 InitReg(MISCREG_ID_PFR0)
3127 .allPrivileges().exceptUserMode().writes(0);
3128 InitReg(MISCREG_ID_PFR1)
3129 .allPrivileges().exceptUserMode().writes(0);
3130 InitReg(MISCREG_ID_DFR0)
3131 .allPrivileges().exceptUserMode().writes(0);
3132 InitReg(MISCREG_ID_AFR0)
3133 .allPrivileges().exceptUserMode().writes(0);
3134 InitReg(MISCREG_ID_MMFR0)
3135 .allPrivileges().exceptUserMode().writes(0);
3136 InitReg(MISCREG_ID_MMFR1)
3137 .allPrivileges().exceptUserMode().writes(0);
3138 InitReg(MISCREG_ID_MMFR2)
3139 .allPrivileges().exceptUserMode().writes(0);
3140 InitReg(MISCREG_ID_MMFR3)
3141 .allPrivileges().exceptUserMode().writes(0);
3142 InitReg(MISCREG_ID_ISAR0)
3143 .allPrivileges().exceptUserMode().writes(0);
3144 InitReg(MISCREG_ID_ISAR1)
3145 .allPrivileges().exceptUserMode().writes(0);
3146 InitReg(MISCREG_ID_ISAR2)
3147 .allPrivileges().exceptUserMode().writes(0);
3148 InitReg(MISCREG_ID_ISAR3)
3149 .allPrivileges().exceptUserMode().writes(0);
3150 InitReg(MISCREG_ID_ISAR4)
3151 .allPrivileges().exceptUserMode().writes(0);
3152 InitReg(MISCREG_ID_ISAR5)
3153 .allPrivileges().exceptUserMode().writes(0);
3154 InitReg(MISCREG_CCSIDR)
3155 .allPrivileges().exceptUserMode().writes(0);
3156 InitReg(MISCREG_CLIDR)
3157 .allPrivileges().exceptUserMode().writes(0);
3158 InitReg(MISCREG_AIDR)
3159 .allPrivileges().exceptUserMode().writes(0);
3160 InitReg(MISCREG_CSSELR)
3161 .banked();
3162 InitReg(MISCREG_CSSELR_NS)
3163 .bankedChild()
3164 .privSecure(!aarch32EL3)
3165 .nonSecure().exceptUserMode();
3166 InitReg(MISCREG_CSSELR_S)
3167 .bankedChild()
3168 .secure().exceptUserMode();
3169 InitReg(MISCREG_VPIDR)
3170 .hyp().monNonSecure();
3171 InitReg(MISCREG_VMPIDR)
3172 .hyp().monNonSecure();
3173 InitReg(MISCREG_SCTLR)
3174 .banked()
3175 // readMiscRegNoEffect() uses this metadata
3176 // despite using children (below) as backing store
3177 .res0(0x8d22c600)
3178 .res1(0x00400800 | (SPAN ? 0 : 0x800000)
3179 | (LSMAOE ? 0 : 0x10)
3180 | (nTLSMD ? 0 : 0x8));
3181 InitReg(MISCREG_SCTLR_NS)
3182 .bankedChild()
3183 .privSecure(!aarch32EL3)
3184 .nonSecure().exceptUserMode();
3185 InitReg(MISCREG_SCTLR_S)
3186 .bankedChild()
3187 .secure().exceptUserMode();
3188 InitReg(MISCREG_ACTLR)
3189 .banked();
3190 InitReg(MISCREG_ACTLR_NS)
3191 .bankedChild()
3192 .privSecure(!aarch32EL3)
3193 .nonSecure().exceptUserMode();
3194 InitReg(MISCREG_ACTLR_S)
3195 .bankedChild()
3196 .secure().exceptUserMode();
3197 InitReg(MISCREG_CPACR)
3198 .allPrivileges().exceptUserMode();
3199 InitReg(MISCREG_SCR)
3200 .mon().secure().exceptUserMode()
3201 .res0(0xff40) // [31:16], [6]
3202 .res1(0x0030); // [5:4]
3203 InitReg(MISCREG_SDER)
3204 .mon();
3205 InitReg(MISCREG_NSACR)
3206 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3207 InitReg(MISCREG_HSCTLR)
3208 .hyp().monNonSecure()
3209 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3210 | (IESB ? 0 : 0x200000)
3211 | (EnDA ? 0 : 0x8000000)
3212 | (EnIB ? 0 : 0x40000000)
3213 | (EnIA ? 0 : 0x80000000))
3214 .res1(0x30c50830);
3215 InitReg(MISCREG_HACTLR)
3216 .hyp().monNonSecure();
3217 InitReg(MISCREG_HCR)
3218 .hyp().monNonSecure();
3219 InitReg(MISCREG_HDCR)
3220 .hyp().monNonSecure();
3221 InitReg(MISCREG_HCPTR)
3222 .hyp().monNonSecure();
3223 InitReg(MISCREG_HSTR)
3224 .hyp().monNonSecure();
3225 InitReg(MISCREG_HACR)
3226 .unimplemented()
3227 .warnNotFail()
3228 .hyp().monNonSecure();
3229 InitReg(MISCREG_TTBR0)
3230 .banked();
3231 InitReg(MISCREG_TTBR0_NS)
3232 .bankedChild()
3233 .privSecure(!aarch32EL3)
3234 .nonSecure().exceptUserMode();
3235 InitReg(MISCREG_TTBR0_S)
3236 .bankedChild()
3237 .secure().exceptUserMode();
3238 InitReg(MISCREG_TTBR1)
3239 .banked();
3240 InitReg(MISCREG_TTBR1_NS)
3241 .bankedChild()
3242 .privSecure(!aarch32EL3)
3243 .nonSecure().exceptUserMode();
3244 InitReg(MISCREG_TTBR1_S)
3245 .bankedChild()
3246 .secure().exceptUserMode();
3247 InitReg(MISCREG_TTBCR)
3248 .banked();
3249 InitReg(MISCREG_TTBCR_NS)
3250 .bankedChild()
3251 .privSecure(!aarch32EL3)
3252 .nonSecure().exceptUserMode();
3253 InitReg(MISCREG_TTBCR_S)
3254 .bankedChild()
3255 .secure().exceptUserMode();
3256 InitReg(MISCREG_HTCR)
3257 .hyp().monNonSecure();
3258 InitReg(MISCREG_VTCR)
3259 .hyp().monNonSecure();
3260 InitReg(MISCREG_DACR)
3261 .banked();
3262 InitReg(MISCREG_DACR_NS)
3263 .bankedChild()
3264 .privSecure(!aarch32EL3)
3265 .nonSecure().exceptUserMode();
3266 InitReg(MISCREG_DACR_S)
3267 .bankedChild()
3268 .secure().exceptUserMode();
3269 InitReg(MISCREG_DFSR)
3270 .banked();
3271 InitReg(MISCREG_DFSR_NS)
3272 .bankedChild()
3273 .privSecure(!aarch32EL3)
3274 .nonSecure().exceptUserMode();
3275 InitReg(MISCREG_DFSR_S)
3276 .bankedChild()
3277 .secure().exceptUserMode();
3278 InitReg(MISCREG_IFSR)
3279 .banked();
3280 InitReg(MISCREG_IFSR_NS)
3281 .bankedChild()
3282 .privSecure(!aarch32EL3)
3283 .nonSecure().exceptUserMode();
3284 InitReg(MISCREG_IFSR_S)
3285 .bankedChild()
3286 .secure().exceptUserMode();
3287 InitReg(MISCREG_ADFSR)
3288 .unimplemented()
3289 .warnNotFail()
3290 .banked();
3291 InitReg(MISCREG_ADFSR_NS)
3292 .unimplemented()
3293 .warnNotFail()
3294 .bankedChild()
3295 .privSecure(!aarch32EL3)
3296 .nonSecure().exceptUserMode();
3297 InitReg(MISCREG_ADFSR_S)
3298 .unimplemented()
3299 .warnNotFail()
3300 .bankedChild()
3301 .secure().exceptUserMode();
3302 InitReg(MISCREG_AIFSR)
3303 .unimplemented()
3304 .warnNotFail()
3305 .banked();
3306 InitReg(MISCREG_AIFSR_NS)
3307 .unimplemented()
3308 .warnNotFail()
3309 .bankedChild()
3310 .privSecure(!aarch32EL3)
3311 .nonSecure().exceptUserMode();
3312 InitReg(MISCREG_AIFSR_S)
3313 .unimplemented()
3314 .warnNotFail()
3315 .bankedChild()
3316 .secure().exceptUserMode();
3317 InitReg(MISCREG_HADFSR)
3318 .hyp().monNonSecure();
3319 InitReg(MISCREG_HAIFSR)
3320 .hyp().monNonSecure();
3321 InitReg(MISCREG_HSR)
3322 .hyp().monNonSecure();
3323 InitReg(MISCREG_DFAR)
3324 .banked();
3325 InitReg(MISCREG_DFAR_NS)
3326 .bankedChild()
3327 .privSecure(!aarch32EL3)
3328 .nonSecure().exceptUserMode();
3329 InitReg(MISCREG_DFAR_S)
3330 .bankedChild()
3331 .secure().exceptUserMode();
3332 InitReg(MISCREG_IFAR)
3333 .banked();
3334 InitReg(MISCREG_IFAR_NS)
3335 .bankedChild()
3336 .privSecure(!aarch32EL3)
3337 .nonSecure().exceptUserMode();
3338 InitReg(MISCREG_IFAR_S)
3339 .bankedChild()
3340 .secure().exceptUserMode();
3341 InitReg(MISCREG_HDFAR)
3342 .hyp().monNonSecure();
3343 InitReg(MISCREG_HIFAR)
3344 .hyp().monNonSecure();
3345 InitReg(MISCREG_HPFAR)
3346 .hyp().monNonSecure();
3347 InitReg(MISCREG_ICIALLUIS)
3348 .unimplemented()
3349 .warnNotFail()
3350 .writes(1).exceptUserMode();
3351 InitReg(MISCREG_BPIALLIS)
3352 .unimplemented()
3353 .warnNotFail()
3354 .writes(1).exceptUserMode();
3355 InitReg(MISCREG_PAR)
3356 .banked();
3357 InitReg(MISCREG_PAR_NS)
3358 .bankedChild()
3359 .privSecure(!aarch32EL3)
3360 .nonSecure().exceptUserMode();
3361 InitReg(MISCREG_PAR_S)
3362 .bankedChild()
3363 .secure().exceptUserMode();
3364 InitReg(MISCREG_ICIALLU)
3365 .writes(1).exceptUserMode();
3366 InitReg(MISCREG_ICIMVAU)
3367 .unimplemented()
3368 .warnNotFail()
3369 .writes(1).exceptUserMode();
3370 InitReg(MISCREG_CP15ISB)
3371 .writes(1);
3372 InitReg(MISCREG_BPIALL)
3373 .unimplemented()
3374 .warnNotFail()
3375 .writes(1).exceptUserMode();
3376 InitReg(MISCREG_BPIMVA)
3377 .unimplemented()
3378 .warnNotFail()
3379 .writes(1).exceptUserMode();
3380 InitReg(MISCREG_DCIMVAC)
3381 .unimplemented()
3382 .warnNotFail()
3383 .writes(1).exceptUserMode();
3384 InitReg(MISCREG_DCISW)
3385 .unimplemented()
3386 .warnNotFail()
3387 .writes(1).exceptUserMode();
3388 InitReg(MISCREG_ATS1CPR)
3389 .writes(1).exceptUserMode();
3390 InitReg(MISCREG_ATS1CPW)
3391 .writes(1).exceptUserMode();
3392 InitReg(MISCREG_ATS1CUR)
3393 .writes(1).exceptUserMode();
3394 InitReg(MISCREG_ATS1CUW)
3395 .writes(1).exceptUserMode();
3396 InitReg(MISCREG_ATS12NSOPR)
3397 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3398 InitReg(MISCREG_ATS12NSOPW)
3399 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3400 InitReg(MISCREG_ATS12NSOUR)
3401 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3402 InitReg(MISCREG_ATS12NSOUW)
3403 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3404 InitReg(MISCREG_DCCMVAC)
3405 .writes(1).exceptUserMode();
3406 InitReg(MISCREG_DCCSW)
3407 .unimplemented()
3408 .warnNotFail()
3409 .writes(1).exceptUserMode();
3410 InitReg(MISCREG_CP15DSB)
3411 .writes(1);
3412 InitReg(MISCREG_CP15DMB)
3413 .writes(1);
3414 InitReg(MISCREG_DCCMVAU)
3415 .unimplemented()
3416 .warnNotFail()
3417 .writes(1).exceptUserMode();
3418 InitReg(MISCREG_DCCIMVAC)
3419 .unimplemented()
3420 .warnNotFail()
3421 .writes(1).exceptUserMode();
3422 InitReg(MISCREG_DCCISW)
3423 .unimplemented()
3424 .warnNotFail()
3425 .writes(1).exceptUserMode();
3426 InitReg(MISCREG_ATS1HR)
3427 .monNonSecureWrite().hypWrite();
3428 InitReg(MISCREG_ATS1HW)
3429 .monNonSecureWrite().hypWrite();
3430 InitReg(MISCREG_TLBIALLIS)
3431 .writes(1).exceptUserMode();
3432 InitReg(MISCREG_TLBIMVAIS)
3433 .writes(1).exceptUserMode();
3434 InitReg(MISCREG_TLBIASIDIS)
3435 .writes(1).exceptUserMode();
3436 InitReg(MISCREG_TLBIMVAAIS)
3437 .writes(1).exceptUserMode();
3438 InitReg(MISCREG_TLBIMVALIS)
3439 .writes(1).exceptUserMode();
3440 InitReg(MISCREG_TLBIMVAALIS)
3441 .writes(1).exceptUserMode();
3442 InitReg(MISCREG_ITLBIALL)
3443 .writes(1).exceptUserMode();
3444 InitReg(MISCREG_ITLBIMVA)
3445 .writes(1).exceptUserMode();
3446 InitReg(MISCREG_ITLBIASID)
3447 .writes(1).exceptUserMode();
3448 InitReg(MISCREG_DTLBIALL)
3449 .writes(1).exceptUserMode();
3450 InitReg(MISCREG_DTLBIMVA)
3451 .writes(1).exceptUserMode();
3452 InitReg(MISCREG_DTLBIASID)
3453 .writes(1).exceptUserMode();
3454 InitReg(MISCREG_TLBIALL)
3455 .writes(1).exceptUserMode();
3456 InitReg(MISCREG_TLBIMVA)
3457 .writes(1).exceptUserMode();
3458 InitReg(MISCREG_TLBIASID)
3459 .writes(1).exceptUserMode();
3460 InitReg(MISCREG_TLBIMVAA)
3461 .writes(1).exceptUserMode();
3462 InitReg(MISCREG_TLBIMVAL)
3463 .writes(1).exceptUserMode();
3464 InitReg(MISCREG_TLBIMVAAL)
3465 .writes(1).exceptUserMode();
3466 InitReg(MISCREG_TLBIIPAS2IS)
3467 .monNonSecureWrite().hypWrite();
3468 InitReg(MISCREG_TLBIIPAS2LIS)
3469 .monNonSecureWrite().hypWrite();
3470 InitReg(MISCREG_TLBIALLHIS)
3471 .monNonSecureWrite().hypWrite();
3472 InitReg(MISCREG_TLBIMVAHIS)
3473 .monNonSecureWrite().hypWrite();
3474 InitReg(MISCREG_TLBIALLNSNHIS)
3475 .monNonSecureWrite().hypWrite();
3476 InitReg(MISCREG_TLBIMVALHIS)
3477 .monNonSecureWrite().hypWrite();
3478 InitReg(MISCREG_TLBIIPAS2)
3479 .monNonSecureWrite().hypWrite();
3480 InitReg(MISCREG_TLBIIPAS2L)
3481 .monNonSecureWrite().hypWrite();
3482 InitReg(MISCREG_TLBIALLH)
3483 .monNonSecureWrite().hypWrite();
3484 InitReg(MISCREG_TLBIMVAH)
3485 .monNonSecureWrite().hypWrite();
3486 InitReg(MISCREG_TLBIALLNSNH)
3487 .monNonSecureWrite().hypWrite();
3488 InitReg(MISCREG_TLBIMVALH)
3489 .monNonSecureWrite().hypWrite();
3490 InitReg(MISCREG_PMCR)
3491 .allPrivileges();
3492 InitReg(MISCREG_PMCNTENSET)
3493 .allPrivileges();
3494 InitReg(MISCREG_PMCNTENCLR)
3495 .allPrivileges();
3496 InitReg(MISCREG_PMOVSR)
3497 .allPrivileges();
3498 InitReg(MISCREG_PMSWINC)
3499 .allPrivileges();
3500 InitReg(MISCREG_PMSELR)
3501 .allPrivileges();
3502 InitReg(MISCREG_PMCEID0)
3503 .allPrivileges();
3504 InitReg(MISCREG_PMCEID1)
3505 .allPrivileges();
3506 InitReg(MISCREG_PMCCNTR)
3507 .allPrivileges();
3508 InitReg(MISCREG_PMXEVTYPER)
3509 .allPrivileges();
3510 InitReg(MISCREG_PMCCFILTR)
3511 .allPrivileges();
3512 InitReg(MISCREG_PMXEVCNTR)
3513 .allPrivileges();
3514 InitReg(MISCREG_PMUSERENR)
3515 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3516 InitReg(MISCREG_PMINTENSET)
3517 .allPrivileges().exceptUserMode();
3518 InitReg(MISCREG_PMINTENCLR)
3519 .allPrivileges().exceptUserMode();
3520 InitReg(MISCREG_PMOVSSET)
3521 .unimplemented()
3522 .allPrivileges();
3523 InitReg(MISCREG_L2CTLR)
3524 .allPrivileges().exceptUserMode();
3525 InitReg(MISCREG_L2ECTLR)
3526 .unimplemented()
3527 .allPrivileges().exceptUserMode();
3528 InitReg(MISCREG_PRRR)
3529 .banked();
3530 InitReg(MISCREG_PRRR_NS)
3531 .bankedChild()
3532 .privSecure(!aarch32EL3)
3533 .nonSecure().exceptUserMode();
3534 InitReg(MISCREG_PRRR_S)
3535 .bankedChild()
3536 .secure().exceptUserMode();
3537 InitReg(MISCREG_MAIR0)
3538 .banked();
3539 InitReg(MISCREG_MAIR0_NS)
3540 .bankedChild()
3541 .privSecure(!aarch32EL3)
3542 .nonSecure().exceptUserMode();
3543 InitReg(MISCREG_MAIR0_S)
3544 .bankedChild()
3545 .secure().exceptUserMode();
3546 InitReg(MISCREG_NMRR)
3547 .banked();
3548 InitReg(MISCREG_NMRR_NS)
3549 .bankedChild()
3550 .privSecure(!aarch32EL3)
3551 .nonSecure().exceptUserMode();
3552 InitReg(MISCREG_NMRR_S)
3553 .bankedChild()
3554 .secure().exceptUserMode();
3555 InitReg(MISCREG_MAIR1)
3556 .banked();
3557 InitReg(MISCREG_MAIR1_NS)
3558 .bankedChild()
3559 .privSecure(!aarch32EL3)
3560 .nonSecure().exceptUserMode();
3561 InitReg(MISCREG_MAIR1_S)
3562 .bankedChild()
3563 .secure().exceptUserMode();
3564 InitReg(MISCREG_AMAIR0)
3565 .banked();
3566 InitReg(MISCREG_AMAIR0_NS)
3567 .bankedChild()
3568 .privSecure(!aarch32EL3)
3569 .nonSecure().exceptUserMode();
3570 InitReg(MISCREG_AMAIR0_S)
3571 .bankedChild()
3572 .secure().exceptUserMode();
3573 InitReg(MISCREG_AMAIR1)
3574 .banked();
3575 InitReg(MISCREG_AMAIR1_NS)
3576 .bankedChild()
3577 .privSecure(!aarch32EL3)
3578 .nonSecure().exceptUserMode();
3579 InitReg(MISCREG_AMAIR1_S)
3580 .bankedChild()
3581 .secure().exceptUserMode();
3582 InitReg(MISCREG_HMAIR0)
3583 .hyp().monNonSecure();
3584 InitReg(MISCREG_HMAIR1)
3585 .hyp().monNonSecure();
3586 InitReg(MISCREG_HAMAIR0)
3587 .unimplemented()
3588 .warnNotFail()
3589 .hyp().monNonSecure();
3590 InitReg(MISCREG_HAMAIR1)
3591 .unimplemented()
3592 .warnNotFail()
3593 .hyp().monNonSecure();
3594 InitReg(MISCREG_VBAR)
3595 .banked();
3596 InitReg(MISCREG_VBAR_NS)
3597 .bankedChild()
3598 .privSecure(!aarch32EL3)
3599 .nonSecure().exceptUserMode();
3600 InitReg(MISCREG_VBAR_S)
3601 .bankedChild()
3602 .secure().exceptUserMode();
3603 InitReg(MISCREG_MVBAR)
3604 .mon().secure()
3605 .hypRead(FullSystem && system->highestEL() == EL2)
3606 .privRead(FullSystem && system->highestEL() == EL1)
3607 .exceptUserMode();
3608 InitReg(MISCREG_RMR)
3609 .unimplemented()
3610 .mon().secure().exceptUserMode();
3611 InitReg(MISCREG_ISR)
3612 .allPrivileges().exceptUserMode().writes(0);
3613 InitReg(MISCREG_HVBAR)
3614 .hyp().monNonSecure()
3615 .res0(0x1f);
3616 InitReg(MISCREG_FCSEIDR)
3617 .unimplemented()
3618 .warnNotFail()
3619 .allPrivileges().exceptUserMode();
3620 InitReg(MISCREG_CONTEXTIDR)
3621 .banked();
3622 InitReg(MISCREG_CONTEXTIDR_NS)
3623 .bankedChild()
3624 .privSecure(!aarch32EL3)
3625 .nonSecure().exceptUserMode();
3626 InitReg(MISCREG_CONTEXTIDR_S)
3627 .bankedChild()
3628 .secure().exceptUserMode();
3629 InitReg(MISCREG_TPIDRURW)
3630 .banked();
3631 InitReg(MISCREG_TPIDRURW_NS)
3632 .bankedChild()
3633 .allPrivileges()
3634 .privSecure(!aarch32EL3)
3635 .monSecure(0);
3636 InitReg(MISCREG_TPIDRURW_S)
3637 .bankedChild()
3638 .secure();
3639 InitReg(MISCREG_TPIDRURO)
3640 .banked();
3641 InitReg(MISCREG_TPIDRURO_NS)
3642 .bankedChild()
3643 .allPrivileges()
3644 .userNonSecureWrite(0).userSecureRead(1)
3645 .privSecure(!aarch32EL3)
3646 .monSecure(0);
3647 InitReg(MISCREG_TPIDRURO_S)
3648 .bankedChild()
3649 .secure().userSecureWrite(0);
3650 InitReg(MISCREG_TPIDRPRW)
3651 .banked();
3652 InitReg(MISCREG_TPIDRPRW_NS)
3653 .bankedChild()
3654 .nonSecure().exceptUserMode()
3655 .privSecure(!aarch32EL3);
3656 InitReg(MISCREG_TPIDRPRW_S)
3657 .bankedChild()
3658 .secure().exceptUserMode();
3659 InitReg(MISCREG_HTPIDR)
3660 .hyp().monNonSecure();
3661 InitReg(MISCREG_CNTFRQ)
3662 .unverifiable()
3663 .reads(1).mon();
3664 InitReg(MISCREG_CNTKCTL)
3665 .allPrivileges().exceptUserMode();
3666 InitReg(MISCREG_CNTP_TVAL)
3667 .banked();
3668 InitReg(MISCREG_CNTP_TVAL_NS)
3669 .bankedChild()
3670 .allPrivileges()
3671 .privSecure(!aarch32EL3)
3672 .monSecure(0);
3673 InitReg(MISCREG_CNTP_TVAL_S)
3674 .bankedChild()
3675 .secure().user(1);
3676 InitReg(MISCREG_CNTP_CTL)
3677 .banked();
3678 InitReg(MISCREG_CNTP_CTL_NS)
3679 .bankedChild()
3680 .allPrivileges()
3681 .privSecure(!aarch32EL3)
3682 .monSecure(0);
3683 InitReg(MISCREG_CNTP_CTL_S)
3684 .bankedChild()
3685 .secure().user(1);
3686 InitReg(MISCREG_CNTV_TVAL)
3687 .allPrivileges();
3688 InitReg(MISCREG_CNTV_CTL)
3689 .allPrivileges();
3690 InitReg(MISCREG_CNTHCTL)
3691 .hypWrite().monNonSecureRead();
3692 InitReg(MISCREG_CNTHP_TVAL)
3693 .hypWrite().monNonSecureRead();
3694 InitReg(MISCREG_CNTHP_CTL)
3695 .hypWrite().monNonSecureRead();
3696 InitReg(MISCREG_IL1DATA0)
3697 .unimplemented()
3698 .allPrivileges().exceptUserMode();
3699 InitReg(MISCREG_IL1DATA1)
3700 .unimplemented()
3701 .allPrivileges().exceptUserMode();
3702 InitReg(MISCREG_IL1DATA2)
3703 .unimplemented()
3704 .allPrivileges().exceptUserMode();
3705 InitReg(MISCREG_IL1DATA3)
3706 .unimplemented()
3707 .allPrivileges().exceptUserMode();
3708 InitReg(MISCREG_DL1DATA0)
3709 .unimplemented()
3710 .allPrivileges().exceptUserMode();
3711 InitReg(MISCREG_DL1DATA1)
3712 .unimplemented()
3713 .allPrivileges().exceptUserMode();
3714 InitReg(MISCREG_DL1DATA2)
3715 .unimplemented()
3716 .allPrivileges().exceptUserMode();
3717 InitReg(MISCREG_DL1DATA3)
3718 .unimplemented()
3719 .allPrivileges().exceptUserMode();
3720 InitReg(MISCREG_DL1DATA4)
3721 .unimplemented()
3722 .allPrivileges().exceptUserMode();
3723 InitReg(MISCREG_RAMINDEX)
3724 .unimplemented()
3725 .writes(1).exceptUserMode();
3726 InitReg(MISCREG_L2ACTLR)
3727 .unimplemented()
3728 .allPrivileges().exceptUserMode();
3729 InitReg(MISCREG_CBAR)
3730 .unimplemented()
3731 .allPrivileges().exceptUserMode().writes(0);
3732 InitReg(MISCREG_HTTBR)
3733 .hyp().monNonSecure();
3734 InitReg(MISCREG_VTTBR)
3735 .hyp().monNonSecure();
3736 InitReg(MISCREG_CNTPCT)
3737 .reads(1);
3738 InitReg(MISCREG_CNTVCT)
3739 .unverifiable()
3740 .reads(1);
3741 InitReg(MISCREG_CNTP_CVAL)
3742 .banked();
3743 InitReg(MISCREG_CNTP_CVAL_NS)
3744 .bankedChild()
3745 .allPrivileges()
3746 .privSecure(!aarch32EL3)
3747 .monSecure(0);
3748 InitReg(MISCREG_CNTP_CVAL_S)
3749 .bankedChild()
3750 .secure().user(1);
3751 InitReg(MISCREG_CNTV_CVAL)
3752 .allPrivileges();
3753 InitReg(MISCREG_CNTVOFF)
3754 .hyp().monNonSecure();
3755 InitReg(MISCREG_CNTHP_CVAL)
3756 .hypWrite().monNonSecureRead();
3757 InitReg(MISCREG_CPUMERRSR)
3758 .unimplemented()
3759 .allPrivileges().exceptUserMode();
3760 InitReg(MISCREG_L2MERRSR)
3761 .unimplemented()
3762 .warnNotFail()
3763 .allPrivileges().exceptUserMode();
3764
3765 // AArch64 registers (Op0=2);
3766 InitReg(MISCREG_MDCCINT_EL1)
3767 .allPrivileges();
3768 InitReg(MISCREG_OSDTRRX_EL1)
3769 .allPrivileges()
3770 .mapsTo(MISCREG_DBGDTRRXext);
3771 InitReg(MISCREG_MDSCR_EL1)
3772 .allPrivileges()
3773 .mapsTo(MISCREG_DBGDSCRext);
3774 InitReg(MISCREG_OSDTRTX_EL1)
3775 .allPrivileges()
3776 .mapsTo(MISCREG_DBGDTRTXext);
3777 InitReg(MISCREG_OSECCR_EL1)
3778 .allPrivileges()
3779 .mapsTo(MISCREG_DBGOSECCR);
3780 InitReg(MISCREG_DBGBVR0_EL1)
3781 .allPrivileges()
3782 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3783 InitReg(MISCREG_DBGBVR1_EL1)
3784 .allPrivileges()
3785 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3786 InitReg(MISCREG_DBGBVR2_EL1)
3787 .allPrivileges()
3788 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3789 InitReg(MISCREG_DBGBVR3_EL1)
3790 .allPrivileges()
3791 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3792 InitReg(MISCREG_DBGBVR4_EL1)
3793 .allPrivileges()
3794 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3795 InitReg(MISCREG_DBGBVR5_EL1)
3796 .allPrivileges()
3797 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3798 InitReg(MISCREG_DBGBCR0_EL1)
3799 .allPrivileges()
3800 .mapsTo(MISCREG_DBGBCR0);
3801 InitReg(MISCREG_DBGBCR1_EL1)
3802 .allPrivileges()
3803 .mapsTo(MISCREG_DBGBCR1);
3804 InitReg(MISCREG_DBGBCR2_EL1)
3805 .allPrivileges()
3806 .mapsTo(MISCREG_DBGBCR2);
3807 InitReg(MISCREG_DBGBCR3_EL1)
3808 .allPrivileges()
3809 .mapsTo(MISCREG_DBGBCR3);
3810 InitReg(MISCREG_DBGBCR4_EL1)
3811 .allPrivileges()
3812 .mapsTo(MISCREG_DBGBCR4);
3813 InitReg(MISCREG_DBGBCR5_EL1)
3814 .allPrivileges()
3815 .mapsTo(MISCREG_DBGBCR5);
3816 InitReg(MISCREG_DBGWVR0_EL1)
3817 .allPrivileges()
3818 .mapsTo(MISCREG_DBGWVR0);
3819 InitReg(MISCREG_DBGWVR1_EL1)
3820 .allPrivileges()
3821 .mapsTo(MISCREG_DBGWVR1);
3822 InitReg(MISCREG_DBGWVR2_EL1)
3823 .allPrivileges()
3824 .mapsTo(MISCREG_DBGWVR2);
3825 InitReg(MISCREG_DBGWVR3_EL1)
3826 .allPrivileges()
3827 .mapsTo(MISCREG_DBGWVR3);
3828 InitReg(MISCREG_DBGWCR0_EL1)
3829 .allPrivileges()
3830 .mapsTo(MISCREG_DBGWCR0);
3831 InitReg(MISCREG_DBGWCR1_EL1)
3832 .allPrivileges()
3833 .mapsTo(MISCREG_DBGWCR1);
3834 InitReg(MISCREG_DBGWCR2_EL1)
3835 .allPrivileges()
3836 .mapsTo(MISCREG_DBGWCR2);
3837 InitReg(MISCREG_DBGWCR3_EL1)
3838 .allPrivileges()
3839 .mapsTo(MISCREG_DBGWCR3);
3840 InitReg(MISCREG_MDCCSR_EL0)
3841 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3842 .mapsTo(MISCREG_DBGDSCRint);
3843 InitReg(MISCREG_MDDTR_EL0)
3844 .allPrivileges();
3845 InitReg(MISCREG_MDDTRTX_EL0)
3846 .allPrivileges();
3847 InitReg(MISCREG_MDDTRRX_EL0)
3848 .allPrivileges();
3849 InitReg(MISCREG_DBGVCR32_EL2)
3850 .allPrivileges()
3851 .mapsTo(MISCREG_DBGVCR);
3852 InitReg(MISCREG_MDRAR_EL1)
3853 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3854 .mapsTo(MISCREG_DBGDRAR);
3855 InitReg(MISCREG_OSLAR_EL1)
3856 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3857 .mapsTo(MISCREG_DBGOSLAR);
3858 InitReg(MISCREG_OSLSR_EL1)
3859 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3860 .mapsTo(MISCREG_DBGOSLSR);
3861 InitReg(MISCREG_OSDLR_EL1)
3862 .allPrivileges()
3863 .mapsTo(MISCREG_DBGOSDLR);
3864 InitReg(MISCREG_DBGPRCR_EL1)
3865 .allPrivileges()
3866 .mapsTo(MISCREG_DBGPRCR);
3867 InitReg(MISCREG_DBGCLAIMSET_EL1)
3868 .allPrivileges()
3869 .mapsTo(MISCREG_DBGCLAIMSET);
3870 InitReg(MISCREG_DBGCLAIMCLR_EL1)
3871 .allPrivileges()
3872 .mapsTo(MISCREG_DBGCLAIMCLR);
3873 InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3874 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3875 .mapsTo(MISCREG_DBGAUTHSTATUS);
3876 InitReg(MISCREG_TEECR32_EL1);
3877 InitReg(MISCREG_TEEHBR32_EL1);
3878
3879 // AArch64 registers (Op0=1,3);
3880 InitReg(MISCREG_MIDR_EL1)
3881 .allPrivileges().exceptUserMode().writes(0);
3882 InitReg(MISCREG_MPIDR_EL1)
3883 .allPrivileges().exceptUserMode().writes(0);
3884 InitReg(MISCREG_REVIDR_EL1)
3885 .allPrivileges().exceptUserMode().writes(0);
3886 InitReg(MISCREG_ID_PFR0_EL1)
3887 .allPrivileges().exceptUserMode().writes(0)
3888 .mapsTo(MISCREG_ID_PFR0);
3889 InitReg(MISCREG_ID_PFR1_EL1)
3890 .allPrivileges().exceptUserMode().writes(0)
3891 .mapsTo(MISCREG_ID_PFR1);
3892 InitReg(MISCREG_ID_DFR0_EL1)
3893 .allPrivileges().exceptUserMode().writes(0)
3894 .mapsTo(MISCREG_ID_DFR0);
3895 InitReg(MISCREG_ID_AFR0_EL1)
3896 .allPrivileges().exceptUserMode().writes(0)
3897 .mapsTo(MISCREG_ID_AFR0);
3898 InitReg(MISCREG_ID_MMFR0_EL1)
3899 .allPrivileges().exceptUserMode().writes(0)
3900 .mapsTo(MISCREG_ID_MMFR0);
3901 InitReg(MISCREG_ID_MMFR1_EL1)
3902 .allPrivileges().exceptUserMode().writes(0)
3903 .mapsTo(MISCREG_ID_MMFR1);
3904 InitReg(MISCREG_ID_MMFR2_EL1)
3905 .allPrivileges().exceptUserMode().writes(0)
3906 .mapsTo(MISCREG_ID_MMFR2);
3907 InitReg(MISCREG_ID_MMFR3_EL1)
3908 .allPrivileges().exceptUserMode().writes(0)
3909 .mapsTo(MISCREG_ID_MMFR3);
3910 InitReg(MISCREG_ID_ISAR0_EL1)
3911 .allPrivileges().exceptUserMode().writes(0)
3912 .mapsTo(MISCREG_ID_ISAR0);
3913 InitReg(MISCREG_ID_ISAR1_EL1)
3914 .allPrivileges().exceptUserMode().writes(0)
3915 .mapsTo(MISCREG_ID_ISAR1);
3916 InitReg(MISCREG_ID_ISAR2_EL1)
3917 .allPrivileges().exceptUserMode().writes(0)
3918 .mapsTo(MISCREG_ID_ISAR2);
3919 InitReg(MISCREG_ID_ISAR3_EL1)
3920 .allPrivileges().exceptUserMode().writes(0)
3921 .mapsTo(MISCREG_ID_ISAR3);
3922 InitReg(MISCREG_ID_ISAR4_EL1)
3923 .allPrivileges().exceptUserMode().writes(0)
3924 .mapsTo(MISCREG_ID_ISAR4);
3925 InitReg(MISCREG_ID_ISAR5_EL1)
3926 .allPrivileges().exceptUserMode().writes(0)
3927 .mapsTo(MISCREG_ID_ISAR5);
3928 InitReg(MISCREG_MVFR0_EL1)
3929 .allPrivileges().exceptUserMode().writes(0);
3930 InitReg(MISCREG_MVFR1_EL1)
3931 .allPrivileges().exceptUserMode().writes(0);
3932 InitReg(MISCREG_MVFR2_EL1)
3933 .allPrivileges().exceptUserMode().writes(0);
3934 InitReg(MISCREG_ID_AA64PFR0_EL1)
3935 .allPrivileges().exceptUserMode().writes(0);
3936 InitReg(MISCREG_ID_AA64PFR1_EL1)
3937 .allPrivileges().exceptUserMode().writes(0);
3938 InitReg(MISCREG_ID_AA64DFR0_EL1)
3939 .allPrivileges().exceptUserMode().writes(0);
3940 InitReg(MISCREG_ID_AA64DFR1_EL1)
3941 .allPrivileges().exceptUserMode().writes(0);
3942 InitReg(MISCREG_ID_AA64AFR0_EL1)
3943 .allPrivileges().exceptUserMode().writes(0);
3944 InitReg(MISCREG_ID_AA64AFR1_EL1)
3945 .allPrivileges().exceptUserMode().writes(0);
3946 InitReg(MISCREG_ID_AA64ISAR0_EL1)
3947 .allPrivileges().exceptUserMode().writes(0);
3948 InitReg(MISCREG_ID_AA64ISAR1_EL1)
3949 .allPrivileges().exceptUserMode().writes(0);
3950 InitReg(MISCREG_ID_AA64MMFR0_EL1)
3951 .allPrivileges().exceptUserMode().writes(0);
3952 InitReg(MISCREG_ID_AA64MMFR1_EL1)
3953 .allPrivileges().exceptUserMode().writes(0);
3954 InitReg(MISCREG_ID_AA64MMFR2_EL1)
3955 .allPrivileges().exceptUserMode().writes(0);
3956 InitReg(MISCREG_CCSIDR_EL1)
3957 .allPrivileges().exceptUserMode().writes(0);
3958 InitReg(MISCREG_CLIDR_EL1)
3959 .allPrivileges().exceptUserMode().writes(0);
3960 InitReg(MISCREG_AIDR_EL1)
3961 .allPrivileges().exceptUserMode().writes(0);
3962 InitReg(MISCREG_CSSELR_EL1)
3963 .allPrivileges().exceptUserMode()
3964 .mapsTo(MISCREG_CSSELR_NS);
3965 InitReg(MISCREG_CTR_EL0)
3966 .reads(1);
3967 InitReg(MISCREG_DCZID_EL0)
3968 .reads(1);
3969 InitReg(MISCREG_VPIDR_EL2)
3970 .hyp().mon()
3971 .mapsTo(MISCREG_VPIDR);
3972 InitReg(MISCREG_VMPIDR_EL2)
3973 .hyp().mon()
3974 .mapsTo(MISCREG_VMPIDR);
3975 InitReg(MISCREG_SCTLR_EL1)
3976 .allPrivileges().exceptUserMode()
3977 .res0( 0x20440 | (EnDB ? 0 : 0x2000)
3978 | (IESB ? 0 : 0x200000)
3979 | (EnDA ? 0 : 0x8000000)
3980 | (EnIB ? 0 : 0x40000000)
3981 | (EnIA ? 0 : 0x80000000))
3982 .res1(0x500800 | (SPAN ? 0 : 0x800000)
3983 | (nTLSMD ? 0 : 0x8000000)
3984 | (LSMAOE ? 0 : 0x10000000))
3985 .mapsTo(MISCREG_SCTLR_NS);
3986 InitReg(MISCREG_ACTLR_EL1)
3987 .allPrivileges().exceptUserMode()
3988 .mapsTo(MISCREG_ACTLR_NS);
3989 InitReg(MISCREG_CPACR_EL1)
3990 .allPrivileges().exceptUserMode()
3991 .mapsTo(MISCREG_CPACR);
3992 InitReg(MISCREG_SCTLR_EL2)
3993 .hyp().mon()
3994 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3995 | (IESB ? 0 : 0x200000)
3996 | (EnDA ? 0 : 0x8000000)
3997 | (EnIB ? 0 : 0x40000000)
3998 | (EnIA ? 0 : 0x80000000))
3999 .res1(0x30c50830)
4000 .mapsTo(MISCREG_HSCTLR);
4001 InitReg(MISCREG_ACTLR_EL2)
4002 .hyp().mon()
4003 .mapsTo(MISCREG_HACTLR);
4004 InitReg(MISCREG_HCR_EL2)
4005 .hyp().mon()
4006 .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
4007 InitReg(MISCREG_MDCR_EL2)
4008 .hyp().mon()
4009 .mapsTo(MISCREG_HDCR);
4010 InitReg(MISCREG_CPTR_EL2)
4011 .hyp().mon()
4012 .mapsTo(MISCREG_HCPTR);
4013 InitReg(MISCREG_HSTR_EL2)
4014 .hyp().mon()
4015 .mapsTo(MISCREG_HSTR);
4016 InitReg(MISCREG_HACR_EL2)
4017 .hyp().mon()
4018 .mapsTo(MISCREG_HACR);
4019 InitReg(MISCREG_SCTLR_EL3)
4020 .mon()
4021 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4022 | (IESB ? 0 : 0x200000)
4023 | (EnDA ? 0 : 0x8000000)
4024 | (EnIB ? 0 : 0x40000000)
4025 | (EnIA ? 0 : 0x80000000))
4026 .res1(0x30c50830);
4027 InitReg(MISCREG_ACTLR_EL3)
4028 .mon();
4029 InitReg(MISCREG_SCR_EL3)
4030 .mon()
4031 .mapsTo(MISCREG_SCR); // NAM D7-2005
4032 InitReg(MISCREG_SDER32_EL3)
4033 .mon()
4034 .mapsTo(MISCREG_SDER);
4035 InitReg(MISCREG_CPTR_EL3)
4036 .mon();
4037 InitReg(MISCREG_MDCR_EL3)
4038 .mon();
4039 InitReg(MISCREG_TTBR0_EL1)
4040 .allPrivileges().exceptUserMode()
4041 .mapsTo(MISCREG_TTBR0_NS);
4042 InitReg(MISCREG_TTBR1_EL1)
4043 .allPrivileges().exceptUserMode()
4044 .mapsTo(MISCREG_TTBR1_NS);
4045 InitReg(MISCREG_TCR_EL1)
4046 .allPrivileges().exceptUserMode()
4047 .mapsTo(MISCREG_TTBCR_NS);
4048 InitReg(MISCREG_TTBR0_EL2)
4049 .hyp().mon()
4050 .mapsTo(MISCREG_HTTBR);
4051 InitReg(MISCREG_TTBR1_EL2)
4052 .hyp().mon();
4053 InitReg(MISCREG_TCR_EL2)
4054 .hyp().mon()
4055 .mapsTo(MISCREG_HTCR);
4056 InitReg(MISCREG_VTTBR_EL2)
4057 .hyp().mon()
4058 .mapsTo(MISCREG_VTTBR);
4059 InitReg(MISCREG_VTCR_EL2)
4060 .hyp().mon()
4061 .mapsTo(MISCREG_VTCR);
4062 InitReg(MISCREG_TTBR0_EL3)
4063 .mon();
4064 InitReg(MISCREG_TCR_EL3)
4065 .mon();
4066 InitReg(MISCREG_DACR32_EL2)
4067 .hyp().mon()
4068 .mapsTo(MISCREG_DACR_NS);
4069 InitReg(MISCREG_SPSR_EL1)
4070 .allPrivileges().exceptUserMode()
4071 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
4072 InitReg(MISCREG_ELR_EL1)
4073 .allPrivileges().exceptUserMode();
4074 InitReg(MISCREG_SP_EL0)
4075 .allPrivileges().exceptUserMode();
4076 InitReg(MISCREG_SPSEL)
4077 .allPrivileges().exceptUserMode();
4078 InitReg(MISCREG_CURRENTEL)
4079 .allPrivileges().exceptUserMode().writes(0);
4080 InitReg(MISCREG_PAN)
4081 .allPrivileges().exceptUserMode()
4082 .implemented(havePAN);
4083 InitReg(MISCREG_NZCV)
4084 .allPrivileges();
4085 InitReg(MISCREG_DAIF)
4086 .allPrivileges();
4087 InitReg(MISCREG_FPCR)
4088 .allPrivileges();
4089 InitReg(MISCREG_FPSR)
4090 .allPrivileges();
4091 InitReg(MISCREG_DSPSR_EL0)
4092 .allPrivileges();
4093 InitReg(MISCREG_DLR_EL0)
4094 .allPrivileges();
4095 InitReg(MISCREG_SPSR_EL2)
4096 .hyp().mon()
4097 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
4098 InitReg(MISCREG_ELR_EL2)
4099 .hyp().mon();
4100 InitReg(MISCREG_SP_EL1)
4101 .hyp().mon();
4102 InitReg(MISCREG_SPSR_IRQ_AA64)
4103 .hyp().mon();
4104 InitReg(MISCREG_SPSR_ABT_AA64)
4105 .hyp().mon();
4106 InitReg(MISCREG_SPSR_UND_AA64)
4107 .hyp().mon();
4108 InitReg(MISCREG_SPSR_FIQ_AA64)
4109 .hyp().mon();
4110 InitReg(MISCREG_SPSR_EL3)
4111 .mon()
4112 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
4113 InitReg(MISCREG_ELR_EL3)
4114 .mon();
4115 InitReg(MISCREG_SP_EL2)
4116 .mon();
4117 InitReg(MISCREG_AFSR0_EL1)
4118 .allPrivileges().exceptUserMode()
4119 .mapsTo(MISCREG_ADFSR_NS);
4120 InitReg(MISCREG_AFSR1_EL1)
4121 .allPrivileges().exceptUserMode()
4122 .mapsTo(MISCREG_AIFSR_NS);
4123 InitReg(MISCREG_ESR_EL1)
4124 .allPrivileges().exceptUserMode();
4125 InitReg(MISCREG_IFSR32_EL2)
4126 .hyp().mon()
4127 .mapsTo(MISCREG_IFSR_NS);
4128 InitReg(MISCREG_AFSR0_EL2)
4129 .hyp().mon()
4130 .mapsTo(MISCREG_HADFSR);
4131 InitReg(MISCREG_AFSR1_EL2)
4132 .hyp().mon()
4133 .mapsTo(MISCREG_HAIFSR);
4134 InitReg(MISCREG_ESR_EL2)
4135 .hyp().mon()
4136 .mapsTo(MISCREG_HSR);
4137 InitReg(MISCREG_FPEXC32_EL2)
4138 .hyp().mon().mapsTo(MISCREG_FPEXC);
4139 InitReg(MISCREG_AFSR0_EL3)
4140 .mon();
4141 InitReg(MISCREG_AFSR1_EL3)
4142 .mon();
4143 InitReg(MISCREG_ESR_EL3)
4144 .mon();
4145 InitReg(MISCREG_FAR_EL1)
4146 .allPrivileges().exceptUserMode()
4147 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
4148 InitReg(MISCREG_FAR_EL2)
4149 .hyp().mon()
4150 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
4151 InitReg(MISCREG_HPFAR_EL2)
4152 .hyp().mon()
4153 .mapsTo(MISCREG_HPFAR);
4154 InitReg(MISCREG_FAR_EL3)
4155 .mon();
4156 InitReg(MISCREG_IC_IALLUIS)
4157 .warnNotFail()
4158 .writes(1).exceptUserMode();
4159 InitReg(MISCREG_PAR_EL1)
4160 .allPrivileges().exceptUserMode()
4161 .mapsTo(MISCREG_PAR_NS);
4162 InitReg(MISCREG_IC_IALLU)
4163 .warnNotFail()
4164 .writes(1).exceptUserMode();
4165 InitReg(MISCREG_DC_IVAC_Xt)
4166 .warnNotFail()
4167 .writes(1).exceptUserMode();
4168 InitReg(MISCREG_DC_ISW_Xt)
4169 .warnNotFail()
4170 .writes(1).exceptUserMode();
4171 InitReg(MISCREG_AT_S1E1R_Xt)
4172 .writes(1).exceptUserMode();
4173 InitReg(MISCREG_AT_S1E1W_Xt)
4174 .writes(1).exceptUserMode();
4175 InitReg(MISCREG_AT_S1E0R_Xt)
4176 .writes(1).exceptUserMode();
4177 InitReg(MISCREG_AT_S1E0W_Xt)
4178 .writes(1).exceptUserMode();
4179 InitReg(MISCREG_DC_CSW_Xt)
4180 .warnNotFail()
4181 .writes(1).exceptUserMode();
4182 InitReg(MISCREG_DC_CISW_Xt)
4183 .warnNotFail()
4184 .writes(1).exceptUserMode();
4185 InitReg(MISCREG_DC_ZVA_Xt)
4186 .warnNotFail()
4187 .writes(1).userSecureWrite(0);
4188 InitReg(MISCREG_IC_IVAU_Xt)
4189 .writes(1);
4190 InitReg(MISCREG_DC_CVAC_Xt)
4191 .warnNotFail()
4192 .writes(1);
4193 InitReg(MISCREG_DC_CVAU_Xt)
4194 .warnNotFail()
4195 .writes(1);
4196 InitReg(MISCREG_DC_CIVAC_Xt)
4197 .warnNotFail()
4198 .writes(1);
4199 InitReg(MISCREG_AT_S1E2R_Xt)
4200 .monNonSecureWrite().hypWrite();
4201 InitReg(MISCREG_AT_S1E2W_Xt)
4202 .monNonSecureWrite().hypWrite();
4203 InitReg(MISCREG_AT_S12E1R_Xt)
4204 .hypWrite().monSecureWrite().monNonSecureWrite();
4205 InitReg(MISCREG_AT_S12E1W_Xt)
4206 .hypWrite().monSecureWrite().monNonSecureWrite();
4207 InitReg(MISCREG_AT_S12E0R_Xt)
4208 .hypWrite().monSecureWrite().monNonSecureWrite();
4209 InitReg(MISCREG_AT_S12E0W_Xt)
4210 .hypWrite().monSecureWrite().monNonSecureWrite();
4211 InitReg(MISCREG_AT_S1E3R_Xt)
4212 .monSecureWrite().monNonSecureWrite();
4213 InitReg(MISCREG_AT_S1E3W_Xt)
4214 .monSecureWrite().monNonSecureWrite();
4215 InitReg(MISCREG_TLBI_VMALLE1IS)
4216 .writes(1).exceptUserMode();
4217 InitReg(MISCREG_TLBI_VAE1IS_Xt)
4218 .writes(1).exceptUserMode();
4219 InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
4220 .writes(1).exceptUserMode();
4221 InitReg(MISCREG_TLBI_VAAE1IS_Xt)
4222 .writes(1).exceptUserMode();
4223 InitReg(MISCREG_TLBI_VALE1IS_Xt)
4224 .writes(1).exceptUserMode();
4225 InitReg(MISCREG_TLBI_VAALE1IS_Xt)
4226 .writes(1).exceptUserMode();
4227 InitReg(MISCREG_TLBI_VMALLE1)
4228 .writes(1).exceptUserMode();
4229 InitReg(MISCREG_TLBI_VAE1_Xt)
4230 .writes(1).exceptUserMode();
4231 InitReg(MISCREG_TLBI_ASIDE1_Xt)
4232 .writes(1).exceptUserMode();
4233 InitReg(MISCREG_TLBI_VAAE1_Xt)
4234 .writes(1).exceptUserMode();
4235 InitReg(MISCREG_TLBI_VALE1_Xt)
4236 .writes(1).exceptUserMode();
4237 InitReg(MISCREG_TLBI_VAALE1_Xt)
4238 .writes(1).exceptUserMode();
4239 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
4240 .hypWrite().monSecureWrite().monNonSecureWrite();
4241 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
4242 .hypWrite().monSecureWrite().monNonSecureWrite();
4243 InitReg(MISCREG_TLBI_ALLE2IS)
4244 .monNonSecureWrite().hypWrite();
4245 InitReg(MISCREG_TLBI_VAE2IS_Xt)
4246 .monNonSecureWrite().hypWrite();
4247 InitReg(MISCREG_TLBI_ALLE1IS)
4248 .hypWrite().monSecureWrite().monNonSecureWrite();
4249 InitReg(MISCREG_TLBI_VALE2IS_Xt)
4250 .monNonSecureWrite().hypWrite();
4251 InitReg(MISCREG_TLBI_VMALLS12E1IS)
4252 .hypWrite().monSecureWrite().monNonSecureWrite();
4253 InitReg(MISCREG_TLBI_IPAS2E1_Xt)
4254 .hypWrite().monSecureWrite().monNonSecureWrite();
4255 InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
4256 .hypWrite().monSecureWrite().monNonSecureWrite();
4257 InitReg(MISCREG_TLBI_ALLE2)
4258 .monNonSecureWrite().hypWrite();
4259 InitReg(MISCREG_TLBI_VAE2_Xt)
4260 .monNonSecureWrite().hypWrite();
4261 InitReg(MISCREG_TLBI_ALLE1)
4262 .hypWrite().monSecureWrite().monNonSecureWrite();
4263 InitReg(MISCREG_TLBI_VALE2_Xt)
4264 .monNonSecureWrite().hypWrite();
4265 InitReg(MISCREG_TLBI_VMALLS12E1)
4266 .hypWrite().monSecureWrite().monNonSecureWrite();
4267 InitReg(MISCREG_TLBI_ALLE3IS)
4268 .monSecureWrite().monNonSecureWrite();
4269 InitReg(MISCREG_TLBI_VAE3IS_Xt)
4270 .monSecureWrite().monNonSecureWrite();
4271 InitReg(MISCREG_TLBI_VALE3IS_Xt)
4272 .monSecureWrite().monNonSecureWrite();
4273 InitReg(MISCREG_TLBI_ALLE3)
4274 .monSecureWrite().monNonSecureWrite();
4275 InitReg(MISCREG_TLBI_VAE3_Xt)
4276 .monSecureWrite().monNonSecureWrite();
4277 InitReg(MISCREG_TLBI_VALE3_Xt)
4278 .monSecureWrite().monNonSecureWrite();
4279 InitReg(MISCREG_PMINTENSET_EL1)
4280 .allPrivileges().exceptUserMode()
4281 .mapsTo(MISCREG_PMINTENSET);
4282 InitReg(MISCREG_PMINTENCLR_EL1)
4283 .allPrivileges().exceptUserMode()
4284 .mapsTo(MISCREG_PMINTENCLR);
4285 InitReg(MISCREG_PMCR_EL0)
4286 .allPrivileges()
4287 .mapsTo(MISCREG_PMCR);
4288 InitReg(MISCREG_PMCNTENSET_EL0)
4289 .allPrivileges()
4290 .mapsTo(MISCREG_PMCNTENSET);
4291 InitReg(MISCREG_PMCNTENCLR_EL0)
4292 .allPrivileges()
4293 .mapsTo(MISCREG_PMCNTENCLR);
4294 InitReg(MISCREG_PMOVSCLR_EL0)
4295 .allPrivileges();
4296// .mapsTo(MISCREG_PMOVSCLR);
4297 InitReg(MISCREG_PMSWINC_EL0)
4298 .writes(1).user()
4299 .mapsTo(MISCREG_PMSWINC);
4300 InitReg(MISCREG_PMSELR_EL0)
4301 .allPrivileges()
4302 .mapsTo(MISCREG_PMSELR);
4303 InitReg(MISCREG_PMCEID0_EL0)
4304 .reads(1).user()
4305 .mapsTo(MISCREG_PMCEID0);
4306 InitReg(MISCREG_PMCEID1_EL0)
4307 .reads(1).user()
4308 .mapsTo(MISCREG_PMCEID1);
4309 InitReg(MISCREG_PMCCNTR_EL0)
4310 .allPrivileges()
4311 .mapsTo(MISCREG_PMCCNTR);
4312 InitReg(MISCREG_PMXEVTYPER_EL0)
4313 .allPrivileges()
4314 .mapsTo(MISCREG_PMXEVTYPER);
4315 InitReg(MISCREG_PMCCFILTR_EL0)
4316 .allPrivileges();
4317 InitReg(MISCREG_PMXEVCNTR_EL0)
4318 .allPrivileges()
4319 .mapsTo(MISCREG_PMXEVCNTR);
4320 InitReg(MISCREG_PMUSERENR_EL0)
4321 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4322 .mapsTo(MISCREG_PMUSERENR);
4323 InitReg(MISCREG_PMOVSSET_EL0)
4324 .allPrivileges()
4325 .mapsTo(MISCREG_PMOVSSET);
4326 InitReg(MISCREG_MAIR_EL1)
4327 .allPrivileges().exceptUserMode()
4328 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
4329 InitReg(MISCREG_AMAIR_EL1)
4330 .allPrivileges().exceptUserMode()
4331 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
4332 InitReg(MISCREG_MAIR_EL2)
4333 .hyp().mon()
4334 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
4335 InitReg(MISCREG_AMAIR_EL2)
4336 .hyp().mon()
4337 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
4338 InitReg(MISCREG_MAIR_EL3)
4339 .mon();
4340 InitReg(MISCREG_AMAIR_EL3)
4341 .mon();
4342 InitReg(MISCREG_L2CTLR_EL1)
4343 .allPrivileges().exceptUserMode();
4344 InitReg(MISCREG_L2ECTLR_EL1)
4345 .allPrivileges().exceptUserMode();
4346 InitReg(MISCREG_VBAR_EL1)
4347 .allPrivileges().exceptUserMode()
4348 .mapsTo(MISCREG_VBAR_NS);
4349 InitReg(MISCREG_RVBAR_EL1)
4350 .allPrivileges().exceptUserMode().writes(0);
4351 InitReg(MISCREG_ISR_EL1)
4352 .allPrivileges().exceptUserMode().writes(0);
4353 InitReg(MISCREG_VBAR_EL2)
4354 .hyp().mon()
4355 .res0(0x7ff)
4356 .mapsTo(MISCREG_HVBAR);
4357 InitReg(MISCREG_RVBAR_EL2)
4358 .mon().hyp().writes(0);
4359 InitReg(MISCREG_VBAR_EL3)
4360 .mon();
4361 InitReg(MISCREG_RVBAR_EL3)
4362 .mon().writes(0);
4363 InitReg(MISCREG_RMR_EL3)
4364 .mon();
4365 InitReg(MISCREG_CONTEXTIDR_EL1)
4366 .allPrivileges().exceptUserMode()
4367 .mapsTo(MISCREG_CONTEXTIDR_NS);
4368 InitReg(MISCREG_TPIDR_EL1)
4369 .allPrivileges().exceptUserMode()
4370 .mapsTo(MISCREG_TPIDRPRW_NS);
4371 InitReg(MISCREG_TPIDR_EL0)
4372 .allPrivileges()
4373 .mapsTo(MISCREG_TPIDRURW_NS);
4374 InitReg(MISCREG_TPIDRRO_EL0)
4375 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
4376 .mapsTo(MISCREG_TPIDRURO_NS);
4377 InitReg(MISCREG_TPIDR_EL2)
4378 .hyp().mon()
4379 .mapsTo(MISCREG_HTPIDR);
4380 InitReg(MISCREG_TPIDR_EL3)
4381 .mon();
4382 InitReg(MISCREG_CNTKCTL_EL1)
4383 .allPrivileges().exceptUserMode()
4384 .mapsTo(MISCREG_CNTKCTL);
4385 InitReg(MISCREG_CNTFRQ_EL0)
4386 .reads(1).mon()
4387 .mapsTo(MISCREG_CNTFRQ);
4388 InitReg(MISCREG_CNTPCT_EL0)
4389 .reads(1)
4390 .mapsTo(MISCREG_CNTPCT); /* 64b */
4391 InitReg(MISCREG_CNTVCT_EL0)
4392 .unverifiable()
4393 .reads(1)
4394 .mapsTo(MISCREG_CNTVCT); /* 64b */
4395 InitReg(MISCREG_CNTP_TVAL_EL0)
4396 .allPrivileges()
4397 .mapsTo(MISCREG_CNTP_TVAL_NS);
4398 InitReg(MISCREG_CNTP_CTL_EL0)
4399 .allPrivileges()
4400 .mapsTo(MISCREG_CNTP_CTL_NS);
4401 InitReg(MISCREG_CNTP_CVAL_EL0)
4402 .allPrivileges()
4403 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
4404 InitReg(MISCREG_CNTV_TVAL_EL0)
4405 .allPrivileges()
4406 .mapsTo(MISCREG_CNTV_TVAL);
4407 InitReg(MISCREG_CNTV_CTL_EL0)
4408 .allPrivileges()
4409 .mapsTo(MISCREG_CNTV_CTL);
4410 InitReg(MISCREG_CNTV_CVAL_EL0)
4411 .allPrivileges()
4412 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
4413 InitReg(MISCREG_PMEVCNTR0_EL0)
4414 .allPrivileges();
4415// .mapsTo(MISCREG_PMEVCNTR0);
4416 InitReg(MISCREG_PMEVCNTR1_EL0)
4417 .allPrivileges();
4418// .mapsTo(MISCREG_PMEVCNTR1);
4419 InitReg(MISCREG_PMEVCNTR2_EL0)
4420 .allPrivileges();
4421// .mapsTo(MISCREG_PMEVCNTR2);
4422 InitReg(MISCREG_PMEVCNTR3_EL0)
4423 .allPrivileges();
4424// .mapsTo(MISCREG_PMEVCNTR3);
4425 InitReg(MISCREG_PMEVCNTR4_EL0)
4426 .allPrivileges();
4427// .mapsTo(MISCREG_PMEVCNTR4);
4428 InitReg(MISCREG_PMEVCNTR5_EL0)
4429 .allPrivileges();
4430// .mapsTo(MISCREG_PMEVCNTR5);
4431 InitReg(MISCREG_PMEVTYPER0_EL0)
4432 .allPrivileges();
4433// .mapsTo(MISCREG_PMEVTYPER0);
4434 InitReg(MISCREG_PMEVTYPER1_EL0)
4435 .allPrivileges();
4436// .mapsTo(MISCREG_PMEVTYPER1);
4437 InitReg(MISCREG_PMEVTYPER2_EL0)
4438 .allPrivileges();
4439// .mapsTo(MISCREG_PMEVTYPER2);
4440 InitReg(MISCREG_PMEVTYPER3_EL0)
4441 .allPrivileges();
4442// .mapsTo(MISCREG_PMEVTYPER3);
4443 InitReg(MISCREG_PMEVTYPER4_EL0)
4444 .allPrivileges();
4445// .mapsTo(MISCREG_PMEVTYPER4);
4446 InitReg(MISCREG_PMEVTYPER5_EL0)
4447 .allPrivileges();
4448// .mapsTo(MISCREG_PMEVTYPER5);
4449 InitReg(MISCREG_CNTVOFF_EL2)
4450 .hyp().mon()
4451 .mapsTo(MISCREG_CNTVOFF); /* 64b */
4452 InitReg(MISCREG_CNTHCTL_EL2)
4453 .mon().hyp()
4454 .mapsTo(MISCREG_CNTHCTL);
4455 InitReg(MISCREG_CNTHP_TVAL_EL2)
4456 .mon().hyp()
4457 .mapsTo(MISCREG_CNTHP_TVAL);
4458 InitReg(MISCREG_CNTHP_CTL_EL2)
4459 .mon().hyp()
4460 .mapsTo(MISCREG_CNTHP_CTL);
4461 InitReg(MISCREG_CNTHP_CVAL_EL2)
4462 .mon().hyp()
4463 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
4464 InitReg(MISCREG_CNTPS_TVAL_EL1)
4465 .mon().privSecure();
4466 InitReg(MISCREG_CNTPS_CTL_EL1)
4467 .mon().privSecure();
4468 InitReg(MISCREG_CNTPS_CVAL_EL1)
4469 .mon().privSecure();
4470 InitReg(MISCREG_IL1DATA0_EL1)
4471 .allPrivileges().exceptUserMode();
4472 InitReg(MISCREG_IL1DATA1_EL1)
4473 .allPrivileges().exceptUserMode();
4474 InitReg(MISCREG_IL1DATA2_EL1)
4475 .allPrivileges().exceptUserMode();
4476 InitReg(MISCREG_IL1DATA3_EL1)
4477 .allPrivileges().exceptUserMode();
4478 InitReg(MISCREG_DL1DATA0_EL1)
4479 .allPrivileges().exceptUserMode();
4480 InitReg(MISCREG_DL1DATA1_EL1)
4481 .allPrivileges().exceptUserMode();
4482 InitReg(MISCREG_DL1DATA2_EL1)
4483 .allPrivileges().exceptUserMode();
4484 InitReg(MISCREG_DL1DATA3_EL1)
4485 .allPrivileges().exceptUserMode();
4486 InitReg(MISCREG_DL1DATA4_EL1)
4487 .allPrivileges().exceptUserMode();
4488 InitReg(MISCREG_L2ACTLR_EL1)
4489 .allPrivileges().exceptUserMode();
4490 InitReg(MISCREG_CPUACTLR_EL1)
4491 .allPrivileges().exceptUserMode();
4492 InitReg(MISCREG_CPUECTLR_EL1)
4493 .allPrivileges().exceptUserMode();
4494 InitReg(MISCREG_CPUMERRSR_EL1)
4495 .allPrivileges().exceptUserMode();
4496 InitReg(MISCREG_L2MERRSR_EL1)
4497 .unimplemented()
4498 .warnNotFail()
4499 .allPrivileges().exceptUserMode();
4500 InitReg(MISCREG_CBAR_EL1)
4501 .allPrivileges().exceptUserMode().writes(0);
4502 InitReg(MISCREG_CONTEXTIDR_EL2)
4503 .mon().hyp();
4504
4505 // GICv3 AArch64
4506 InitReg(MISCREG_ICC_PMR_EL1)
4507 .res0(0xffffff00) // [31:8]
4508 .allPrivileges().exceptUserMode()
4509 .mapsTo(MISCREG_ICC_PMR);
4510 InitReg(MISCREG_ICC_IAR0_EL1)
4511 .allPrivileges().exceptUserMode().writes(0)
4512 .mapsTo(MISCREG_ICC_IAR0);
4513 InitReg(MISCREG_ICC_EOIR0_EL1)
4514 .allPrivileges().exceptUserMode().reads(0)
4515 .mapsTo(MISCREG_ICC_EOIR0);
4516 InitReg(MISCREG_ICC_HPPIR0_EL1)
4517 .allPrivileges().exceptUserMode().writes(0)
4518 .mapsTo(MISCREG_ICC_HPPIR0);
4519 InitReg(MISCREG_ICC_BPR0_EL1)
4520 .res0(0xfffffff8) // [31:3]
4521 .allPrivileges().exceptUserMode()
4522 .mapsTo(MISCREG_ICC_BPR0);
4523 InitReg(MISCREG_ICC_AP0R0_EL1)
4524 .allPrivileges().exceptUserMode()
4525 .mapsTo(MISCREG_ICC_AP0R0);
4526 InitReg(MISCREG_ICC_AP0R1_EL1)
4527 .allPrivileges().exceptUserMode()
4528 .mapsTo(MISCREG_ICC_AP0R1);
4529 InitReg(MISCREG_ICC_AP0R2_EL1)
4530 .allPrivileges().exceptUserMode()
4531 .mapsTo(MISCREG_ICC_AP0R2);
4532 InitReg(MISCREG_ICC_AP0R3_EL1)
4533 .allPrivileges().exceptUserMode()
4534 .mapsTo(MISCREG_ICC_AP0R3);
4535 InitReg(MISCREG_ICC_AP1R0_EL1)
4536 .banked()
4537 .mapsTo(MISCREG_ICC_AP1R0);
4538 InitReg(MISCREG_ICC_AP1R0_EL1_NS)
4539 .bankedChild()
4540 .allPrivileges().exceptUserMode()
4541 .mapsTo(MISCREG_ICC_AP1R0_NS);
4542 InitReg(MISCREG_ICC_AP1R0_EL1_S)
4543 .bankedChild()
4544 .allPrivileges().exceptUserMode()
4545 .mapsTo(MISCREG_ICC_AP1R0_S);
4546 InitReg(MISCREG_ICC_AP1R1_EL1)
4547 .banked()
4548 .mapsTo(MISCREG_ICC_AP1R1);
4549 InitReg(MISCREG_ICC_AP1R1_EL1_NS)
4550 .bankedChild()
4551 .allPrivileges().exceptUserMode()
4552 .mapsTo(MISCREG_ICC_AP1R1_NS);
4553 InitReg(MISCREG_ICC_AP1R1_EL1_S)
4554 .bankedChild()
4555 .allPrivileges().exceptUserMode()
4556 .mapsTo(MISCREG_ICC_AP1R1_S);
4557 InitReg(MISCREG_ICC_AP1R2_EL1)
4558 .banked()
4559 .mapsTo(MISCREG_ICC_AP1R2);
4560 InitReg(MISCREG_ICC_AP1R2_EL1_NS)
4561 .bankedChild()
4562 .allPrivileges().exceptUserMode()
4563 .mapsTo(MISCREG_ICC_AP1R2_NS);
4564 InitReg(MISCREG_ICC_AP1R2_EL1_S)
4565 .bankedChild()
4566 .allPrivileges().exceptUserMode()
4567 .mapsTo(MISCREG_ICC_AP1R2_S);
4568 InitReg(MISCREG_ICC_AP1R3_EL1)
4569 .banked()
4570 .mapsTo(MISCREG_ICC_AP1R3);
4571 InitReg(MISCREG_ICC_AP1R3_EL1_NS)
4572 .bankedChild()
4573 .allPrivileges().exceptUserMode()
4574 .mapsTo(MISCREG_ICC_AP1R3_NS);
4575 InitReg(MISCREG_ICC_AP1R3_EL1_S)
4576 .bankedChild()
4577 .allPrivileges().exceptUserMode()
4578 .mapsTo(MISCREG_ICC_AP1R3_S);
4579 InitReg(MISCREG_ICC_DIR_EL1)
4580 .res0(0xFF000000) // [31:24]
4581 .allPrivileges().exceptUserMode().reads(0)
4582 .mapsTo(MISCREG_ICC_DIR);
4583 InitReg(MISCREG_ICC_RPR_EL1)
4584 .allPrivileges().exceptUserMode().writes(0)
4585 .mapsTo(MISCREG_ICC_RPR);
4586 InitReg(MISCREG_ICC_SGI1R_EL1)
4587 .allPrivileges().exceptUserMode().reads(0)
4588 .mapsTo(MISCREG_ICC_SGI1R);
4589 InitReg(MISCREG_ICC_ASGI1R_EL1)
4590 .allPrivileges().exceptUserMode().reads(0)
4591 .mapsTo(MISCREG_ICC_ASGI1R);
4592 InitReg(MISCREG_ICC_SGI0R_EL1)
4593 .allPrivileges().exceptUserMode().reads(0)
4594 .mapsTo(MISCREG_ICC_SGI0R);
4595 InitReg(MISCREG_ICC_IAR1_EL1)
4596 .allPrivileges().exceptUserMode().writes(0)
4597 .mapsTo(MISCREG_ICC_IAR1);
4598 InitReg(MISCREG_ICC_EOIR1_EL1)
4599 .res0(0xFF000000) // [31:24]
4600 .allPrivileges().exceptUserMode().reads(0)
4601 .mapsTo(MISCREG_ICC_EOIR1);
4602 InitReg(MISCREG_ICC_HPPIR1_EL1)
4603 .allPrivileges().exceptUserMode().writes(0)
4604 .mapsTo(MISCREG_ICC_HPPIR1);
4605 InitReg(MISCREG_ICC_BPR1_EL1)
4606 .banked64()
4607 .mapsTo(MISCREG_ICC_BPR1);
4608 InitReg(MISCREG_ICC_BPR1_EL1_NS)
4609 .bankedChild()
4610 .res0(0xfffffff8) // [31:3]
4611 .allPrivileges().exceptUserMode()
4612 .mapsTo(MISCREG_ICC_BPR1_NS);
4613 InitReg(MISCREG_ICC_BPR1_EL1_S)
4614 .bankedChild()
4615 .res0(0xfffffff8) // [31:3]
4616 .secure().exceptUserMode()
4617 .mapsTo(MISCREG_ICC_BPR1_S);
4618 InitReg(MISCREG_ICC_CTLR_EL1)
4619 .banked()
4619 .banked64()
4620 .mapsTo(MISCREG_ICC_CTLR);
4621 InitReg(MISCREG_ICC_CTLR_EL1_NS)
4622 .bankedChild()
4623 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4624 .allPrivileges().exceptUserMode()
4625 .mapsTo(MISCREG_ICC_CTLR_NS);
4626 InitReg(MISCREG_ICC_CTLR_EL1_S)
4627 .bankedChild()
4628 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4629 .secure().exceptUserMode()
4630 .mapsTo(MISCREG_ICC_CTLR_S);
4631 InitReg(MISCREG_ICC_SRE_EL1)
4632 .banked()
4633 .mapsTo(MISCREG_ICC_SRE);
4634 InitReg(MISCREG_ICC_SRE_EL1_NS)
4635 .bankedChild()
4636 .res0(0xFFFFFFF8) // [31:3]
4637 .allPrivileges().exceptUserMode()
4638 .mapsTo(MISCREG_ICC_SRE_NS);
4639 InitReg(MISCREG_ICC_SRE_EL1_S)
4640 .bankedChild()
4641 .res0(0xFFFFFFF8) // [31:3]
4642 .secure().exceptUserMode()
4643 .mapsTo(MISCREG_ICC_SRE_S);
4644 InitReg(MISCREG_ICC_IGRPEN0_EL1)
4645 .res0(0xFFFFFFFE) // [31:1]
4646 .allPrivileges().exceptUserMode()
4647 .mapsTo(MISCREG_ICC_IGRPEN0);
4648 InitReg(MISCREG_ICC_IGRPEN1_EL1)
4649 .banked()
4650 .mapsTo(MISCREG_ICC_IGRPEN1);
4651 InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
4652 .bankedChild()
4653 .res0(0xFFFFFFFE) // [31:1]
4654 .allPrivileges().exceptUserMode()
4655 .mapsTo(MISCREG_ICC_IGRPEN1_NS);
4656 InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
4657 .bankedChild()
4658 .res0(0xFFFFFFFE) // [31:1]
4659 .secure().exceptUserMode()
4660 .mapsTo(MISCREG_ICC_IGRPEN1_S);
4661 InitReg(MISCREG_ICC_SRE_EL2)
4662 .hyp().mon()
4663 .mapsTo(MISCREG_ICC_HSRE);
4664 InitReg(MISCREG_ICC_CTLR_EL3)
4665 .allPrivileges().exceptUserMode()
4666 .mapsTo(MISCREG_ICC_MCTLR);
4667 InitReg(MISCREG_ICC_SRE_EL3)
4668 .allPrivileges().exceptUserMode()
4669 .mapsTo(MISCREG_ICC_MSRE);
4670 InitReg(MISCREG_ICC_IGRPEN1_EL3)
4671 .allPrivileges().exceptUserMode()
4672 .mapsTo(MISCREG_ICC_MGRPEN1);
4673
4674 InitReg(MISCREG_ICH_AP0R0_EL2)
4675 .hyp().mon()
4676 .mapsTo(MISCREG_ICH_AP0R0);
4677 InitReg(MISCREG_ICH_AP0R1_EL2)
4678 .hyp().mon()
4679 .unimplemented()
4680 .mapsTo(MISCREG_ICH_AP0R1);
4681 InitReg(MISCREG_ICH_AP0R2_EL2)
4682 .hyp().mon()
4683 .unimplemented()
4684 .mapsTo(MISCREG_ICH_AP0R2);
4685 InitReg(MISCREG_ICH_AP0R3_EL2)
4686 .hyp().mon()
4687 .unimplemented()
4688 .mapsTo(MISCREG_ICH_AP0R3);
4689 InitReg(MISCREG_ICH_AP1R0_EL2)
4690 .hyp().mon()
4691 .mapsTo(MISCREG_ICH_AP1R0);
4692 InitReg(MISCREG_ICH_AP1R1_EL2)
4693 .hyp().mon()
4694 .unimplemented()
4695 .mapsTo(MISCREG_ICH_AP1R1);
4696 InitReg(MISCREG_ICH_AP1R2_EL2)
4697 .hyp().mon()
4698 .unimplemented()
4699 .mapsTo(MISCREG_ICH_AP1R2);
4700 InitReg(MISCREG_ICH_AP1R3_EL2)
4701 .hyp().mon()
4702 .unimplemented()
4703 .mapsTo(MISCREG_ICH_AP1R3);
4704 InitReg(MISCREG_ICH_HCR_EL2)
4705 .hyp().mon()
4706 .mapsTo(MISCREG_ICH_HCR);
4707 InitReg(MISCREG_ICH_VTR_EL2)
4708 .hyp().mon().writes(0)
4709 .mapsTo(MISCREG_ICH_VTR);
4710 InitReg(MISCREG_ICH_MISR_EL2)
4711 .hyp().mon().writes(0)
4712 .mapsTo(MISCREG_ICH_MISR);
4713 InitReg(MISCREG_ICH_EISR_EL2)
4714 .hyp().mon().writes(0)
4715 .mapsTo(MISCREG_ICH_EISR);
4716 InitReg(MISCREG_ICH_ELRSR_EL2)
4717 .hyp().mon().writes(0)
4718 .mapsTo(MISCREG_ICH_ELRSR);
4719 InitReg(MISCREG_ICH_VMCR_EL2)
4720 .hyp().mon()
4721 .mapsTo(MISCREG_ICH_VMCR);
4722 InitReg(MISCREG_ICH_LR0_EL2)
4723 .hyp().mon()
4724 .allPrivileges().exceptUserMode();
4725 InitReg(MISCREG_ICH_LR1_EL2)
4726 .hyp().mon()
4727 .allPrivileges().exceptUserMode();
4728 InitReg(MISCREG_ICH_LR2_EL2)
4729 .hyp().mon()
4730 .allPrivileges().exceptUserMode();
4731 InitReg(MISCREG_ICH_LR3_EL2)
4732 .hyp().mon()
4733 .allPrivileges().exceptUserMode();
4734 InitReg(MISCREG_ICH_LR4_EL2)
4735 .hyp().mon()
4736 .allPrivileges().exceptUserMode();
4737 InitReg(MISCREG_ICH_LR5_EL2)
4738 .hyp().mon()
4739 .allPrivileges().exceptUserMode();
4740 InitReg(MISCREG_ICH_LR6_EL2)
4741 .hyp().mon()
4742 .allPrivileges().exceptUserMode();
4743 InitReg(MISCREG_ICH_LR7_EL2)
4744 .hyp().mon()
4745 .allPrivileges().exceptUserMode();
4746 InitReg(MISCREG_ICH_LR8_EL2)
4747 .hyp().mon()
4748 .allPrivileges().exceptUserMode();
4749 InitReg(MISCREG_ICH_LR9_EL2)
4750 .hyp().mon()
4751 .allPrivileges().exceptUserMode();
4752 InitReg(MISCREG_ICH_LR10_EL2)
4753 .hyp().mon()
4754 .allPrivileges().exceptUserMode();
4755 InitReg(MISCREG_ICH_LR11_EL2)
4756 .hyp().mon()
4757 .allPrivileges().exceptUserMode();
4758 InitReg(MISCREG_ICH_LR12_EL2)
4759 .hyp().mon()
4760 .allPrivileges().exceptUserMode();
4761 InitReg(MISCREG_ICH_LR13_EL2)
4762 .hyp().mon()
4763 .allPrivileges().exceptUserMode();
4764 InitReg(MISCREG_ICH_LR14_EL2)
4765 .hyp().mon()
4766 .allPrivileges().exceptUserMode();
4767 InitReg(MISCREG_ICH_LR15_EL2)
4768 .hyp().mon()
4769 .allPrivileges().exceptUserMode();
4770
4771 // GICv3 AArch32
4772 InitReg(MISCREG_ICC_AP0R0)
4773 .allPrivileges().exceptUserMode();
4774 InitReg(MISCREG_ICC_AP0R1)
4775 .allPrivileges().exceptUserMode();
4776 InitReg(MISCREG_ICC_AP0R2)
4777 .allPrivileges().exceptUserMode();
4778 InitReg(MISCREG_ICC_AP0R3)
4779 .allPrivileges().exceptUserMode();
4780 InitReg(MISCREG_ICC_AP1R0)
4781 .allPrivileges().exceptUserMode();
4782 InitReg(MISCREG_ICC_AP1R0_NS)
4783 .allPrivileges().exceptUserMode();
4784 InitReg(MISCREG_ICC_AP1R0_S)
4785 .allPrivileges().exceptUserMode();
4786 InitReg(MISCREG_ICC_AP1R1)
4787 .allPrivileges().exceptUserMode();
4788 InitReg(MISCREG_ICC_AP1R1_NS)
4789 .allPrivileges().exceptUserMode();
4790 InitReg(MISCREG_ICC_AP1R1_S)
4791 .allPrivileges().exceptUserMode();
4792 InitReg(MISCREG_ICC_AP1R2)
4793 .allPrivileges().exceptUserMode();
4794 InitReg(MISCREG_ICC_AP1R2_NS)
4795 .allPrivileges().exceptUserMode();
4796 InitReg(MISCREG_ICC_AP1R2_S)
4797 .allPrivileges().exceptUserMode();
4798 InitReg(MISCREG_ICC_AP1R3)
4799 .allPrivileges().exceptUserMode();
4800 InitReg(MISCREG_ICC_AP1R3_NS)
4801 .allPrivileges().exceptUserMode();
4802 InitReg(MISCREG_ICC_AP1R3_S)
4803 .allPrivileges().exceptUserMode();
4804 InitReg(MISCREG_ICC_ASGI1R)
4805 .allPrivileges().exceptUserMode().reads(0);
4806 InitReg(MISCREG_ICC_BPR0)
4807 .allPrivileges().exceptUserMode();
4808 InitReg(MISCREG_ICC_BPR1)
4809 .allPrivileges().exceptUserMode();
4810 InitReg(MISCREG_ICC_BPR1_NS)
4811 .allPrivileges().exceptUserMode();
4812 InitReg(MISCREG_ICC_BPR1_S)
4813 .allPrivileges().exceptUserMode();
4814 InitReg(MISCREG_ICC_CTLR)
4815 .allPrivileges().exceptUserMode();
4816 InitReg(MISCREG_ICC_CTLR_NS)
4817 .allPrivileges().exceptUserMode();
4818 InitReg(MISCREG_ICC_CTLR_S)
4819 .allPrivileges().exceptUserMode();
4820 InitReg(MISCREG_ICC_DIR)
4821 .allPrivileges().exceptUserMode().reads(0);
4822 InitReg(MISCREG_ICC_EOIR0)
4823 .allPrivileges().exceptUserMode().reads(0);
4824 InitReg(MISCREG_ICC_EOIR1)
4825 .allPrivileges().exceptUserMode().reads(0);
4826 InitReg(MISCREG_ICC_HPPIR0)
4827 .allPrivileges().exceptUserMode().writes(0);
4828 InitReg(MISCREG_ICC_HPPIR1)
4829 .allPrivileges().exceptUserMode().writes(0);
4830 InitReg(MISCREG_ICC_HSRE)
4831 .allPrivileges().exceptUserMode();
4832 InitReg(MISCREG_ICC_IAR0)
4833 .allPrivileges().exceptUserMode().writes(0);
4834 InitReg(MISCREG_ICC_IAR1)
4835 .allPrivileges().exceptUserMode().writes(0);
4836 InitReg(MISCREG_ICC_IGRPEN0)
4837 .allPrivileges().exceptUserMode();
4838 InitReg(MISCREG_ICC_IGRPEN1)
4839 .allPrivileges().exceptUserMode();
4840 InitReg(MISCREG_ICC_IGRPEN1_NS)
4841 .allPrivileges().exceptUserMode();
4842 InitReg(MISCREG_ICC_IGRPEN1_S)
4843 .allPrivileges().exceptUserMode();
4844 InitReg(MISCREG_ICC_MCTLR)
4845 .allPrivileges().exceptUserMode();
4846 InitReg(MISCREG_ICC_MGRPEN1)
4847 .allPrivileges().exceptUserMode();
4848 InitReg(MISCREG_ICC_MSRE)
4849 .allPrivileges().exceptUserMode();
4850 InitReg(MISCREG_ICC_PMR)
4851 .allPrivileges().exceptUserMode();
4852 InitReg(MISCREG_ICC_RPR)
4853 .allPrivileges().exceptUserMode().writes(0);
4854 InitReg(MISCREG_ICC_SGI0R)
4855 .allPrivileges().exceptUserMode().reads(0);
4856 InitReg(MISCREG_ICC_SGI1R)
4857 .allPrivileges().exceptUserMode().reads(0);
4858 InitReg(MISCREG_ICC_SRE)
4859 .allPrivileges().exceptUserMode();
4860 InitReg(MISCREG_ICC_SRE_NS)
4861 .allPrivileges().exceptUserMode();
4862 InitReg(MISCREG_ICC_SRE_S)
4863 .allPrivileges().exceptUserMode();
4864
4865 InitReg(MISCREG_ICH_AP0R0)
4866 .hyp().mon();
4867 InitReg(MISCREG_ICH_AP0R1)
4868 .hyp().mon();
4869 InitReg(MISCREG_ICH_AP0R2)
4870 .hyp().mon();
4871 InitReg(MISCREG_ICH_AP0R3)
4872 .hyp().mon();
4873 InitReg(MISCREG_ICH_AP1R0)
4874 .hyp().mon();
4875 InitReg(MISCREG_ICH_AP1R1)
4876 .hyp().mon();
4877 InitReg(MISCREG_ICH_AP1R2)
4878 .hyp().mon();
4879 InitReg(MISCREG_ICH_AP1R3)
4880 .hyp().mon();
4881 InitReg(MISCREG_ICH_HCR)
4882 .hyp().mon();
4883 InitReg(MISCREG_ICH_VTR)
4884 .hyp().mon().writes(0);
4885 InitReg(MISCREG_ICH_MISR)
4886 .hyp().mon().writes(0);
4887 InitReg(MISCREG_ICH_EISR)
4888 .hyp().mon().writes(0);
4889 InitReg(MISCREG_ICH_ELRSR)
4890 .hyp().mon().writes(0);
4891 InitReg(MISCREG_ICH_VMCR)
4892 .hyp().mon();
4893 InitReg(MISCREG_ICH_LR0)
4894 .hyp().mon();
4895 InitReg(MISCREG_ICH_LR1)
4896 .hyp().mon();
4897 InitReg(MISCREG_ICH_LR2)
4898 .hyp().mon();
4899 InitReg(MISCREG_ICH_LR3)
4900 .hyp().mon();
4901 InitReg(MISCREG_ICH_LR4)
4902 .hyp().mon();
4903 InitReg(MISCREG_ICH_LR5)
4904 .hyp().mon();
4905 InitReg(MISCREG_ICH_LR6)
4906 .hyp().mon();
4907 InitReg(MISCREG_ICH_LR7)
4908 .hyp().mon();
4909 InitReg(MISCREG_ICH_LR8)
4910 .hyp().mon();
4911 InitReg(MISCREG_ICH_LR9)
4912 .hyp().mon();
4913 InitReg(MISCREG_ICH_LR10)
4914 .hyp().mon();
4915 InitReg(MISCREG_ICH_LR11)
4916 .hyp().mon();
4917 InitReg(MISCREG_ICH_LR12)
4918 .hyp().mon();
4919 InitReg(MISCREG_ICH_LR13)
4920 .hyp().mon();
4921 InitReg(MISCREG_ICH_LR14)
4922 .hyp().mon();
4923 InitReg(MISCREG_ICH_LR15)
4924 .hyp().mon();
4925 InitReg(MISCREG_ICH_LRC0)
4926 .mapsTo(MISCREG_ICH_LR0)
4927 .hyp().mon();
4928 InitReg(MISCREG_ICH_LRC1)
4929 .mapsTo(MISCREG_ICH_LR1)
4930 .hyp().mon();
4931 InitReg(MISCREG_ICH_LRC2)
4932 .mapsTo(MISCREG_ICH_LR2)
4933 .hyp().mon();
4934 InitReg(MISCREG_ICH_LRC3)
4935 .mapsTo(MISCREG_ICH_LR3)
4936 .hyp().mon();
4937 InitReg(MISCREG_ICH_LRC4)
4938 .mapsTo(MISCREG_ICH_LR4)
4939 .hyp().mon();
4940 InitReg(MISCREG_ICH_LRC5)
4941 .mapsTo(MISCREG_ICH_LR5)
4942 .hyp().mon();
4943 InitReg(MISCREG_ICH_LRC6)
4944 .mapsTo(MISCREG_ICH_LR6)
4945 .hyp().mon();
4946 InitReg(MISCREG_ICH_LRC7)
4947 .mapsTo(MISCREG_ICH_LR7)
4948 .hyp().mon();
4949 InitReg(MISCREG_ICH_LRC8)
4950 .mapsTo(MISCREG_ICH_LR8)
4951 .hyp().mon();
4952 InitReg(MISCREG_ICH_LRC9)
4953 .mapsTo(MISCREG_ICH_LR9)
4954 .hyp().mon();
4955 InitReg(MISCREG_ICH_LRC10)
4956 .mapsTo(MISCREG_ICH_LR10)
4957 .hyp().mon();
4958 InitReg(MISCREG_ICH_LRC11)
4959 .mapsTo(MISCREG_ICH_LR11)
4960 .hyp().mon();
4961 InitReg(MISCREG_ICH_LRC12)
4962 .mapsTo(MISCREG_ICH_LR12)
4963 .hyp().mon();
4964 InitReg(MISCREG_ICH_LRC13)
4965 .mapsTo(MISCREG_ICH_LR13)
4966 .hyp().mon();
4967 InitReg(MISCREG_ICH_LRC14)
4968 .mapsTo(MISCREG_ICH_LR14)
4969 .hyp().mon();
4970 InitReg(MISCREG_ICH_LRC15)
4971 .mapsTo(MISCREG_ICH_LR15)
4972 .hyp().mon();
4973
4974 InitReg(MISCREG_CNTHV_CTL_EL2)
4975 .mon().hyp();
4976 InitReg(MISCREG_CNTHV_CVAL_EL2)
4977 .mon().hyp();
4978 InitReg(MISCREG_CNTHV_TVAL_EL2)
4979 .mon().hyp();
4980
4981 // SVE
4982 InitReg(MISCREG_ID_AA64ZFR0_EL1)
4983 .allPrivileges().exceptUserMode().writes(0);
4984 InitReg(MISCREG_ZCR_EL3)
4985 .mon();
4986 InitReg(MISCREG_ZCR_EL2)
4987 .hyp().mon();
4988 InitReg(MISCREG_ZCR_EL12)
4989 .unimplemented().warnNotFail();
4990 InitReg(MISCREG_ZCR_EL1)
4991 .allPrivileges().exceptUserMode();
4992
4993 // Dummy registers
4994 InitReg(MISCREG_NOP)
4995 .allPrivileges();
4996 InitReg(MISCREG_RAZ)
4997 .allPrivileges().exceptUserMode().writes(0);
4998 InitReg(MISCREG_CP14_UNIMPL)
4999 .unimplemented()
5000 .warnNotFail();
5001 InitReg(MISCREG_CP15_UNIMPL)
5002 .unimplemented()
5003 .warnNotFail();
5004 InitReg(MISCREG_UNKNOWN);
5005 InitReg(MISCREG_IMPDEF_UNIMPL)
5006 .unimplemented()
5007 .warnNotFail(impdefAsNop);
5008
5009 // RAS extension (unimplemented)
5010 InitReg(MISCREG_ERRIDR_EL1)
5011 .unimplemented()
5012 .warnNotFail();
5013 InitReg(MISCREG_ERRSELR_EL1)
5014 .unimplemented()
5015 .warnNotFail();
5016 InitReg(MISCREG_ERXFR_EL1)
5017 .unimplemented()
5018 .warnNotFail();
5019 InitReg(MISCREG_ERXCTLR_EL1)
5020 .unimplemented()
5021 .warnNotFail();
5022 InitReg(MISCREG_ERXSTATUS_EL1)
5023 .unimplemented()
5024 .warnNotFail();
5025 InitReg(MISCREG_ERXADDR_EL1)
5026 .unimplemented()
5027 .warnNotFail();
5028 InitReg(MISCREG_ERXMISC0_EL1)
5029 .unimplemented()
5030 .warnNotFail();
5031 InitReg(MISCREG_ERXMISC1_EL1)
5032 .unimplemented()
5033 .warnNotFail();
5034 InitReg(MISCREG_DISR_EL1)
5035 .unimplemented()
5036 .warnNotFail();
5037 InitReg(MISCREG_VSESR_EL2)
5038 .unimplemented()
5039 .warnNotFail();
5040 InitReg(MISCREG_VDISR_EL2)
5041 .unimplemented()
5042 .warnNotFail();
5043
5044 // Register mappings for some unimplemented registers:
5045 // ESR_EL1 -> DFSR
5046 // RMR_EL1 -> RMR
5047 // RMR_EL2 -> HRMR
5048 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
5049 // DBGDTRRX_EL0 -> DBGDTRRXint
5050 // DBGDTRTX_EL0 -> DBGDTRRXint
5051 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
5052
5053 completed = true;
5054}
5055
5056} // namespace ArmISA
4620 .mapsTo(MISCREG_ICC_CTLR);
4621 InitReg(MISCREG_ICC_CTLR_EL1_NS)
4622 .bankedChild()
4623 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4624 .allPrivileges().exceptUserMode()
4625 .mapsTo(MISCREG_ICC_CTLR_NS);
4626 InitReg(MISCREG_ICC_CTLR_EL1_S)
4627 .bankedChild()
4628 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
4629 .secure().exceptUserMode()
4630 .mapsTo(MISCREG_ICC_CTLR_S);
4631 InitReg(MISCREG_ICC_SRE_EL1)
4632 .banked()
4633 .mapsTo(MISCREG_ICC_SRE);
4634 InitReg(MISCREG_ICC_SRE_EL1_NS)
4635 .bankedChild()
4636 .res0(0xFFFFFFF8) // [31:3]
4637 .allPrivileges().exceptUserMode()
4638 .mapsTo(MISCREG_ICC_SRE_NS);
4639 InitReg(MISCREG_ICC_SRE_EL1_S)
4640 .bankedChild()
4641 .res0(0xFFFFFFF8) // [31:3]
4642 .secure().exceptUserMode()
4643 .mapsTo(MISCREG_ICC_SRE_S);
4644 InitReg(MISCREG_ICC_IGRPEN0_EL1)
4645 .res0(0xFFFFFFFE) // [31:1]
4646 .allPrivileges().exceptUserMode()
4647 .mapsTo(MISCREG_ICC_IGRPEN0);
4648 InitReg(MISCREG_ICC_IGRPEN1_EL1)
4649 .banked()
4650 .mapsTo(MISCREG_ICC_IGRPEN1);
4651 InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
4652 .bankedChild()
4653 .res0(0xFFFFFFFE) // [31:1]
4654 .allPrivileges().exceptUserMode()
4655 .mapsTo(MISCREG_ICC_IGRPEN1_NS);
4656 InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
4657 .bankedChild()
4658 .res0(0xFFFFFFFE) // [31:1]
4659 .secure().exceptUserMode()
4660 .mapsTo(MISCREG_ICC_IGRPEN1_S);
4661 InitReg(MISCREG_ICC_SRE_EL2)
4662 .hyp().mon()
4663 .mapsTo(MISCREG_ICC_HSRE);
4664 InitReg(MISCREG_ICC_CTLR_EL3)
4665 .allPrivileges().exceptUserMode()
4666 .mapsTo(MISCREG_ICC_MCTLR);
4667 InitReg(MISCREG_ICC_SRE_EL3)
4668 .allPrivileges().exceptUserMode()
4669 .mapsTo(MISCREG_ICC_MSRE);
4670 InitReg(MISCREG_ICC_IGRPEN1_EL3)
4671 .allPrivileges().exceptUserMode()
4672 .mapsTo(MISCREG_ICC_MGRPEN1);
4673
4674 InitReg(MISCREG_ICH_AP0R0_EL2)
4675 .hyp().mon()
4676 .mapsTo(MISCREG_ICH_AP0R0);
4677 InitReg(MISCREG_ICH_AP0R1_EL2)
4678 .hyp().mon()
4679 .unimplemented()
4680 .mapsTo(MISCREG_ICH_AP0R1);
4681 InitReg(MISCREG_ICH_AP0R2_EL2)
4682 .hyp().mon()
4683 .unimplemented()
4684 .mapsTo(MISCREG_ICH_AP0R2);
4685 InitReg(MISCREG_ICH_AP0R3_EL2)
4686 .hyp().mon()
4687 .unimplemented()
4688 .mapsTo(MISCREG_ICH_AP0R3);
4689 InitReg(MISCREG_ICH_AP1R0_EL2)
4690 .hyp().mon()
4691 .mapsTo(MISCREG_ICH_AP1R0);
4692 InitReg(MISCREG_ICH_AP1R1_EL2)
4693 .hyp().mon()
4694 .unimplemented()
4695 .mapsTo(MISCREG_ICH_AP1R1);
4696 InitReg(MISCREG_ICH_AP1R2_EL2)
4697 .hyp().mon()
4698 .unimplemented()
4699 .mapsTo(MISCREG_ICH_AP1R2);
4700 InitReg(MISCREG_ICH_AP1R3_EL2)
4701 .hyp().mon()
4702 .unimplemented()
4703 .mapsTo(MISCREG_ICH_AP1R3);
4704 InitReg(MISCREG_ICH_HCR_EL2)
4705 .hyp().mon()
4706 .mapsTo(MISCREG_ICH_HCR);
4707 InitReg(MISCREG_ICH_VTR_EL2)
4708 .hyp().mon().writes(0)
4709 .mapsTo(MISCREG_ICH_VTR);
4710 InitReg(MISCREG_ICH_MISR_EL2)
4711 .hyp().mon().writes(0)
4712 .mapsTo(MISCREG_ICH_MISR);
4713 InitReg(MISCREG_ICH_EISR_EL2)
4714 .hyp().mon().writes(0)
4715 .mapsTo(MISCREG_ICH_EISR);
4716 InitReg(MISCREG_ICH_ELRSR_EL2)
4717 .hyp().mon().writes(0)
4718 .mapsTo(MISCREG_ICH_ELRSR);
4719 InitReg(MISCREG_ICH_VMCR_EL2)
4720 .hyp().mon()
4721 .mapsTo(MISCREG_ICH_VMCR);
4722 InitReg(MISCREG_ICH_LR0_EL2)
4723 .hyp().mon()
4724 .allPrivileges().exceptUserMode();
4725 InitReg(MISCREG_ICH_LR1_EL2)
4726 .hyp().mon()
4727 .allPrivileges().exceptUserMode();
4728 InitReg(MISCREG_ICH_LR2_EL2)
4729 .hyp().mon()
4730 .allPrivileges().exceptUserMode();
4731 InitReg(MISCREG_ICH_LR3_EL2)
4732 .hyp().mon()
4733 .allPrivileges().exceptUserMode();
4734 InitReg(MISCREG_ICH_LR4_EL2)
4735 .hyp().mon()
4736 .allPrivileges().exceptUserMode();
4737 InitReg(MISCREG_ICH_LR5_EL2)
4738 .hyp().mon()
4739 .allPrivileges().exceptUserMode();
4740 InitReg(MISCREG_ICH_LR6_EL2)
4741 .hyp().mon()
4742 .allPrivileges().exceptUserMode();
4743 InitReg(MISCREG_ICH_LR7_EL2)
4744 .hyp().mon()
4745 .allPrivileges().exceptUserMode();
4746 InitReg(MISCREG_ICH_LR8_EL2)
4747 .hyp().mon()
4748 .allPrivileges().exceptUserMode();
4749 InitReg(MISCREG_ICH_LR9_EL2)
4750 .hyp().mon()
4751 .allPrivileges().exceptUserMode();
4752 InitReg(MISCREG_ICH_LR10_EL2)
4753 .hyp().mon()
4754 .allPrivileges().exceptUserMode();
4755 InitReg(MISCREG_ICH_LR11_EL2)
4756 .hyp().mon()
4757 .allPrivileges().exceptUserMode();
4758 InitReg(MISCREG_ICH_LR12_EL2)
4759 .hyp().mon()
4760 .allPrivileges().exceptUserMode();
4761 InitReg(MISCREG_ICH_LR13_EL2)
4762 .hyp().mon()
4763 .allPrivileges().exceptUserMode();
4764 InitReg(MISCREG_ICH_LR14_EL2)
4765 .hyp().mon()
4766 .allPrivileges().exceptUserMode();
4767 InitReg(MISCREG_ICH_LR15_EL2)
4768 .hyp().mon()
4769 .allPrivileges().exceptUserMode();
4770
4771 // GICv3 AArch32
4772 InitReg(MISCREG_ICC_AP0R0)
4773 .allPrivileges().exceptUserMode();
4774 InitReg(MISCREG_ICC_AP0R1)
4775 .allPrivileges().exceptUserMode();
4776 InitReg(MISCREG_ICC_AP0R2)
4777 .allPrivileges().exceptUserMode();
4778 InitReg(MISCREG_ICC_AP0R3)
4779 .allPrivileges().exceptUserMode();
4780 InitReg(MISCREG_ICC_AP1R0)
4781 .allPrivileges().exceptUserMode();
4782 InitReg(MISCREG_ICC_AP1R0_NS)
4783 .allPrivileges().exceptUserMode();
4784 InitReg(MISCREG_ICC_AP1R0_S)
4785 .allPrivileges().exceptUserMode();
4786 InitReg(MISCREG_ICC_AP1R1)
4787 .allPrivileges().exceptUserMode();
4788 InitReg(MISCREG_ICC_AP1R1_NS)
4789 .allPrivileges().exceptUserMode();
4790 InitReg(MISCREG_ICC_AP1R1_S)
4791 .allPrivileges().exceptUserMode();
4792 InitReg(MISCREG_ICC_AP1R2)
4793 .allPrivileges().exceptUserMode();
4794 InitReg(MISCREG_ICC_AP1R2_NS)
4795 .allPrivileges().exceptUserMode();
4796 InitReg(MISCREG_ICC_AP1R2_S)
4797 .allPrivileges().exceptUserMode();
4798 InitReg(MISCREG_ICC_AP1R3)
4799 .allPrivileges().exceptUserMode();
4800 InitReg(MISCREG_ICC_AP1R3_NS)
4801 .allPrivileges().exceptUserMode();
4802 InitReg(MISCREG_ICC_AP1R3_S)
4803 .allPrivileges().exceptUserMode();
4804 InitReg(MISCREG_ICC_ASGI1R)
4805 .allPrivileges().exceptUserMode().reads(0);
4806 InitReg(MISCREG_ICC_BPR0)
4807 .allPrivileges().exceptUserMode();
4808 InitReg(MISCREG_ICC_BPR1)
4809 .allPrivileges().exceptUserMode();
4810 InitReg(MISCREG_ICC_BPR1_NS)
4811 .allPrivileges().exceptUserMode();
4812 InitReg(MISCREG_ICC_BPR1_S)
4813 .allPrivileges().exceptUserMode();
4814 InitReg(MISCREG_ICC_CTLR)
4815 .allPrivileges().exceptUserMode();
4816 InitReg(MISCREG_ICC_CTLR_NS)
4817 .allPrivileges().exceptUserMode();
4818 InitReg(MISCREG_ICC_CTLR_S)
4819 .allPrivileges().exceptUserMode();
4820 InitReg(MISCREG_ICC_DIR)
4821 .allPrivileges().exceptUserMode().reads(0);
4822 InitReg(MISCREG_ICC_EOIR0)
4823 .allPrivileges().exceptUserMode().reads(0);
4824 InitReg(MISCREG_ICC_EOIR1)
4825 .allPrivileges().exceptUserMode().reads(0);
4826 InitReg(MISCREG_ICC_HPPIR0)
4827 .allPrivileges().exceptUserMode().writes(0);
4828 InitReg(MISCREG_ICC_HPPIR1)
4829 .allPrivileges().exceptUserMode().writes(0);
4830 InitReg(MISCREG_ICC_HSRE)
4831 .allPrivileges().exceptUserMode();
4832 InitReg(MISCREG_ICC_IAR0)
4833 .allPrivileges().exceptUserMode().writes(0);
4834 InitReg(MISCREG_ICC_IAR1)
4835 .allPrivileges().exceptUserMode().writes(0);
4836 InitReg(MISCREG_ICC_IGRPEN0)
4837 .allPrivileges().exceptUserMode();
4838 InitReg(MISCREG_ICC_IGRPEN1)
4839 .allPrivileges().exceptUserMode();
4840 InitReg(MISCREG_ICC_IGRPEN1_NS)
4841 .allPrivileges().exceptUserMode();
4842 InitReg(MISCREG_ICC_IGRPEN1_S)
4843 .allPrivileges().exceptUserMode();
4844 InitReg(MISCREG_ICC_MCTLR)
4845 .allPrivileges().exceptUserMode();
4846 InitReg(MISCREG_ICC_MGRPEN1)
4847 .allPrivileges().exceptUserMode();
4848 InitReg(MISCREG_ICC_MSRE)
4849 .allPrivileges().exceptUserMode();
4850 InitReg(MISCREG_ICC_PMR)
4851 .allPrivileges().exceptUserMode();
4852 InitReg(MISCREG_ICC_RPR)
4853 .allPrivileges().exceptUserMode().writes(0);
4854 InitReg(MISCREG_ICC_SGI0R)
4855 .allPrivileges().exceptUserMode().reads(0);
4856 InitReg(MISCREG_ICC_SGI1R)
4857 .allPrivileges().exceptUserMode().reads(0);
4858 InitReg(MISCREG_ICC_SRE)
4859 .allPrivileges().exceptUserMode();
4860 InitReg(MISCREG_ICC_SRE_NS)
4861 .allPrivileges().exceptUserMode();
4862 InitReg(MISCREG_ICC_SRE_S)
4863 .allPrivileges().exceptUserMode();
4864
4865 InitReg(MISCREG_ICH_AP0R0)
4866 .hyp().mon();
4867 InitReg(MISCREG_ICH_AP0R1)
4868 .hyp().mon();
4869 InitReg(MISCREG_ICH_AP0R2)
4870 .hyp().mon();
4871 InitReg(MISCREG_ICH_AP0R3)
4872 .hyp().mon();
4873 InitReg(MISCREG_ICH_AP1R0)
4874 .hyp().mon();
4875 InitReg(MISCREG_ICH_AP1R1)
4876 .hyp().mon();
4877 InitReg(MISCREG_ICH_AP1R2)
4878 .hyp().mon();
4879 InitReg(MISCREG_ICH_AP1R3)
4880 .hyp().mon();
4881 InitReg(MISCREG_ICH_HCR)
4882 .hyp().mon();
4883 InitReg(MISCREG_ICH_VTR)
4884 .hyp().mon().writes(0);
4885 InitReg(MISCREG_ICH_MISR)
4886 .hyp().mon().writes(0);
4887 InitReg(MISCREG_ICH_EISR)
4888 .hyp().mon().writes(0);
4889 InitReg(MISCREG_ICH_ELRSR)
4890 .hyp().mon().writes(0);
4891 InitReg(MISCREG_ICH_VMCR)
4892 .hyp().mon();
4893 InitReg(MISCREG_ICH_LR0)
4894 .hyp().mon();
4895 InitReg(MISCREG_ICH_LR1)
4896 .hyp().mon();
4897 InitReg(MISCREG_ICH_LR2)
4898 .hyp().mon();
4899 InitReg(MISCREG_ICH_LR3)
4900 .hyp().mon();
4901 InitReg(MISCREG_ICH_LR4)
4902 .hyp().mon();
4903 InitReg(MISCREG_ICH_LR5)
4904 .hyp().mon();
4905 InitReg(MISCREG_ICH_LR6)
4906 .hyp().mon();
4907 InitReg(MISCREG_ICH_LR7)
4908 .hyp().mon();
4909 InitReg(MISCREG_ICH_LR8)
4910 .hyp().mon();
4911 InitReg(MISCREG_ICH_LR9)
4912 .hyp().mon();
4913 InitReg(MISCREG_ICH_LR10)
4914 .hyp().mon();
4915 InitReg(MISCREG_ICH_LR11)
4916 .hyp().mon();
4917 InitReg(MISCREG_ICH_LR12)
4918 .hyp().mon();
4919 InitReg(MISCREG_ICH_LR13)
4920 .hyp().mon();
4921 InitReg(MISCREG_ICH_LR14)
4922 .hyp().mon();
4923 InitReg(MISCREG_ICH_LR15)
4924 .hyp().mon();
4925 InitReg(MISCREG_ICH_LRC0)
4926 .mapsTo(MISCREG_ICH_LR0)
4927 .hyp().mon();
4928 InitReg(MISCREG_ICH_LRC1)
4929 .mapsTo(MISCREG_ICH_LR1)
4930 .hyp().mon();
4931 InitReg(MISCREG_ICH_LRC2)
4932 .mapsTo(MISCREG_ICH_LR2)
4933 .hyp().mon();
4934 InitReg(MISCREG_ICH_LRC3)
4935 .mapsTo(MISCREG_ICH_LR3)
4936 .hyp().mon();
4937 InitReg(MISCREG_ICH_LRC4)
4938 .mapsTo(MISCREG_ICH_LR4)
4939 .hyp().mon();
4940 InitReg(MISCREG_ICH_LRC5)
4941 .mapsTo(MISCREG_ICH_LR5)
4942 .hyp().mon();
4943 InitReg(MISCREG_ICH_LRC6)
4944 .mapsTo(MISCREG_ICH_LR6)
4945 .hyp().mon();
4946 InitReg(MISCREG_ICH_LRC7)
4947 .mapsTo(MISCREG_ICH_LR7)
4948 .hyp().mon();
4949 InitReg(MISCREG_ICH_LRC8)
4950 .mapsTo(MISCREG_ICH_LR8)
4951 .hyp().mon();
4952 InitReg(MISCREG_ICH_LRC9)
4953 .mapsTo(MISCREG_ICH_LR9)
4954 .hyp().mon();
4955 InitReg(MISCREG_ICH_LRC10)
4956 .mapsTo(MISCREG_ICH_LR10)
4957 .hyp().mon();
4958 InitReg(MISCREG_ICH_LRC11)
4959 .mapsTo(MISCREG_ICH_LR11)
4960 .hyp().mon();
4961 InitReg(MISCREG_ICH_LRC12)
4962 .mapsTo(MISCREG_ICH_LR12)
4963 .hyp().mon();
4964 InitReg(MISCREG_ICH_LRC13)
4965 .mapsTo(MISCREG_ICH_LR13)
4966 .hyp().mon();
4967 InitReg(MISCREG_ICH_LRC14)
4968 .mapsTo(MISCREG_ICH_LR14)
4969 .hyp().mon();
4970 InitReg(MISCREG_ICH_LRC15)
4971 .mapsTo(MISCREG_ICH_LR15)
4972 .hyp().mon();
4973
4974 InitReg(MISCREG_CNTHV_CTL_EL2)
4975 .mon().hyp();
4976 InitReg(MISCREG_CNTHV_CVAL_EL2)
4977 .mon().hyp();
4978 InitReg(MISCREG_CNTHV_TVAL_EL2)
4979 .mon().hyp();
4980
4981 // SVE
4982 InitReg(MISCREG_ID_AA64ZFR0_EL1)
4983 .allPrivileges().exceptUserMode().writes(0);
4984 InitReg(MISCREG_ZCR_EL3)
4985 .mon();
4986 InitReg(MISCREG_ZCR_EL2)
4987 .hyp().mon();
4988 InitReg(MISCREG_ZCR_EL12)
4989 .unimplemented().warnNotFail();
4990 InitReg(MISCREG_ZCR_EL1)
4991 .allPrivileges().exceptUserMode();
4992
4993 // Dummy registers
4994 InitReg(MISCREG_NOP)
4995 .allPrivileges();
4996 InitReg(MISCREG_RAZ)
4997 .allPrivileges().exceptUserMode().writes(0);
4998 InitReg(MISCREG_CP14_UNIMPL)
4999 .unimplemented()
5000 .warnNotFail();
5001 InitReg(MISCREG_CP15_UNIMPL)
5002 .unimplemented()
5003 .warnNotFail();
5004 InitReg(MISCREG_UNKNOWN);
5005 InitReg(MISCREG_IMPDEF_UNIMPL)
5006 .unimplemented()
5007 .warnNotFail(impdefAsNop);
5008
5009 // RAS extension (unimplemented)
5010 InitReg(MISCREG_ERRIDR_EL1)
5011 .unimplemented()
5012 .warnNotFail();
5013 InitReg(MISCREG_ERRSELR_EL1)
5014 .unimplemented()
5015 .warnNotFail();
5016 InitReg(MISCREG_ERXFR_EL1)
5017 .unimplemented()
5018 .warnNotFail();
5019 InitReg(MISCREG_ERXCTLR_EL1)
5020 .unimplemented()
5021 .warnNotFail();
5022 InitReg(MISCREG_ERXSTATUS_EL1)
5023 .unimplemented()
5024 .warnNotFail();
5025 InitReg(MISCREG_ERXADDR_EL1)
5026 .unimplemented()
5027 .warnNotFail();
5028 InitReg(MISCREG_ERXMISC0_EL1)
5029 .unimplemented()
5030 .warnNotFail();
5031 InitReg(MISCREG_ERXMISC1_EL1)
5032 .unimplemented()
5033 .warnNotFail();
5034 InitReg(MISCREG_DISR_EL1)
5035 .unimplemented()
5036 .warnNotFail();
5037 InitReg(MISCREG_VSESR_EL2)
5038 .unimplemented()
5039 .warnNotFail();
5040 InitReg(MISCREG_VDISR_EL2)
5041 .unimplemented()
5042 .warnNotFail();
5043
5044 // Register mappings for some unimplemented registers:
5045 // ESR_EL1 -> DFSR
5046 // RMR_EL1 -> RMR
5047 // RMR_EL2 -> HRMR
5048 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
5049 // DBGDTRRX_EL0 -> DBGDTRRXint
5050 // DBGDTRTX_EL0 -> DBGDTRRXint
5051 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
5052
5053 completed = true;
5054}
5055
5056} // namespace ArmISA