1/* 2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 * Giacomo Gabrielli 40 */ 41 42#include "arch/arm/miscregs.hh" 43 44#include <tuple> 45 46#include "arch/arm/isa.hh" 47#include "base/logging.hh" 48#include "cpu/thread_context.hh" 49#include "sim/full_system.hh" 50 51namespace ArmISA 52{ 53 54MiscRegIndex 55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 56{ 57 switch(crn) { 58 case 0: 59 switch (opc1) { 60 case 0: 61 switch (opc2) { 62 case 0: 63 switch (crm) { 64 case 0: 65 return MISCREG_DBGDIDR; 66 case 1: 67 return MISCREG_DBGDSCRint; 68 } 69 break; 70 } 71 break; 72 case 7: 73 switch (opc2) { 74 case 0: 75 switch (crm) { 76 case 0: 77 return MISCREG_JIDR; 78 } 79 break; 80 } 81 break; 82 } 83 break; 84 case 1: 85 switch (opc1) { 86 case 6: 87 switch (crm) { 88 case 0: 89 switch (opc2) { 90 case 0: 91 return MISCREG_TEEHBR; 92 } 93 break; 94 } 95 break; 96 case 7: 97 switch (crm) { 98 case 0: 99 switch (opc2) { 100 case 0: 101 return MISCREG_JOSCR; 102 } 103 break; 104 } 105 break; 106 } 107 break; 108 case 2: 109 switch (opc1) { 110 case 7: 111 switch (crm) { 112 case 0: 113 switch (opc2) { 114 case 0: 115 return MISCREG_JMCR; 116 } 117 break; 118 } 119 break; 120 } 121 break; 122 } 123 // If we get here then it must be a register that we haven't implemented 124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", 125 crn, opc1, crm, opc2); 126 return MISCREG_CP14_UNIMPL; 127} 128 129using namespace std; 130 131MiscRegIndex 132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 133{ 134 switch (crn) { 135 case 0: 136 switch (opc1) { 137 case 0: 138 switch (crm) { 139 case 0: 140 switch (opc2) { 141 case 1: 142 return MISCREG_CTR; 143 case 2: 144 return MISCREG_TCMTR; 145 case 3: 146 return MISCREG_TLBTR; 147 case 5: 148 return MISCREG_MPIDR; 149 case 6: 150 return MISCREG_REVIDR; 151 default: 152 return MISCREG_MIDR; 153 } 154 break; 155 case 1: 156 switch (opc2) { 157 case 0: 158 return MISCREG_ID_PFR0; 159 case 1: 160 return MISCREG_ID_PFR1; 161 case 2: 162 return MISCREG_ID_DFR0; 163 case 3: 164 return MISCREG_ID_AFR0; 165 case 4: 166 return MISCREG_ID_MMFR0; 167 case 5: 168 return MISCREG_ID_MMFR1; 169 case 6: 170 return MISCREG_ID_MMFR2; 171 case 7: 172 return MISCREG_ID_MMFR3; 173 } 174 break; 175 case 2: 176 switch (opc2) { 177 case 0: 178 return MISCREG_ID_ISAR0; 179 case 1: 180 return MISCREG_ID_ISAR1; 181 case 2: 182 return MISCREG_ID_ISAR2; 183 case 3: 184 return MISCREG_ID_ISAR3; 185 case 4: 186 return MISCREG_ID_ISAR4; 187 case 5: 188 return MISCREG_ID_ISAR5; 189 case 6: 190 case 7: 191 return MISCREG_RAZ; // read as zero 192 } 193 break; 194 default: 195 return MISCREG_RAZ; // read as zero 196 } 197 break; 198 case 1: 199 if (crm == 0) { 200 switch (opc2) { 201 case 0: 202 return MISCREG_CCSIDR; 203 case 1: 204 return MISCREG_CLIDR; 205 case 7: 206 return MISCREG_AIDR; 207 } 208 } 209 break; 210 case 2: 211 if (crm == 0 && opc2 == 0) { 212 return MISCREG_CSSELR; 213 } 214 break; 215 case 4: 216 if (crm == 0) { 217 if (opc2 == 0) 218 return MISCREG_VPIDR; 219 else if (opc2 == 5) 220 return MISCREG_VMPIDR; 221 } 222 break; 223 } 224 break; 225 case 1: 226 if (opc1 == 0) { 227 if (crm == 0) { 228 switch (opc2) { 229 case 0: 230 return MISCREG_SCTLR; 231 case 1: 232 return MISCREG_ACTLR; 233 case 0x2: 234 return MISCREG_CPACR; 235 } 236 } else if (crm == 1) { 237 switch (opc2) { 238 case 0: 239 return MISCREG_SCR; 240 case 1: 241 return MISCREG_SDER; 242 case 2: 243 return MISCREG_NSACR; 244 } 245 } 246 } else if (opc1 == 4) { 247 if (crm == 0) { 248 if (opc2 == 0) 249 return MISCREG_HSCTLR; 250 else if (opc2 == 1) 251 return MISCREG_HACTLR; 252 } else if (crm == 1) { 253 switch (opc2) { 254 case 0: 255 return MISCREG_HCR; 256 case 1: 257 return MISCREG_HDCR; 258 case 2: 259 return MISCREG_HCPTR; 260 case 3: 261 return MISCREG_HSTR; 262 case 7: 263 return MISCREG_HACR; 264 } 265 } 266 } 267 break; 268 case 2: 269 if (opc1 == 0 && crm == 0) { 270 switch (opc2) { 271 case 0: 272 return MISCREG_TTBR0; 273 case 1: 274 return MISCREG_TTBR1; 275 case 2: 276 return MISCREG_TTBCR; 277 } 278 } else if (opc1 == 4) { 279 if (crm == 0 && opc2 == 2) 280 return MISCREG_HTCR; 281 else if (crm == 1 && opc2 == 2) 282 return MISCREG_VTCR; 283 } 284 break; 285 case 3: 286 if (opc1 == 0 && crm == 0 && opc2 == 0) { 287 return MISCREG_DACR; 288 } 289 break;
| 1/* 2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 * Giacomo Gabrielli 40 */ 41 42#include "arch/arm/miscregs.hh" 43 44#include <tuple> 45 46#include "arch/arm/isa.hh" 47#include "base/logging.hh" 48#include "cpu/thread_context.hh" 49#include "sim/full_system.hh" 50 51namespace ArmISA 52{ 53 54MiscRegIndex 55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 56{ 57 switch(crn) { 58 case 0: 59 switch (opc1) { 60 case 0: 61 switch (opc2) { 62 case 0: 63 switch (crm) { 64 case 0: 65 return MISCREG_DBGDIDR; 66 case 1: 67 return MISCREG_DBGDSCRint; 68 } 69 break; 70 } 71 break; 72 case 7: 73 switch (opc2) { 74 case 0: 75 switch (crm) { 76 case 0: 77 return MISCREG_JIDR; 78 } 79 break; 80 } 81 break; 82 } 83 break; 84 case 1: 85 switch (opc1) { 86 case 6: 87 switch (crm) { 88 case 0: 89 switch (opc2) { 90 case 0: 91 return MISCREG_TEEHBR; 92 } 93 break; 94 } 95 break; 96 case 7: 97 switch (crm) { 98 case 0: 99 switch (opc2) { 100 case 0: 101 return MISCREG_JOSCR; 102 } 103 break; 104 } 105 break; 106 } 107 break; 108 case 2: 109 switch (opc1) { 110 case 7: 111 switch (crm) { 112 case 0: 113 switch (opc2) { 114 case 0: 115 return MISCREG_JMCR; 116 } 117 break; 118 } 119 break; 120 } 121 break; 122 } 123 // If we get here then it must be a register that we haven't implemented 124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", 125 crn, opc1, crm, opc2); 126 return MISCREG_CP14_UNIMPL; 127} 128 129using namespace std; 130 131MiscRegIndex 132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) 133{ 134 switch (crn) { 135 case 0: 136 switch (opc1) { 137 case 0: 138 switch (crm) { 139 case 0: 140 switch (opc2) { 141 case 1: 142 return MISCREG_CTR; 143 case 2: 144 return MISCREG_TCMTR; 145 case 3: 146 return MISCREG_TLBTR; 147 case 5: 148 return MISCREG_MPIDR; 149 case 6: 150 return MISCREG_REVIDR; 151 default: 152 return MISCREG_MIDR; 153 } 154 break; 155 case 1: 156 switch (opc2) { 157 case 0: 158 return MISCREG_ID_PFR0; 159 case 1: 160 return MISCREG_ID_PFR1; 161 case 2: 162 return MISCREG_ID_DFR0; 163 case 3: 164 return MISCREG_ID_AFR0; 165 case 4: 166 return MISCREG_ID_MMFR0; 167 case 5: 168 return MISCREG_ID_MMFR1; 169 case 6: 170 return MISCREG_ID_MMFR2; 171 case 7: 172 return MISCREG_ID_MMFR3; 173 } 174 break; 175 case 2: 176 switch (opc2) { 177 case 0: 178 return MISCREG_ID_ISAR0; 179 case 1: 180 return MISCREG_ID_ISAR1; 181 case 2: 182 return MISCREG_ID_ISAR2; 183 case 3: 184 return MISCREG_ID_ISAR3; 185 case 4: 186 return MISCREG_ID_ISAR4; 187 case 5: 188 return MISCREG_ID_ISAR5; 189 case 6: 190 case 7: 191 return MISCREG_RAZ; // read as zero 192 } 193 break; 194 default: 195 return MISCREG_RAZ; // read as zero 196 } 197 break; 198 case 1: 199 if (crm == 0) { 200 switch (opc2) { 201 case 0: 202 return MISCREG_CCSIDR; 203 case 1: 204 return MISCREG_CLIDR; 205 case 7: 206 return MISCREG_AIDR; 207 } 208 } 209 break; 210 case 2: 211 if (crm == 0 && opc2 == 0) { 212 return MISCREG_CSSELR; 213 } 214 break; 215 case 4: 216 if (crm == 0) { 217 if (opc2 == 0) 218 return MISCREG_VPIDR; 219 else if (opc2 == 5) 220 return MISCREG_VMPIDR; 221 } 222 break; 223 } 224 break; 225 case 1: 226 if (opc1 == 0) { 227 if (crm == 0) { 228 switch (opc2) { 229 case 0: 230 return MISCREG_SCTLR; 231 case 1: 232 return MISCREG_ACTLR; 233 case 0x2: 234 return MISCREG_CPACR; 235 } 236 } else if (crm == 1) { 237 switch (opc2) { 238 case 0: 239 return MISCREG_SCR; 240 case 1: 241 return MISCREG_SDER; 242 case 2: 243 return MISCREG_NSACR; 244 } 245 } 246 } else if (opc1 == 4) { 247 if (crm == 0) { 248 if (opc2 == 0) 249 return MISCREG_HSCTLR; 250 else if (opc2 == 1) 251 return MISCREG_HACTLR; 252 } else if (crm == 1) { 253 switch (opc2) { 254 case 0: 255 return MISCREG_HCR; 256 case 1: 257 return MISCREG_HDCR; 258 case 2: 259 return MISCREG_HCPTR; 260 case 3: 261 return MISCREG_HSTR; 262 case 7: 263 return MISCREG_HACR; 264 } 265 } 266 } 267 break; 268 case 2: 269 if (opc1 == 0 && crm == 0) { 270 switch (opc2) { 271 case 0: 272 return MISCREG_TTBR0; 273 case 1: 274 return MISCREG_TTBR1; 275 case 2: 276 return MISCREG_TTBCR; 277 } 278 } else if (opc1 == 4) { 279 if (crm == 0 && opc2 == 2) 280 return MISCREG_HTCR; 281 else if (crm == 1 && opc2 == 2) 282 return MISCREG_VTCR; 283 } 284 break; 285 case 3: 286 if (opc1 == 0 && crm == 0 && opc2 == 0) { 287 return MISCREG_DACR; 288 } 289 break;
|
| 290 case 4: 291 if (opc1 == 0 && crm == 6 && opc2 == 0) { 292 return MISCREG_ICC_PMR; 293 } 294 break;
|
290 case 5: 291 if (opc1 == 0) { 292 if (crm == 0) { 293 if (opc2 == 0) { 294 return MISCREG_DFSR; 295 } else if (opc2 == 1) { 296 return MISCREG_IFSR; 297 } 298 } else if (crm == 1) { 299 if (opc2 == 0) { 300 return MISCREG_ADFSR; 301 } else if (opc2 == 1) { 302 return MISCREG_AIFSR; 303 } 304 } 305 } else if (opc1 == 4) { 306 if (crm == 1) { 307 if (opc2 == 0) 308 return MISCREG_HADFSR; 309 else if (opc2 == 1) 310 return MISCREG_HAIFSR; 311 } else if (crm == 2 && opc2 == 0) { 312 return MISCREG_HSR; 313 } 314 } 315 break; 316 case 6: 317 if (opc1 == 0 && crm == 0) { 318 switch (opc2) { 319 case 0: 320 return MISCREG_DFAR; 321 case 2: 322 return MISCREG_IFAR; 323 } 324 } else if (opc1 == 4 && crm == 0) { 325 switch (opc2) { 326 case 0: 327 return MISCREG_HDFAR; 328 case 2: 329 return MISCREG_HIFAR; 330 case 4: 331 return MISCREG_HPFAR; 332 } 333 } 334 break; 335 case 7: 336 if (opc1 == 0) { 337 switch (crm) { 338 case 0: 339 if (opc2 == 4) { 340 return MISCREG_NOP; 341 } 342 break; 343 case 1: 344 switch (opc2) { 345 case 0: 346 return MISCREG_ICIALLUIS; 347 case 6: 348 return MISCREG_BPIALLIS; 349 } 350 break; 351 case 4: 352 if (opc2 == 0) { 353 return MISCREG_PAR; 354 } 355 break; 356 case 5: 357 switch (opc2) { 358 case 0: 359 return MISCREG_ICIALLU; 360 case 1: 361 return MISCREG_ICIMVAU; 362 case 4: 363 return MISCREG_CP15ISB; 364 case 6: 365 return MISCREG_BPIALL; 366 case 7: 367 return MISCREG_BPIMVA; 368 } 369 break; 370 case 6: 371 if (opc2 == 1) { 372 return MISCREG_DCIMVAC; 373 } else if (opc2 == 2) { 374 return MISCREG_DCISW; 375 } 376 break; 377 case 8: 378 switch (opc2) { 379 case 0: 380 return MISCREG_ATS1CPR; 381 case 1: 382 return MISCREG_ATS1CPW; 383 case 2: 384 return MISCREG_ATS1CUR; 385 case 3: 386 return MISCREG_ATS1CUW; 387 case 4: 388 return MISCREG_ATS12NSOPR; 389 case 5: 390 return MISCREG_ATS12NSOPW; 391 case 6: 392 return MISCREG_ATS12NSOUR; 393 case 7: 394 return MISCREG_ATS12NSOUW; 395 } 396 break; 397 case 10: 398 switch (opc2) { 399 case 1: 400 return MISCREG_DCCMVAC; 401 case 2: 402 return MISCREG_DCCSW; 403 case 4: 404 return MISCREG_CP15DSB; 405 case 5: 406 return MISCREG_CP15DMB; 407 } 408 break; 409 case 11: 410 if (opc2 == 1) { 411 return MISCREG_DCCMVAU; 412 } 413 break; 414 case 13: 415 if (opc2 == 1) { 416 return MISCREG_NOP; 417 } 418 break; 419 case 14: 420 if (opc2 == 1) { 421 return MISCREG_DCCIMVAC; 422 } else if (opc2 == 2) { 423 return MISCREG_DCCISW; 424 } 425 break; 426 } 427 } else if (opc1 == 4 && crm == 8) { 428 if (opc2 == 0) 429 return MISCREG_ATS1HR; 430 else if (opc2 == 1) 431 return MISCREG_ATS1HW; 432 } 433 break; 434 case 8: 435 if (opc1 == 0) { 436 switch (crm) { 437 case 3: 438 switch (opc2) { 439 case 0: 440 return MISCREG_TLBIALLIS; 441 case 1: 442 return MISCREG_TLBIMVAIS; 443 case 2: 444 return MISCREG_TLBIASIDIS; 445 case 3: 446 return MISCREG_TLBIMVAAIS; 447 case 5: 448 return MISCREG_TLBIMVALIS; 449 case 7: 450 return MISCREG_TLBIMVAALIS; 451 } 452 break; 453 case 5: 454 switch (opc2) { 455 case 0: 456 return MISCREG_ITLBIALL; 457 case 1: 458 return MISCREG_ITLBIMVA; 459 case 2: 460 return MISCREG_ITLBIASID; 461 } 462 break; 463 case 6: 464 switch (opc2) { 465 case 0: 466 return MISCREG_DTLBIALL; 467 case 1: 468 return MISCREG_DTLBIMVA; 469 case 2: 470 return MISCREG_DTLBIASID; 471 } 472 break; 473 case 7: 474 switch (opc2) { 475 case 0: 476 return MISCREG_TLBIALL; 477 case 1: 478 return MISCREG_TLBIMVA; 479 case 2: 480 return MISCREG_TLBIASID; 481 case 3: 482 return MISCREG_TLBIMVAA; 483 case 5: 484 return MISCREG_TLBIMVAL; 485 case 7: 486 return MISCREG_TLBIMVAAL; 487 } 488 break; 489 } 490 } else if (opc1 == 4) { 491 if (crm == 0) { 492 switch (opc2) { 493 case 1: 494 return MISCREG_TLBIIPAS2IS; 495 case 5: 496 return MISCREG_TLBIIPAS2LIS; 497 } 498 } else if (crm == 3) { 499 switch (opc2) { 500 case 0: 501 return MISCREG_TLBIALLHIS; 502 case 1: 503 return MISCREG_TLBIMVAHIS; 504 case 4: 505 return MISCREG_TLBIALLNSNHIS; 506 case 5: 507 return MISCREG_TLBIMVALHIS; 508 } 509 } else if (crm == 4) { 510 switch (opc2) { 511 case 1: 512 return MISCREG_TLBIIPAS2; 513 case 5: 514 return MISCREG_TLBIIPAS2L; 515 } 516 } else if (crm == 7) { 517 switch (opc2) { 518 case 0: 519 return MISCREG_TLBIALLH; 520 case 1: 521 return MISCREG_TLBIMVAH; 522 case 4: 523 return MISCREG_TLBIALLNSNH; 524 case 5: 525 return MISCREG_TLBIMVALH; 526 } 527 } 528 } 529 break; 530 case 9: 531 // Every cop register with CRn = 9 and CRm in 532 // {0-2}, {5-8} is implementation defined regardless 533 // of opc1 and opc2. 534 switch (crm) { 535 case 0: 536 case 1: 537 case 2: 538 case 5: 539 case 6: 540 case 7: 541 case 8: 542 return MISCREG_IMPDEF_UNIMPL; 543 } 544 if (opc1 == 0) { 545 switch (crm) { 546 case 12: 547 switch (opc2) { 548 case 0: 549 return MISCREG_PMCR; 550 case 1: 551 return MISCREG_PMCNTENSET; 552 case 2: 553 return MISCREG_PMCNTENCLR; 554 case 3: 555 return MISCREG_PMOVSR; 556 case 4: 557 return MISCREG_PMSWINC; 558 case 5: 559 return MISCREG_PMSELR; 560 case 6: 561 return MISCREG_PMCEID0; 562 case 7: 563 return MISCREG_PMCEID1; 564 } 565 break; 566 case 13: 567 switch (opc2) { 568 case 0: 569 return MISCREG_PMCCNTR; 570 case 1: 571 // Selector is PMSELR.SEL 572 return MISCREG_PMXEVTYPER_PMCCFILTR; 573 case 2: 574 return MISCREG_PMXEVCNTR; 575 } 576 break; 577 case 14: 578 switch (opc2) { 579 case 0: 580 return MISCREG_PMUSERENR; 581 case 1: 582 return MISCREG_PMINTENSET; 583 case 2: 584 return MISCREG_PMINTENCLR; 585 case 3: 586 return MISCREG_PMOVSSET; 587 } 588 break; 589 } 590 } else if (opc1 == 1) { 591 switch (crm) { 592 case 0: 593 switch (opc2) { 594 case 2: // L2CTLR, L2 Control Register 595 return MISCREG_L2CTLR; 596 case 3: 597 return MISCREG_L2ECTLR; 598 } 599 break; 600 break; 601 } 602 } 603 break; 604 case 10: 605 if (opc1 == 0) { 606 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown 607 if (crm < 2) { 608 return MISCREG_IMPDEF_UNIMPL; 609 } else if (crm == 2) { // TEX Remap Registers 610 if (opc2 == 0) { 611 // Selector is TTBCR.EAE 612 return MISCREG_PRRR_MAIR0; 613 } else if (opc2 == 1) { 614 // Selector is TTBCR.EAE 615 return MISCREG_NMRR_MAIR1; 616 } 617 } else if (crm == 3) { 618 if (opc2 == 0) { 619 return MISCREG_AMAIR0; 620 } else if (opc2 == 1) { 621 return MISCREG_AMAIR1; 622 } 623 } 624 } else if (opc1 == 4) { 625 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown 626 if (crm == 2) { 627 if (opc2 == 0) 628 return MISCREG_HMAIR0; 629 else if (opc2 == 1) 630 return MISCREG_HMAIR1; 631 } else if (crm == 3) { 632 if (opc2 == 0) 633 return MISCREG_HAMAIR0; 634 else if (opc2 == 1) 635 return MISCREG_HAMAIR1; 636 } 637 } 638 break; 639 case 11: 640 if (opc1 <=7) { 641 switch (crm) { 642 case 0: 643 case 1: 644 case 2: 645 case 3: 646 case 4: 647 case 5: 648 case 6: 649 case 7: 650 case 8: 651 case 15: 652 // Reserved for DMA operations for TCM access 653 return MISCREG_IMPDEF_UNIMPL; 654 default: 655 break; 656 } 657 } 658 break; 659 case 12: 660 if (opc1 == 0) { 661 if (crm == 0) { 662 if (opc2 == 0) { 663 return MISCREG_VBAR; 664 } else if (opc2 == 1) { 665 return MISCREG_MVBAR; 666 } 667 } else if (crm == 1) { 668 if (opc2 == 0) { 669 return MISCREG_ISR; 670 }
| 295 case 5: 296 if (opc1 == 0) { 297 if (crm == 0) { 298 if (opc2 == 0) { 299 return MISCREG_DFSR; 300 } else if (opc2 == 1) { 301 return MISCREG_IFSR; 302 } 303 } else if (crm == 1) { 304 if (opc2 == 0) { 305 return MISCREG_ADFSR; 306 } else if (opc2 == 1) { 307 return MISCREG_AIFSR; 308 } 309 } 310 } else if (opc1 == 4) { 311 if (crm == 1) { 312 if (opc2 == 0) 313 return MISCREG_HADFSR; 314 else if (opc2 == 1) 315 return MISCREG_HAIFSR; 316 } else if (crm == 2 && opc2 == 0) { 317 return MISCREG_HSR; 318 } 319 } 320 break; 321 case 6: 322 if (opc1 == 0 && crm == 0) { 323 switch (opc2) { 324 case 0: 325 return MISCREG_DFAR; 326 case 2: 327 return MISCREG_IFAR; 328 } 329 } else if (opc1 == 4 && crm == 0) { 330 switch (opc2) { 331 case 0: 332 return MISCREG_HDFAR; 333 case 2: 334 return MISCREG_HIFAR; 335 case 4: 336 return MISCREG_HPFAR; 337 } 338 } 339 break; 340 case 7: 341 if (opc1 == 0) { 342 switch (crm) { 343 case 0: 344 if (opc2 == 4) { 345 return MISCREG_NOP; 346 } 347 break; 348 case 1: 349 switch (opc2) { 350 case 0: 351 return MISCREG_ICIALLUIS; 352 case 6: 353 return MISCREG_BPIALLIS; 354 } 355 break; 356 case 4: 357 if (opc2 == 0) { 358 return MISCREG_PAR; 359 } 360 break; 361 case 5: 362 switch (opc2) { 363 case 0: 364 return MISCREG_ICIALLU; 365 case 1: 366 return MISCREG_ICIMVAU; 367 case 4: 368 return MISCREG_CP15ISB; 369 case 6: 370 return MISCREG_BPIALL; 371 case 7: 372 return MISCREG_BPIMVA; 373 } 374 break; 375 case 6: 376 if (opc2 == 1) { 377 return MISCREG_DCIMVAC; 378 } else if (opc2 == 2) { 379 return MISCREG_DCISW; 380 } 381 break; 382 case 8: 383 switch (opc2) { 384 case 0: 385 return MISCREG_ATS1CPR; 386 case 1: 387 return MISCREG_ATS1CPW; 388 case 2: 389 return MISCREG_ATS1CUR; 390 case 3: 391 return MISCREG_ATS1CUW; 392 case 4: 393 return MISCREG_ATS12NSOPR; 394 case 5: 395 return MISCREG_ATS12NSOPW; 396 case 6: 397 return MISCREG_ATS12NSOUR; 398 case 7: 399 return MISCREG_ATS12NSOUW; 400 } 401 break; 402 case 10: 403 switch (opc2) { 404 case 1: 405 return MISCREG_DCCMVAC; 406 case 2: 407 return MISCREG_DCCSW; 408 case 4: 409 return MISCREG_CP15DSB; 410 case 5: 411 return MISCREG_CP15DMB; 412 } 413 break; 414 case 11: 415 if (opc2 == 1) { 416 return MISCREG_DCCMVAU; 417 } 418 break; 419 case 13: 420 if (opc2 == 1) { 421 return MISCREG_NOP; 422 } 423 break; 424 case 14: 425 if (opc2 == 1) { 426 return MISCREG_DCCIMVAC; 427 } else if (opc2 == 2) { 428 return MISCREG_DCCISW; 429 } 430 break; 431 } 432 } else if (opc1 == 4 && crm == 8) { 433 if (opc2 == 0) 434 return MISCREG_ATS1HR; 435 else if (opc2 == 1) 436 return MISCREG_ATS1HW; 437 } 438 break; 439 case 8: 440 if (opc1 == 0) { 441 switch (crm) { 442 case 3: 443 switch (opc2) { 444 case 0: 445 return MISCREG_TLBIALLIS; 446 case 1: 447 return MISCREG_TLBIMVAIS; 448 case 2: 449 return MISCREG_TLBIASIDIS; 450 case 3: 451 return MISCREG_TLBIMVAAIS; 452 case 5: 453 return MISCREG_TLBIMVALIS; 454 case 7: 455 return MISCREG_TLBIMVAALIS; 456 } 457 break; 458 case 5: 459 switch (opc2) { 460 case 0: 461 return MISCREG_ITLBIALL; 462 case 1: 463 return MISCREG_ITLBIMVA; 464 case 2: 465 return MISCREG_ITLBIASID; 466 } 467 break; 468 case 6: 469 switch (opc2) { 470 case 0: 471 return MISCREG_DTLBIALL; 472 case 1: 473 return MISCREG_DTLBIMVA; 474 case 2: 475 return MISCREG_DTLBIASID; 476 } 477 break; 478 case 7: 479 switch (opc2) { 480 case 0: 481 return MISCREG_TLBIALL; 482 case 1: 483 return MISCREG_TLBIMVA; 484 case 2: 485 return MISCREG_TLBIASID; 486 case 3: 487 return MISCREG_TLBIMVAA; 488 case 5: 489 return MISCREG_TLBIMVAL; 490 case 7: 491 return MISCREG_TLBIMVAAL; 492 } 493 break; 494 } 495 } else if (opc1 == 4) { 496 if (crm == 0) { 497 switch (opc2) { 498 case 1: 499 return MISCREG_TLBIIPAS2IS; 500 case 5: 501 return MISCREG_TLBIIPAS2LIS; 502 } 503 } else if (crm == 3) { 504 switch (opc2) { 505 case 0: 506 return MISCREG_TLBIALLHIS; 507 case 1: 508 return MISCREG_TLBIMVAHIS; 509 case 4: 510 return MISCREG_TLBIALLNSNHIS; 511 case 5: 512 return MISCREG_TLBIMVALHIS; 513 } 514 } else if (crm == 4) { 515 switch (opc2) { 516 case 1: 517 return MISCREG_TLBIIPAS2; 518 case 5: 519 return MISCREG_TLBIIPAS2L; 520 } 521 } else if (crm == 7) { 522 switch (opc2) { 523 case 0: 524 return MISCREG_TLBIALLH; 525 case 1: 526 return MISCREG_TLBIMVAH; 527 case 4: 528 return MISCREG_TLBIALLNSNH; 529 case 5: 530 return MISCREG_TLBIMVALH; 531 } 532 } 533 } 534 break; 535 case 9: 536 // Every cop register with CRn = 9 and CRm in 537 // {0-2}, {5-8} is implementation defined regardless 538 // of opc1 and opc2. 539 switch (crm) { 540 case 0: 541 case 1: 542 case 2: 543 case 5: 544 case 6: 545 case 7: 546 case 8: 547 return MISCREG_IMPDEF_UNIMPL; 548 } 549 if (opc1 == 0) { 550 switch (crm) { 551 case 12: 552 switch (opc2) { 553 case 0: 554 return MISCREG_PMCR; 555 case 1: 556 return MISCREG_PMCNTENSET; 557 case 2: 558 return MISCREG_PMCNTENCLR; 559 case 3: 560 return MISCREG_PMOVSR; 561 case 4: 562 return MISCREG_PMSWINC; 563 case 5: 564 return MISCREG_PMSELR; 565 case 6: 566 return MISCREG_PMCEID0; 567 case 7: 568 return MISCREG_PMCEID1; 569 } 570 break; 571 case 13: 572 switch (opc2) { 573 case 0: 574 return MISCREG_PMCCNTR; 575 case 1: 576 // Selector is PMSELR.SEL 577 return MISCREG_PMXEVTYPER_PMCCFILTR; 578 case 2: 579 return MISCREG_PMXEVCNTR; 580 } 581 break; 582 case 14: 583 switch (opc2) { 584 case 0: 585 return MISCREG_PMUSERENR; 586 case 1: 587 return MISCREG_PMINTENSET; 588 case 2: 589 return MISCREG_PMINTENCLR; 590 case 3: 591 return MISCREG_PMOVSSET; 592 } 593 break; 594 } 595 } else if (opc1 == 1) { 596 switch (crm) { 597 case 0: 598 switch (opc2) { 599 case 2: // L2CTLR, L2 Control Register 600 return MISCREG_L2CTLR; 601 case 3: 602 return MISCREG_L2ECTLR; 603 } 604 break; 605 break; 606 } 607 } 608 break; 609 case 10: 610 if (opc1 == 0) { 611 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown 612 if (crm < 2) { 613 return MISCREG_IMPDEF_UNIMPL; 614 } else if (crm == 2) { // TEX Remap Registers 615 if (opc2 == 0) { 616 // Selector is TTBCR.EAE 617 return MISCREG_PRRR_MAIR0; 618 } else if (opc2 == 1) { 619 // Selector is TTBCR.EAE 620 return MISCREG_NMRR_MAIR1; 621 } 622 } else if (crm == 3) { 623 if (opc2 == 0) { 624 return MISCREG_AMAIR0; 625 } else if (opc2 == 1) { 626 return MISCREG_AMAIR1; 627 } 628 } 629 } else if (opc1 == 4) { 630 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown 631 if (crm == 2) { 632 if (opc2 == 0) 633 return MISCREG_HMAIR0; 634 else if (opc2 == 1) 635 return MISCREG_HMAIR1; 636 } else if (crm == 3) { 637 if (opc2 == 0) 638 return MISCREG_HAMAIR0; 639 else if (opc2 == 1) 640 return MISCREG_HAMAIR1; 641 } 642 } 643 break; 644 case 11: 645 if (opc1 <=7) { 646 switch (crm) { 647 case 0: 648 case 1: 649 case 2: 650 case 3: 651 case 4: 652 case 5: 653 case 6: 654 case 7: 655 case 8: 656 case 15: 657 // Reserved for DMA operations for TCM access 658 return MISCREG_IMPDEF_UNIMPL; 659 default: 660 break; 661 } 662 } 663 break; 664 case 12: 665 if (opc1 == 0) { 666 if (crm == 0) { 667 if (opc2 == 0) { 668 return MISCREG_VBAR; 669 } else if (opc2 == 1) { 670 return MISCREG_MVBAR; 671 } 672 } else if (crm == 1) { 673 if (opc2 == 0) { 674 return MISCREG_ISR; 675 }
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| 676 } else if (crm == 8) { 677 switch (opc2) { 678 case 0: 679 return MISCREG_ICC_IAR0; 680 case 1: 681 return MISCREG_ICC_EOIR0; 682 case 2: 683 return MISCREG_ICC_HPPIR0; 684 case 3: 685 return MISCREG_ICC_BPR0; 686 case 4: 687 return MISCREG_ICC_AP0R0; 688 case 5: 689 return MISCREG_ICC_AP0R1; 690 case 6: 691 return MISCREG_ICC_AP0R2; 692 case 7: 693 return MISCREG_ICC_AP0R3; 694 } 695 } else if (crm == 9) { 696 switch (opc2) { 697 case 0: 698 return MISCREG_ICC_AP1R0; 699 case 1: 700 return MISCREG_ICC_AP1R1; 701 case 2: 702 return MISCREG_ICC_AP1R2; 703 case 3: 704 return MISCREG_ICC_AP1R3; 705 } 706 } else if (crm == 11) { 707 switch (opc2) { 708 case 1: 709 return MISCREG_ICC_DIR; 710 case 3: 711 return MISCREG_ICC_RPR; 712 } 713 } else if (crm == 12) { 714 switch (opc2) { 715 case 0: 716 return MISCREG_ICC_IAR1; 717 case 1: 718 return MISCREG_ICC_EOIR1; 719 case 2: 720 return MISCREG_ICC_HPPIR1; 721 case 3: 722 return MISCREG_ICC_BPR1; 723 case 4: 724 return MISCREG_ICC_CTLR; 725 case 5: 726 return MISCREG_ICC_SRE; 727 case 6: 728 return MISCREG_ICC_IGRPEN0; 729 case 7: 730 return MISCREG_ICC_IGRPEN1; 731 }
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671 } 672 } else if (opc1 == 4) {
| 732 } 733 } else if (opc1 == 4) {
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673 if (crm == 0 && opc2 == 0)
| 734 if (crm == 0 && opc2 == 0) {
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674 return MISCREG_HVBAR;
| 735 return MISCREG_HVBAR;
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| 736 } else if (crm == 8) { 737 switch (opc2) { 738 case 0: 739 return MISCREG_ICH_AP0R0; 740 case 1: 741 return MISCREG_ICH_AP0R1; 742 case 2: 743 return MISCREG_ICH_AP0R2; 744 case 3: 745 return MISCREG_ICH_AP0R3; 746 } 747 } else if (crm == 9) { 748 switch (opc2) { 749 case 0: 750 return MISCREG_ICH_AP1R0; 751 case 1: 752 return MISCREG_ICH_AP1R1; 753 case 2: 754 return MISCREG_ICH_AP1R2; 755 case 3: 756 return MISCREG_ICH_AP1R3; 757 case 5: 758 return MISCREG_ICC_HSRE; 759 } 760 } else if (crm == 11) { 761 switch (opc2) { 762 case 0: 763 return MISCREG_ICH_HCR; 764 case 1: 765 return MISCREG_ICH_VTR; 766 case 2: 767 return MISCREG_ICH_MISR; 768 case 3: 769 return MISCREG_ICH_EISR; 770 case 5: 771 return MISCREG_ICH_ELRSR; 772 case 7: 773 return MISCREG_ICH_VMCR; 774 } 775 } else if (crm == 12) { 776 switch (opc2) { 777 case 0: 778 return MISCREG_ICH_LR0; 779 case 1: 780 return MISCREG_ICH_LR1; 781 case 2: 782 return MISCREG_ICH_LR2; 783 case 3: 784 return MISCREG_ICH_LR3; 785 case 4: 786 return MISCREG_ICH_LR4; 787 case 5: 788 return MISCREG_ICH_LR5; 789 case 6: 790 return MISCREG_ICH_LR6; 791 case 7: 792 return MISCREG_ICH_LR7; 793 } 794 } else if (crm == 13) { 795 switch (opc2) { 796 case 0: 797 return MISCREG_ICH_LR8; 798 case 1: 799 return MISCREG_ICH_LR9; 800 case 2: 801 return MISCREG_ICH_LR10; 802 case 3: 803 return MISCREG_ICH_LR11; 804 case 4: 805 return MISCREG_ICH_LR12; 806 case 5: 807 return MISCREG_ICH_LR13; 808 case 6: 809 return MISCREG_ICH_LR14; 810 case 7: 811 return MISCREG_ICH_LR15; 812 } 813 } else if (crm == 14) { 814 switch (opc2) { 815 case 0: 816 return MISCREG_ICH_LRC0; 817 case 1: 818 return MISCREG_ICH_LRC1; 819 case 2: 820 return MISCREG_ICH_LRC2; 821 case 3: 822 return MISCREG_ICH_LRC3; 823 case 4: 824 return MISCREG_ICH_LRC4; 825 case 5: 826 return MISCREG_ICH_LRC5; 827 case 6: 828 return MISCREG_ICH_LRC6; 829 case 7: 830 return MISCREG_ICH_LRC7; 831 } 832 } else if (crm == 15) { 833 switch (opc2) { 834 case 0: 835 return MISCREG_ICH_LRC8; 836 case 1: 837 return MISCREG_ICH_LRC9; 838 case 2: 839 return MISCREG_ICH_LRC10; 840 case 3: 841 return MISCREG_ICH_LRC11; 842 case 4: 843 return MISCREG_ICH_LRC12; 844 case 5: 845 return MISCREG_ICH_LRC13; 846 case 6: 847 return MISCREG_ICH_LRC14; 848 case 7: 849 return MISCREG_ICH_LRC15; 850 } 851 } 852 } else if (opc1 == 6) { 853 if (crm == 12) { 854 switch (opc2) { 855 case 4: 856 return MISCREG_ICC_MCTLR; 857 case 5: 858 return MISCREG_ICC_MSRE; 859 case 7: 860 return MISCREG_ICC_MGRPEN1; 861 } 862 }
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675 } 676 break; 677 case 13: 678 if (opc1 == 0) { 679 if (crm == 0) { 680 switch (opc2) { 681 case 0: 682 return MISCREG_FCSEIDR; 683 case 1: 684 return MISCREG_CONTEXTIDR; 685 case 2: 686 return MISCREG_TPIDRURW; 687 case 3: 688 return MISCREG_TPIDRURO; 689 case 4: 690 return MISCREG_TPIDRPRW; 691 } 692 } 693 } else if (opc1 == 4) { 694 if (crm == 0 && opc2 == 2) 695 return MISCREG_HTPIDR; 696 } 697 break; 698 case 14: 699 if (opc1 == 0) { 700 switch (crm) { 701 case 0: 702 if (opc2 == 0) 703 return MISCREG_CNTFRQ; 704 break; 705 case 1: 706 if (opc2 == 0) 707 return MISCREG_CNTKCTL; 708 break; 709 case 2: 710 if (opc2 == 0) 711 return MISCREG_CNTP_TVAL; 712 else if (opc2 == 1) 713 return MISCREG_CNTP_CTL; 714 break; 715 case 3: 716 if (opc2 == 0) 717 return MISCREG_CNTV_TVAL; 718 else if (opc2 == 1) 719 return MISCREG_CNTV_CTL; 720 break; 721 } 722 } else if (opc1 == 4) { 723 if (crm == 1 && opc2 == 0) { 724 return MISCREG_CNTHCTL; 725 } else if (crm == 2) { 726 if (opc2 == 0) 727 return MISCREG_CNTHP_TVAL; 728 else if (opc2 == 1) 729 return MISCREG_CNTHP_CTL; 730 } 731 } 732 break; 733 case 15: 734 // Implementation defined 735 return MISCREG_IMPDEF_UNIMPL; 736 } 737 // Unrecognized register 738 return MISCREG_CP15_UNIMPL; 739} 740 741MiscRegIndex 742decodeCP15Reg64(unsigned crm, unsigned opc1) 743{ 744 switch (crm) { 745 case 2: 746 switch (opc1) { 747 case 0: 748 return MISCREG_TTBR0; 749 case 1: 750 return MISCREG_TTBR1; 751 case 4: 752 return MISCREG_HTTBR; 753 case 6: 754 return MISCREG_VTTBR; 755 } 756 break; 757 case 7: 758 if (opc1 == 0) 759 return MISCREG_PAR; 760 break; 761 case 14: 762 switch (opc1) { 763 case 0: 764 return MISCREG_CNTPCT; 765 case 1: 766 return MISCREG_CNTVCT; 767 case 2: 768 return MISCREG_CNTP_CVAL; 769 case 3: 770 return MISCREG_CNTV_CVAL; 771 case 4: 772 return MISCREG_CNTVOFF; 773 case 6: 774 return MISCREG_CNTHP_CVAL; 775 } 776 break; 777 case 15: 778 if (opc1 == 0) 779 return MISCREG_CPUMERRSR; 780 else if (opc1 == 1) 781 return MISCREG_L2MERRSR; 782 break; 783 } 784 // Unrecognized register 785 return MISCREG_CP15_UNIMPL; 786} 787 788std::tuple<bool, bool> 789canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) 790{ 791 bool secure = !scr.ns; 792 bool canRead = false; 793 bool undefined = false; 794 795 switch (cpsr.mode) { 796 case MODE_USER: 797 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 798 miscRegInfo[reg][MISCREG_USR_NS_RD]; 799 break; 800 case MODE_FIQ: 801 case MODE_IRQ: 802 case MODE_SVC: 803 case MODE_ABORT: 804 case MODE_UNDEFINED: 805 case MODE_SYSTEM: 806 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 807 miscRegInfo[reg][MISCREG_PRI_NS_RD]; 808 break; 809 case MODE_MON: 810 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 811 miscRegInfo[reg][MISCREG_MON_NS1_RD]; 812 break; 813 case MODE_HYP: 814 canRead = miscRegInfo[reg][MISCREG_HYP_RD]; 815 break; 816 default: 817 undefined = true; 818 } 819 // can't do permissions checkes on the root of a banked pair of regs 820 assert(!miscRegInfo[reg][MISCREG_BANKED]); 821 return std::make_tuple(canRead, undefined); 822} 823 824std::tuple<bool, bool> 825canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) 826{ 827 bool secure = !scr.ns; 828 bool canWrite = false; 829 bool undefined = false; 830 831 switch (cpsr.mode) { 832 case MODE_USER: 833 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 834 miscRegInfo[reg][MISCREG_USR_NS_WR]; 835 break; 836 case MODE_FIQ: 837 case MODE_IRQ: 838 case MODE_SVC: 839 case MODE_ABORT: 840 case MODE_UNDEFINED: 841 case MODE_SYSTEM: 842 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 843 miscRegInfo[reg][MISCREG_PRI_NS_WR]; 844 break; 845 case MODE_MON: 846 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 847 miscRegInfo[reg][MISCREG_MON_NS1_WR]; 848 break; 849 case MODE_HYP: 850 canWrite = miscRegInfo[reg][MISCREG_HYP_WR]; 851 break; 852 default: 853 undefined = true; 854 } 855 // can't do permissions checkes on the root of a banked pair of regs 856 assert(!miscRegInfo[reg][MISCREG_BANKED]); 857 return std::make_tuple(canWrite, undefined); 858} 859 860int 861snsBankedIndex(MiscRegIndex reg, ThreadContext *tc) 862{ 863 SCR scr = tc->readMiscReg(MISCREG_SCR); 864 return snsBankedIndex(reg, tc, scr.ns); 865} 866 867int 868snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns) 869{ 870 int reg_as_int = static_cast<int>(reg); 871 if (miscRegInfo[reg][MISCREG_BANKED]) { 872 reg_as_int += (ArmSystem::haveSecurity(tc) && 873 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1; 874 } 875 return reg_as_int; 876} 877 878 879/** 880 * If the reg is a child reg of a banked set, then the parent is the last 881 * banked one in the list. This is messy, and the wish is to eventually have 882 * the bitmap replaced with a better data structure. the preUnflatten function 883 * initializes a lookup table to speed up the search for these banked 884 * registers. 885 */ 886 887int unflattenResultMiscReg[NUM_MISCREGS]; 888 889void 890preUnflattenMiscReg() 891{ 892 int reg = -1; 893 for (int i = 0 ; i < NUM_MISCREGS; i++){ 894 if (miscRegInfo[i][MISCREG_BANKED]) 895 reg = i; 896 if (miscRegInfo[i][MISCREG_BANKED_CHILD]) 897 unflattenResultMiscReg[i] = reg; 898 else 899 unflattenResultMiscReg[i] = i; 900 // if this assert fails, no parent was found, and something is broken 901 assert(unflattenResultMiscReg[i] > -1); 902 } 903} 904 905int 906unflattenMiscReg(int reg) 907{ 908 return unflattenResultMiscReg[reg]; 909} 910 911bool 912canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 913{ 914 // Check for SP_EL0 access while SPSEL == 0 915 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) 916 return false; 917 918 // Check for RVBAR access 919 if (reg == MISCREG_RVBAR_EL1) { 920 ExceptionLevel highest_el = ArmSystem::highestEL(tc); 921 if (highest_el == EL2 || highest_el == EL3) 922 return false; 923 } 924 if (reg == MISCREG_RVBAR_EL2) { 925 ExceptionLevel highest_el = ArmSystem::highestEL(tc); 926 if (highest_el == EL3) 927 return false; 928 } 929 930 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; 931 932 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) { 933 case EL0: 934 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 935 miscRegInfo[reg][MISCREG_USR_NS_RD]; 936 case EL1: 937 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 938 miscRegInfo[reg][MISCREG_PRI_NS_RD]; 939 case EL2: 940 return miscRegInfo[reg][MISCREG_HYP_RD]; 941 case EL3: 942 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 943 miscRegInfo[reg][MISCREG_MON_NS1_RD]; 944 default: 945 panic("Invalid exception level"); 946 } 947} 948 949bool 950canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 951{ 952 // Check for SP_EL0 access while SPSEL == 0 953 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) 954 return false; 955 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode); 956 if (reg == MISCREG_DAIF) { 957 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 958 if (el == EL0 && !sctlr.uma) 959 return false; 960 } 961 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) { 962 // In syscall-emulation mode, this test is skipped and DCZVA is always 963 // allowed at EL0 964 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 965 if (el == EL0 && !sctlr.dze) 966 return false; 967 } 968 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) { 969 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 970 if (el == EL0 && !sctlr.uci) 971 return false; 972 } 973 974 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; 975 976 switch (el) { 977 case EL0: 978 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 979 miscRegInfo[reg][MISCREG_USR_NS_WR]; 980 case EL1: 981 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 982 miscRegInfo[reg][MISCREG_PRI_NS_WR]; 983 case EL2: 984 return miscRegInfo[reg][MISCREG_HYP_WR]; 985 case EL3: 986 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 987 miscRegInfo[reg][MISCREG_MON_NS1_WR]; 988 default: 989 panic("Invalid exception level"); 990 } 991} 992 993MiscRegIndex 994decodeAArch64SysReg(unsigned op0, unsigned op1, 995 unsigned crn, unsigned crm, 996 unsigned op2) 997{ 998 switch (op0) { 999 case 1: 1000 switch (crn) { 1001 case 7: 1002 switch (op1) { 1003 case 0: 1004 switch (crm) { 1005 case 1: 1006 switch (op2) { 1007 case 0: 1008 return MISCREG_IC_IALLUIS; 1009 } 1010 break; 1011 case 5: 1012 switch (op2) { 1013 case 0: 1014 return MISCREG_IC_IALLU; 1015 } 1016 break; 1017 case 6: 1018 switch (op2) { 1019 case 1: 1020 return MISCREG_DC_IVAC_Xt; 1021 case 2: 1022 return MISCREG_DC_ISW_Xt; 1023 } 1024 break; 1025 case 8: 1026 switch (op2) { 1027 case 0: 1028 return MISCREG_AT_S1E1R_Xt; 1029 case 1: 1030 return MISCREG_AT_S1E1W_Xt; 1031 case 2: 1032 return MISCREG_AT_S1E0R_Xt; 1033 case 3: 1034 return MISCREG_AT_S1E0W_Xt; 1035 } 1036 break; 1037 case 10: 1038 switch (op2) { 1039 case 2: 1040 return MISCREG_DC_CSW_Xt; 1041 } 1042 break; 1043 case 14: 1044 switch (op2) { 1045 case 2: 1046 return MISCREG_DC_CISW_Xt; 1047 } 1048 break; 1049 } 1050 break; 1051 case 3: 1052 switch (crm) { 1053 case 4: 1054 switch (op2) { 1055 case 1: 1056 return MISCREG_DC_ZVA_Xt; 1057 } 1058 break; 1059 case 5: 1060 switch (op2) { 1061 case 1: 1062 return MISCREG_IC_IVAU_Xt; 1063 } 1064 break; 1065 case 10: 1066 switch (op2) { 1067 case 1: 1068 return MISCREG_DC_CVAC_Xt; 1069 } 1070 break; 1071 case 11: 1072 switch (op2) { 1073 case 1: 1074 return MISCREG_DC_CVAU_Xt; 1075 } 1076 break; 1077 case 14: 1078 switch (op2) { 1079 case 1: 1080 return MISCREG_DC_CIVAC_Xt; 1081 } 1082 break; 1083 } 1084 break; 1085 case 4: 1086 switch (crm) { 1087 case 8: 1088 switch (op2) { 1089 case 0: 1090 return MISCREG_AT_S1E2R_Xt; 1091 case 1: 1092 return MISCREG_AT_S1E2W_Xt; 1093 case 4: 1094 return MISCREG_AT_S12E1R_Xt; 1095 case 5: 1096 return MISCREG_AT_S12E1W_Xt; 1097 case 6: 1098 return MISCREG_AT_S12E0R_Xt; 1099 case 7: 1100 return MISCREG_AT_S12E0W_Xt; 1101 } 1102 break; 1103 } 1104 break; 1105 case 6: 1106 switch (crm) { 1107 case 8: 1108 switch (op2) { 1109 case 0: 1110 return MISCREG_AT_S1E3R_Xt; 1111 case 1: 1112 return MISCREG_AT_S1E3W_Xt; 1113 } 1114 break; 1115 } 1116 break; 1117 } 1118 break; 1119 case 8: 1120 switch (op1) { 1121 case 0: 1122 switch (crm) { 1123 case 3: 1124 switch (op2) { 1125 case 0: 1126 return MISCREG_TLBI_VMALLE1IS; 1127 case 1: 1128 return MISCREG_TLBI_VAE1IS_Xt; 1129 case 2: 1130 return MISCREG_TLBI_ASIDE1IS_Xt; 1131 case 3: 1132 return MISCREG_TLBI_VAAE1IS_Xt; 1133 case 5: 1134 return MISCREG_TLBI_VALE1IS_Xt; 1135 case 7: 1136 return MISCREG_TLBI_VAALE1IS_Xt; 1137 } 1138 break; 1139 case 7: 1140 switch (op2) { 1141 case 0: 1142 return MISCREG_TLBI_VMALLE1; 1143 case 1: 1144 return MISCREG_TLBI_VAE1_Xt; 1145 case 2: 1146 return MISCREG_TLBI_ASIDE1_Xt; 1147 case 3: 1148 return MISCREG_TLBI_VAAE1_Xt; 1149 case 5: 1150 return MISCREG_TLBI_VALE1_Xt; 1151 case 7: 1152 return MISCREG_TLBI_VAALE1_Xt; 1153 } 1154 break; 1155 } 1156 break; 1157 case 4: 1158 switch (crm) { 1159 case 0: 1160 switch (op2) { 1161 case 1: 1162 return MISCREG_TLBI_IPAS2E1IS_Xt; 1163 case 5: 1164 return MISCREG_TLBI_IPAS2LE1IS_Xt; 1165 } 1166 break; 1167 case 3: 1168 switch (op2) { 1169 case 0: 1170 return MISCREG_TLBI_ALLE2IS; 1171 case 1: 1172 return MISCREG_TLBI_VAE2IS_Xt; 1173 case 4: 1174 return MISCREG_TLBI_ALLE1IS; 1175 case 5: 1176 return MISCREG_TLBI_VALE2IS_Xt; 1177 case 6: 1178 return MISCREG_TLBI_VMALLS12E1IS; 1179 } 1180 break; 1181 case 4: 1182 switch (op2) { 1183 case 1: 1184 return MISCREG_TLBI_IPAS2E1_Xt; 1185 case 5: 1186 return MISCREG_TLBI_IPAS2LE1_Xt; 1187 } 1188 break; 1189 case 7: 1190 switch (op2) { 1191 case 0: 1192 return MISCREG_TLBI_ALLE2; 1193 case 1: 1194 return MISCREG_TLBI_VAE2_Xt; 1195 case 4: 1196 return MISCREG_TLBI_ALLE1; 1197 case 5: 1198 return MISCREG_TLBI_VALE2_Xt; 1199 case 6: 1200 return MISCREG_TLBI_VMALLS12E1; 1201 } 1202 break; 1203 } 1204 break; 1205 case 6: 1206 switch (crm) { 1207 case 3: 1208 switch (op2) { 1209 case 0: 1210 return MISCREG_TLBI_ALLE3IS; 1211 case 1: 1212 return MISCREG_TLBI_VAE3IS_Xt; 1213 case 5: 1214 return MISCREG_TLBI_VALE3IS_Xt; 1215 } 1216 break; 1217 case 7: 1218 switch (op2) { 1219 case 0: 1220 return MISCREG_TLBI_ALLE3; 1221 case 1: 1222 return MISCREG_TLBI_VAE3_Xt; 1223 case 5: 1224 return MISCREG_TLBI_VALE3_Xt; 1225 } 1226 break; 1227 } 1228 break; 1229 } 1230 break; 1231 case 11: 1232 case 15: 1233 // SYS Instruction with CRn = { 11, 15 } 1234 // (Trappable by HCR_EL2.TIDCP) 1235 return MISCREG_IMPDEF_UNIMPL; 1236 } 1237 break; 1238 case 2: 1239 switch (crn) { 1240 case 0: 1241 switch (op1) { 1242 case 0: 1243 switch (crm) { 1244 case 0: 1245 switch (op2) { 1246 case 2: 1247 return MISCREG_OSDTRRX_EL1; 1248 case 4: 1249 return MISCREG_DBGBVR0_EL1; 1250 case 5: 1251 return MISCREG_DBGBCR0_EL1; 1252 case 6: 1253 return MISCREG_DBGWVR0_EL1; 1254 case 7: 1255 return MISCREG_DBGWCR0_EL1; 1256 } 1257 break; 1258 case 1: 1259 switch (op2) { 1260 case 4: 1261 return MISCREG_DBGBVR1_EL1; 1262 case 5: 1263 return MISCREG_DBGBCR1_EL1; 1264 case 6: 1265 return MISCREG_DBGWVR1_EL1; 1266 case 7: 1267 return MISCREG_DBGWCR1_EL1; 1268 } 1269 break; 1270 case 2: 1271 switch (op2) { 1272 case 0: 1273 return MISCREG_MDCCINT_EL1; 1274 case 2: 1275 return MISCREG_MDSCR_EL1; 1276 case 4: 1277 return MISCREG_DBGBVR2_EL1; 1278 case 5: 1279 return MISCREG_DBGBCR2_EL1; 1280 case 6: 1281 return MISCREG_DBGWVR2_EL1; 1282 case 7: 1283 return MISCREG_DBGWCR2_EL1; 1284 } 1285 break; 1286 case 3: 1287 switch (op2) { 1288 case 2: 1289 return MISCREG_OSDTRTX_EL1; 1290 case 4: 1291 return MISCREG_DBGBVR3_EL1; 1292 case 5: 1293 return MISCREG_DBGBCR3_EL1; 1294 case 6: 1295 return MISCREG_DBGWVR3_EL1; 1296 case 7: 1297 return MISCREG_DBGWCR3_EL1; 1298 } 1299 break; 1300 case 4: 1301 switch (op2) { 1302 case 4: 1303 return MISCREG_DBGBVR4_EL1; 1304 case 5: 1305 return MISCREG_DBGBCR4_EL1; 1306 } 1307 break; 1308 case 5: 1309 switch (op2) { 1310 case 4: 1311 return MISCREG_DBGBVR5_EL1; 1312 case 5: 1313 return MISCREG_DBGBCR5_EL1; 1314 } 1315 break; 1316 case 6: 1317 switch (op2) { 1318 case 2: 1319 return MISCREG_OSECCR_EL1; 1320 } 1321 break; 1322 } 1323 break; 1324 case 2: 1325 switch (crm) { 1326 case 0: 1327 switch (op2) { 1328 case 0: 1329 return MISCREG_TEECR32_EL1; 1330 } 1331 break; 1332 } 1333 break; 1334 case 3: 1335 switch (crm) { 1336 case 1: 1337 switch (op2) { 1338 case 0: 1339 return MISCREG_MDCCSR_EL0; 1340 } 1341 break; 1342 case 4: 1343 switch (op2) { 1344 case 0: 1345 return MISCREG_MDDTR_EL0; 1346 } 1347 break; 1348 case 5: 1349 switch (op2) { 1350 case 0: 1351 return MISCREG_MDDTRRX_EL0; 1352 } 1353 break; 1354 } 1355 break; 1356 case 4: 1357 switch (crm) { 1358 case 7: 1359 switch (op2) { 1360 case 0: 1361 return MISCREG_DBGVCR32_EL2; 1362 } 1363 break; 1364 } 1365 break; 1366 } 1367 break; 1368 case 1: 1369 switch (op1) { 1370 case 0: 1371 switch (crm) { 1372 case 0: 1373 switch (op2) { 1374 case 0: 1375 return MISCREG_MDRAR_EL1; 1376 case 4: 1377 return MISCREG_OSLAR_EL1; 1378 } 1379 break; 1380 case 1: 1381 switch (op2) { 1382 case 4: 1383 return MISCREG_OSLSR_EL1; 1384 } 1385 break; 1386 case 3: 1387 switch (op2) { 1388 case 4: 1389 return MISCREG_OSDLR_EL1; 1390 } 1391 break; 1392 case 4: 1393 switch (op2) { 1394 case 4: 1395 return MISCREG_DBGPRCR_EL1; 1396 } 1397 break; 1398 } 1399 break; 1400 case 2: 1401 switch (crm) { 1402 case 0: 1403 switch (op2) { 1404 case 0: 1405 return MISCREG_TEEHBR32_EL1; 1406 } 1407 break; 1408 } 1409 break; 1410 } 1411 break; 1412 case 7: 1413 switch (op1) { 1414 case 0: 1415 switch (crm) { 1416 case 8: 1417 switch (op2) { 1418 case 6: 1419 return MISCREG_DBGCLAIMSET_EL1; 1420 } 1421 break; 1422 case 9: 1423 switch (op2) { 1424 case 6: 1425 return MISCREG_DBGCLAIMCLR_EL1; 1426 } 1427 break; 1428 case 14: 1429 switch (op2) { 1430 case 6: 1431 return MISCREG_DBGAUTHSTATUS_EL1; 1432 } 1433 break; 1434 } 1435 break; 1436 } 1437 break; 1438 } 1439 break; 1440 case 3: 1441 switch (crn) { 1442 case 0: 1443 switch (op1) { 1444 case 0: 1445 switch (crm) { 1446 case 0: 1447 switch (op2) { 1448 case 0: 1449 return MISCREG_MIDR_EL1; 1450 case 5: 1451 return MISCREG_MPIDR_EL1; 1452 case 6: 1453 return MISCREG_REVIDR_EL1; 1454 } 1455 break; 1456 case 1: 1457 switch (op2) { 1458 case 0: 1459 return MISCREG_ID_PFR0_EL1; 1460 case 1: 1461 return MISCREG_ID_PFR1_EL1; 1462 case 2: 1463 return MISCREG_ID_DFR0_EL1; 1464 case 3: 1465 return MISCREG_ID_AFR0_EL1; 1466 case 4: 1467 return MISCREG_ID_MMFR0_EL1; 1468 case 5: 1469 return MISCREG_ID_MMFR1_EL1; 1470 case 6: 1471 return MISCREG_ID_MMFR2_EL1; 1472 case 7: 1473 return MISCREG_ID_MMFR3_EL1; 1474 } 1475 break; 1476 case 2: 1477 switch (op2) { 1478 case 0: 1479 return MISCREG_ID_ISAR0_EL1; 1480 case 1: 1481 return MISCREG_ID_ISAR1_EL1; 1482 case 2: 1483 return MISCREG_ID_ISAR2_EL1; 1484 case 3: 1485 return MISCREG_ID_ISAR3_EL1; 1486 case 4: 1487 return MISCREG_ID_ISAR4_EL1; 1488 case 5: 1489 return MISCREG_ID_ISAR5_EL1; 1490 } 1491 break; 1492 case 3: 1493 switch (op2) { 1494 case 0: 1495 return MISCREG_MVFR0_EL1; 1496 case 1: 1497 return MISCREG_MVFR1_EL1; 1498 case 2: 1499 return MISCREG_MVFR2_EL1; 1500 case 3 ... 7: 1501 return MISCREG_RAZ; 1502 } 1503 break; 1504 case 4: 1505 switch (op2) { 1506 case 0: 1507 return MISCREG_ID_AA64PFR0_EL1; 1508 case 1: 1509 return MISCREG_ID_AA64PFR1_EL1; 1510 case 2 ... 7: 1511 return MISCREG_RAZ; 1512 } 1513 break; 1514 case 5: 1515 switch (op2) { 1516 case 0: 1517 return MISCREG_ID_AA64DFR0_EL1; 1518 case 1: 1519 return MISCREG_ID_AA64DFR1_EL1; 1520 case 4: 1521 return MISCREG_ID_AA64AFR0_EL1; 1522 case 5: 1523 return MISCREG_ID_AA64AFR1_EL1; 1524 case 2: 1525 case 3: 1526 case 6: 1527 case 7: 1528 return MISCREG_RAZ; 1529 } 1530 break; 1531 case 6: 1532 switch (op2) { 1533 case 0: 1534 return MISCREG_ID_AA64ISAR0_EL1; 1535 case 1: 1536 return MISCREG_ID_AA64ISAR1_EL1; 1537 case 2 ... 7: 1538 return MISCREG_RAZ; 1539 } 1540 break; 1541 case 7: 1542 switch (op2) { 1543 case 0: 1544 return MISCREG_ID_AA64MMFR0_EL1; 1545 case 1: 1546 return MISCREG_ID_AA64MMFR1_EL1; 1547 case 2: 1548 return MISCREG_ID_AA64MMFR2_EL1; 1549 case 3 ... 7: 1550 return MISCREG_RAZ; 1551 } 1552 break; 1553 } 1554 break; 1555 case 1: 1556 switch (crm) { 1557 case 0: 1558 switch (op2) { 1559 case 0: 1560 return MISCREG_CCSIDR_EL1; 1561 case 1: 1562 return MISCREG_CLIDR_EL1; 1563 case 7: 1564 return MISCREG_AIDR_EL1; 1565 } 1566 break; 1567 } 1568 break; 1569 case 2: 1570 switch (crm) { 1571 case 0: 1572 switch (op2) { 1573 case 0: 1574 return MISCREG_CSSELR_EL1; 1575 } 1576 break; 1577 } 1578 break; 1579 case 3: 1580 switch (crm) { 1581 case 0: 1582 switch (op2) { 1583 case 1: 1584 return MISCREG_CTR_EL0; 1585 case 7: 1586 return MISCREG_DCZID_EL0; 1587 } 1588 break; 1589 } 1590 break; 1591 case 4: 1592 switch (crm) { 1593 case 0: 1594 switch (op2) { 1595 case 0: 1596 return MISCREG_VPIDR_EL2; 1597 case 5: 1598 return MISCREG_VMPIDR_EL2; 1599 } 1600 break; 1601 } 1602 break; 1603 } 1604 break; 1605 case 1: 1606 switch (op1) { 1607 case 0: 1608 switch (crm) { 1609 case 0: 1610 switch (op2) { 1611 case 0: 1612 return MISCREG_SCTLR_EL1; 1613 case 1: 1614 return MISCREG_ACTLR_EL1; 1615 case 2: 1616 return MISCREG_CPACR_EL1; 1617 } 1618 break; 1619 } 1620 break; 1621 case 4: 1622 switch (crm) { 1623 case 0: 1624 switch (op2) { 1625 case 0: 1626 return MISCREG_SCTLR_EL2; 1627 case 1: 1628 return MISCREG_ACTLR_EL2; 1629 } 1630 break; 1631 case 1: 1632 switch (op2) { 1633 case 0: 1634 return MISCREG_HCR_EL2; 1635 case 1: 1636 return MISCREG_MDCR_EL2; 1637 case 2: 1638 return MISCREG_CPTR_EL2; 1639 case 3: 1640 return MISCREG_HSTR_EL2; 1641 case 7: 1642 return MISCREG_HACR_EL2; 1643 } 1644 break; 1645 } 1646 break; 1647 case 6: 1648 switch (crm) { 1649 case 0: 1650 switch (op2) { 1651 case 0: 1652 return MISCREG_SCTLR_EL3; 1653 case 1: 1654 return MISCREG_ACTLR_EL3; 1655 } 1656 break; 1657 case 1: 1658 switch (op2) { 1659 case 0: 1660 return MISCREG_SCR_EL3; 1661 case 1: 1662 return MISCREG_SDER32_EL3; 1663 case 2: 1664 return MISCREG_CPTR_EL3; 1665 } 1666 break; 1667 case 3: 1668 switch (op2) { 1669 case 1: 1670 return MISCREG_MDCR_EL3; 1671 } 1672 break; 1673 } 1674 break; 1675 } 1676 break; 1677 case 2: 1678 switch (op1) { 1679 case 0: 1680 switch (crm) { 1681 case 0: 1682 switch (op2) { 1683 case 0: 1684 return MISCREG_TTBR0_EL1; 1685 case 1: 1686 return MISCREG_TTBR1_EL1; 1687 case 2: 1688 return MISCREG_TCR_EL1; 1689 } 1690 break; 1691 } 1692 break; 1693 case 4: 1694 switch (crm) { 1695 case 0: 1696 switch (op2) { 1697 case 0: 1698 return MISCREG_TTBR0_EL2; 1699 case 1: 1700 return MISCREG_TTBR1_EL2; 1701 case 2: 1702 return MISCREG_TCR_EL2; 1703 } 1704 break; 1705 case 1: 1706 switch (op2) { 1707 case 0: 1708 return MISCREG_VTTBR_EL2; 1709 case 2: 1710 return MISCREG_VTCR_EL2; 1711 } 1712 break; 1713 } 1714 break; 1715 case 6: 1716 switch (crm) { 1717 case 0: 1718 switch (op2) { 1719 case 0: 1720 return MISCREG_TTBR0_EL3; 1721 case 2: 1722 return MISCREG_TCR_EL3; 1723 } 1724 break; 1725 } 1726 break; 1727 } 1728 break; 1729 case 3: 1730 switch (op1) { 1731 case 4: 1732 switch (crm) { 1733 case 0: 1734 switch (op2) { 1735 case 0: 1736 return MISCREG_DACR32_EL2; 1737 } 1738 break; 1739 } 1740 break; 1741 } 1742 break; 1743 case 4: 1744 switch (op1) { 1745 case 0: 1746 switch (crm) { 1747 case 0: 1748 switch (op2) { 1749 case 0: 1750 return MISCREG_SPSR_EL1; 1751 case 1: 1752 return MISCREG_ELR_EL1; 1753 } 1754 break; 1755 case 1: 1756 switch (op2) { 1757 case 0: 1758 return MISCREG_SP_EL0; 1759 } 1760 break; 1761 case 2: 1762 switch (op2) { 1763 case 0: 1764 return MISCREG_SPSEL; 1765 case 2: 1766 return MISCREG_CURRENTEL; 1767 } 1768 break;
| 863 } 864 break; 865 case 13: 866 if (opc1 == 0) { 867 if (crm == 0) { 868 switch (opc2) { 869 case 0: 870 return MISCREG_FCSEIDR; 871 case 1: 872 return MISCREG_CONTEXTIDR; 873 case 2: 874 return MISCREG_TPIDRURW; 875 case 3: 876 return MISCREG_TPIDRURO; 877 case 4: 878 return MISCREG_TPIDRPRW; 879 } 880 } 881 } else if (opc1 == 4) { 882 if (crm == 0 && opc2 == 2) 883 return MISCREG_HTPIDR; 884 } 885 break; 886 case 14: 887 if (opc1 == 0) { 888 switch (crm) { 889 case 0: 890 if (opc2 == 0) 891 return MISCREG_CNTFRQ; 892 break; 893 case 1: 894 if (opc2 == 0) 895 return MISCREG_CNTKCTL; 896 break; 897 case 2: 898 if (opc2 == 0) 899 return MISCREG_CNTP_TVAL; 900 else if (opc2 == 1) 901 return MISCREG_CNTP_CTL; 902 break; 903 case 3: 904 if (opc2 == 0) 905 return MISCREG_CNTV_TVAL; 906 else if (opc2 == 1) 907 return MISCREG_CNTV_CTL; 908 break; 909 } 910 } else if (opc1 == 4) { 911 if (crm == 1 && opc2 == 0) { 912 return MISCREG_CNTHCTL; 913 } else if (crm == 2) { 914 if (opc2 == 0) 915 return MISCREG_CNTHP_TVAL; 916 else if (opc2 == 1) 917 return MISCREG_CNTHP_CTL; 918 } 919 } 920 break; 921 case 15: 922 // Implementation defined 923 return MISCREG_IMPDEF_UNIMPL; 924 } 925 // Unrecognized register 926 return MISCREG_CP15_UNIMPL; 927} 928 929MiscRegIndex 930decodeCP15Reg64(unsigned crm, unsigned opc1) 931{ 932 switch (crm) { 933 case 2: 934 switch (opc1) { 935 case 0: 936 return MISCREG_TTBR0; 937 case 1: 938 return MISCREG_TTBR1; 939 case 4: 940 return MISCREG_HTTBR; 941 case 6: 942 return MISCREG_VTTBR; 943 } 944 break; 945 case 7: 946 if (opc1 == 0) 947 return MISCREG_PAR; 948 break; 949 case 14: 950 switch (opc1) { 951 case 0: 952 return MISCREG_CNTPCT; 953 case 1: 954 return MISCREG_CNTVCT; 955 case 2: 956 return MISCREG_CNTP_CVAL; 957 case 3: 958 return MISCREG_CNTV_CVAL; 959 case 4: 960 return MISCREG_CNTVOFF; 961 case 6: 962 return MISCREG_CNTHP_CVAL; 963 } 964 break; 965 case 15: 966 if (opc1 == 0) 967 return MISCREG_CPUMERRSR; 968 else if (opc1 == 1) 969 return MISCREG_L2MERRSR; 970 break; 971 } 972 // Unrecognized register 973 return MISCREG_CP15_UNIMPL; 974} 975 976std::tuple<bool, bool> 977canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) 978{ 979 bool secure = !scr.ns; 980 bool canRead = false; 981 bool undefined = false; 982 983 switch (cpsr.mode) { 984 case MODE_USER: 985 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 986 miscRegInfo[reg][MISCREG_USR_NS_RD]; 987 break; 988 case MODE_FIQ: 989 case MODE_IRQ: 990 case MODE_SVC: 991 case MODE_ABORT: 992 case MODE_UNDEFINED: 993 case MODE_SYSTEM: 994 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 995 miscRegInfo[reg][MISCREG_PRI_NS_RD]; 996 break; 997 case MODE_MON: 998 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 999 miscRegInfo[reg][MISCREG_MON_NS1_RD]; 1000 break; 1001 case MODE_HYP: 1002 canRead = miscRegInfo[reg][MISCREG_HYP_RD]; 1003 break; 1004 default: 1005 undefined = true; 1006 } 1007 // can't do permissions checkes on the root of a banked pair of regs 1008 assert(!miscRegInfo[reg][MISCREG_BANKED]); 1009 return std::make_tuple(canRead, undefined); 1010} 1011 1012std::tuple<bool, bool> 1013canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) 1014{ 1015 bool secure = !scr.ns; 1016 bool canWrite = false; 1017 bool undefined = false; 1018 1019 switch (cpsr.mode) { 1020 case MODE_USER: 1021 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 1022 miscRegInfo[reg][MISCREG_USR_NS_WR]; 1023 break; 1024 case MODE_FIQ: 1025 case MODE_IRQ: 1026 case MODE_SVC: 1027 case MODE_ABORT: 1028 case MODE_UNDEFINED: 1029 case MODE_SYSTEM: 1030 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 1031 miscRegInfo[reg][MISCREG_PRI_NS_WR]; 1032 break; 1033 case MODE_MON: 1034 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 1035 miscRegInfo[reg][MISCREG_MON_NS1_WR]; 1036 break; 1037 case MODE_HYP: 1038 canWrite = miscRegInfo[reg][MISCREG_HYP_WR]; 1039 break; 1040 default: 1041 undefined = true; 1042 } 1043 // can't do permissions checkes on the root of a banked pair of regs 1044 assert(!miscRegInfo[reg][MISCREG_BANKED]); 1045 return std::make_tuple(canWrite, undefined); 1046} 1047 1048int 1049snsBankedIndex(MiscRegIndex reg, ThreadContext *tc) 1050{ 1051 SCR scr = tc->readMiscReg(MISCREG_SCR); 1052 return snsBankedIndex(reg, tc, scr.ns); 1053} 1054 1055int 1056snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns) 1057{ 1058 int reg_as_int = static_cast<int>(reg); 1059 if (miscRegInfo[reg][MISCREG_BANKED]) { 1060 reg_as_int += (ArmSystem::haveSecurity(tc) && 1061 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1; 1062 } 1063 return reg_as_int; 1064} 1065 1066 1067/** 1068 * If the reg is a child reg of a banked set, then the parent is the last 1069 * banked one in the list. This is messy, and the wish is to eventually have 1070 * the bitmap replaced with a better data structure. the preUnflatten function 1071 * initializes a lookup table to speed up the search for these banked 1072 * registers. 1073 */ 1074 1075int unflattenResultMiscReg[NUM_MISCREGS]; 1076 1077void 1078preUnflattenMiscReg() 1079{ 1080 int reg = -1; 1081 for (int i = 0 ; i < NUM_MISCREGS; i++){ 1082 if (miscRegInfo[i][MISCREG_BANKED]) 1083 reg = i; 1084 if (miscRegInfo[i][MISCREG_BANKED_CHILD]) 1085 unflattenResultMiscReg[i] = reg; 1086 else 1087 unflattenResultMiscReg[i] = i; 1088 // if this assert fails, no parent was found, and something is broken 1089 assert(unflattenResultMiscReg[i] > -1); 1090 } 1091} 1092 1093int 1094unflattenMiscReg(int reg) 1095{ 1096 return unflattenResultMiscReg[reg]; 1097} 1098 1099bool 1100canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 1101{ 1102 // Check for SP_EL0 access while SPSEL == 0 1103 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) 1104 return false; 1105 1106 // Check for RVBAR access 1107 if (reg == MISCREG_RVBAR_EL1) { 1108 ExceptionLevel highest_el = ArmSystem::highestEL(tc); 1109 if (highest_el == EL2 || highest_el == EL3) 1110 return false; 1111 } 1112 if (reg == MISCREG_RVBAR_EL2) { 1113 ExceptionLevel highest_el = ArmSystem::highestEL(tc); 1114 if (highest_el == EL3) 1115 return false; 1116 } 1117 1118 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; 1119 1120 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) { 1121 case EL0: 1122 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 1123 miscRegInfo[reg][MISCREG_USR_NS_RD]; 1124 case EL1: 1125 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 1126 miscRegInfo[reg][MISCREG_PRI_NS_RD]; 1127 case EL2: 1128 return miscRegInfo[reg][MISCREG_HYP_RD]; 1129 case EL3: 1130 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 1131 miscRegInfo[reg][MISCREG_MON_NS1_RD]; 1132 default: 1133 panic("Invalid exception level"); 1134 } 1135} 1136 1137bool 1138canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) 1139{ 1140 // Check for SP_EL0 access while SPSEL == 0 1141 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) 1142 return false; 1143 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode); 1144 if (reg == MISCREG_DAIF) { 1145 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 1146 if (el == EL0 && !sctlr.uma) 1147 return false; 1148 } 1149 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) { 1150 // In syscall-emulation mode, this test is skipped and DCZVA is always 1151 // allowed at EL0 1152 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 1153 if (el == EL0 && !sctlr.dze) 1154 return false; 1155 } 1156 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) { 1157 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); 1158 if (el == EL0 && !sctlr.uci) 1159 return false; 1160 } 1161 1162 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; 1163 1164 switch (el) { 1165 case EL0: 1166 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 1167 miscRegInfo[reg][MISCREG_USR_NS_WR]; 1168 case EL1: 1169 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 1170 miscRegInfo[reg][MISCREG_PRI_NS_WR]; 1171 case EL2: 1172 return miscRegInfo[reg][MISCREG_HYP_WR]; 1173 case EL3: 1174 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 1175 miscRegInfo[reg][MISCREG_MON_NS1_WR]; 1176 default: 1177 panic("Invalid exception level"); 1178 } 1179} 1180 1181MiscRegIndex 1182decodeAArch64SysReg(unsigned op0, unsigned op1, 1183 unsigned crn, unsigned crm, 1184 unsigned op2) 1185{ 1186 switch (op0) { 1187 case 1: 1188 switch (crn) { 1189 case 7: 1190 switch (op1) { 1191 case 0: 1192 switch (crm) { 1193 case 1: 1194 switch (op2) { 1195 case 0: 1196 return MISCREG_IC_IALLUIS; 1197 } 1198 break; 1199 case 5: 1200 switch (op2) { 1201 case 0: 1202 return MISCREG_IC_IALLU; 1203 } 1204 break; 1205 case 6: 1206 switch (op2) { 1207 case 1: 1208 return MISCREG_DC_IVAC_Xt; 1209 case 2: 1210 return MISCREG_DC_ISW_Xt; 1211 } 1212 break; 1213 case 8: 1214 switch (op2) { 1215 case 0: 1216 return MISCREG_AT_S1E1R_Xt; 1217 case 1: 1218 return MISCREG_AT_S1E1W_Xt; 1219 case 2: 1220 return MISCREG_AT_S1E0R_Xt; 1221 case 3: 1222 return MISCREG_AT_S1E0W_Xt; 1223 } 1224 break; 1225 case 10: 1226 switch (op2) { 1227 case 2: 1228 return MISCREG_DC_CSW_Xt; 1229 } 1230 break; 1231 case 14: 1232 switch (op2) { 1233 case 2: 1234 return MISCREG_DC_CISW_Xt; 1235 } 1236 break; 1237 } 1238 break; 1239 case 3: 1240 switch (crm) { 1241 case 4: 1242 switch (op2) { 1243 case 1: 1244 return MISCREG_DC_ZVA_Xt; 1245 } 1246 break; 1247 case 5: 1248 switch (op2) { 1249 case 1: 1250 return MISCREG_IC_IVAU_Xt; 1251 } 1252 break; 1253 case 10: 1254 switch (op2) { 1255 case 1: 1256 return MISCREG_DC_CVAC_Xt; 1257 } 1258 break; 1259 case 11: 1260 switch (op2) { 1261 case 1: 1262 return MISCREG_DC_CVAU_Xt; 1263 } 1264 break; 1265 case 14: 1266 switch (op2) { 1267 case 1: 1268 return MISCREG_DC_CIVAC_Xt; 1269 } 1270 break; 1271 } 1272 break; 1273 case 4: 1274 switch (crm) { 1275 case 8: 1276 switch (op2) { 1277 case 0: 1278 return MISCREG_AT_S1E2R_Xt; 1279 case 1: 1280 return MISCREG_AT_S1E2W_Xt; 1281 case 4: 1282 return MISCREG_AT_S12E1R_Xt; 1283 case 5: 1284 return MISCREG_AT_S12E1W_Xt; 1285 case 6: 1286 return MISCREG_AT_S12E0R_Xt; 1287 case 7: 1288 return MISCREG_AT_S12E0W_Xt; 1289 } 1290 break; 1291 } 1292 break; 1293 case 6: 1294 switch (crm) { 1295 case 8: 1296 switch (op2) { 1297 case 0: 1298 return MISCREG_AT_S1E3R_Xt; 1299 case 1: 1300 return MISCREG_AT_S1E3W_Xt; 1301 } 1302 break; 1303 } 1304 break; 1305 } 1306 break; 1307 case 8: 1308 switch (op1) { 1309 case 0: 1310 switch (crm) { 1311 case 3: 1312 switch (op2) { 1313 case 0: 1314 return MISCREG_TLBI_VMALLE1IS; 1315 case 1: 1316 return MISCREG_TLBI_VAE1IS_Xt; 1317 case 2: 1318 return MISCREG_TLBI_ASIDE1IS_Xt; 1319 case 3: 1320 return MISCREG_TLBI_VAAE1IS_Xt; 1321 case 5: 1322 return MISCREG_TLBI_VALE1IS_Xt; 1323 case 7: 1324 return MISCREG_TLBI_VAALE1IS_Xt; 1325 } 1326 break; 1327 case 7: 1328 switch (op2) { 1329 case 0: 1330 return MISCREG_TLBI_VMALLE1; 1331 case 1: 1332 return MISCREG_TLBI_VAE1_Xt; 1333 case 2: 1334 return MISCREG_TLBI_ASIDE1_Xt; 1335 case 3: 1336 return MISCREG_TLBI_VAAE1_Xt; 1337 case 5: 1338 return MISCREG_TLBI_VALE1_Xt; 1339 case 7: 1340 return MISCREG_TLBI_VAALE1_Xt; 1341 } 1342 break; 1343 } 1344 break; 1345 case 4: 1346 switch (crm) { 1347 case 0: 1348 switch (op2) { 1349 case 1: 1350 return MISCREG_TLBI_IPAS2E1IS_Xt; 1351 case 5: 1352 return MISCREG_TLBI_IPAS2LE1IS_Xt; 1353 } 1354 break; 1355 case 3: 1356 switch (op2) { 1357 case 0: 1358 return MISCREG_TLBI_ALLE2IS; 1359 case 1: 1360 return MISCREG_TLBI_VAE2IS_Xt; 1361 case 4: 1362 return MISCREG_TLBI_ALLE1IS; 1363 case 5: 1364 return MISCREG_TLBI_VALE2IS_Xt; 1365 case 6: 1366 return MISCREG_TLBI_VMALLS12E1IS; 1367 } 1368 break; 1369 case 4: 1370 switch (op2) { 1371 case 1: 1372 return MISCREG_TLBI_IPAS2E1_Xt; 1373 case 5: 1374 return MISCREG_TLBI_IPAS2LE1_Xt; 1375 } 1376 break; 1377 case 7: 1378 switch (op2) { 1379 case 0: 1380 return MISCREG_TLBI_ALLE2; 1381 case 1: 1382 return MISCREG_TLBI_VAE2_Xt; 1383 case 4: 1384 return MISCREG_TLBI_ALLE1; 1385 case 5: 1386 return MISCREG_TLBI_VALE2_Xt; 1387 case 6: 1388 return MISCREG_TLBI_VMALLS12E1; 1389 } 1390 break; 1391 } 1392 break; 1393 case 6: 1394 switch (crm) { 1395 case 3: 1396 switch (op2) { 1397 case 0: 1398 return MISCREG_TLBI_ALLE3IS; 1399 case 1: 1400 return MISCREG_TLBI_VAE3IS_Xt; 1401 case 5: 1402 return MISCREG_TLBI_VALE3IS_Xt; 1403 } 1404 break; 1405 case 7: 1406 switch (op2) { 1407 case 0: 1408 return MISCREG_TLBI_ALLE3; 1409 case 1: 1410 return MISCREG_TLBI_VAE3_Xt; 1411 case 5: 1412 return MISCREG_TLBI_VALE3_Xt; 1413 } 1414 break; 1415 } 1416 break; 1417 } 1418 break; 1419 case 11: 1420 case 15: 1421 // SYS Instruction with CRn = { 11, 15 } 1422 // (Trappable by HCR_EL2.TIDCP) 1423 return MISCREG_IMPDEF_UNIMPL; 1424 } 1425 break; 1426 case 2: 1427 switch (crn) { 1428 case 0: 1429 switch (op1) { 1430 case 0: 1431 switch (crm) { 1432 case 0: 1433 switch (op2) { 1434 case 2: 1435 return MISCREG_OSDTRRX_EL1; 1436 case 4: 1437 return MISCREG_DBGBVR0_EL1; 1438 case 5: 1439 return MISCREG_DBGBCR0_EL1; 1440 case 6: 1441 return MISCREG_DBGWVR0_EL1; 1442 case 7: 1443 return MISCREG_DBGWCR0_EL1; 1444 } 1445 break; 1446 case 1: 1447 switch (op2) { 1448 case 4: 1449 return MISCREG_DBGBVR1_EL1; 1450 case 5: 1451 return MISCREG_DBGBCR1_EL1; 1452 case 6: 1453 return MISCREG_DBGWVR1_EL1; 1454 case 7: 1455 return MISCREG_DBGWCR1_EL1; 1456 } 1457 break; 1458 case 2: 1459 switch (op2) { 1460 case 0: 1461 return MISCREG_MDCCINT_EL1; 1462 case 2: 1463 return MISCREG_MDSCR_EL1; 1464 case 4: 1465 return MISCREG_DBGBVR2_EL1; 1466 case 5: 1467 return MISCREG_DBGBCR2_EL1; 1468 case 6: 1469 return MISCREG_DBGWVR2_EL1; 1470 case 7: 1471 return MISCREG_DBGWCR2_EL1; 1472 } 1473 break; 1474 case 3: 1475 switch (op2) { 1476 case 2: 1477 return MISCREG_OSDTRTX_EL1; 1478 case 4: 1479 return MISCREG_DBGBVR3_EL1; 1480 case 5: 1481 return MISCREG_DBGBCR3_EL1; 1482 case 6: 1483 return MISCREG_DBGWVR3_EL1; 1484 case 7: 1485 return MISCREG_DBGWCR3_EL1; 1486 } 1487 break; 1488 case 4: 1489 switch (op2) { 1490 case 4: 1491 return MISCREG_DBGBVR4_EL1; 1492 case 5: 1493 return MISCREG_DBGBCR4_EL1; 1494 } 1495 break; 1496 case 5: 1497 switch (op2) { 1498 case 4: 1499 return MISCREG_DBGBVR5_EL1; 1500 case 5: 1501 return MISCREG_DBGBCR5_EL1; 1502 } 1503 break; 1504 case 6: 1505 switch (op2) { 1506 case 2: 1507 return MISCREG_OSECCR_EL1; 1508 } 1509 break; 1510 } 1511 break; 1512 case 2: 1513 switch (crm) { 1514 case 0: 1515 switch (op2) { 1516 case 0: 1517 return MISCREG_TEECR32_EL1; 1518 } 1519 break; 1520 } 1521 break; 1522 case 3: 1523 switch (crm) { 1524 case 1: 1525 switch (op2) { 1526 case 0: 1527 return MISCREG_MDCCSR_EL0; 1528 } 1529 break; 1530 case 4: 1531 switch (op2) { 1532 case 0: 1533 return MISCREG_MDDTR_EL0; 1534 } 1535 break; 1536 case 5: 1537 switch (op2) { 1538 case 0: 1539 return MISCREG_MDDTRRX_EL0; 1540 } 1541 break; 1542 } 1543 break; 1544 case 4: 1545 switch (crm) { 1546 case 7: 1547 switch (op2) { 1548 case 0: 1549 return MISCREG_DBGVCR32_EL2; 1550 } 1551 break; 1552 } 1553 break; 1554 } 1555 break; 1556 case 1: 1557 switch (op1) { 1558 case 0: 1559 switch (crm) { 1560 case 0: 1561 switch (op2) { 1562 case 0: 1563 return MISCREG_MDRAR_EL1; 1564 case 4: 1565 return MISCREG_OSLAR_EL1; 1566 } 1567 break; 1568 case 1: 1569 switch (op2) { 1570 case 4: 1571 return MISCREG_OSLSR_EL1; 1572 } 1573 break; 1574 case 3: 1575 switch (op2) { 1576 case 4: 1577 return MISCREG_OSDLR_EL1; 1578 } 1579 break; 1580 case 4: 1581 switch (op2) { 1582 case 4: 1583 return MISCREG_DBGPRCR_EL1; 1584 } 1585 break; 1586 } 1587 break; 1588 case 2: 1589 switch (crm) { 1590 case 0: 1591 switch (op2) { 1592 case 0: 1593 return MISCREG_TEEHBR32_EL1; 1594 } 1595 break; 1596 } 1597 break; 1598 } 1599 break; 1600 case 7: 1601 switch (op1) { 1602 case 0: 1603 switch (crm) { 1604 case 8: 1605 switch (op2) { 1606 case 6: 1607 return MISCREG_DBGCLAIMSET_EL1; 1608 } 1609 break; 1610 case 9: 1611 switch (op2) { 1612 case 6: 1613 return MISCREG_DBGCLAIMCLR_EL1; 1614 } 1615 break; 1616 case 14: 1617 switch (op2) { 1618 case 6: 1619 return MISCREG_DBGAUTHSTATUS_EL1; 1620 } 1621 break; 1622 } 1623 break; 1624 } 1625 break; 1626 } 1627 break; 1628 case 3: 1629 switch (crn) { 1630 case 0: 1631 switch (op1) { 1632 case 0: 1633 switch (crm) { 1634 case 0: 1635 switch (op2) { 1636 case 0: 1637 return MISCREG_MIDR_EL1; 1638 case 5: 1639 return MISCREG_MPIDR_EL1; 1640 case 6: 1641 return MISCREG_REVIDR_EL1; 1642 } 1643 break; 1644 case 1: 1645 switch (op2) { 1646 case 0: 1647 return MISCREG_ID_PFR0_EL1; 1648 case 1: 1649 return MISCREG_ID_PFR1_EL1; 1650 case 2: 1651 return MISCREG_ID_DFR0_EL1; 1652 case 3: 1653 return MISCREG_ID_AFR0_EL1; 1654 case 4: 1655 return MISCREG_ID_MMFR0_EL1; 1656 case 5: 1657 return MISCREG_ID_MMFR1_EL1; 1658 case 6: 1659 return MISCREG_ID_MMFR2_EL1; 1660 case 7: 1661 return MISCREG_ID_MMFR3_EL1; 1662 } 1663 break; 1664 case 2: 1665 switch (op2) { 1666 case 0: 1667 return MISCREG_ID_ISAR0_EL1; 1668 case 1: 1669 return MISCREG_ID_ISAR1_EL1; 1670 case 2: 1671 return MISCREG_ID_ISAR2_EL1; 1672 case 3: 1673 return MISCREG_ID_ISAR3_EL1; 1674 case 4: 1675 return MISCREG_ID_ISAR4_EL1; 1676 case 5: 1677 return MISCREG_ID_ISAR5_EL1; 1678 } 1679 break; 1680 case 3: 1681 switch (op2) { 1682 case 0: 1683 return MISCREG_MVFR0_EL1; 1684 case 1: 1685 return MISCREG_MVFR1_EL1; 1686 case 2: 1687 return MISCREG_MVFR2_EL1; 1688 case 3 ... 7: 1689 return MISCREG_RAZ; 1690 } 1691 break; 1692 case 4: 1693 switch (op2) { 1694 case 0: 1695 return MISCREG_ID_AA64PFR0_EL1; 1696 case 1: 1697 return MISCREG_ID_AA64PFR1_EL1; 1698 case 2 ... 7: 1699 return MISCREG_RAZ; 1700 } 1701 break; 1702 case 5: 1703 switch (op2) { 1704 case 0: 1705 return MISCREG_ID_AA64DFR0_EL1; 1706 case 1: 1707 return MISCREG_ID_AA64DFR1_EL1; 1708 case 4: 1709 return MISCREG_ID_AA64AFR0_EL1; 1710 case 5: 1711 return MISCREG_ID_AA64AFR1_EL1; 1712 case 2: 1713 case 3: 1714 case 6: 1715 case 7: 1716 return MISCREG_RAZ; 1717 } 1718 break; 1719 case 6: 1720 switch (op2) { 1721 case 0: 1722 return MISCREG_ID_AA64ISAR0_EL1; 1723 case 1: 1724 return MISCREG_ID_AA64ISAR1_EL1; 1725 case 2 ... 7: 1726 return MISCREG_RAZ; 1727 } 1728 break; 1729 case 7: 1730 switch (op2) { 1731 case 0: 1732 return MISCREG_ID_AA64MMFR0_EL1; 1733 case 1: 1734 return MISCREG_ID_AA64MMFR1_EL1; 1735 case 2: 1736 return MISCREG_ID_AA64MMFR2_EL1; 1737 case 3 ... 7: 1738 return MISCREG_RAZ; 1739 } 1740 break; 1741 } 1742 break; 1743 case 1: 1744 switch (crm) { 1745 case 0: 1746 switch (op2) { 1747 case 0: 1748 return MISCREG_CCSIDR_EL1; 1749 case 1: 1750 return MISCREG_CLIDR_EL1; 1751 case 7: 1752 return MISCREG_AIDR_EL1; 1753 } 1754 break; 1755 } 1756 break; 1757 case 2: 1758 switch (crm) { 1759 case 0: 1760 switch (op2) { 1761 case 0: 1762 return MISCREG_CSSELR_EL1; 1763 } 1764 break; 1765 } 1766 break; 1767 case 3: 1768 switch (crm) { 1769 case 0: 1770 switch (op2) { 1771 case 1: 1772 return MISCREG_CTR_EL0; 1773 case 7: 1774 return MISCREG_DCZID_EL0; 1775 } 1776 break; 1777 } 1778 break; 1779 case 4: 1780 switch (crm) { 1781 case 0: 1782 switch (op2) { 1783 case 0: 1784 return MISCREG_VPIDR_EL2; 1785 case 5: 1786 return MISCREG_VMPIDR_EL2; 1787 } 1788 break; 1789 } 1790 break; 1791 } 1792 break; 1793 case 1: 1794 switch (op1) { 1795 case 0: 1796 switch (crm) { 1797 case 0: 1798 switch (op2) { 1799 case 0: 1800 return MISCREG_SCTLR_EL1; 1801 case 1: 1802 return MISCREG_ACTLR_EL1; 1803 case 2: 1804 return MISCREG_CPACR_EL1; 1805 } 1806 break; 1807 } 1808 break; 1809 case 4: 1810 switch (crm) { 1811 case 0: 1812 switch (op2) { 1813 case 0: 1814 return MISCREG_SCTLR_EL2; 1815 case 1: 1816 return MISCREG_ACTLR_EL2; 1817 } 1818 break; 1819 case 1: 1820 switch (op2) { 1821 case 0: 1822 return MISCREG_HCR_EL2; 1823 case 1: 1824 return MISCREG_MDCR_EL2; 1825 case 2: 1826 return MISCREG_CPTR_EL2; 1827 case 3: 1828 return MISCREG_HSTR_EL2; 1829 case 7: 1830 return MISCREG_HACR_EL2; 1831 } 1832 break; 1833 } 1834 break; 1835 case 6: 1836 switch (crm) { 1837 case 0: 1838 switch (op2) { 1839 case 0: 1840 return MISCREG_SCTLR_EL3; 1841 case 1: 1842 return MISCREG_ACTLR_EL3; 1843 } 1844 break; 1845 case 1: 1846 switch (op2) { 1847 case 0: 1848 return MISCREG_SCR_EL3; 1849 case 1: 1850 return MISCREG_SDER32_EL3; 1851 case 2: 1852 return MISCREG_CPTR_EL3; 1853 } 1854 break; 1855 case 3: 1856 switch (op2) { 1857 case 1: 1858 return MISCREG_MDCR_EL3; 1859 } 1860 break; 1861 } 1862 break; 1863 } 1864 break; 1865 case 2: 1866 switch (op1) { 1867 case 0: 1868 switch (crm) { 1869 case 0: 1870 switch (op2) { 1871 case 0: 1872 return MISCREG_TTBR0_EL1; 1873 case 1: 1874 return MISCREG_TTBR1_EL1; 1875 case 2: 1876 return MISCREG_TCR_EL1; 1877 } 1878 break; 1879 } 1880 break; 1881 case 4: 1882 switch (crm) { 1883 case 0: 1884 switch (op2) { 1885 case 0: 1886 return MISCREG_TTBR0_EL2; 1887 case 1: 1888 return MISCREG_TTBR1_EL2; 1889 case 2: 1890 return MISCREG_TCR_EL2; 1891 } 1892 break; 1893 case 1: 1894 switch (op2) { 1895 case 0: 1896 return MISCREG_VTTBR_EL2; 1897 case 2: 1898 return MISCREG_VTCR_EL2; 1899 } 1900 break; 1901 } 1902 break; 1903 case 6: 1904 switch (crm) { 1905 case 0: 1906 switch (op2) { 1907 case 0: 1908 return MISCREG_TTBR0_EL3; 1909 case 2: 1910 return MISCREG_TCR_EL3; 1911 } 1912 break; 1913 } 1914 break; 1915 } 1916 break; 1917 case 3: 1918 switch (op1) { 1919 case 4: 1920 switch (crm) { 1921 case 0: 1922 switch (op2) { 1923 case 0: 1924 return MISCREG_DACR32_EL2; 1925 } 1926 break; 1927 } 1928 break; 1929 } 1930 break; 1931 case 4: 1932 switch (op1) { 1933 case 0: 1934 switch (crm) { 1935 case 0: 1936 switch (op2) { 1937 case 0: 1938 return MISCREG_SPSR_EL1; 1939 case 1: 1940 return MISCREG_ELR_EL1; 1941 } 1942 break; 1943 case 1: 1944 switch (op2) { 1945 case 0: 1946 return MISCREG_SP_EL0; 1947 } 1948 break; 1949 case 2: 1950 switch (op2) { 1951 case 0: 1952 return MISCREG_SPSEL; 1953 case 2: 1954 return MISCREG_CURRENTEL; 1955 } 1956 break;
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| 1957 case 6: 1958 switch (op2) { 1959 case 0: 1960 return MISCREG_ICC_PMR_EL1; 1961 } 1962 break;
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1769 } 1770 break; 1771 case 3: 1772 switch (crm) { 1773 case 2: 1774 switch (op2) { 1775 case 0: 1776 return MISCREG_NZCV; 1777 case 1: 1778 return MISCREG_DAIF; 1779 } 1780 break; 1781 case 4: 1782 switch (op2) { 1783 case 0: 1784 return MISCREG_FPCR; 1785 case 1: 1786 return MISCREG_FPSR; 1787 } 1788 break; 1789 case 5: 1790 switch (op2) { 1791 case 0: 1792 return MISCREG_DSPSR_EL0; 1793 case 1: 1794 return MISCREG_DLR_EL0; 1795 } 1796 break; 1797 } 1798 break; 1799 case 4: 1800 switch (crm) { 1801 case 0: 1802 switch (op2) { 1803 case 0: 1804 return MISCREG_SPSR_EL2; 1805 case 1: 1806 return MISCREG_ELR_EL2; 1807 } 1808 break; 1809 case 1: 1810 switch (op2) { 1811 case 0: 1812 return MISCREG_SP_EL1; 1813 } 1814 break; 1815 case 3: 1816 switch (op2) { 1817 case 0: 1818 return MISCREG_SPSR_IRQ_AA64; 1819 case 1: 1820 return MISCREG_SPSR_ABT_AA64; 1821 case 2: 1822 return MISCREG_SPSR_UND_AA64; 1823 case 3: 1824 return MISCREG_SPSR_FIQ_AA64; 1825 } 1826 break; 1827 } 1828 break; 1829 case 6: 1830 switch (crm) { 1831 case 0: 1832 switch (op2) { 1833 case 0: 1834 return MISCREG_SPSR_EL3; 1835 case 1: 1836 return MISCREG_ELR_EL3; 1837 } 1838 break; 1839 case 1: 1840 switch (op2) { 1841 case 0: 1842 return MISCREG_SP_EL2; 1843 } 1844 break; 1845 } 1846 break; 1847 } 1848 break; 1849 case 5: 1850 switch (op1) { 1851 case 0: 1852 switch (crm) { 1853 case 1: 1854 switch (op2) { 1855 case 0: 1856 return MISCREG_AFSR0_EL1; 1857 case 1: 1858 return MISCREG_AFSR1_EL1; 1859 } 1860 break; 1861 case 2: 1862 switch (op2) { 1863 case 0: 1864 return MISCREG_ESR_EL1; 1865 } 1866 break; 1867 case 3: 1868 switch (op2) { 1869 case 0: 1870 return MISCREG_ERRIDR_EL1; 1871 case 1: 1872 return MISCREG_ERRSELR_EL1; 1873 } 1874 break; 1875 case 4: 1876 switch (op2) { 1877 case 0: 1878 return MISCREG_ERXFR_EL1; 1879 case 1: 1880 return MISCREG_ERXCTLR_EL1; 1881 case 2: 1882 return MISCREG_ERXSTATUS_EL1; 1883 case 3: 1884 return MISCREG_ERXADDR_EL1; 1885 } 1886 break; 1887 case 5: 1888 switch (op2) { 1889 case 0: 1890 return MISCREG_ERXMISC0_EL1; 1891 case 1: 1892 return MISCREG_ERXMISC1_EL1; 1893 } 1894 break; 1895 } 1896 break; 1897 case 4: 1898 switch (crm) { 1899 case 0: 1900 switch (op2) { 1901 case 1: 1902 return MISCREG_IFSR32_EL2; 1903 } 1904 break; 1905 case 1: 1906 switch (op2) { 1907 case 0: 1908 return MISCREG_AFSR0_EL2; 1909 case 1: 1910 return MISCREG_AFSR1_EL2; 1911 } 1912 break; 1913 case 2: 1914 switch (op2) { 1915 case 0: 1916 return MISCREG_ESR_EL2; 1917 case 3: 1918 return MISCREG_VSESR_EL2; 1919 } 1920 break; 1921 case 3: 1922 switch (op2) { 1923 case 0: 1924 return MISCREG_FPEXC32_EL2; 1925 } 1926 break; 1927 } 1928 break; 1929 case 6: 1930 switch (crm) { 1931 case 1: 1932 switch (op2) { 1933 case 0: 1934 return MISCREG_AFSR0_EL3; 1935 case 1: 1936 return MISCREG_AFSR1_EL3; 1937 } 1938 break; 1939 case 2: 1940 switch (op2) { 1941 case 0: 1942 return MISCREG_ESR_EL3; 1943 } 1944 break; 1945 } 1946 break; 1947 } 1948 break; 1949 case 6: 1950 switch (op1) { 1951 case 0: 1952 switch (crm) { 1953 case 0: 1954 switch (op2) { 1955 case 0: 1956 return MISCREG_FAR_EL1; 1957 } 1958 break; 1959 } 1960 break; 1961 case 4: 1962 switch (crm) { 1963 case 0: 1964 switch (op2) { 1965 case 0: 1966 return MISCREG_FAR_EL2; 1967 case 4: 1968 return MISCREG_HPFAR_EL2; 1969 } 1970 break; 1971 } 1972 break; 1973 case 6: 1974 switch (crm) { 1975 case 0: 1976 switch (op2) { 1977 case 0: 1978 return MISCREG_FAR_EL3; 1979 } 1980 break; 1981 } 1982 break; 1983 } 1984 break; 1985 case 7: 1986 switch (op1) { 1987 case 0: 1988 switch (crm) { 1989 case 4: 1990 switch (op2) { 1991 case 0: 1992 return MISCREG_PAR_EL1; 1993 } 1994 break; 1995 } 1996 break; 1997 } 1998 break; 1999 case 9: 2000 switch (op1) { 2001 case 0: 2002 switch (crm) { 2003 case 14: 2004 switch (op2) { 2005 case 1: 2006 return MISCREG_PMINTENSET_EL1; 2007 case 2: 2008 return MISCREG_PMINTENCLR_EL1; 2009 } 2010 break; 2011 } 2012 break; 2013 case 3: 2014 switch (crm) { 2015 case 12: 2016 switch (op2) { 2017 case 0: 2018 return MISCREG_PMCR_EL0; 2019 case 1: 2020 return MISCREG_PMCNTENSET_EL0; 2021 case 2: 2022 return MISCREG_PMCNTENCLR_EL0; 2023 case 3: 2024 return MISCREG_PMOVSCLR_EL0; 2025 case 4: 2026 return MISCREG_PMSWINC_EL0; 2027 case 5: 2028 return MISCREG_PMSELR_EL0; 2029 case 6: 2030 return MISCREG_PMCEID0_EL0; 2031 case 7: 2032 return MISCREG_PMCEID1_EL0; 2033 } 2034 break; 2035 case 13: 2036 switch (op2) { 2037 case 0: 2038 return MISCREG_PMCCNTR_EL0; 2039 case 1: 2040 return MISCREG_PMXEVTYPER_EL0; 2041 case 2: 2042 return MISCREG_PMXEVCNTR_EL0; 2043 } 2044 break; 2045 case 14: 2046 switch (op2) { 2047 case 0: 2048 return MISCREG_PMUSERENR_EL0; 2049 case 3: 2050 return MISCREG_PMOVSSET_EL0; 2051 } 2052 break; 2053 } 2054 break; 2055 } 2056 break; 2057 case 10: 2058 switch (op1) { 2059 case 0: 2060 switch (crm) { 2061 case 2: 2062 switch (op2) { 2063 case 0: 2064 return MISCREG_MAIR_EL1; 2065 } 2066 break; 2067 case 3: 2068 switch (op2) { 2069 case 0: 2070 return MISCREG_AMAIR_EL1; 2071 } 2072 break; 2073 } 2074 break; 2075 case 4: 2076 switch (crm) { 2077 case 2: 2078 switch (op2) { 2079 case 0: 2080 return MISCREG_MAIR_EL2; 2081 } 2082 break; 2083 case 3: 2084 switch (op2) { 2085 case 0: 2086 return MISCREG_AMAIR_EL2; 2087 } 2088 break; 2089 } 2090 break; 2091 case 6: 2092 switch (crm) { 2093 case 2: 2094 switch (op2) { 2095 case 0: 2096 return MISCREG_MAIR_EL3; 2097 } 2098 break; 2099 case 3: 2100 switch (op2) { 2101 case 0: 2102 return MISCREG_AMAIR_EL3; 2103 } 2104 break; 2105 } 2106 break; 2107 } 2108 break; 2109 case 11: 2110 switch (op1) { 2111 case 1: 2112 switch (crm) { 2113 case 0: 2114 switch (op2) { 2115 case 2: 2116 return MISCREG_L2CTLR_EL1; 2117 case 3: 2118 return MISCREG_L2ECTLR_EL1; 2119 } 2120 break; 2121 } 2122 M5_FALLTHROUGH; 2123 default: 2124 // S3_<op1>_11_<Cm>_<op2> 2125 return MISCREG_IMPDEF_UNIMPL; 2126 } 2127 M5_UNREACHABLE; 2128 case 12: 2129 switch (op1) { 2130 case 0: 2131 switch (crm) { 2132 case 0: 2133 switch (op2) { 2134 case 0: 2135 return MISCREG_VBAR_EL1; 2136 case 1: 2137 return MISCREG_RVBAR_EL1; 2138 } 2139 break; 2140 case 1: 2141 switch (op2) { 2142 case 0: 2143 return MISCREG_ISR_EL1; 2144 case 1: 2145 return MISCREG_DISR_EL1; 2146 } 2147 break;
| 1963 } 1964 break; 1965 case 3: 1966 switch (crm) { 1967 case 2: 1968 switch (op2) { 1969 case 0: 1970 return MISCREG_NZCV; 1971 case 1: 1972 return MISCREG_DAIF; 1973 } 1974 break; 1975 case 4: 1976 switch (op2) { 1977 case 0: 1978 return MISCREG_FPCR; 1979 case 1: 1980 return MISCREG_FPSR; 1981 } 1982 break; 1983 case 5: 1984 switch (op2) { 1985 case 0: 1986 return MISCREG_DSPSR_EL0; 1987 case 1: 1988 return MISCREG_DLR_EL0; 1989 } 1990 break; 1991 } 1992 break; 1993 case 4: 1994 switch (crm) { 1995 case 0: 1996 switch (op2) { 1997 case 0: 1998 return MISCREG_SPSR_EL2; 1999 case 1: 2000 return MISCREG_ELR_EL2; 2001 } 2002 break; 2003 case 1: 2004 switch (op2) { 2005 case 0: 2006 return MISCREG_SP_EL1; 2007 } 2008 break; 2009 case 3: 2010 switch (op2) { 2011 case 0: 2012 return MISCREG_SPSR_IRQ_AA64; 2013 case 1: 2014 return MISCREG_SPSR_ABT_AA64; 2015 case 2: 2016 return MISCREG_SPSR_UND_AA64; 2017 case 3: 2018 return MISCREG_SPSR_FIQ_AA64; 2019 } 2020 break; 2021 } 2022 break; 2023 case 6: 2024 switch (crm) { 2025 case 0: 2026 switch (op2) { 2027 case 0: 2028 return MISCREG_SPSR_EL3; 2029 case 1: 2030 return MISCREG_ELR_EL3; 2031 } 2032 break; 2033 case 1: 2034 switch (op2) { 2035 case 0: 2036 return MISCREG_SP_EL2; 2037 } 2038 break; 2039 } 2040 break; 2041 } 2042 break; 2043 case 5: 2044 switch (op1) { 2045 case 0: 2046 switch (crm) { 2047 case 1: 2048 switch (op2) { 2049 case 0: 2050 return MISCREG_AFSR0_EL1; 2051 case 1: 2052 return MISCREG_AFSR1_EL1; 2053 } 2054 break; 2055 case 2: 2056 switch (op2) { 2057 case 0: 2058 return MISCREG_ESR_EL1; 2059 } 2060 break; 2061 case 3: 2062 switch (op2) { 2063 case 0: 2064 return MISCREG_ERRIDR_EL1; 2065 case 1: 2066 return MISCREG_ERRSELR_EL1; 2067 } 2068 break; 2069 case 4: 2070 switch (op2) { 2071 case 0: 2072 return MISCREG_ERXFR_EL1; 2073 case 1: 2074 return MISCREG_ERXCTLR_EL1; 2075 case 2: 2076 return MISCREG_ERXSTATUS_EL1; 2077 case 3: 2078 return MISCREG_ERXADDR_EL1; 2079 } 2080 break; 2081 case 5: 2082 switch (op2) { 2083 case 0: 2084 return MISCREG_ERXMISC0_EL1; 2085 case 1: 2086 return MISCREG_ERXMISC1_EL1; 2087 } 2088 break; 2089 } 2090 break; 2091 case 4: 2092 switch (crm) { 2093 case 0: 2094 switch (op2) { 2095 case 1: 2096 return MISCREG_IFSR32_EL2; 2097 } 2098 break; 2099 case 1: 2100 switch (op2) { 2101 case 0: 2102 return MISCREG_AFSR0_EL2; 2103 case 1: 2104 return MISCREG_AFSR1_EL2; 2105 } 2106 break; 2107 case 2: 2108 switch (op2) { 2109 case 0: 2110 return MISCREG_ESR_EL2; 2111 case 3: 2112 return MISCREG_VSESR_EL2; 2113 } 2114 break; 2115 case 3: 2116 switch (op2) { 2117 case 0: 2118 return MISCREG_FPEXC32_EL2; 2119 } 2120 break; 2121 } 2122 break; 2123 case 6: 2124 switch (crm) { 2125 case 1: 2126 switch (op2) { 2127 case 0: 2128 return MISCREG_AFSR0_EL3; 2129 case 1: 2130 return MISCREG_AFSR1_EL3; 2131 } 2132 break; 2133 case 2: 2134 switch (op2) { 2135 case 0: 2136 return MISCREG_ESR_EL3; 2137 } 2138 break; 2139 } 2140 break; 2141 } 2142 break; 2143 case 6: 2144 switch (op1) { 2145 case 0: 2146 switch (crm) { 2147 case 0: 2148 switch (op2) { 2149 case 0: 2150 return MISCREG_FAR_EL1; 2151 } 2152 break; 2153 } 2154 break; 2155 case 4: 2156 switch (crm) { 2157 case 0: 2158 switch (op2) { 2159 case 0: 2160 return MISCREG_FAR_EL2; 2161 case 4: 2162 return MISCREG_HPFAR_EL2; 2163 } 2164 break; 2165 } 2166 break; 2167 case 6: 2168 switch (crm) { 2169 case 0: 2170 switch (op2) { 2171 case 0: 2172 return MISCREG_FAR_EL3; 2173 } 2174 break; 2175 } 2176 break; 2177 } 2178 break; 2179 case 7: 2180 switch (op1) { 2181 case 0: 2182 switch (crm) { 2183 case 4: 2184 switch (op2) { 2185 case 0: 2186 return MISCREG_PAR_EL1; 2187 } 2188 break; 2189 } 2190 break; 2191 } 2192 break; 2193 case 9: 2194 switch (op1) { 2195 case 0: 2196 switch (crm) { 2197 case 14: 2198 switch (op2) { 2199 case 1: 2200 return MISCREG_PMINTENSET_EL1; 2201 case 2: 2202 return MISCREG_PMINTENCLR_EL1; 2203 } 2204 break; 2205 } 2206 break; 2207 case 3: 2208 switch (crm) { 2209 case 12: 2210 switch (op2) { 2211 case 0: 2212 return MISCREG_PMCR_EL0; 2213 case 1: 2214 return MISCREG_PMCNTENSET_EL0; 2215 case 2: 2216 return MISCREG_PMCNTENCLR_EL0; 2217 case 3: 2218 return MISCREG_PMOVSCLR_EL0; 2219 case 4: 2220 return MISCREG_PMSWINC_EL0; 2221 case 5: 2222 return MISCREG_PMSELR_EL0; 2223 case 6: 2224 return MISCREG_PMCEID0_EL0; 2225 case 7: 2226 return MISCREG_PMCEID1_EL0; 2227 } 2228 break; 2229 case 13: 2230 switch (op2) { 2231 case 0: 2232 return MISCREG_PMCCNTR_EL0; 2233 case 1: 2234 return MISCREG_PMXEVTYPER_EL0; 2235 case 2: 2236 return MISCREG_PMXEVCNTR_EL0; 2237 } 2238 break; 2239 case 14: 2240 switch (op2) { 2241 case 0: 2242 return MISCREG_PMUSERENR_EL0; 2243 case 3: 2244 return MISCREG_PMOVSSET_EL0; 2245 } 2246 break; 2247 } 2248 break; 2249 } 2250 break; 2251 case 10: 2252 switch (op1) { 2253 case 0: 2254 switch (crm) { 2255 case 2: 2256 switch (op2) { 2257 case 0: 2258 return MISCREG_MAIR_EL1; 2259 } 2260 break; 2261 case 3: 2262 switch (op2) { 2263 case 0: 2264 return MISCREG_AMAIR_EL1; 2265 } 2266 break; 2267 } 2268 break; 2269 case 4: 2270 switch (crm) { 2271 case 2: 2272 switch (op2) { 2273 case 0: 2274 return MISCREG_MAIR_EL2; 2275 } 2276 break; 2277 case 3: 2278 switch (op2) { 2279 case 0: 2280 return MISCREG_AMAIR_EL2; 2281 } 2282 break; 2283 } 2284 break; 2285 case 6: 2286 switch (crm) { 2287 case 2: 2288 switch (op2) { 2289 case 0: 2290 return MISCREG_MAIR_EL3; 2291 } 2292 break; 2293 case 3: 2294 switch (op2) { 2295 case 0: 2296 return MISCREG_AMAIR_EL3; 2297 } 2298 break; 2299 } 2300 break; 2301 } 2302 break; 2303 case 11: 2304 switch (op1) { 2305 case 1: 2306 switch (crm) { 2307 case 0: 2308 switch (op2) { 2309 case 2: 2310 return MISCREG_L2CTLR_EL1; 2311 case 3: 2312 return MISCREG_L2ECTLR_EL1; 2313 } 2314 break; 2315 } 2316 M5_FALLTHROUGH; 2317 default: 2318 // S3_<op1>_11_<Cm>_<op2> 2319 return MISCREG_IMPDEF_UNIMPL; 2320 } 2321 M5_UNREACHABLE; 2322 case 12: 2323 switch (op1) { 2324 case 0: 2325 switch (crm) { 2326 case 0: 2327 switch (op2) { 2328 case 0: 2329 return MISCREG_VBAR_EL1; 2330 case 1: 2331 return MISCREG_RVBAR_EL1; 2332 } 2333 break; 2334 case 1: 2335 switch (op2) { 2336 case 0: 2337 return MISCREG_ISR_EL1; 2338 case 1: 2339 return MISCREG_DISR_EL1; 2340 } 2341 break;
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| 2342 case 8: 2343 switch (op2) { 2344 case 0: 2345 return MISCREG_ICC_IAR0_EL1; 2346 case 1: 2347 return MISCREG_ICC_EOIR0_EL1; 2348 case 2: 2349 return MISCREG_ICC_HPPIR0_EL1; 2350 case 3: 2351 return MISCREG_ICC_BPR0_EL1; 2352 case 4: 2353 return MISCREG_ICC_AP0R0_EL1; 2354 case 5: 2355 return MISCREG_ICC_AP0R1_EL1; 2356 case 6: 2357 return MISCREG_ICC_AP0R2_EL1; 2358 case 7: 2359 return MISCREG_ICC_AP0R3_EL1; 2360 } 2361 break; 2362 case 9: 2363 switch (op2) { 2364 case 0: 2365 return MISCREG_ICC_AP1R0_EL1; 2366 case 1: 2367 return MISCREG_ICC_AP1R1_EL1; 2368 case 2: 2369 return MISCREG_ICC_AP1R2_EL1; 2370 case 3: 2371 return MISCREG_ICC_AP1R3_EL1; 2372 } 2373 break; 2374 case 11: 2375 switch (op2) { 2376 case 1: 2377 return MISCREG_ICC_DIR_EL1; 2378 case 3: 2379 return MISCREG_ICC_RPR_EL1; 2380 case 5: 2381 return MISCREG_ICC_SGI1R_EL1; 2382 case 6: 2383 return MISCREG_ICC_ASGI1R_EL1; 2384 case 7: 2385 return MISCREG_ICC_SGI0R_EL1; 2386 } 2387 break; 2388 case 12: 2389 switch (op2) { 2390 case 0: 2391 return MISCREG_ICC_IAR1_EL1; 2392 case 1: 2393 return MISCREG_ICC_EOIR1_EL1; 2394 case 2: 2395 return MISCREG_ICC_HPPIR1_EL1; 2396 case 3: 2397 return MISCREG_ICC_BPR1_EL1; 2398 case 4: 2399 return MISCREG_ICC_CTLR_EL1; 2400 case 5: 2401 return MISCREG_ICC_SRE_EL1; 2402 case 6: 2403 return MISCREG_ICC_IGRPEN0_EL1; 2404 case 7: 2405 return MISCREG_ICC_IGRPEN1_EL1; 2406 } 2407 break;
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2148 } 2149 break; 2150 case 4: 2151 switch (crm) { 2152 case 0: 2153 switch (op2) { 2154 case 0: 2155 return MISCREG_VBAR_EL2; 2156 case 1: 2157 return MISCREG_RVBAR_EL2; 2158 } 2159 break; 2160 case 1: 2161 switch (op2) { 2162 case 1: 2163 return MISCREG_VDISR_EL2; 2164 } 2165 break;
| 2408 } 2409 break; 2410 case 4: 2411 switch (crm) { 2412 case 0: 2413 switch (op2) { 2414 case 0: 2415 return MISCREG_VBAR_EL2; 2416 case 1: 2417 return MISCREG_RVBAR_EL2; 2418 } 2419 break; 2420 case 1: 2421 switch (op2) { 2422 case 1: 2423 return MISCREG_VDISR_EL2; 2424 } 2425 break;
|
| 2426 case 8: 2427 switch (op2) { 2428 case 0: 2429 return MISCREG_ICH_AP0R0_EL2; 2430 case 1: 2431 return MISCREG_ICH_AP0R1_EL2; 2432 case 2: 2433 return MISCREG_ICH_AP0R2_EL2; 2434 case 3: 2435 return MISCREG_ICH_AP0R3_EL2; 2436 } 2437 break; 2438 case 9: 2439 switch (op2) { 2440 case 0: 2441 return MISCREG_ICH_AP1R0_EL2; 2442 case 1: 2443 return MISCREG_ICH_AP1R1_EL2; 2444 case 2: 2445 return MISCREG_ICH_AP1R2_EL2; 2446 case 3: 2447 return MISCREG_ICH_AP1R3_EL2; 2448 case 5: 2449 return MISCREG_ICC_SRE_EL2; 2450 } 2451 break; 2452 case 11: 2453 switch (op2) { 2454 case 0: 2455 return MISCREG_ICH_HCR_EL2; 2456 case 1: 2457 return MISCREG_ICH_VTR_EL2; 2458 case 2: 2459 return MISCREG_ICH_MISR_EL2; 2460 case 3: 2461 return MISCREG_ICH_EISR_EL2; 2462 case 5: 2463 return MISCREG_ICH_ELRSR_EL2; 2464 case 7: 2465 return MISCREG_ICH_VMCR_EL2; 2466 } 2467 break; 2468 case 12: 2469 switch (op2) { 2470 case 0: 2471 return MISCREG_ICH_LR0_EL2; 2472 case 1: 2473 return MISCREG_ICH_LR1_EL2; 2474 case 2: 2475 return MISCREG_ICH_LR2_EL2; 2476 case 3: 2477 return MISCREG_ICH_LR3_EL2; 2478 case 4: 2479 return MISCREG_ICH_LR4_EL2; 2480 case 5: 2481 return MISCREG_ICH_LR5_EL2; 2482 case 6: 2483 return MISCREG_ICH_LR6_EL2; 2484 case 7: 2485 return MISCREG_ICH_LR7_EL2; 2486 } 2487 break; 2488 case 13: 2489 switch (op2) { 2490 case 0: 2491 return MISCREG_ICH_LR8_EL2; 2492 case 1: 2493 return MISCREG_ICH_LR9_EL2; 2494 case 2: 2495 return MISCREG_ICH_LR10_EL2; 2496 case 3: 2497 return MISCREG_ICH_LR11_EL2; 2498 case 4: 2499 return MISCREG_ICH_LR12_EL2; 2500 case 5: 2501 return MISCREG_ICH_LR13_EL2; 2502 case 6: 2503 return MISCREG_ICH_LR14_EL2; 2504 case 7: 2505 return MISCREG_ICH_LR15_EL2; 2506 } 2507 break;
|
2166 } 2167 break; 2168 case 6: 2169 switch (crm) { 2170 case 0: 2171 switch (op2) { 2172 case 0: 2173 return MISCREG_VBAR_EL3; 2174 case 1: 2175 return MISCREG_RVBAR_EL3; 2176 case 2: 2177 return MISCREG_RMR_EL3; 2178 } 2179 break;
| 2508 } 2509 break; 2510 case 6: 2511 switch (crm) { 2512 case 0: 2513 switch (op2) { 2514 case 0: 2515 return MISCREG_VBAR_EL3; 2516 case 1: 2517 return MISCREG_RVBAR_EL3; 2518 case 2: 2519 return MISCREG_RMR_EL3; 2520 } 2521 break;
|
| 2522 case 12: 2523 switch (op2) { 2524 case 4: 2525 return MISCREG_ICC_CTLR_EL3; 2526 case 5: 2527 return MISCREG_ICC_SRE_EL3; 2528 case 7: 2529 return MISCREG_ICC_IGRPEN1_EL3; 2530 } 2531 break;
|
2180 } 2181 break; 2182 } 2183 break; 2184 case 13: 2185 switch (op1) { 2186 case 0: 2187 switch (crm) { 2188 case 0: 2189 switch (op2) { 2190 case 1: 2191 return MISCREG_CONTEXTIDR_EL1; 2192 case 4: 2193 return MISCREG_TPIDR_EL1; 2194 } 2195 break; 2196 } 2197 break; 2198 case 3: 2199 switch (crm) { 2200 case 0: 2201 switch (op2) { 2202 case 2: 2203 return MISCREG_TPIDR_EL0; 2204 case 3: 2205 return MISCREG_TPIDRRO_EL0; 2206 } 2207 break; 2208 } 2209 break; 2210 case 4: 2211 switch (crm) { 2212 case 0: 2213 switch (op2) { 2214 case 1: 2215 return MISCREG_CONTEXTIDR_EL2; 2216 case 2: 2217 return MISCREG_TPIDR_EL2; 2218 } 2219 break; 2220 } 2221 break; 2222 case 6: 2223 switch (crm) { 2224 case 0: 2225 switch (op2) { 2226 case 2: 2227 return MISCREG_TPIDR_EL3; 2228 } 2229 break; 2230 } 2231 break; 2232 } 2233 break; 2234 case 14: 2235 switch (op1) { 2236 case 0: 2237 switch (crm) { 2238 case 1: 2239 switch (op2) { 2240 case 0: 2241 return MISCREG_CNTKCTL_EL1; 2242 } 2243 break; 2244 } 2245 break; 2246 case 3: 2247 switch (crm) { 2248 case 0: 2249 switch (op2) { 2250 case 0: 2251 return MISCREG_CNTFRQ_EL0; 2252 case 1: 2253 return MISCREG_CNTPCT_EL0; 2254 case 2: 2255 return MISCREG_CNTVCT_EL0; 2256 } 2257 break; 2258 case 2: 2259 switch (op2) { 2260 case 0: 2261 return MISCREG_CNTP_TVAL_EL0; 2262 case 1: 2263 return MISCREG_CNTP_CTL_EL0; 2264 case 2: 2265 return MISCREG_CNTP_CVAL_EL0; 2266 } 2267 break; 2268 case 3: 2269 switch (op2) { 2270 case 0: 2271 return MISCREG_CNTV_TVAL_EL0; 2272 case 1: 2273 return MISCREG_CNTV_CTL_EL0; 2274 case 2: 2275 return MISCREG_CNTV_CVAL_EL0; 2276 } 2277 break; 2278 case 8: 2279 switch (op2) { 2280 case 0: 2281 return MISCREG_PMEVCNTR0_EL0; 2282 case 1: 2283 return MISCREG_PMEVCNTR1_EL0; 2284 case 2: 2285 return MISCREG_PMEVCNTR2_EL0; 2286 case 3: 2287 return MISCREG_PMEVCNTR3_EL0; 2288 case 4: 2289 return MISCREG_PMEVCNTR4_EL0; 2290 case 5: 2291 return MISCREG_PMEVCNTR5_EL0; 2292 } 2293 break; 2294 case 12: 2295 switch (op2) { 2296 case 0: 2297 return MISCREG_PMEVTYPER0_EL0; 2298 case 1: 2299 return MISCREG_PMEVTYPER1_EL0; 2300 case 2: 2301 return MISCREG_PMEVTYPER2_EL0; 2302 case 3: 2303 return MISCREG_PMEVTYPER3_EL0; 2304 case 4: 2305 return MISCREG_PMEVTYPER4_EL0; 2306 case 5: 2307 return MISCREG_PMEVTYPER5_EL0; 2308 } 2309 break; 2310 case 15: 2311 switch (op2) { 2312 case 7: 2313 return MISCREG_PMCCFILTR_EL0; 2314 } 2315 } 2316 break; 2317 case 4: 2318 switch (crm) { 2319 case 0: 2320 switch (op2) { 2321 case 3: 2322 return MISCREG_CNTVOFF_EL2; 2323 } 2324 break; 2325 case 1: 2326 switch (op2) { 2327 case 0: 2328 return MISCREG_CNTHCTL_EL2; 2329 } 2330 break; 2331 case 2: 2332 switch (op2) { 2333 case 0: 2334 return MISCREG_CNTHP_TVAL_EL2; 2335 case 1: 2336 return MISCREG_CNTHP_CTL_EL2; 2337 case 2: 2338 return MISCREG_CNTHP_CVAL_EL2; 2339 } 2340 break; 2341 case 3: 2342 switch (op2) { 2343 case 0: 2344 return MISCREG_CNTHV_TVAL_EL2; 2345 case 1: 2346 return MISCREG_CNTHV_CTL_EL2; 2347 case 2: 2348 return MISCREG_CNTHV_CVAL_EL2; 2349 } 2350 break; 2351 } 2352 break; 2353 case 7: 2354 switch (crm) { 2355 case 2: 2356 switch (op2) { 2357 case 0: 2358 return MISCREG_CNTPS_TVAL_EL1; 2359 case 1: 2360 return MISCREG_CNTPS_CTL_EL1; 2361 case 2: 2362 return MISCREG_CNTPS_CVAL_EL1; 2363 } 2364 break; 2365 } 2366 break; 2367 } 2368 break; 2369 case 15: 2370 switch (op1) { 2371 case 0: 2372 switch (crm) { 2373 case 0: 2374 switch (op2) { 2375 case 0: 2376 return MISCREG_IL1DATA0_EL1; 2377 case 1: 2378 return MISCREG_IL1DATA1_EL1; 2379 case 2: 2380 return MISCREG_IL1DATA2_EL1; 2381 case 3: 2382 return MISCREG_IL1DATA3_EL1; 2383 } 2384 break; 2385 case 1: 2386 switch (op2) { 2387 case 0: 2388 return MISCREG_DL1DATA0_EL1; 2389 case 1: 2390 return MISCREG_DL1DATA1_EL1; 2391 case 2: 2392 return MISCREG_DL1DATA2_EL1; 2393 case 3: 2394 return MISCREG_DL1DATA3_EL1; 2395 case 4: 2396 return MISCREG_DL1DATA4_EL1; 2397 } 2398 break; 2399 } 2400 break; 2401 case 1: 2402 switch (crm) { 2403 case 0: 2404 switch (op2) { 2405 case 0: 2406 return MISCREG_L2ACTLR_EL1; 2407 } 2408 break; 2409 case 2: 2410 switch (op2) { 2411 case 0: 2412 return MISCREG_CPUACTLR_EL1; 2413 case 1: 2414 return MISCREG_CPUECTLR_EL1; 2415 case 2: 2416 return MISCREG_CPUMERRSR_EL1; 2417 case 3: 2418 return MISCREG_L2MERRSR_EL1; 2419 } 2420 break; 2421 case 3: 2422 switch (op2) { 2423 case 0: 2424 return MISCREG_CBAR_EL1; 2425 2426 } 2427 break; 2428 } 2429 break; 2430 } 2431 // S3_<op1>_15_<Cm>_<op2> 2432 return MISCREG_IMPDEF_UNIMPL; 2433 } 2434 break; 2435 } 2436 2437 return MISCREG_UNKNOWN; 2438} 2439 2440bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below 2441 2442void 2443ISA::initializeMiscRegMetadata() 2444{ 2445 // the MiscReg metadata tables are shared across all instances of the 2446 // ISA object, so there's no need to initialize them multiple times. 2447 static bool completed = false; 2448 if (completed) 2449 return; 2450 2451 // This boolean variable specifies if the system is running in aarch32 at 2452 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it 2453 // is running in aarch64 (aarch32EL3 = false) 2454 bool aarch32EL3 = haveSecurity && !highestELIs64; 2455 2456 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+), 2457 // unsupported 2458 bool SPAN = false; 2459 2460 // Implicit error synchronization event enable (Arm 8.2+), unsupported 2461 bool IESB = false; 2462 2463 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+), 2464 // unsupported 2465 bool LSMAOE = false; 2466 2467 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported 2468 bool nTLSMD = false; 2469 2470 // Pointer authentication (Arm 8.3+), unsupported 2471 bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1 2472 bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1 2473 bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1 2474 bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1 2475 2476 /** 2477 * Some registers alias with others, and therefore need to be translated. 2478 * When two mapping registers are given, they are the 32b lower and 2479 * upper halves, respectively, of the 64b register being mapped. 2480 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 2481 * 2482 * NAM = "not architecturally mandated", 2483 * from ARM DDI 0487A.i, template text 2484 * "AArch64 System register ___ can be mapped to 2485 * AArch32 System register ___, but this is not 2486 * architecturally mandated." 2487 */ 2488 2489 InitReg(MISCREG_CPSR) 2490 .allPrivileges(); 2491 InitReg(MISCREG_SPSR) 2492 .allPrivileges(); 2493 InitReg(MISCREG_SPSR_FIQ) 2494 .allPrivileges(); 2495 InitReg(MISCREG_SPSR_IRQ) 2496 .allPrivileges(); 2497 InitReg(MISCREG_SPSR_SVC) 2498 .allPrivileges(); 2499 InitReg(MISCREG_SPSR_MON) 2500 .allPrivileges(); 2501 InitReg(MISCREG_SPSR_ABT) 2502 .allPrivileges(); 2503 InitReg(MISCREG_SPSR_HYP) 2504 .allPrivileges(); 2505 InitReg(MISCREG_SPSR_UND) 2506 .allPrivileges(); 2507 InitReg(MISCREG_ELR_HYP) 2508 .allPrivileges(); 2509 InitReg(MISCREG_FPSID) 2510 .allPrivileges(); 2511 InitReg(MISCREG_FPSCR) 2512 .allPrivileges(); 2513 InitReg(MISCREG_MVFR1) 2514 .allPrivileges(); 2515 InitReg(MISCREG_MVFR0) 2516 .allPrivileges(); 2517 InitReg(MISCREG_FPEXC) 2518 .allPrivileges(); 2519 2520 // Helper registers 2521 InitReg(MISCREG_CPSR_MODE) 2522 .allPrivileges(); 2523 InitReg(MISCREG_CPSR_Q) 2524 .allPrivileges(); 2525 InitReg(MISCREG_FPSCR_EXC) 2526 .allPrivileges(); 2527 InitReg(MISCREG_FPSCR_QC) 2528 .allPrivileges(); 2529 InitReg(MISCREG_LOCKADDR) 2530 .allPrivileges(); 2531 InitReg(MISCREG_LOCKFLAG) 2532 .allPrivileges(); 2533 InitReg(MISCREG_PRRR_MAIR0) 2534 .mutex() 2535 .banked(); 2536 InitReg(MISCREG_PRRR_MAIR0_NS) 2537 .mutex() 2538 .privSecure(!aarch32EL3) 2539 .bankedChild(); 2540 InitReg(MISCREG_PRRR_MAIR0_S) 2541 .mutex() 2542 .bankedChild(); 2543 InitReg(MISCREG_NMRR_MAIR1) 2544 .mutex() 2545 .banked(); 2546 InitReg(MISCREG_NMRR_MAIR1_NS) 2547 .mutex() 2548 .privSecure(!aarch32EL3) 2549 .bankedChild(); 2550 InitReg(MISCREG_NMRR_MAIR1_S) 2551 .mutex() 2552 .bankedChild(); 2553 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR) 2554 .mutex(); 2555 InitReg(MISCREG_SCTLR_RST) 2556 .allPrivileges(); 2557 InitReg(MISCREG_SEV_MAILBOX) 2558 .allPrivileges(); 2559 2560 // AArch32 CP14 registers 2561 InitReg(MISCREG_DBGDIDR) 2562 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2563 InitReg(MISCREG_DBGDSCRint) 2564 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2565 InitReg(MISCREG_DBGDCCINT) 2566 .unimplemented() 2567 .allPrivileges(); 2568 InitReg(MISCREG_DBGDTRTXint) 2569 .unimplemented() 2570 .allPrivileges(); 2571 InitReg(MISCREG_DBGDTRRXint) 2572 .unimplemented() 2573 .allPrivileges(); 2574 InitReg(MISCREG_DBGWFAR) 2575 .unimplemented() 2576 .allPrivileges(); 2577 InitReg(MISCREG_DBGVCR) 2578 .unimplemented() 2579 .allPrivileges(); 2580 InitReg(MISCREG_DBGDTRRXext) 2581 .unimplemented() 2582 .allPrivileges(); 2583 InitReg(MISCREG_DBGDSCRext) 2584 .unimplemented() 2585 .warnNotFail() 2586 .allPrivileges(); 2587 InitReg(MISCREG_DBGDTRTXext) 2588 .unimplemented() 2589 .allPrivileges(); 2590 InitReg(MISCREG_DBGOSECCR) 2591 .unimplemented() 2592 .allPrivileges(); 2593 InitReg(MISCREG_DBGBVR0) 2594 .unimplemented() 2595 .allPrivileges(); 2596 InitReg(MISCREG_DBGBVR1) 2597 .unimplemented() 2598 .allPrivileges(); 2599 InitReg(MISCREG_DBGBVR2) 2600 .unimplemented() 2601 .allPrivileges(); 2602 InitReg(MISCREG_DBGBVR3) 2603 .unimplemented() 2604 .allPrivileges(); 2605 InitReg(MISCREG_DBGBVR4) 2606 .unimplemented() 2607 .allPrivileges(); 2608 InitReg(MISCREG_DBGBVR5) 2609 .unimplemented() 2610 .allPrivileges(); 2611 InitReg(MISCREG_DBGBCR0) 2612 .unimplemented() 2613 .allPrivileges(); 2614 InitReg(MISCREG_DBGBCR1) 2615 .unimplemented() 2616 .allPrivileges(); 2617 InitReg(MISCREG_DBGBCR2) 2618 .unimplemented() 2619 .allPrivileges(); 2620 InitReg(MISCREG_DBGBCR3) 2621 .unimplemented() 2622 .allPrivileges(); 2623 InitReg(MISCREG_DBGBCR4) 2624 .unimplemented() 2625 .allPrivileges(); 2626 InitReg(MISCREG_DBGBCR5) 2627 .unimplemented() 2628 .allPrivileges(); 2629 InitReg(MISCREG_DBGWVR0) 2630 .unimplemented() 2631 .allPrivileges(); 2632 InitReg(MISCREG_DBGWVR1) 2633 .unimplemented() 2634 .allPrivileges(); 2635 InitReg(MISCREG_DBGWVR2) 2636 .unimplemented() 2637 .allPrivileges(); 2638 InitReg(MISCREG_DBGWVR3) 2639 .unimplemented() 2640 .allPrivileges(); 2641 InitReg(MISCREG_DBGWCR0) 2642 .unimplemented() 2643 .allPrivileges(); 2644 InitReg(MISCREG_DBGWCR1) 2645 .unimplemented() 2646 .allPrivileges(); 2647 InitReg(MISCREG_DBGWCR2) 2648 .unimplemented() 2649 .allPrivileges(); 2650 InitReg(MISCREG_DBGWCR3) 2651 .unimplemented() 2652 .allPrivileges(); 2653 InitReg(MISCREG_DBGDRAR) 2654 .unimplemented() 2655 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2656 InitReg(MISCREG_DBGBXVR4) 2657 .unimplemented() 2658 .allPrivileges(); 2659 InitReg(MISCREG_DBGBXVR5) 2660 .unimplemented() 2661 .allPrivileges(); 2662 InitReg(MISCREG_DBGOSLAR) 2663 .unimplemented() 2664 .allPrivileges().monSecureRead(0).monNonSecureRead(0); 2665 InitReg(MISCREG_DBGOSLSR) 2666 .unimplemented() 2667 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2668 InitReg(MISCREG_DBGOSDLR) 2669 .unimplemented() 2670 .allPrivileges(); 2671 InitReg(MISCREG_DBGPRCR) 2672 .unimplemented() 2673 .allPrivileges(); 2674 InitReg(MISCREG_DBGDSAR) 2675 .unimplemented() 2676 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2677 InitReg(MISCREG_DBGCLAIMSET) 2678 .unimplemented() 2679 .allPrivileges(); 2680 InitReg(MISCREG_DBGCLAIMCLR) 2681 .unimplemented() 2682 .allPrivileges(); 2683 InitReg(MISCREG_DBGAUTHSTATUS) 2684 .unimplemented() 2685 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2686 InitReg(MISCREG_DBGDEVID2) 2687 .unimplemented() 2688 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2689 InitReg(MISCREG_DBGDEVID1) 2690 .unimplemented() 2691 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2692 InitReg(MISCREG_DBGDEVID0) 2693 .unimplemented() 2694 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2695 InitReg(MISCREG_TEECR) 2696 .unimplemented() 2697 .allPrivileges(); 2698 InitReg(MISCREG_JIDR) 2699 .allPrivileges(); 2700 InitReg(MISCREG_TEEHBR) 2701 .allPrivileges(); 2702 InitReg(MISCREG_JOSCR) 2703 .allPrivileges(); 2704 InitReg(MISCREG_JMCR) 2705 .allPrivileges(); 2706 2707 // AArch32 CP15 registers 2708 InitReg(MISCREG_MIDR) 2709 .allPrivileges().exceptUserMode().writes(0); 2710 InitReg(MISCREG_CTR) 2711 .allPrivileges().exceptUserMode().writes(0); 2712 InitReg(MISCREG_TCMTR) 2713 .allPrivileges().exceptUserMode().writes(0); 2714 InitReg(MISCREG_TLBTR) 2715 .allPrivileges().exceptUserMode().writes(0); 2716 InitReg(MISCREG_MPIDR) 2717 .allPrivileges().exceptUserMode().writes(0); 2718 InitReg(MISCREG_REVIDR) 2719 .unimplemented() 2720 .warnNotFail() 2721 .allPrivileges().exceptUserMode().writes(0); 2722 InitReg(MISCREG_ID_PFR0) 2723 .allPrivileges().exceptUserMode().writes(0); 2724 InitReg(MISCREG_ID_PFR1) 2725 .allPrivileges().exceptUserMode().writes(0); 2726 InitReg(MISCREG_ID_DFR0) 2727 .allPrivileges().exceptUserMode().writes(0); 2728 InitReg(MISCREG_ID_AFR0) 2729 .allPrivileges().exceptUserMode().writes(0); 2730 InitReg(MISCREG_ID_MMFR0) 2731 .allPrivileges().exceptUserMode().writes(0); 2732 InitReg(MISCREG_ID_MMFR1) 2733 .allPrivileges().exceptUserMode().writes(0); 2734 InitReg(MISCREG_ID_MMFR2) 2735 .allPrivileges().exceptUserMode().writes(0); 2736 InitReg(MISCREG_ID_MMFR3) 2737 .allPrivileges().exceptUserMode().writes(0); 2738 InitReg(MISCREG_ID_ISAR0) 2739 .allPrivileges().exceptUserMode().writes(0); 2740 InitReg(MISCREG_ID_ISAR1) 2741 .allPrivileges().exceptUserMode().writes(0); 2742 InitReg(MISCREG_ID_ISAR2) 2743 .allPrivileges().exceptUserMode().writes(0); 2744 InitReg(MISCREG_ID_ISAR3) 2745 .allPrivileges().exceptUserMode().writes(0); 2746 InitReg(MISCREG_ID_ISAR4) 2747 .allPrivileges().exceptUserMode().writes(0); 2748 InitReg(MISCREG_ID_ISAR5) 2749 .allPrivileges().exceptUserMode().writes(0); 2750 InitReg(MISCREG_CCSIDR) 2751 .allPrivileges().exceptUserMode().writes(0); 2752 InitReg(MISCREG_CLIDR) 2753 .allPrivileges().exceptUserMode().writes(0); 2754 InitReg(MISCREG_AIDR) 2755 .allPrivileges().exceptUserMode().writes(0); 2756 InitReg(MISCREG_CSSELR) 2757 .banked(); 2758 InitReg(MISCREG_CSSELR_NS) 2759 .bankedChild() 2760 .privSecure(!aarch32EL3) 2761 .nonSecure().exceptUserMode(); 2762 InitReg(MISCREG_CSSELR_S) 2763 .bankedChild() 2764 .secure().exceptUserMode(); 2765 InitReg(MISCREG_VPIDR) 2766 .hyp().monNonSecure(); 2767 InitReg(MISCREG_VMPIDR) 2768 .hyp().monNonSecure(); 2769 InitReg(MISCREG_SCTLR) 2770 .banked() 2771 // readMiscRegNoEffect() uses this metadata 2772 // despite using children (below) as backing store 2773 .res0(0x8d22c600) 2774 .res1(0x00400800 | (SPAN ? 0 : 0x800000) 2775 | (LSMAOE ? 0 : 0x10) 2776 | (nTLSMD ? 0 : 0x8)); 2777 InitReg(MISCREG_SCTLR_NS) 2778 .bankedChild() 2779 .privSecure(!aarch32EL3) 2780 .nonSecure().exceptUserMode(); 2781 InitReg(MISCREG_SCTLR_S) 2782 .bankedChild() 2783 .secure().exceptUserMode(); 2784 InitReg(MISCREG_ACTLR) 2785 .banked(); 2786 InitReg(MISCREG_ACTLR_NS) 2787 .bankedChild() 2788 .privSecure(!aarch32EL3) 2789 .nonSecure().exceptUserMode(); 2790 InitReg(MISCREG_ACTLR_S) 2791 .bankedChild() 2792 .secure().exceptUserMode(); 2793 InitReg(MISCREG_CPACR) 2794 .allPrivileges().exceptUserMode(); 2795 InitReg(MISCREG_SCR) 2796 .mon().secure().exceptUserMode() 2797 .res0(0xff40) // [31:16], [6] 2798 .res1(0x0030); // [5:4] 2799 InitReg(MISCREG_SDER) 2800 .mon(); 2801 InitReg(MISCREG_NSACR) 2802 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode(); 2803 InitReg(MISCREG_HSCTLR) 2804 .hyp().monNonSecure() 2805 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000) 2806 | (IESB ? 0 : 0x200000) 2807 | (EnDA ? 0 : 0x8000000) 2808 | (EnIB ? 0 : 0x40000000) 2809 | (EnIA ? 0 : 0x80000000)) 2810 .res1(0x30c50830); 2811 InitReg(MISCREG_HACTLR) 2812 .hyp().monNonSecure(); 2813 InitReg(MISCREG_HCR) 2814 .hyp().monNonSecure(); 2815 InitReg(MISCREG_HDCR) 2816 .hyp().monNonSecure(); 2817 InitReg(MISCREG_HCPTR) 2818 .hyp().monNonSecure(); 2819 InitReg(MISCREG_HSTR) 2820 .hyp().monNonSecure(); 2821 InitReg(MISCREG_HACR) 2822 .unimplemented() 2823 .warnNotFail() 2824 .hyp().monNonSecure(); 2825 InitReg(MISCREG_TTBR0) 2826 .banked(); 2827 InitReg(MISCREG_TTBR0_NS) 2828 .bankedChild() 2829 .privSecure(!aarch32EL3) 2830 .nonSecure().exceptUserMode(); 2831 InitReg(MISCREG_TTBR0_S) 2832 .bankedChild() 2833 .secure().exceptUserMode(); 2834 InitReg(MISCREG_TTBR1) 2835 .banked(); 2836 InitReg(MISCREG_TTBR1_NS) 2837 .bankedChild() 2838 .privSecure(!aarch32EL3) 2839 .nonSecure().exceptUserMode(); 2840 InitReg(MISCREG_TTBR1_S) 2841 .bankedChild() 2842 .secure().exceptUserMode(); 2843 InitReg(MISCREG_TTBCR) 2844 .banked(); 2845 InitReg(MISCREG_TTBCR_NS) 2846 .bankedChild() 2847 .privSecure(!aarch32EL3) 2848 .nonSecure().exceptUserMode(); 2849 InitReg(MISCREG_TTBCR_S) 2850 .bankedChild() 2851 .secure().exceptUserMode(); 2852 InitReg(MISCREG_HTCR) 2853 .hyp().monNonSecure(); 2854 InitReg(MISCREG_VTCR) 2855 .hyp().monNonSecure(); 2856 InitReg(MISCREG_DACR) 2857 .banked(); 2858 InitReg(MISCREG_DACR_NS) 2859 .bankedChild() 2860 .privSecure(!aarch32EL3) 2861 .nonSecure().exceptUserMode(); 2862 InitReg(MISCREG_DACR_S) 2863 .bankedChild() 2864 .secure().exceptUserMode(); 2865 InitReg(MISCREG_DFSR) 2866 .banked(); 2867 InitReg(MISCREG_DFSR_NS) 2868 .bankedChild() 2869 .privSecure(!aarch32EL3) 2870 .nonSecure().exceptUserMode(); 2871 InitReg(MISCREG_DFSR_S) 2872 .bankedChild() 2873 .secure().exceptUserMode(); 2874 InitReg(MISCREG_IFSR) 2875 .banked(); 2876 InitReg(MISCREG_IFSR_NS) 2877 .bankedChild() 2878 .privSecure(!aarch32EL3) 2879 .nonSecure().exceptUserMode(); 2880 InitReg(MISCREG_IFSR_S) 2881 .bankedChild() 2882 .secure().exceptUserMode(); 2883 InitReg(MISCREG_ADFSR) 2884 .unimplemented() 2885 .warnNotFail() 2886 .banked(); 2887 InitReg(MISCREG_ADFSR_NS) 2888 .unimplemented() 2889 .warnNotFail() 2890 .bankedChild() 2891 .privSecure(!aarch32EL3) 2892 .nonSecure().exceptUserMode(); 2893 InitReg(MISCREG_ADFSR_S) 2894 .unimplemented() 2895 .warnNotFail() 2896 .bankedChild() 2897 .secure().exceptUserMode(); 2898 InitReg(MISCREG_AIFSR) 2899 .unimplemented() 2900 .warnNotFail() 2901 .banked(); 2902 InitReg(MISCREG_AIFSR_NS) 2903 .unimplemented() 2904 .warnNotFail() 2905 .bankedChild() 2906 .privSecure(!aarch32EL3) 2907 .nonSecure().exceptUserMode(); 2908 InitReg(MISCREG_AIFSR_S) 2909 .unimplemented() 2910 .warnNotFail() 2911 .bankedChild() 2912 .secure().exceptUserMode(); 2913 InitReg(MISCREG_HADFSR) 2914 .hyp().monNonSecure(); 2915 InitReg(MISCREG_HAIFSR) 2916 .hyp().monNonSecure(); 2917 InitReg(MISCREG_HSR) 2918 .hyp().monNonSecure(); 2919 InitReg(MISCREG_DFAR) 2920 .banked(); 2921 InitReg(MISCREG_DFAR_NS) 2922 .bankedChild() 2923 .privSecure(!aarch32EL3) 2924 .nonSecure().exceptUserMode(); 2925 InitReg(MISCREG_DFAR_S) 2926 .bankedChild() 2927 .secure().exceptUserMode(); 2928 InitReg(MISCREG_IFAR) 2929 .banked(); 2930 InitReg(MISCREG_IFAR_NS) 2931 .bankedChild() 2932 .privSecure(!aarch32EL3) 2933 .nonSecure().exceptUserMode(); 2934 InitReg(MISCREG_IFAR_S) 2935 .bankedChild() 2936 .secure().exceptUserMode(); 2937 InitReg(MISCREG_HDFAR) 2938 .hyp().monNonSecure(); 2939 InitReg(MISCREG_HIFAR) 2940 .hyp().monNonSecure(); 2941 InitReg(MISCREG_HPFAR) 2942 .hyp().monNonSecure(); 2943 InitReg(MISCREG_ICIALLUIS) 2944 .unimplemented() 2945 .warnNotFail() 2946 .writes(1).exceptUserMode(); 2947 InitReg(MISCREG_BPIALLIS) 2948 .unimplemented() 2949 .warnNotFail() 2950 .writes(1).exceptUserMode(); 2951 InitReg(MISCREG_PAR) 2952 .banked(); 2953 InitReg(MISCREG_PAR_NS) 2954 .bankedChild() 2955 .privSecure(!aarch32EL3) 2956 .nonSecure().exceptUserMode(); 2957 InitReg(MISCREG_PAR_S) 2958 .bankedChild() 2959 .secure().exceptUserMode(); 2960 InitReg(MISCREG_ICIALLU) 2961 .writes(1).exceptUserMode(); 2962 InitReg(MISCREG_ICIMVAU) 2963 .unimplemented() 2964 .warnNotFail() 2965 .writes(1).exceptUserMode(); 2966 InitReg(MISCREG_CP15ISB) 2967 .writes(1); 2968 InitReg(MISCREG_BPIALL) 2969 .unimplemented() 2970 .warnNotFail() 2971 .writes(1).exceptUserMode(); 2972 InitReg(MISCREG_BPIMVA) 2973 .unimplemented() 2974 .warnNotFail() 2975 .writes(1).exceptUserMode(); 2976 InitReg(MISCREG_DCIMVAC) 2977 .unimplemented() 2978 .warnNotFail() 2979 .writes(1).exceptUserMode(); 2980 InitReg(MISCREG_DCISW) 2981 .unimplemented() 2982 .warnNotFail() 2983 .writes(1).exceptUserMode(); 2984 InitReg(MISCREG_ATS1CPR) 2985 .writes(1).exceptUserMode(); 2986 InitReg(MISCREG_ATS1CPW) 2987 .writes(1).exceptUserMode(); 2988 InitReg(MISCREG_ATS1CUR) 2989 .writes(1).exceptUserMode(); 2990 InitReg(MISCREG_ATS1CUW) 2991 .writes(1).exceptUserMode(); 2992 InitReg(MISCREG_ATS12NSOPR) 2993 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2994 InitReg(MISCREG_ATS12NSOPW) 2995 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2996 InitReg(MISCREG_ATS12NSOUR) 2997 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 2998 InitReg(MISCREG_ATS12NSOUW) 2999 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 3000 InitReg(MISCREG_DCCMVAC) 3001 .writes(1).exceptUserMode(); 3002 InitReg(MISCREG_DCCSW) 3003 .unimplemented() 3004 .warnNotFail() 3005 .writes(1).exceptUserMode(); 3006 InitReg(MISCREG_CP15DSB) 3007 .writes(1); 3008 InitReg(MISCREG_CP15DMB) 3009 .writes(1); 3010 InitReg(MISCREG_DCCMVAU) 3011 .unimplemented() 3012 .warnNotFail() 3013 .writes(1).exceptUserMode(); 3014 InitReg(MISCREG_DCCIMVAC) 3015 .unimplemented() 3016 .warnNotFail() 3017 .writes(1).exceptUserMode(); 3018 InitReg(MISCREG_DCCISW) 3019 .unimplemented() 3020 .warnNotFail() 3021 .writes(1).exceptUserMode(); 3022 InitReg(MISCREG_ATS1HR) 3023 .monNonSecureWrite().hypWrite(); 3024 InitReg(MISCREG_ATS1HW) 3025 .monNonSecureWrite().hypWrite(); 3026 InitReg(MISCREG_TLBIALLIS) 3027 .writes(1).exceptUserMode(); 3028 InitReg(MISCREG_TLBIMVAIS) 3029 .writes(1).exceptUserMode(); 3030 InitReg(MISCREG_TLBIASIDIS) 3031 .writes(1).exceptUserMode(); 3032 InitReg(MISCREG_TLBIMVAAIS) 3033 .writes(1).exceptUserMode(); 3034 InitReg(MISCREG_TLBIMVALIS) 3035 .writes(1).exceptUserMode(); 3036 InitReg(MISCREG_TLBIMVAALIS) 3037 .writes(1).exceptUserMode(); 3038 InitReg(MISCREG_ITLBIALL) 3039 .writes(1).exceptUserMode(); 3040 InitReg(MISCREG_ITLBIMVA) 3041 .writes(1).exceptUserMode(); 3042 InitReg(MISCREG_ITLBIASID) 3043 .writes(1).exceptUserMode(); 3044 InitReg(MISCREG_DTLBIALL) 3045 .writes(1).exceptUserMode(); 3046 InitReg(MISCREG_DTLBIMVA) 3047 .writes(1).exceptUserMode(); 3048 InitReg(MISCREG_DTLBIASID) 3049 .writes(1).exceptUserMode(); 3050 InitReg(MISCREG_TLBIALL) 3051 .writes(1).exceptUserMode(); 3052 InitReg(MISCREG_TLBIMVA) 3053 .writes(1).exceptUserMode(); 3054 InitReg(MISCREG_TLBIASID) 3055 .writes(1).exceptUserMode(); 3056 InitReg(MISCREG_TLBIMVAA) 3057 .writes(1).exceptUserMode(); 3058 InitReg(MISCREG_TLBIMVAL) 3059 .writes(1).exceptUserMode(); 3060 InitReg(MISCREG_TLBIMVAAL) 3061 .writes(1).exceptUserMode(); 3062 InitReg(MISCREG_TLBIIPAS2IS) 3063 .monNonSecureWrite().hypWrite(); 3064 InitReg(MISCREG_TLBIIPAS2LIS) 3065 .monNonSecureWrite().hypWrite(); 3066 InitReg(MISCREG_TLBIALLHIS) 3067 .monNonSecureWrite().hypWrite(); 3068 InitReg(MISCREG_TLBIMVAHIS) 3069 .monNonSecureWrite().hypWrite(); 3070 InitReg(MISCREG_TLBIALLNSNHIS) 3071 .monNonSecureWrite().hypWrite(); 3072 InitReg(MISCREG_TLBIMVALHIS) 3073 .monNonSecureWrite().hypWrite(); 3074 InitReg(MISCREG_TLBIIPAS2) 3075 .monNonSecureWrite().hypWrite(); 3076 InitReg(MISCREG_TLBIIPAS2L) 3077 .monNonSecureWrite().hypWrite(); 3078 InitReg(MISCREG_TLBIALLH) 3079 .monNonSecureWrite().hypWrite(); 3080 InitReg(MISCREG_TLBIMVAH) 3081 .monNonSecureWrite().hypWrite(); 3082 InitReg(MISCREG_TLBIALLNSNH) 3083 .monNonSecureWrite().hypWrite(); 3084 InitReg(MISCREG_TLBIMVALH) 3085 .monNonSecureWrite().hypWrite(); 3086 InitReg(MISCREG_PMCR) 3087 .allPrivileges(); 3088 InitReg(MISCREG_PMCNTENSET) 3089 .allPrivileges(); 3090 InitReg(MISCREG_PMCNTENCLR) 3091 .allPrivileges(); 3092 InitReg(MISCREG_PMOVSR) 3093 .allPrivileges(); 3094 InitReg(MISCREG_PMSWINC) 3095 .allPrivileges(); 3096 InitReg(MISCREG_PMSELR) 3097 .allPrivileges(); 3098 InitReg(MISCREG_PMCEID0) 3099 .allPrivileges(); 3100 InitReg(MISCREG_PMCEID1) 3101 .allPrivileges(); 3102 InitReg(MISCREG_PMCCNTR) 3103 .allPrivileges(); 3104 InitReg(MISCREG_PMXEVTYPER) 3105 .allPrivileges(); 3106 InitReg(MISCREG_PMCCFILTR) 3107 .allPrivileges(); 3108 InitReg(MISCREG_PMXEVCNTR) 3109 .allPrivileges(); 3110 InitReg(MISCREG_PMUSERENR) 3111 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0); 3112 InitReg(MISCREG_PMINTENSET) 3113 .allPrivileges().exceptUserMode(); 3114 InitReg(MISCREG_PMINTENCLR) 3115 .allPrivileges().exceptUserMode(); 3116 InitReg(MISCREG_PMOVSSET) 3117 .unimplemented() 3118 .allPrivileges(); 3119 InitReg(MISCREG_L2CTLR) 3120 .allPrivileges().exceptUserMode(); 3121 InitReg(MISCREG_L2ECTLR) 3122 .unimplemented() 3123 .allPrivileges().exceptUserMode(); 3124 InitReg(MISCREG_PRRR) 3125 .banked(); 3126 InitReg(MISCREG_PRRR_NS) 3127 .bankedChild() 3128 .privSecure(!aarch32EL3) 3129 .nonSecure().exceptUserMode(); 3130 InitReg(MISCREG_PRRR_S) 3131 .bankedChild() 3132 .secure().exceptUserMode(); 3133 InitReg(MISCREG_MAIR0) 3134 .banked(); 3135 InitReg(MISCREG_MAIR0_NS) 3136 .bankedChild() 3137 .privSecure(!aarch32EL3) 3138 .nonSecure().exceptUserMode(); 3139 InitReg(MISCREG_MAIR0_S) 3140 .bankedChild() 3141 .secure().exceptUserMode(); 3142 InitReg(MISCREG_NMRR) 3143 .banked(); 3144 InitReg(MISCREG_NMRR_NS) 3145 .bankedChild() 3146 .privSecure(!aarch32EL3) 3147 .nonSecure().exceptUserMode(); 3148 InitReg(MISCREG_NMRR_S) 3149 .bankedChild() 3150 .secure().exceptUserMode(); 3151 InitReg(MISCREG_MAIR1) 3152 .banked(); 3153 InitReg(MISCREG_MAIR1_NS) 3154 .bankedChild() 3155 .privSecure(!aarch32EL3) 3156 .nonSecure().exceptUserMode(); 3157 InitReg(MISCREG_MAIR1_S) 3158 .bankedChild() 3159 .secure().exceptUserMode(); 3160 InitReg(MISCREG_AMAIR0) 3161 .banked(); 3162 InitReg(MISCREG_AMAIR0_NS) 3163 .bankedChild() 3164 .privSecure(!aarch32EL3) 3165 .nonSecure().exceptUserMode(); 3166 InitReg(MISCREG_AMAIR0_S) 3167 .bankedChild() 3168 .secure().exceptUserMode(); 3169 InitReg(MISCREG_AMAIR1) 3170 .banked(); 3171 InitReg(MISCREG_AMAIR1_NS) 3172 .bankedChild() 3173 .privSecure(!aarch32EL3) 3174 .nonSecure().exceptUserMode(); 3175 InitReg(MISCREG_AMAIR1_S) 3176 .bankedChild() 3177 .secure().exceptUserMode(); 3178 InitReg(MISCREG_HMAIR0) 3179 .hyp().monNonSecure(); 3180 InitReg(MISCREG_HMAIR1) 3181 .hyp().monNonSecure(); 3182 InitReg(MISCREG_HAMAIR0) 3183 .unimplemented() 3184 .warnNotFail() 3185 .hyp().monNonSecure(); 3186 InitReg(MISCREG_HAMAIR1) 3187 .unimplemented() 3188 .warnNotFail() 3189 .hyp().monNonSecure(); 3190 InitReg(MISCREG_VBAR) 3191 .banked(); 3192 InitReg(MISCREG_VBAR_NS) 3193 .bankedChild() 3194 .privSecure(!aarch32EL3) 3195 .nonSecure().exceptUserMode(); 3196 InitReg(MISCREG_VBAR_S) 3197 .bankedChild() 3198 .secure().exceptUserMode(); 3199 InitReg(MISCREG_MVBAR) 3200 .mon().secure() 3201 .hypRead(FullSystem && system->highestEL() == EL2) 3202 .privRead(FullSystem && system->highestEL() == EL1) 3203 .exceptUserMode(); 3204 InitReg(MISCREG_RMR) 3205 .unimplemented() 3206 .mon().secure().exceptUserMode(); 3207 InitReg(MISCREG_ISR) 3208 .allPrivileges().exceptUserMode().writes(0); 3209 InitReg(MISCREG_HVBAR) 3210 .hyp().monNonSecure() 3211 .res0(0x1f); 3212 InitReg(MISCREG_FCSEIDR) 3213 .unimplemented() 3214 .warnNotFail() 3215 .allPrivileges().exceptUserMode(); 3216 InitReg(MISCREG_CONTEXTIDR) 3217 .banked(); 3218 InitReg(MISCREG_CONTEXTIDR_NS) 3219 .bankedChild() 3220 .privSecure(!aarch32EL3) 3221 .nonSecure().exceptUserMode(); 3222 InitReg(MISCREG_CONTEXTIDR_S) 3223 .bankedChild() 3224 .secure().exceptUserMode(); 3225 InitReg(MISCREG_TPIDRURW) 3226 .banked(); 3227 InitReg(MISCREG_TPIDRURW_NS) 3228 .bankedChild() 3229 .allPrivileges() 3230 .privSecure(!aarch32EL3) 3231 .monSecure(0); 3232 InitReg(MISCREG_TPIDRURW_S) 3233 .bankedChild() 3234 .secure(); 3235 InitReg(MISCREG_TPIDRURO) 3236 .banked(); 3237 InitReg(MISCREG_TPIDRURO_NS) 3238 .bankedChild() 3239 .allPrivileges() 3240 .userNonSecureWrite(0).userSecureRead(1) 3241 .privSecure(!aarch32EL3) 3242 .monSecure(0); 3243 InitReg(MISCREG_TPIDRURO_S) 3244 .bankedChild() 3245 .secure().userSecureWrite(0); 3246 InitReg(MISCREG_TPIDRPRW) 3247 .banked(); 3248 InitReg(MISCREG_TPIDRPRW_NS) 3249 .bankedChild() 3250 .nonSecure().exceptUserMode() 3251 .privSecure(!aarch32EL3); 3252 InitReg(MISCREG_TPIDRPRW_S) 3253 .bankedChild() 3254 .secure().exceptUserMode(); 3255 InitReg(MISCREG_HTPIDR) 3256 .hyp().monNonSecure(); 3257 InitReg(MISCREG_CNTFRQ) 3258 .unverifiable() 3259 .reads(1).mon(); 3260 InitReg(MISCREG_CNTKCTL) 3261 .allPrivileges().exceptUserMode(); 3262 InitReg(MISCREG_CNTP_TVAL) 3263 .banked(); 3264 InitReg(MISCREG_CNTP_TVAL_NS) 3265 .bankedChild() 3266 .allPrivileges() 3267 .privSecure(!aarch32EL3) 3268 .monSecure(0); 3269 InitReg(MISCREG_CNTP_TVAL_S) 3270 .bankedChild() 3271 .secure().user(1); 3272 InitReg(MISCREG_CNTP_CTL) 3273 .banked(); 3274 InitReg(MISCREG_CNTP_CTL_NS) 3275 .bankedChild() 3276 .allPrivileges() 3277 .privSecure(!aarch32EL3) 3278 .monSecure(0); 3279 InitReg(MISCREG_CNTP_CTL_S) 3280 .bankedChild() 3281 .secure().user(1); 3282 InitReg(MISCREG_CNTV_TVAL) 3283 .allPrivileges(); 3284 InitReg(MISCREG_CNTV_CTL) 3285 .allPrivileges(); 3286 InitReg(MISCREG_CNTHCTL) 3287 .hypWrite().monNonSecureRead(); 3288 InitReg(MISCREG_CNTHP_TVAL) 3289 .hypWrite().monNonSecureRead(); 3290 InitReg(MISCREG_CNTHP_CTL) 3291 .hypWrite().monNonSecureRead(); 3292 InitReg(MISCREG_IL1DATA0) 3293 .unimplemented() 3294 .allPrivileges().exceptUserMode(); 3295 InitReg(MISCREG_IL1DATA1) 3296 .unimplemented() 3297 .allPrivileges().exceptUserMode(); 3298 InitReg(MISCREG_IL1DATA2) 3299 .unimplemented() 3300 .allPrivileges().exceptUserMode(); 3301 InitReg(MISCREG_IL1DATA3) 3302 .unimplemented() 3303 .allPrivileges().exceptUserMode(); 3304 InitReg(MISCREG_DL1DATA0) 3305 .unimplemented() 3306 .allPrivileges().exceptUserMode(); 3307 InitReg(MISCREG_DL1DATA1) 3308 .unimplemented() 3309 .allPrivileges().exceptUserMode(); 3310 InitReg(MISCREG_DL1DATA2) 3311 .unimplemented() 3312 .allPrivileges().exceptUserMode(); 3313 InitReg(MISCREG_DL1DATA3) 3314 .unimplemented() 3315 .allPrivileges().exceptUserMode(); 3316 InitReg(MISCREG_DL1DATA4) 3317 .unimplemented() 3318 .allPrivileges().exceptUserMode(); 3319 InitReg(MISCREG_RAMINDEX) 3320 .unimplemented() 3321 .writes(1).exceptUserMode(); 3322 InitReg(MISCREG_L2ACTLR) 3323 .unimplemented() 3324 .allPrivileges().exceptUserMode(); 3325 InitReg(MISCREG_CBAR) 3326 .unimplemented() 3327 .allPrivileges().exceptUserMode().writes(0); 3328 InitReg(MISCREG_HTTBR) 3329 .hyp().monNonSecure(); 3330 InitReg(MISCREG_VTTBR) 3331 .hyp().monNonSecure(); 3332 InitReg(MISCREG_CNTPCT) 3333 .reads(1); 3334 InitReg(MISCREG_CNTVCT) 3335 .unverifiable() 3336 .reads(1); 3337 InitReg(MISCREG_CNTP_CVAL) 3338 .banked(); 3339 InitReg(MISCREG_CNTP_CVAL_NS) 3340 .bankedChild() 3341 .allPrivileges() 3342 .privSecure(!aarch32EL3) 3343 .monSecure(0); 3344 InitReg(MISCREG_CNTP_CVAL_S) 3345 .bankedChild() 3346 .secure().user(1); 3347 InitReg(MISCREG_CNTV_CVAL) 3348 .allPrivileges(); 3349 InitReg(MISCREG_CNTVOFF) 3350 .hyp().monNonSecure(); 3351 InitReg(MISCREG_CNTHP_CVAL) 3352 .hypWrite().monNonSecureRead(); 3353 InitReg(MISCREG_CPUMERRSR) 3354 .unimplemented() 3355 .allPrivileges().exceptUserMode(); 3356 InitReg(MISCREG_L2MERRSR) 3357 .unimplemented() 3358 .warnNotFail() 3359 .allPrivileges().exceptUserMode(); 3360 3361 // AArch64 registers (Op0=2); 3362 InitReg(MISCREG_MDCCINT_EL1) 3363 .allPrivileges(); 3364 InitReg(MISCREG_OSDTRRX_EL1) 3365 .allPrivileges() 3366 .mapsTo(MISCREG_DBGDTRRXext); 3367 InitReg(MISCREG_MDSCR_EL1) 3368 .allPrivileges() 3369 .mapsTo(MISCREG_DBGDSCRext); 3370 InitReg(MISCREG_OSDTRTX_EL1) 3371 .allPrivileges() 3372 .mapsTo(MISCREG_DBGDTRTXext); 3373 InitReg(MISCREG_OSECCR_EL1) 3374 .allPrivileges() 3375 .mapsTo(MISCREG_DBGOSECCR); 3376 InitReg(MISCREG_DBGBVR0_EL1) 3377 .allPrivileges() 3378 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */); 3379 InitReg(MISCREG_DBGBVR1_EL1) 3380 .allPrivileges() 3381 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */); 3382 InitReg(MISCREG_DBGBVR2_EL1) 3383 .allPrivileges() 3384 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */); 3385 InitReg(MISCREG_DBGBVR3_EL1) 3386 .allPrivileges() 3387 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */); 3388 InitReg(MISCREG_DBGBVR4_EL1) 3389 .allPrivileges() 3390 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */); 3391 InitReg(MISCREG_DBGBVR5_EL1) 3392 .allPrivileges() 3393 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */); 3394 InitReg(MISCREG_DBGBCR0_EL1) 3395 .allPrivileges() 3396 .mapsTo(MISCREG_DBGBCR0); 3397 InitReg(MISCREG_DBGBCR1_EL1) 3398 .allPrivileges() 3399 .mapsTo(MISCREG_DBGBCR1); 3400 InitReg(MISCREG_DBGBCR2_EL1) 3401 .allPrivileges() 3402 .mapsTo(MISCREG_DBGBCR2); 3403 InitReg(MISCREG_DBGBCR3_EL1) 3404 .allPrivileges() 3405 .mapsTo(MISCREG_DBGBCR3); 3406 InitReg(MISCREG_DBGBCR4_EL1) 3407 .allPrivileges() 3408 .mapsTo(MISCREG_DBGBCR4); 3409 InitReg(MISCREG_DBGBCR5_EL1) 3410 .allPrivileges() 3411 .mapsTo(MISCREG_DBGBCR5); 3412 InitReg(MISCREG_DBGWVR0_EL1) 3413 .allPrivileges() 3414 .mapsTo(MISCREG_DBGWVR0); 3415 InitReg(MISCREG_DBGWVR1_EL1) 3416 .allPrivileges() 3417 .mapsTo(MISCREG_DBGWVR1); 3418 InitReg(MISCREG_DBGWVR2_EL1) 3419 .allPrivileges() 3420 .mapsTo(MISCREG_DBGWVR2); 3421 InitReg(MISCREG_DBGWVR3_EL1) 3422 .allPrivileges() 3423 .mapsTo(MISCREG_DBGWVR3); 3424 InitReg(MISCREG_DBGWCR0_EL1) 3425 .allPrivileges() 3426 .mapsTo(MISCREG_DBGWCR0); 3427 InitReg(MISCREG_DBGWCR1_EL1) 3428 .allPrivileges() 3429 .mapsTo(MISCREG_DBGWCR1); 3430 InitReg(MISCREG_DBGWCR2_EL1) 3431 .allPrivileges() 3432 .mapsTo(MISCREG_DBGWCR2); 3433 InitReg(MISCREG_DBGWCR3_EL1) 3434 .allPrivileges() 3435 .mapsTo(MISCREG_DBGWCR3); 3436 InitReg(MISCREG_MDCCSR_EL0) 3437 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3438 .mapsTo(MISCREG_DBGDSCRint); 3439 InitReg(MISCREG_MDDTR_EL0) 3440 .allPrivileges(); 3441 InitReg(MISCREG_MDDTRTX_EL0) 3442 .allPrivileges(); 3443 InitReg(MISCREG_MDDTRRX_EL0) 3444 .allPrivileges(); 3445 InitReg(MISCREG_DBGVCR32_EL2) 3446 .allPrivileges() 3447 .mapsTo(MISCREG_DBGVCR); 3448 InitReg(MISCREG_MDRAR_EL1) 3449 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3450 .mapsTo(MISCREG_DBGDRAR); 3451 InitReg(MISCREG_OSLAR_EL1) 3452 .allPrivileges().monSecureRead(0).monNonSecureRead(0) 3453 .mapsTo(MISCREG_DBGOSLAR); 3454 InitReg(MISCREG_OSLSR_EL1) 3455 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3456 .mapsTo(MISCREG_DBGOSLSR); 3457 InitReg(MISCREG_OSDLR_EL1) 3458 .allPrivileges() 3459 .mapsTo(MISCREG_DBGOSDLR); 3460 InitReg(MISCREG_DBGPRCR_EL1) 3461 .allPrivileges() 3462 .mapsTo(MISCREG_DBGPRCR); 3463 InitReg(MISCREG_DBGCLAIMSET_EL1) 3464 .allPrivileges() 3465 .mapsTo(MISCREG_DBGCLAIMSET); 3466 InitReg(MISCREG_DBGCLAIMCLR_EL1) 3467 .allPrivileges() 3468 .mapsTo(MISCREG_DBGCLAIMCLR); 3469 InitReg(MISCREG_DBGAUTHSTATUS_EL1) 3470 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3471 .mapsTo(MISCREG_DBGAUTHSTATUS); 3472 InitReg(MISCREG_TEECR32_EL1); 3473 InitReg(MISCREG_TEEHBR32_EL1); 3474 3475 // AArch64 registers (Op0=1,3); 3476 InitReg(MISCREG_MIDR_EL1) 3477 .allPrivileges().exceptUserMode().writes(0); 3478 InitReg(MISCREG_MPIDR_EL1) 3479 .allPrivileges().exceptUserMode().writes(0); 3480 InitReg(MISCREG_REVIDR_EL1) 3481 .allPrivileges().exceptUserMode().writes(0); 3482 InitReg(MISCREG_ID_PFR0_EL1) 3483 .allPrivileges().exceptUserMode().writes(0) 3484 .mapsTo(MISCREG_ID_PFR0); 3485 InitReg(MISCREG_ID_PFR1_EL1) 3486 .allPrivileges().exceptUserMode().writes(0) 3487 .mapsTo(MISCREG_ID_PFR1); 3488 InitReg(MISCREG_ID_DFR0_EL1) 3489 .allPrivileges().exceptUserMode().writes(0) 3490 .mapsTo(MISCREG_ID_DFR0); 3491 InitReg(MISCREG_ID_AFR0_EL1) 3492 .allPrivileges().exceptUserMode().writes(0) 3493 .mapsTo(MISCREG_ID_AFR0); 3494 InitReg(MISCREG_ID_MMFR0_EL1) 3495 .allPrivileges().exceptUserMode().writes(0) 3496 .mapsTo(MISCREG_ID_MMFR0); 3497 InitReg(MISCREG_ID_MMFR1_EL1) 3498 .allPrivileges().exceptUserMode().writes(0) 3499 .mapsTo(MISCREG_ID_MMFR1); 3500 InitReg(MISCREG_ID_MMFR2_EL1) 3501 .allPrivileges().exceptUserMode().writes(0) 3502 .mapsTo(MISCREG_ID_MMFR2); 3503 InitReg(MISCREG_ID_MMFR3_EL1) 3504 .allPrivileges().exceptUserMode().writes(0) 3505 .mapsTo(MISCREG_ID_MMFR3); 3506 InitReg(MISCREG_ID_ISAR0_EL1) 3507 .allPrivileges().exceptUserMode().writes(0) 3508 .mapsTo(MISCREG_ID_ISAR0); 3509 InitReg(MISCREG_ID_ISAR1_EL1) 3510 .allPrivileges().exceptUserMode().writes(0) 3511 .mapsTo(MISCREG_ID_ISAR1); 3512 InitReg(MISCREG_ID_ISAR2_EL1) 3513 .allPrivileges().exceptUserMode().writes(0) 3514 .mapsTo(MISCREG_ID_ISAR2); 3515 InitReg(MISCREG_ID_ISAR3_EL1) 3516 .allPrivileges().exceptUserMode().writes(0) 3517 .mapsTo(MISCREG_ID_ISAR3); 3518 InitReg(MISCREG_ID_ISAR4_EL1) 3519 .allPrivileges().exceptUserMode().writes(0) 3520 .mapsTo(MISCREG_ID_ISAR4); 3521 InitReg(MISCREG_ID_ISAR5_EL1) 3522 .allPrivileges().exceptUserMode().writes(0) 3523 .mapsTo(MISCREG_ID_ISAR5); 3524 InitReg(MISCREG_MVFR0_EL1) 3525 .allPrivileges().exceptUserMode().writes(0); 3526 InitReg(MISCREG_MVFR1_EL1) 3527 .allPrivileges().exceptUserMode().writes(0); 3528 InitReg(MISCREG_MVFR2_EL1) 3529 .allPrivileges().exceptUserMode().writes(0); 3530 InitReg(MISCREG_ID_AA64PFR0_EL1) 3531 .allPrivileges().exceptUserMode().writes(0); 3532 InitReg(MISCREG_ID_AA64PFR1_EL1) 3533 .allPrivileges().exceptUserMode().writes(0); 3534 InitReg(MISCREG_ID_AA64DFR0_EL1) 3535 .allPrivileges().exceptUserMode().writes(0); 3536 InitReg(MISCREG_ID_AA64DFR1_EL1) 3537 .allPrivileges().exceptUserMode().writes(0); 3538 InitReg(MISCREG_ID_AA64AFR0_EL1) 3539 .allPrivileges().exceptUserMode().writes(0); 3540 InitReg(MISCREG_ID_AA64AFR1_EL1) 3541 .allPrivileges().exceptUserMode().writes(0); 3542 InitReg(MISCREG_ID_AA64ISAR0_EL1) 3543 .allPrivileges().exceptUserMode().writes(0); 3544 InitReg(MISCREG_ID_AA64ISAR1_EL1) 3545 .allPrivileges().exceptUserMode().writes(0); 3546 InitReg(MISCREG_ID_AA64MMFR0_EL1) 3547 .allPrivileges().exceptUserMode().writes(0); 3548 InitReg(MISCREG_ID_AA64MMFR1_EL1) 3549 .allPrivileges().exceptUserMode().writes(0); 3550 InitReg(MISCREG_ID_AA64MMFR2_EL1) 3551 .allPrivileges().exceptUserMode().writes(0); 3552 InitReg(MISCREG_CCSIDR_EL1) 3553 .allPrivileges().exceptUserMode().writes(0); 3554 InitReg(MISCREG_CLIDR_EL1) 3555 .allPrivileges().exceptUserMode().writes(0); 3556 InitReg(MISCREG_AIDR_EL1) 3557 .allPrivileges().exceptUserMode().writes(0); 3558 InitReg(MISCREG_CSSELR_EL1) 3559 .allPrivileges().exceptUserMode() 3560 .mapsTo(MISCREG_CSSELR_NS); 3561 InitReg(MISCREG_CTR_EL0) 3562 .reads(1); 3563 InitReg(MISCREG_DCZID_EL0) 3564 .reads(1); 3565 InitReg(MISCREG_VPIDR_EL2) 3566 .hyp().mon() 3567 .mapsTo(MISCREG_VPIDR); 3568 InitReg(MISCREG_VMPIDR_EL2) 3569 .hyp().mon() 3570 .mapsTo(MISCREG_VMPIDR); 3571 InitReg(MISCREG_SCTLR_EL1) 3572 .allPrivileges().exceptUserMode() 3573 .res0( 0x20440 | (EnDB ? 0 : 0x2000) 3574 | (IESB ? 0 : 0x200000) 3575 | (EnDA ? 0 : 0x8000000) 3576 | (EnIB ? 0 : 0x40000000) 3577 | (EnIA ? 0 : 0x80000000)) 3578 .res1(0x500800 | (SPAN ? 0 : 0x800000) 3579 | (nTLSMD ? 0 : 0x8000000) 3580 | (LSMAOE ? 0 : 0x10000000)) 3581 .mapsTo(MISCREG_SCTLR_NS); 3582 InitReg(MISCREG_ACTLR_EL1) 3583 .allPrivileges().exceptUserMode() 3584 .mapsTo(MISCREG_ACTLR_NS); 3585 InitReg(MISCREG_CPACR_EL1) 3586 .allPrivileges().exceptUserMode() 3587 .mapsTo(MISCREG_CPACR); 3588 InitReg(MISCREG_SCTLR_EL2) 3589 .hyp().mon() 3590 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000) 3591 | (IESB ? 0 : 0x200000) 3592 | (EnDA ? 0 : 0x8000000) 3593 | (EnIB ? 0 : 0x40000000) 3594 | (EnIA ? 0 : 0x80000000)) 3595 .res1(0x30c50830) 3596 .mapsTo(MISCREG_HSCTLR); 3597 InitReg(MISCREG_ACTLR_EL2) 3598 .hyp().mon() 3599 .mapsTo(MISCREG_HACTLR); 3600 InitReg(MISCREG_HCR_EL2) 3601 .hyp().mon() 3602 .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/); 3603 InitReg(MISCREG_MDCR_EL2) 3604 .hyp().mon() 3605 .mapsTo(MISCREG_HDCR); 3606 InitReg(MISCREG_CPTR_EL2) 3607 .hyp().mon() 3608 .mapsTo(MISCREG_HCPTR); 3609 InitReg(MISCREG_HSTR_EL2) 3610 .hyp().mon() 3611 .mapsTo(MISCREG_HSTR); 3612 InitReg(MISCREG_HACR_EL2) 3613 .hyp().mon() 3614 .mapsTo(MISCREG_HACR); 3615 InitReg(MISCREG_SCTLR_EL3) 3616 .mon() 3617 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000) 3618 | (IESB ? 0 : 0x200000) 3619 | (EnDA ? 0 : 0x8000000) 3620 | (EnIB ? 0 : 0x40000000) 3621 | (EnIA ? 0 : 0x80000000)) 3622 .res1(0x30c50830); 3623 InitReg(MISCREG_ACTLR_EL3) 3624 .mon(); 3625 InitReg(MISCREG_SCR_EL3) 3626 .mon() 3627 .mapsTo(MISCREG_SCR); // NAM D7-2005 3628 InitReg(MISCREG_SDER32_EL3) 3629 .mon() 3630 .mapsTo(MISCREG_SDER); 3631 InitReg(MISCREG_CPTR_EL3) 3632 .mon(); 3633 InitReg(MISCREG_MDCR_EL3) 3634 .mon(); 3635 InitReg(MISCREG_TTBR0_EL1) 3636 .allPrivileges().exceptUserMode() 3637 .mapsTo(MISCREG_TTBR0_NS); 3638 InitReg(MISCREG_TTBR1_EL1) 3639 .allPrivileges().exceptUserMode() 3640 .mapsTo(MISCREG_TTBR1_NS); 3641 InitReg(MISCREG_TCR_EL1) 3642 .allPrivileges().exceptUserMode() 3643 .mapsTo(MISCREG_TTBCR_NS); 3644 InitReg(MISCREG_TTBR0_EL2) 3645 .hyp().mon() 3646 .mapsTo(MISCREG_HTTBR); 3647 InitReg(MISCREG_TTBR1_EL2) 3648 .hyp().mon(); 3649 InitReg(MISCREG_TCR_EL2) 3650 .hyp().mon() 3651 .mapsTo(MISCREG_HTCR); 3652 InitReg(MISCREG_VTTBR_EL2) 3653 .hyp().mon() 3654 .mapsTo(MISCREG_VTTBR); 3655 InitReg(MISCREG_VTCR_EL2) 3656 .hyp().mon() 3657 .mapsTo(MISCREG_VTCR); 3658 InitReg(MISCREG_TTBR0_EL3) 3659 .mon(); 3660 InitReg(MISCREG_TCR_EL3) 3661 .mon(); 3662 InitReg(MISCREG_DACR32_EL2) 3663 .hyp().mon() 3664 .mapsTo(MISCREG_DACR_NS); 3665 InitReg(MISCREG_SPSR_EL1) 3666 .allPrivileges().exceptUserMode() 3667 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1 3668 InitReg(MISCREG_ELR_EL1) 3669 .allPrivileges().exceptUserMode(); 3670 InitReg(MISCREG_SP_EL0) 3671 .allPrivileges().exceptUserMode(); 3672 InitReg(MISCREG_SPSEL) 3673 .allPrivileges().exceptUserMode(); 3674 InitReg(MISCREG_CURRENTEL) 3675 .allPrivileges().exceptUserMode().writes(0); 3676 InitReg(MISCREG_NZCV) 3677 .allPrivileges(); 3678 InitReg(MISCREG_DAIF) 3679 .allPrivileges(); 3680 InitReg(MISCREG_FPCR) 3681 .allPrivileges(); 3682 InitReg(MISCREG_FPSR) 3683 .allPrivileges(); 3684 InitReg(MISCREG_DSPSR_EL0) 3685 .allPrivileges(); 3686 InitReg(MISCREG_DLR_EL0) 3687 .allPrivileges(); 3688 InitReg(MISCREG_SPSR_EL2) 3689 .hyp().mon() 3690 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2 3691 InitReg(MISCREG_ELR_EL2) 3692 .hyp().mon(); 3693 InitReg(MISCREG_SP_EL1) 3694 .hyp().mon(); 3695 InitReg(MISCREG_SPSR_IRQ_AA64) 3696 .hyp().mon(); 3697 InitReg(MISCREG_SPSR_ABT_AA64) 3698 .hyp().mon(); 3699 InitReg(MISCREG_SPSR_UND_AA64) 3700 .hyp().mon(); 3701 InitReg(MISCREG_SPSR_FIQ_AA64) 3702 .hyp().mon(); 3703 InitReg(MISCREG_SPSR_EL3) 3704 .mon() 3705 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3 3706 InitReg(MISCREG_ELR_EL3) 3707 .mon(); 3708 InitReg(MISCREG_SP_EL2) 3709 .mon(); 3710 InitReg(MISCREG_AFSR0_EL1) 3711 .allPrivileges().exceptUserMode() 3712 .mapsTo(MISCREG_ADFSR_NS); 3713 InitReg(MISCREG_AFSR1_EL1) 3714 .allPrivileges().exceptUserMode() 3715 .mapsTo(MISCREG_AIFSR_NS); 3716 InitReg(MISCREG_ESR_EL1) 3717 .allPrivileges().exceptUserMode(); 3718 InitReg(MISCREG_IFSR32_EL2) 3719 .hyp().mon() 3720 .mapsTo(MISCREG_IFSR_NS); 3721 InitReg(MISCREG_AFSR0_EL2) 3722 .hyp().mon() 3723 .mapsTo(MISCREG_HADFSR); 3724 InitReg(MISCREG_AFSR1_EL2) 3725 .hyp().mon() 3726 .mapsTo(MISCREG_HAIFSR); 3727 InitReg(MISCREG_ESR_EL2) 3728 .hyp().mon() 3729 .mapsTo(MISCREG_HSR); 3730 InitReg(MISCREG_FPEXC32_EL2) 3731 .hyp().mon().mapsTo(MISCREG_FPEXC); 3732 InitReg(MISCREG_AFSR0_EL3) 3733 .mon(); 3734 InitReg(MISCREG_AFSR1_EL3) 3735 .mon(); 3736 InitReg(MISCREG_ESR_EL3) 3737 .mon(); 3738 InitReg(MISCREG_FAR_EL1) 3739 .allPrivileges().exceptUserMode() 3740 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS); 3741 InitReg(MISCREG_FAR_EL2) 3742 .hyp().mon() 3743 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR); 3744 InitReg(MISCREG_HPFAR_EL2) 3745 .hyp().mon() 3746 .mapsTo(MISCREG_HPFAR); 3747 InitReg(MISCREG_FAR_EL3) 3748 .mon(); 3749 InitReg(MISCREG_IC_IALLUIS) 3750 .warnNotFail() 3751 .writes(1).exceptUserMode(); 3752 InitReg(MISCREG_PAR_EL1) 3753 .allPrivileges().exceptUserMode() 3754 .mapsTo(MISCREG_PAR_NS); 3755 InitReg(MISCREG_IC_IALLU) 3756 .warnNotFail() 3757 .writes(1).exceptUserMode(); 3758 InitReg(MISCREG_DC_IVAC_Xt) 3759 .warnNotFail() 3760 .writes(1).exceptUserMode(); 3761 InitReg(MISCREG_DC_ISW_Xt) 3762 .warnNotFail() 3763 .writes(1).exceptUserMode(); 3764 InitReg(MISCREG_AT_S1E1R_Xt) 3765 .writes(1).exceptUserMode(); 3766 InitReg(MISCREG_AT_S1E1W_Xt) 3767 .writes(1).exceptUserMode(); 3768 InitReg(MISCREG_AT_S1E0R_Xt) 3769 .writes(1).exceptUserMode(); 3770 InitReg(MISCREG_AT_S1E0W_Xt) 3771 .writes(1).exceptUserMode(); 3772 InitReg(MISCREG_DC_CSW_Xt) 3773 .warnNotFail() 3774 .writes(1).exceptUserMode(); 3775 InitReg(MISCREG_DC_CISW_Xt) 3776 .warnNotFail() 3777 .writes(1).exceptUserMode(); 3778 InitReg(MISCREG_DC_ZVA_Xt) 3779 .warnNotFail() 3780 .writes(1).userSecureWrite(0); 3781 InitReg(MISCREG_IC_IVAU_Xt) 3782 .writes(1); 3783 InitReg(MISCREG_DC_CVAC_Xt) 3784 .warnNotFail() 3785 .writes(1); 3786 InitReg(MISCREG_DC_CVAU_Xt) 3787 .warnNotFail() 3788 .writes(1); 3789 InitReg(MISCREG_DC_CIVAC_Xt) 3790 .warnNotFail() 3791 .writes(1); 3792 InitReg(MISCREG_AT_S1E2R_Xt) 3793 .monNonSecureWrite().hypWrite(); 3794 InitReg(MISCREG_AT_S1E2W_Xt) 3795 .monNonSecureWrite().hypWrite(); 3796 InitReg(MISCREG_AT_S12E1R_Xt) 3797 .hypWrite().monSecureWrite().monNonSecureWrite(); 3798 InitReg(MISCREG_AT_S12E1W_Xt) 3799 .hypWrite().monSecureWrite().monNonSecureWrite(); 3800 InitReg(MISCREG_AT_S12E0R_Xt) 3801 .hypWrite().monSecureWrite().monNonSecureWrite(); 3802 InitReg(MISCREG_AT_S12E0W_Xt) 3803 .hypWrite().monSecureWrite().monNonSecureWrite(); 3804 InitReg(MISCREG_AT_S1E3R_Xt) 3805 .monSecureWrite().monNonSecureWrite(); 3806 InitReg(MISCREG_AT_S1E3W_Xt) 3807 .monSecureWrite().monNonSecureWrite(); 3808 InitReg(MISCREG_TLBI_VMALLE1IS) 3809 .writes(1).exceptUserMode(); 3810 InitReg(MISCREG_TLBI_VAE1IS_Xt) 3811 .writes(1).exceptUserMode(); 3812 InitReg(MISCREG_TLBI_ASIDE1IS_Xt) 3813 .writes(1).exceptUserMode(); 3814 InitReg(MISCREG_TLBI_VAAE1IS_Xt) 3815 .writes(1).exceptUserMode(); 3816 InitReg(MISCREG_TLBI_VALE1IS_Xt) 3817 .writes(1).exceptUserMode(); 3818 InitReg(MISCREG_TLBI_VAALE1IS_Xt) 3819 .writes(1).exceptUserMode(); 3820 InitReg(MISCREG_TLBI_VMALLE1) 3821 .writes(1).exceptUserMode(); 3822 InitReg(MISCREG_TLBI_VAE1_Xt) 3823 .writes(1).exceptUserMode(); 3824 InitReg(MISCREG_TLBI_ASIDE1_Xt) 3825 .writes(1).exceptUserMode(); 3826 InitReg(MISCREG_TLBI_VAAE1_Xt) 3827 .writes(1).exceptUserMode(); 3828 InitReg(MISCREG_TLBI_VALE1_Xt) 3829 .writes(1).exceptUserMode(); 3830 InitReg(MISCREG_TLBI_VAALE1_Xt) 3831 .writes(1).exceptUserMode(); 3832 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt) 3833 .hypWrite().monSecureWrite().monNonSecureWrite(); 3834 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt) 3835 .hypWrite().monSecureWrite().monNonSecureWrite(); 3836 InitReg(MISCREG_TLBI_ALLE2IS) 3837 .monNonSecureWrite().hypWrite(); 3838 InitReg(MISCREG_TLBI_VAE2IS_Xt) 3839 .monNonSecureWrite().hypWrite(); 3840 InitReg(MISCREG_TLBI_ALLE1IS) 3841 .hypWrite().monSecureWrite().monNonSecureWrite(); 3842 InitReg(MISCREG_TLBI_VALE2IS_Xt) 3843 .monNonSecureWrite().hypWrite(); 3844 InitReg(MISCREG_TLBI_VMALLS12E1IS) 3845 .hypWrite().monSecureWrite().monNonSecureWrite(); 3846 InitReg(MISCREG_TLBI_IPAS2E1_Xt) 3847 .hypWrite().monSecureWrite().monNonSecureWrite(); 3848 InitReg(MISCREG_TLBI_IPAS2LE1_Xt) 3849 .hypWrite().monSecureWrite().monNonSecureWrite(); 3850 InitReg(MISCREG_TLBI_ALLE2) 3851 .monNonSecureWrite().hypWrite(); 3852 InitReg(MISCREG_TLBI_VAE2_Xt) 3853 .monNonSecureWrite().hypWrite(); 3854 InitReg(MISCREG_TLBI_ALLE1) 3855 .hypWrite().monSecureWrite().monNonSecureWrite(); 3856 InitReg(MISCREG_TLBI_VALE2_Xt) 3857 .monNonSecureWrite().hypWrite(); 3858 InitReg(MISCREG_TLBI_VMALLS12E1) 3859 .hypWrite().monSecureWrite().monNonSecureWrite(); 3860 InitReg(MISCREG_TLBI_ALLE3IS) 3861 .monSecureWrite().monNonSecureWrite(); 3862 InitReg(MISCREG_TLBI_VAE3IS_Xt) 3863 .monSecureWrite().monNonSecureWrite(); 3864 InitReg(MISCREG_TLBI_VALE3IS_Xt) 3865 .monSecureWrite().monNonSecureWrite(); 3866 InitReg(MISCREG_TLBI_ALLE3) 3867 .monSecureWrite().monNonSecureWrite(); 3868 InitReg(MISCREG_TLBI_VAE3_Xt) 3869 .monSecureWrite().monNonSecureWrite(); 3870 InitReg(MISCREG_TLBI_VALE3_Xt) 3871 .monSecureWrite().monNonSecureWrite(); 3872 InitReg(MISCREG_PMINTENSET_EL1) 3873 .allPrivileges().exceptUserMode() 3874 .mapsTo(MISCREG_PMINTENSET); 3875 InitReg(MISCREG_PMINTENCLR_EL1) 3876 .allPrivileges().exceptUserMode() 3877 .mapsTo(MISCREG_PMINTENCLR); 3878 InitReg(MISCREG_PMCR_EL0) 3879 .allPrivileges() 3880 .mapsTo(MISCREG_PMCR); 3881 InitReg(MISCREG_PMCNTENSET_EL0) 3882 .allPrivileges() 3883 .mapsTo(MISCREG_PMCNTENSET); 3884 InitReg(MISCREG_PMCNTENCLR_EL0) 3885 .allPrivileges() 3886 .mapsTo(MISCREG_PMCNTENCLR); 3887 InitReg(MISCREG_PMOVSCLR_EL0) 3888 .allPrivileges(); 3889// .mapsTo(MISCREG_PMOVSCLR); 3890 InitReg(MISCREG_PMSWINC_EL0) 3891 .writes(1).user() 3892 .mapsTo(MISCREG_PMSWINC); 3893 InitReg(MISCREG_PMSELR_EL0) 3894 .allPrivileges() 3895 .mapsTo(MISCREG_PMSELR); 3896 InitReg(MISCREG_PMCEID0_EL0) 3897 .reads(1).user() 3898 .mapsTo(MISCREG_PMCEID0); 3899 InitReg(MISCREG_PMCEID1_EL0) 3900 .reads(1).user() 3901 .mapsTo(MISCREG_PMCEID1); 3902 InitReg(MISCREG_PMCCNTR_EL0) 3903 .allPrivileges() 3904 .mapsTo(MISCREG_PMCCNTR); 3905 InitReg(MISCREG_PMXEVTYPER_EL0) 3906 .allPrivileges() 3907 .mapsTo(MISCREG_PMXEVTYPER); 3908 InitReg(MISCREG_PMCCFILTR_EL0) 3909 .allPrivileges(); 3910 InitReg(MISCREG_PMXEVCNTR_EL0) 3911 .allPrivileges() 3912 .mapsTo(MISCREG_PMXEVCNTR); 3913 InitReg(MISCREG_PMUSERENR_EL0) 3914 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0) 3915 .mapsTo(MISCREG_PMUSERENR); 3916 InitReg(MISCREG_PMOVSSET_EL0) 3917 .allPrivileges() 3918 .mapsTo(MISCREG_PMOVSSET); 3919 InitReg(MISCREG_MAIR_EL1) 3920 .allPrivileges().exceptUserMode() 3921 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS); 3922 InitReg(MISCREG_AMAIR_EL1) 3923 .allPrivileges().exceptUserMode() 3924 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS); 3925 InitReg(MISCREG_MAIR_EL2) 3926 .hyp().mon() 3927 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1); 3928 InitReg(MISCREG_AMAIR_EL2) 3929 .hyp().mon() 3930 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1); 3931 InitReg(MISCREG_MAIR_EL3) 3932 .mon(); 3933 InitReg(MISCREG_AMAIR_EL3) 3934 .mon(); 3935 InitReg(MISCREG_L2CTLR_EL1) 3936 .allPrivileges().exceptUserMode(); 3937 InitReg(MISCREG_L2ECTLR_EL1) 3938 .allPrivileges().exceptUserMode(); 3939 InitReg(MISCREG_VBAR_EL1) 3940 .allPrivileges().exceptUserMode() 3941 .mapsTo(MISCREG_VBAR_NS); 3942 InitReg(MISCREG_RVBAR_EL1) 3943 .allPrivileges().exceptUserMode().writes(0); 3944 InitReg(MISCREG_ISR_EL1) 3945 .allPrivileges().exceptUserMode().writes(0); 3946 InitReg(MISCREG_VBAR_EL2) 3947 .hyp().mon() 3948 .res0(0x7ff) 3949 .mapsTo(MISCREG_HVBAR); 3950 InitReg(MISCREG_RVBAR_EL2) 3951 .mon().hyp().writes(0); 3952 InitReg(MISCREG_VBAR_EL3) 3953 .mon(); 3954 InitReg(MISCREG_RVBAR_EL3) 3955 .mon().writes(0); 3956 InitReg(MISCREG_RMR_EL3) 3957 .mon(); 3958 InitReg(MISCREG_CONTEXTIDR_EL1) 3959 .allPrivileges().exceptUserMode() 3960 .mapsTo(MISCREG_CONTEXTIDR_NS); 3961 InitReg(MISCREG_TPIDR_EL1) 3962 .allPrivileges().exceptUserMode() 3963 .mapsTo(MISCREG_TPIDRPRW_NS); 3964 InitReg(MISCREG_TPIDR_EL0) 3965 .allPrivileges() 3966 .mapsTo(MISCREG_TPIDRURW_NS); 3967 InitReg(MISCREG_TPIDRRO_EL0) 3968 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0) 3969 .mapsTo(MISCREG_TPIDRURO_NS); 3970 InitReg(MISCREG_TPIDR_EL2) 3971 .hyp().mon() 3972 .mapsTo(MISCREG_HTPIDR); 3973 InitReg(MISCREG_TPIDR_EL3) 3974 .mon(); 3975 InitReg(MISCREG_CNTKCTL_EL1) 3976 .allPrivileges().exceptUserMode() 3977 .mapsTo(MISCREG_CNTKCTL); 3978 InitReg(MISCREG_CNTFRQ_EL0) 3979 .reads(1).mon() 3980 .mapsTo(MISCREG_CNTFRQ); 3981 InitReg(MISCREG_CNTPCT_EL0) 3982 .reads(1) 3983 .mapsTo(MISCREG_CNTPCT); /* 64b */ 3984 InitReg(MISCREG_CNTVCT_EL0) 3985 .unverifiable() 3986 .reads(1) 3987 .mapsTo(MISCREG_CNTVCT); /* 64b */ 3988 InitReg(MISCREG_CNTP_TVAL_EL0) 3989 .allPrivileges() 3990 .mapsTo(MISCREG_CNTP_TVAL_NS); 3991 InitReg(MISCREG_CNTP_CTL_EL0) 3992 .allPrivileges() 3993 .mapsTo(MISCREG_CNTP_CTL_NS); 3994 InitReg(MISCREG_CNTP_CVAL_EL0) 3995 .allPrivileges() 3996 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */ 3997 InitReg(MISCREG_CNTV_TVAL_EL0) 3998 .allPrivileges() 3999 .mapsTo(MISCREG_CNTV_TVAL); 4000 InitReg(MISCREG_CNTV_CTL_EL0) 4001 .allPrivileges() 4002 .mapsTo(MISCREG_CNTV_CTL); 4003 InitReg(MISCREG_CNTV_CVAL_EL0) 4004 .allPrivileges() 4005 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */ 4006 InitReg(MISCREG_PMEVCNTR0_EL0) 4007 .allPrivileges(); 4008// .mapsTo(MISCREG_PMEVCNTR0); 4009 InitReg(MISCREG_PMEVCNTR1_EL0) 4010 .allPrivileges(); 4011// .mapsTo(MISCREG_PMEVCNTR1); 4012 InitReg(MISCREG_PMEVCNTR2_EL0) 4013 .allPrivileges(); 4014// .mapsTo(MISCREG_PMEVCNTR2); 4015 InitReg(MISCREG_PMEVCNTR3_EL0) 4016 .allPrivileges(); 4017// .mapsTo(MISCREG_PMEVCNTR3); 4018 InitReg(MISCREG_PMEVCNTR4_EL0) 4019 .allPrivileges(); 4020// .mapsTo(MISCREG_PMEVCNTR4); 4021 InitReg(MISCREG_PMEVCNTR5_EL0) 4022 .allPrivileges(); 4023// .mapsTo(MISCREG_PMEVCNTR5); 4024 InitReg(MISCREG_PMEVTYPER0_EL0) 4025 .allPrivileges(); 4026// .mapsTo(MISCREG_PMEVTYPER0); 4027 InitReg(MISCREG_PMEVTYPER1_EL0) 4028 .allPrivileges(); 4029// .mapsTo(MISCREG_PMEVTYPER1); 4030 InitReg(MISCREG_PMEVTYPER2_EL0) 4031 .allPrivileges(); 4032// .mapsTo(MISCREG_PMEVTYPER2); 4033 InitReg(MISCREG_PMEVTYPER3_EL0) 4034 .allPrivileges(); 4035// .mapsTo(MISCREG_PMEVTYPER3); 4036 InitReg(MISCREG_PMEVTYPER4_EL0) 4037 .allPrivileges(); 4038// .mapsTo(MISCREG_PMEVTYPER4); 4039 InitReg(MISCREG_PMEVTYPER5_EL0) 4040 .allPrivileges(); 4041// .mapsTo(MISCREG_PMEVTYPER5); 4042 InitReg(MISCREG_CNTVOFF_EL2) 4043 .hyp().mon() 4044 .mapsTo(MISCREG_CNTVOFF); /* 64b */ 4045 InitReg(MISCREG_CNTHCTL_EL2) 4046 .mon().hyp() 4047 .mapsTo(MISCREG_CNTHCTL); 4048 InitReg(MISCREG_CNTHP_TVAL_EL2) 4049 .mon().hyp() 4050 .mapsTo(MISCREG_CNTHP_TVAL); 4051 InitReg(MISCREG_CNTHP_CTL_EL2) 4052 .mon().hyp() 4053 .mapsTo(MISCREG_CNTHP_CTL); 4054 InitReg(MISCREG_CNTHP_CVAL_EL2) 4055 .mon().hyp() 4056 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */ 4057 InitReg(MISCREG_CNTPS_TVAL_EL1) 4058 .mon().privSecure(); 4059 InitReg(MISCREG_CNTPS_CTL_EL1) 4060 .mon().privSecure(); 4061 InitReg(MISCREG_CNTPS_CVAL_EL1) 4062 .mon().privSecure(); 4063 InitReg(MISCREG_IL1DATA0_EL1) 4064 .allPrivileges().exceptUserMode(); 4065 InitReg(MISCREG_IL1DATA1_EL1) 4066 .allPrivileges().exceptUserMode(); 4067 InitReg(MISCREG_IL1DATA2_EL1) 4068 .allPrivileges().exceptUserMode(); 4069 InitReg(MISCREG_IL1DATA3_EL1) 4070 .allPrivileges().exceptUserMode(); 4071 InitReg(MISCREG_DL1DATA0_EL1) 4072 .allPrivileges().exceptUserMode(); 4073 InitReg(MISCREG_DL1DATA1_EL1) 4074 .allPrivileges().exceptUserMode(); 4075 InitReg(MISCREG_DL1DATA2_EL1) 4076 .allPrivileges().exceptUserMode(); 4077 InitReg(MISCREG_DL1DATA3_EL1) 4078 .allPrivileges().exceptUserMode(); 4079 InitReg(MISCREG_DL1DATA4_EL1) 4080 .allPrivileges().exceptUserMode(); 4081 InitReg(MISCREG_L2ACTLR_EL1) 4082 .allPrivileges().exceptUserMode(); 4083 InitReg(MISCREG_CPUACTLR_EL1) 4084 .allPrivileges().exceptUserMode(); 4085 InitReg(MISCREG_CPUECTLR_EL1) 4086 .allPrivileges().exceptUserMode(); 4087 InitReg(MISCREG_CPUMERRSR_EL1) 4088 .allPrivileges().exceptUserMode(); 4089 InitReg(MISCREG_L2MERRSR_EL1) 4090 .unimplemented() 4091 .warnNotFail() 4092 .allPrivileges().exceptUserMode(); 4093 InitReg(MISCREG_CBAR_EL1) 4094 .allPrivileges().exceptUserMode().writes(0); 4095 InitReg(MISCREG_CONTEXTIDR_EL2) 4096 .mon().hyp();
| 2532 } 2533 break; 2534 } 2535 break; 2536 case 13: 2537 switch (op1) { 2538 case 0: 2539 switch (crm) { 2540 case 0: 2541 switch (op2) { 2542 case 1: 2543 return MISCREG_CONTEXTIDR_EL1; 2544 case 4: 2545 return MISCREG_TPIDR_EL1; 2546 } 2547 break; 2548 } 2549 break; 2550 case 3: 2551 switch (crm) { 2552 case 0: 2553 switch (op2) { 2554 case 2: 2555 return MISCREG_TPIDR_EL0; 2556 case 3: 2557 return MISCREG_TPIDRRO_EL0; 2558 } 2559 break; 2560 } 2561 break; 2562 case 4: 2563 switch (crm) { 2564 case 0: 2565 switch (op2) { 2566 case 1: 2567 return MISCREG_CONTEXTIDR_EL2; 2568 case 2: 2569 return MISCREG_TPIDR_EL2; 2570 } 2571 break; 2572 } 2573 break; 2574 case 6: 2575 switch (crm) { 2576 case 0: 2577 switch (op2) { 2578 case 2: 2579 return MISCREG_TPIDR_EL3; 2580 } 2581 break; 2582 } 2583 break; 2584 } 2585 break; 2586 case 14: 2587 switch (op1) { 2588 case 0: 2589 switch (crm) { 2590 case 1: 2591 switch (op2) { 2592 case 0: 2593 return MISCREG_CNTKCTL_EL1; 2594 } 2595 break; 2596 } 2597 break; 2598 case 3: 2599 switch (crm) { 2600 case 0: 2601 switch (op2) { 2602 case 0: 2603 return MISCREG_CNTFRQ_EL0; 2604 case 1: 2605 return MISCREG_CNTPCT_EL0; 2606 case 2: 2607 return MISCREG_CNTVCT_EL0; 2608 } 2609 break; 2610 case 2: 2611 switch (op2) { 2612 case 0: 2613 return MISCREG_CNTP_TVAL_EL0; 2614 case 1: 2615 return MISCREG_CNTP_CTL_EL0; 2616 case 2: 2617 return MISCREG_CNTP_CVAL_EL0; 2618 } 2619 break; 2620 case 3: 2621 switch (op2) { 2622 case 0: 2623 return MISCREG_CNTV_TVAL_EL0; 2624 case 1: 2625 return MISCREG_CNTV_CTL_EL0; 2626 case 2: 2627 return MISCREG_CNTV_CVAL_EL0; 2628 } 2629 break; 2630 case 8: 2631 switch (op2) { 2632 case 0: 2633 return MISCREG_PMEVCNTR0_EL0; 2634 case 1: 2635 return MISCREG_PMEVCNTR1_EL0; 2636 case 2: 2637 return MISCREG_PMEVCNTR2_EL0; 2638 case 3: 2639 return MISCREG_PMEVCNTR3_EL0; 2640 case 4: 2641 return MISCREG_PMEVCNTR4_EL0; 2642 case 5: 2643 return MISCREG_PMEVCNTR5_EL0; 2644 } 2645 break; 2646 case 12: 2647 switch (op2) { 2648 case 0: 2649 return MISCREG_PMEVTYPER0_EL0; 2650 case 1: 2651 return MISCREG_PMEVTYPER1_EL0; 2652 case 2: 2653 return MISCREG_PMEVTYPER2_EL0; 2654 case 3: 2655 return MISCREG_PMEVTYPER3_EL0; 2656 case 4: 2657 return MISCREG_PMEVTYPER4_EL0; 2658 case 5: 2659 return MISCREG_PMEVTYPER5_EL0; 2660 } 2661 break; 2662 case 15: 2663 switch (op2) { 2664 case 7: 2665 return MISCREG_PMCCFILTR_EL0; 2666 } 2667 } 2668 break; 2669 case 4: 2670 switch (crm) { 2671 case 0: 2672 switch (op2) { 2673 case 3: 2674 return MISCREG_CNTVOFF_EL2; 2675 } 2676 break; 2677 case 1: 2678 switch (op2) { 2679 case 0: 2680 return MISCREG_CNTHCTL_EL2; 2681 } 2682 break; 2683 case 2: 2684 switch (op2) { 2685 case 0: 2686 return MISCREG_CNTHP_TVAL_EL2; 2687 case 1: 2688 return MISCREG_CNTHP_CTL_EL2; 2689 case 2: 2690 return MISCREG_CNTHP_CVAL_EL2; 2691 } 2692 break; 2693 case 3: 2694 switch (op2) { 2695 case 0: 2696 return MISCREG_CNTHV_TVAL_EL2; 2697 case 1: 2698 return MISCREG_CNTHV_CTL_EL2; 2699 case 2: 2700 return MISCREG_CNTHV_CVAL_EL2; 2701 } 2702 break; 2703 } 2704 break; 2705 case 7: 2706 switch (crm) { 2707 case 2: 2708 switch (op2) { 2709 case 0: 2710 return MISCREG_CNTPS_TVAL_EL1; 2711 case 1: 2712 return MISCREG_CNTPS_CTL_EL1; 2713 case 2: 2714 return MISCREG_CNTPS_CVAL_EL1; 2715 } 2716 break; 2717 } 2718 break; 2719 } 2720 break; 2721 case 15: 2722 switch (op1) { 2723 case 0: 2724 switch (crm) { 2725 case 0: 2726 switch (op2) { 2727 case 0: 2728 return MISCREG_IL1DATA0_EL1; 2729 case 1: 2730 return MISCREG_IL1DATA1_EL1; 2731 case 2: 2732 return MISCREG_IL1DATA2_EL1; 2733 case 3: 2734 return MISCREG_IL1DATA3_EL1; 2735 } 2736 break; 2737 case 1: 2738 switch (op2) { 2739 case 0: 2740 return MISCREG_DL1DATA0_EL1; 2741 case 1: 2742 return MISCREG_DL1DATA1_EL1; 2743 case 2: 2744 return MISCREG_DL1DATA2_EL1; 2745 case 3: 2746 return MISCREG_DL1DATA3_EL1; 2747 case 4: 2748 return MISCREG_DL1DATA4_EL1; 2749 } 2750 break; 2751 } 2752 break; 2753 case 1: 2754 switch (crm) { 2755 case 0: 2756 switch (op2) { 2757 case 0: 2758 return MISCREG_L2ACTLR_EL1; 2759 } 2760 break; 2761 case 2: 2762 switch (op2) { 2763 case 0: 2764 return MISCREG_CPUACTLR_EL1; 2765 case 1: 2766 return MISCREG_CPUECTLR_EL1; 2767 case 2: 2768 return MISCREG_CPUMERRSR_EL1; 2769 case 3: 2770 return MISCREG_L2MERRSR_EL1; 2771 } 2772 break; 2773 case 3: 2774 switch (op2) { 2775 case 0: 2776 return MISCREG_CBAR_EL1; 2777 2778 } 2779 break; 2780 } 2781 break; 2782 } 2783 // S3_<op1>_15_<Cm>_<op2> 2784 return MISCREG_IMPDEF_UNIMPL; 2785 } 2786 break; 2787 } 2788 2789 return MISCREG_UNKNOWN; 2790} 2791 2792bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below 2793 2794void 2795ISA::initializeMiscRegMetadata() 2796{ 2797 // the MiscReg metadata tables are shared across all instances of the 2798 // ISA object, so there's no need to initialize them multiple times. 2799 static bool completed = false; 2800 if (completed) 2801 return; 2802 2803 // This boolean variable specifies if the system is running in aarch32 at 2804 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it 2805 // is running in aarch64 (aarch32EL3 = false) 2806 bool aarch32EL3 = haveSecurity && !highestELIs64; 2807 2808 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+), 2809 // unsupported 2810 bool SPAN = false; 2811 2812 // Implicit error synchronization event enable (Arm 8.2+), unsupported 2813 bool IESB = false; 2814 2815 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+), 2816 // unsupported 2817 bool LSMAOE = false; 2818 2819 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported 2820 bool nTLSMD = false; 2821 2822 // Pointer authentication (Arm 8.3+), unsupported 2823 bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1 2824 bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1 2825 bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1 2826 bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1 2827 2828 /** 2829 * Some registers alias with others, and therefore need to be translated. 2830 * When two mapping registers are given, they are the 32b lower and 2831 * upper halves, respectively, of the 64b register being mapped. 2832 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 2833 * 2834 * NAM = "not architecturally mandated", 2835 * from ARM DDI 0487A.i, template text 2836 * "AArch64 System register ___ can be mapped to 2837 * AArch32 System register ___, but this is not 2838 * architecturally mandated." 2839 */ 2840 2841 InitReg(MISCREG_CPSR) 2842 .allPrivileges(); 2843 InitReg(MISCREG_SPSR) 2844 .allPrivileges(); 2845 InitReg(MISCREG_SPSR_FIQ) 2846 .allPrivileges(); 2847 InitReg(MISCREG_SPSR_IRQ) 2848 .allPrivileges(); 2849 InitReg(MISCREG_SPSR_SVC) 2850 .allPrivileges(); 2851 InitReg(MISCREG_SPSR_MON) 2852 .allPrivileges(); 2853 InitReg(MISCREG_SPSR_ABT) 2854 .allPrivileges(); 2855 InitReg(MISCREG_SPSR_HYP) 2856 .allPrivileges(); 2857 InitReg(MISCREG_SPSR_UND) 2858 .allPrivileges(); 2859 InitReg(MISCREG_ELR_HYP) 2860 .allPrivileges(); 2861 InitReg(MISCREG_FPSID) 2862 .allPrivileges(); 2863 InitReg(MISCREG_FPSCR) 2864 .allPrivileges(); 2865 InitReg(MISCREG_MVFR1) 2866 .allPrivileges(); 2867 InitReg(MISCREG_MVFR0) 2868 .allPrivileges(); 2869 InitReg(MISCREG_FPEXC) 2870 .allPrivileges(); 2871 2872 // Helper registers 2873 InitReg(MISCREG_CPSR_MODE) 2874 .allPrivileges(); 2875 InitReg(MISCREG_CPSR_Q) 2876 .allPrivileges(); 2877 InitReg(MISCREG_FPSCR_EXC) 2878 .allPrivileges(); 2879 InitReg(MISCREG_FPSCR_QC) 2880 .allPrivileges(); 2881 InitReg(MISCREG_LOCKADDR) 2882 .allPrivileges(); 2883 InitReg(MISCREG_LOCKFLAG) 2884 .allPrivileges(); 2885 InitReg(MISCREG_PRRR_MAIR0) 2886 .mutex() 2887 .banked(); 2888 InitReg(MISCREG_PRRR_MAIR0_NS) 2889 .mutex() 2890 .privSecure(!aarch32EL3) 2891 .bankedChild(); 2892 InitReg(MISCREG_PRRR_MAIR0_S) 2893 .mutex() 2894 .bankedChild(); 2895 InitReg(MISCREG_NMRR_MAIR1) 2896 .mutex() 2897 .banked(); 2898 InitReg(MISCREG_NMRR_MAIR1_NS) 2899 .mutex() 2900 .privSecure(!aarch32EL3) 2901 .bankedChild(); 2902 InitReg(MISCREG_NMRR_MAIR1_S) 2903 .mutex() 2904 .bankedChild(); 2905 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR) 2906 .mutex(); 2907 InitReg(MISCREG_SCTLR_RST) 2908 .allPrivileges(); 2909 InitReg(MISCREG_SEV_MAILBOX) 2910 .allPrivileges(); 2911 2912 // AArch32 CP14 registers 2913 InitReg(MISCREG_DBGDIDR) 2914 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2915 InitReg(MISCREG_DBGDSCRint) 2916 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 2917 InitReg(MISCREG_DBGDCCINT) 2918 .unimplemented() 2919 .allPrivileges(); 2920 InitReg(MISCREG_DBGDTRTXint) 2921 .unimplemented() 2922 .allPrivileges(); 2923 InitReg(MISCREG_DBGDTRRXint) 2924 .unimplemented() 2925 .allPrivileges(); 2926 InitReg(MISCREG_DBGWFAR) 2927 .unimplemented() 2928 .allPrivileges(); 2929 InitReg(MISCREG_DBGVCR) 2930 .unimplemented() 2931 .allPrivileges(); 2932 InitReg(MISCREG_DBGDTRRXext) 2933 .unimplemented() 2934 .allPrivileges(); 2935 InitReg(MISCREG_DBGDSCRext) 2936 .unimplemented() 2937 .warnNotFail() 2938 .allPrivileges(); 2939 InitReg(MISCREG_DBGDTRTXext) 2940 .unimplemented() 2941 .allPrivileges(); 2942 InitReg(MISCREG_DBGOSECCR) 2943 .unimplemented() 2944 .allPrivileges(); 2945 InitReg(MISCREG_DBGBVR0) 2946 .unimplemented() 2947 .allPrivileges(); 2948 InitReg(MISCREG_DBGBVR1) 2949 .unimplemented() 2950 .allPrivileges(); 2951 InitReg(MISCREG_DBGBVR2) 2952 .unimplemented() 2953 .allPrivileges(); 2954 InitReg(MISCREG_DBGBVR3) 2955 .unimplemented() 2956 .allPrivileges(); 2957 InitReg(MISCREG_DBGBVR4) 2958 .unimplemented() 2959 .allPrivileges(); 2960 InitReg(MISCREG_DBGBVR5) 2961 .unimplemented() 2962 .allPrivileges(); 2963 InitReg(MISCREG_DBGBCR0) 2964 .unimplemented() 2965 .allPrivileges(); 2966 InitReg(MISCREG_DBGBCR1) 2967 .unimplemented() 2968 .allPrivileges(); 2969 InitReg(MISCREG_DBGBCR2) 2970 .unimplemented() 2971 .allPrivileges(); 2972 InitReg(MISCREG_DBGBCR3) 2973 .unimplemented() 2974 .allPrivileges(); 2975 InitReg(MISCREG_DBGBCR4) 2976 .unimplemented() 2977 .allPrivileges(); 2978 InitReg(MISCREG_DBGBCR5) 2979 .unimplemented() 2980 .allPrivileges(); 2981 InitReg(MISCREG_DBGWVR0) 2982 .unimplemented() 2983 .allPrivileges(); 2984 InitReg(MISCREG_DBGWVR1) 2985 .unimplemented() 2986 .allPrivileges(); 2987 InitReg(MISCREG_DBGWVR2) 2988 .unimplemented() 2989 .allPrivileges(); 2990 InitReg(MISCREG_DBGWVR3) 2991 .unimplemented() 2992 .allPrivileges(); 2993 InitReg(MISCREG_DBGWCR0) 2994 .unimplemented() 2995 .allPrivileges(); 2996 InitReg(MISCREG_DBGWCR1) 2997 .unimplemented() 2998 .allPrivileges(); 2999 InitReg(MISCREG_DBGWCR2) 3000 .unimplemented() 3001 .allPrivileges(); 3002 InitReg(MISCREG_DBGWCR3) 3003 .unimplemented() 3004 .allPrivileges(); 3005 InitReg(MISCREG_DBGDRAR) 3006 .unimplemented() 3007 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 3008 InitReg(MISCREG_DBGBXVR4) 3009 .unimplemented() 3010 .allPrivileges(); 3011 InitReg(MISCREG_DBGBXVR5) 3012 .unimplemented() 3013 .allPrivileges(); 3014 InitReg(MISCREG_DBGOSLAR) 3015 .unimplemented() 3016 .allPrivileges().monSecureRead(0).monNonSecureRead(0); 3017 InitReg(MISCREG_DBGOSLSR) 3018 .unimplemented() 3019 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 3020 InitReg(MISCREG_DBGOSDLR) 3021 .unimplemented() 3022 .allPrivileges(); 3023 InitReg(MISCREG_DBGPRCR) 3024 .unimplemented() 3025 .allPrivileges(); 3026 InitReg(MISCREG_DBGDSAR) 3027 .unimplemented() 3028 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 3029 InitReg(MISCREG_DBGCLAIMSET) 3030 .unimplemented() 3031 .allPrivileges(); 3032 InitReg(MISCREG_DBGCLAIMCLR) 3033 .unimplemented() 3034 .allPrivileges(); 3035 InitReg(MISCREG_DBGAUTHSTATUS) 3036 .unimplemented() 3037 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 3038 InitReg(MISCREG_DBGDEVID2) 3039 .unimplemented() 3040 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 3041 InitReg(MISCREG_DBGDEVID1) 3042 .unimplemented() 3043 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 3044 InitReg(MISCREG_DBGDEVID0) 3045 .unimplemented() 3046 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0); 3047 InitReg(MISCREG_TEECR) 3048 .unimplemented() 3049 .allPrivileges(); 3050 InitReg(MISCREG_JIDR) 3051 .allPrivileges(); 3052 InitReg(MISCREG_TEEHBR) 3053 .allPrivileges(); 3054 InitReg(MISCREG_JOSCR) 3055 .allPrivileges(); 3056 InitReg(MISCREG_JMCR) 3057 .allPrivileges(); 3058 3059 // AArch32 CP15 registers 3060 InitReg(MISCREG_MIDR) 3061 .allPrivileges().exceptUserMode().writes(0); 3062 InitReg(MISCREG_CTR) 3063 .allPrivileges().exceptUserMode().writes(0); 3064 InitReg(MISCREG_TCMTR) 3065 .allPrivileges().exceptUserMode().writes(0); 3066 InitReg(MISCREG_TLBTR) 3067 .allPrivileges().exceptUserMode().writes(0); 3068 InitReg(MISCREG_MPIDR) 3069 .allPrivileges().exceptUserMode().writes(0); 3070 InitReg(MISCREG_REVIDR) 3071 .unimplemented() 3072 .warnNotFail() 3073 .allPrivileges().exceptUserMode().writes(0); 3074 InitReg(MISCREG_ID_PFR0) 3075 .allPrivileges().exceptUserMode().writes(0); 3076 InitReg(MISCREG_ID_PFR1) 3077 .allPrivileges().exceptUserMode().writes(0); 3078 InitReg(MISCREG_ID_DFR0) 3079 .allPrivileges().exceptUserMode().writes(0); 3080 InitReg(MISCREG_ID_AFR0) 3081 .allPrivileges().exceptUserMode().writes(0); 3082 InitReg(MISCREG_ID_MMFR0) 3083 .allPrivileges().exceptUserMode().writes(0); 3084 InitReg(MISCREG_ID_MMFR1) 3085 .allPrivileges().exceptUserMode().writes(0); 3086 InitReg(MISCREG_ID_MMFR2) 3087 .allPrivileges().exceptUserMode().writes(0); 3088 InitReg(MISCREG_ID_MMFR3) 3089 .allPrivileges().exceptUserMode().writes(0); 3090 InitReg(MISCREG_ID_ISAR0) 3091 .allPrivileges().exceptUserMode().writes(0); 3092 InitReg(MISCREG_ID_ISAR1) 3093 .allPrivileges().exceptUserMode().writes(0); 3094 InitReg(MISCREG_ID_ISAR2) 3095 .allPrivileges().exceptUserMode().writes(0); 3096 InitReg(MISCREG_ID_ISAR3) 3097 .allPrivileges().exceptUserMode().writes(0); 3098 InitReg(MISCREG_ID_ISAR4) 3099 .allPrivileges().exceptUserMode().writes(0); 3100 InitReg(MISCREG_ID_ISAR5) 3101 .allPrivileges().exceptUserMode().writes(0); 3102 InitReg(MISCREG_CCSIDR) 3103 .allPrivileges().exceptUserMode().writes(0); 3104 InitReg(MISCREG_CLIDR) 3105 .allPrivileges().exceptUserMode().writes(0); 3106 InitReg(MISCREG_AIDR) 3107 .allPrivileges().exceptUserMode().writes(0); 3108 InitReg(MISCREG_CSSELR) 3109 .banked(); 3110 InitReg(MISCREG_CSSELR_NS) 3111 .bankedChild() 3112 .privSecure(!aarch32EL3) 3113 .nonSecure().exceptUserMode(); 3114 InitReg(MISCREG_CSSELR_S) 3115 .bankedChild() 3116 .secure().exceptUserMode(); 3117 InitReg(MISCREG_VPIDR) 3118 .hyp().monNonSecure(); 3119 InitReg(MISCREG_VMPIDR) 3120 .hyp().monNonSecure(); 3121 InitReg(MISCREG_SCTLR) 3122 .banked() 3123 // readMiscRegNoEffect() uses this metadata 3124 // despite using children (below) as backing store 3125 .res0(0x8d22c600) 3126 .res1(0x00400800 | (SPAN ? 0 : 0x800000) 3127 | (LSMAOE ? 0 : 0x10) 3128 | (nTLSMD ? 0 : 0x8)); 3129 InitReg(MISCREG_SCTLR_NS) 3130 .bankedChild() 3131 .privSecure(!aarch32EL3) 3132 .nonSecure().exceptUserMode(); 3133 InitReg(MISCREG_SCTLR_S) 3134 .bankedChild() 3135 .secure().exceptUserMode(); 3136 InitReg(MISCREG_ACTLR) 3137 .banked(); 3138 InitReg(MISCREG_ACTLR_NS) 3139 .bankedChild() 3140 .privSecure(!aarch32EL3) 3141 .nonSecure().exceptUserMode(); 3142 InitReg(MISCREG_ACTLR_S) 3143 .bankedChild() 3144 .secure().exceptUserMode(); 3145 InitReg(MISCREG_CPACR) 3146 .allPrivileges().exceptUserMode(); 3147 InitReg(MISCREG_SCR) 3148 .mon().secure().exceptUserMode() 3149 .res0(0xff40) // [31:16], [6] 3150 .res1(0x0030); // [5:4] 3151 InitReg(MISCREG_SDER) 3152 .mon(); 3153 InitReg(MISCREG_NSACR) 3154 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode(); 3155 InitReg(MISCREG_HSCTLR) 3156 .hyp().monNonSecure() 3157 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000) 3158 | (IESB ? 0 : 0x200000) 3159 | (EnDA ? 0 : 0x8000000) 3160 | (EnIB ? 0 : 0x40000000) 3161 | (EnIA ? 0 : 0x80000000)) 3162 .res1(0x30c50830); 3163 InitReg(MISCREG_HACTLR) 3164 .hyp().monNonSecure(); 3165 InitReg(MISCREG_HCR) 3166 .hyp().monNonSecure(); 3167 InitReg(MISCREG_HDCR) 3168 .hyp().monNonSecure(); 3169 InitReg(MISCREG_HCPTR) 3170 .hyp().monNonSecure(); 3171 InitReg(MISCREG_HSTR) 3172 .hyp().monNonSecure(); 3173 InitReg(MISCREG_HACR) 3174 .unimplemented() 3175 .warnNotFail() 3176 .hyp().monNonSecure(); 3177 InitReg(MISCREG_TTBR0) 3178 .banked(); 3179 InitReg(MISCREG_TTBR0_NS) 3180 .bankedChild() 3181 .privSecure(!aarch32EL3) 3182 .nonSecure().exceptUserMode(); 3183 InitReg(MISCREG_TTBR0_S) 3184 .bankedChild() 3185 .secure().exceptUserMode(); 3186 InitReg(MISCREG_TTBR1) 3187 .banked(); 3188 InitReg(MISCREG_TTBR1_NS) 3189 .bankedChild() 3190 .privSecure(!aarch32EL3) 3191 .nonSecure().exceptUserMode(); 3192 InitReg(MISCREG_TTBR1_S) 3193 .bankedChild() 3194 .secure().exceptUserMode(); 3195 InitReg(MISCREG_TTBCR) 3196 .banked(); 3197 InitReg(MISCREG_TTBCR_NS) 3198 .bankedChild() 3199 .privSecure(!aarch32EL3) 3200 .nonSecure().exceptUserMode(); 3201 InitReg(MISCREG_TTBCR_S) 3202 .bankedChild() 3203 .secure().exceptUserMode(); 3204 InitReg(MISCREG_HTCR) 3205 .hyp().monNonSecure(); 3206 InitReg(MISCREG_VTCR) 3207 .hyp().monNonSecure(); 3208 InitReg(MISCREG_DACR) 3209 .banked(); 3210 InitReg(MISCREG_DACR_NS) 3211 .bankedChild() 3212 .privSecure(!aarch32EL3) 3213 .nonSecure().exceptUserMode(); 3214 InitReg(MISCREG_DACR_S) 3215 .bankedChild() 3216 .secure().exceptUserMode(); 3217 InitReg(MISCREG_DFSR) 3218 .banked(); 3219 InitReg(MISCREG_DFSR_NS) 3220 .bankedChild() 3221 .privSecure(!aarch32EL3) 3222 .nonSecure().exceptUserMode(); 3223 InitReg(MISCREG_DFSR_S) 3224 .bankedChild() 3225 .secure().exceptUserMode(); 3226 InitReg(MISCREG_IFSR) 3227 .banked(); 3228 InitReg(MISCREG_IFSR_NS) 3229 .bankedChild() 3230 .privSecure(!aarch32EL3) 3231 .nonSecure().exceptUserMode(); 3232 InitReg(MISCREG_IFSR_S) 3233 .bankedChild() 3234 .secure().exceptUserMode(); 3235 InitReg(MISCREG_ADFSR) 3236 .unimplemented() 3237 .warnNotFail() 3238 .banked(); 3239 InitReg(MISCREG_ADFSR_NS) 3240 .unimplemented() 3241 .warnNotFail() 3242 .bankedChild() 3243 .privSecure(!aarch32EL3) 3244 .nonSecure().exceptUserMode(); 3245 InitReg(MISCREG_ADFSR_S) 3246 .unimplemented() 3247 .warnNotFail() 3248 .bankedChild() 3249 .secure().exceptUserMode(); 3250 InitReg(MISCREG_AIFSR) 3251 .unimplemented() 3252 .warnNotFail() 3253 .banked(); 3254 InitReg(MISCREG_AIFSR_NS) 3255 .unimplemented() 3256 .warnNotFail() 3257 .bankedChild() 3258 .privSecure(!aarch32EL3) 3259 .nonSecure().exceptUserMode(); 3260 InitReg(MISCREG_AIFSR_S) 3261 .unimplemented() 3262 .warnNotFail() 3263 .bankedChild() 3264 .secure().exceptUserMode(); 3265 InitReg(MISCREG_HADFSR) 3266 .hyp().monNonSecure(); 3267 InitReg(MISCREG_HAIFSR) 3268 .hyp().monNonSecure(); 3269 InitReg(MISCREG_HSR) 3270 .hyp().monNonSecure(); 3271 InitReg(MISCREG_DFAR) 3272 .banked(); 3273 InitReg(MISCREG_DFAR_NS) 3274 .bankedChild() 3275 .privSecure(!aarch32EL3) 3276 .nonSecure().exceptUserMode(); 3277 InitReg(MISCREG_DFAR_S) 3278 .bankedChild() 3279 .secure().exceptUserMode(); 3280 InitReg(MISCREG_IFAR) 3281 .banked(); 3282 InitReg(MISCREG_IFAR_NS) 3283 .bankedChild() 3284 .privSecure(!aarch32EL3) 3285 .nonSecure().exceptUserMode(); 3286 InitReg(MISCREG_IFAR_S) 3287 .bankedChild() 3288 .secure().exceptUserMode(); 3289 InitReg(MISCREG_HDFAR) 3290 .hyp().monNonSecure(); 3291 InitReg(MISCREG_HIFAR) 3292 .hyp().monNonSecure(); 3293 InitReg(MISCREG_HPFAR) 3294 .hyp().monNonSecure(); 3295 InitReg(MISCREG_ICIALLUIS) 3296 .unimplemented() 3297 .warnNotFail() 3298 .writes(1).exceptUserMode(); 3299 InitReg(MISCREG_BPIALLIS) 3300 .unimplemented() 3301 .warnNotFail() 3302 .writes(1).exceptUserMode(); 3303 InitReg(MISCREG_PAR) 3304 .banked(); 3305 InitReg(MISCREG_PAR_NS) 3306 .bankedChild() 3307 .privSecure(!aarch32EL3) 3308 .nonSecure().exceptUserMode(); 3309 InitReg(MISCREG_PAR_S) 3310 .bankedChild() 3311 .secure().exceptUserMode(); 3312 InitReg(MISCREG_ICIALLU) 3313 .writes(1).exceptUserMode(); 3314 InitReg(MISCREG_ICIMVAU) 3315 .unimplemented() 3316 .warnNotFail() 3317 .writes(1).exceptUserMode(); 3318 InitReg(MISCREG_CP15ISB) 3319 .writes(1); 3320 InitReg(MISCREG_BPIALL) 3321 .unimplemented() 3322 .warnNotFail() 3323 .writes(1).exceptUserMode(); 3324 InitReg(MISCREG_BPIMVA) 3325 .unimplemented() 3326 .warnNotFail() 3327 .writes(1).exceptUserMode(); 3328 InitReg(MISCREG_DCIMVAC) 3329 .unimplemented() 3330 .warnNotFail() 3331 .writes(1).exceptUserMode(); 3332 InitReg(MISCREG_DCISW) 3333 .unimplemented() 3334 .warnNotFail() 3335 .writes(1).exceptUserMode(); 3336 InitReg(MISCREG_ATS1CPR) 3337 .writes(1).exceptUserMode(); 3338 InitReg(MISCREG_ATS1CPW) 3339 .writes(1).exceptUserMode(); 3340 InitReg(MISCREG_ATS1CUR) 3341 .writes(1).exceptUserMode(); 3342 InitReg(MISCREG_ATS1CUW) 3343 .writes(1).exceptUserMode(); 3344 InitReg(MISCREG_ATS12NSOPR) 3345 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 3346 InitReg(MISCREG_ATS12NSOPW) 3347 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 3348 InitReg(MISCREG_ATS12NSOUR) 3349 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 3350 InitReg(MISCREG_ATS12NSOUW) 3351 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite(); 3352 InitReg(MISCREG_DCCMVAC) 3353 .writes(1).exceptUserMode(); 3354 InitReg(MISCREG_DCCSW) 3355 .unimplemented() 3356 .warnNotFail() 3357 .writes(1).exceptUserMode(); 3358 InitReg(MISCREG_CP15DSB) 3359 .writes(1); 3360 InitReg(MISCREG_CP15DMB) 3361 .writes(1); 3362 InitReg(MISCREG_DCCMVAU) 3363 .unimplemented() 3364 .warnNotFail() 3365 .writes(1).exceptUserMode(); 3366 InitReg(MISCREG_DCCIMVAC) 3367 .unimplemented() 3368 .warnNotFail() 3369 .writes(1).exceptUserMode(); 3370 InitReg(MISCREG_DCCISW) 3371 .unimplemented() 3372 .warnNotFail() 3373 .writes(1).exceptUserMode(); 3374 InitReg(MISCREG_ATS1HR) 3375 .monNonSecureWrite().hypWrite(); 3376 InitReg(MISCREG_ATS1HW) 3377 .monNonSecureWrite().hypWrite(); 3378 InitReg(MISCREG_TLBIALLIS) 3379 .writes(1).exceptUserMode(); 3380 InitReg(MISCREG_TLBIMVAIS) 3381 .writes(1).exceptUserMode(); 3382 InitReg(MISCREG_TLBIASIDIS) 3383 .writes(1).exceptUserMode(); 3384 InitReg(MISCREG_TLBIMVAAIS) 3385 .writes(1).exceptUserMode(); 3386 InitReg(MISCREG_TLBIMVALIS) 3387 .writes(1).exceptUserMode(); 3388 InitReg(MISCREG_TLBIMVAALIS) 3389 .writes(1).exceptUserMode(); 3390 InitReg(MISCREG_ITLBIALL) 3391 .writes(1).exceptUserMode(); 3392 InitReg(MISCREG_ITLBIMVA) 3393 .writes(1).exceptUserMode(); 3394 InitReg(MISCREG_ITLBIASID) 3395 .writes(1).exceptUserMode(); 3396 InitReg(MISCREG_DTLBIALL) 3397 .writes(1).exceptUserMode(); 3398 InitReg(MISCREG_DTLBIMVA) 3399 .writes(1).exceptUserMode(); 3400 InitReg(MISCREG_DTLBIASID) 3401 .writes(1).exceptUserMode(); 3402 InitReg(MISCREG_TLBIALL) 3403 .writes(1).exceptUserMode(); 3404 InitReg(MISCREG_TLBIMVA) 3405 .writes(1).exceptUserMode(); 3406 InitReg(MISCREG_TLBIASID) 3407 .writes(1).exceptUserMode(); 3408 InitReg(MISCREG_TLBIMVAA) 3409 .writes(1).exceptUserMode(); 3410 InitReg(MISCREG_TLBIMVAL) 3411 .writes(1).exceptUserMode(); 3412 InitReg(MISCREG_TLBIMVAAL) 3413 .writes(1).exceptUserMode(); 3414 InitReg(MISCREG_TLBIIPAS2IS) 3415 .monNonSecureWrite().hypWrite(); 3416 InitReg(MISCREG_TLBIIPAS2LIS) 3417 .monNonSecureWrite().hypWrite(); 3418 InitReg(MISCREG_TLBIALLHIS) 3419 .monNonSecureWrite().hypWrite(); 3420 InitReg(MISCREG_TLBIMVAHIS) 3421 .monNonSecureWrite().hypWrite(); 3422 InitReg(MISCREG_TLBIALLNSNHIS) 3423 .monNonSecureWrite().hypWrite(); 3424 InitReg(MISCREG_TLBIMVALHIS) 3425 .monNonSecureWrite().hypWrite(); 3426 InitReg(MISCREG_TLBIIPAS2) 3427 .monNonSecureWrite().hypWrite(); 3428 InitReg(MISCREG_TLBIIPAS2L) 3429 .monNonSecureWrite().hypWrite(); 3430 InitReg(MISCREG_TLBIALLH) 3431 .monNonSecureWrite().hypWrite(); 3432 InitReg(MISCREG_TLBIMVAH) 3433 .monNonSecureWrite().hypWrite(); 3434 InitReg(MISCREG_TLBIALLNSNH) 3435 .monNonSecureWrite().hypWrite(); 3436 InitReg(MISCREG_TLBIMVALH) 3437 .monNonSecureWrite().hypWrite(); 3438 InitReg(MISCREG_PMCR) 3439 .allPrivileges(); 3440 InitReg(MISCREG_PMCNTENSET) 3441 .allPrivileges(); 3442 InitReg(MISCREG_PMCNTENCLR) 3443 .allPrivileges(); 3444 InitReg(MISCREG_PMOVSR) 3445 .allPrivileges(); 3446 InitReg(MISCREG_PMSWINC) 3447 .allPrivileges(); 3448 InitReg(MISCREG_PMSELR) 3449 .allPrivileges(); 3450 InitReg(MISCREG_PMCEID0) 3451 .allPrivileges(); 3452 InitReg(MISCREG_PMCEID1) 3453 .allPrivileges(); 3454 InitReg(MISCREG_PMCCNTR) 3455 .allPrivileges(); 3456 InitReg(MISCREG_PMXEVTYPER) 3457 .allPrivileges(); 3458 InitReg(MISCREG_PMCCFILTR) 3459 .allPrivileges(); 3460 InitReg(MISCREG_PMXEVCNTR) 3461 .allPrivileges(); 3462 InitReg(MISCREG_PMUSERENR) 3463 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0); 3464 InitReg(MISCREG_PMINTENSET) 3465 .allPrivileges().exceptUserMode(); 3466 InitReg(MISCREG_PMINTENCLR) 3467 .allPrivileges().exceptUserMode(); 3468 InitReg(MISCREG_PMOVSSET) 3469 .unimplemented() 3470 .allPrivileges(); 3471 InitReg(MISCREG_L2CTLR) 3472 .allPrivileges().exceptUserMode(); 3473 InitReg(MISCREG_L2ECTLR) 3474 .unimplemented() 3475 .allPrivileges().exceptUserMode(); 3476 InitReg(MISCREG_PRRR) 3477 .banked(); 3478 InitReg(MISCREG_PRRR_NS) 3479 .bankedChild() 3480 .privSecure(!aarch32EL3) 3481 .nonSecure().exceptUserMode(); 3482 InitReg(MISCREG_PRRR_S) 3483 .bankedChild() 3484 .secure().exceptUserMode(); 3485 InitReg(MISCREG_MAIR0) 3486 .banked(); 3487 InitReg(MISCREG_MAIR0_NS) 3488 .bankedChild() 3489 .privSecure(!aarch32EL3) 3490 .nonSecure().exceptUserMode(); 3491 InitReg(MISCREG_MAIR0_S) 3492 .bankedChild() 3493 .secure().exceptUserMode(); 3494 InitReg(MISCREG_NMRR) 3495 .banked(); 3496 InitReg(MISCREG_NMRR_NS) 3497 .bankedChild() 3498 .privSecure(!aarch32EL3) 3499 .nonSecure().exceptUserMode(); 3500 InitReg(MISCREG_NMRR_S) 3501 .bankedChild() 3502 .secure().exceptUserMode(); 3503 InitReg(MISCREG_MAIR1) 3504 .banked(); 3505 InitReg(MISCREG_MAIR1_NS) 3506 .bankedChild() 3507 .privSecure(!aarch32EL3) 3508 .nonSecure().exceptUserMode(); 3509 InitReg(MISCREG_MAIR1_S) 3510 .bankedChild() 3511 .secure().exceptUserMode(); 3512 InitReg(MISCREG_AMAIR0) 3513 .banked(); 3514 InitReg(MISCREG_AMAIR0_NS) 3515 .bankedChild() 3516 .privSecure(!aarch32EL3) 3517 .nonSecure().exceptUserMode(); 3518 InitReg(MISCREG_AMAIR0_S) 3519 .bankedChild() 3520 .secure().exceptUserMode(); 3521 InitReg(MISCREG_AMAIR1) 3522 .banked(); 3523 InitReg(MISCREG_AMAIR1_NS) 3524 .bankedChild() 3525 .privSecure(!aarch32EL3) 3526 .nonSecure().exceptUserMode(); 3527 InitReg(MISCREG_AMAIR1_S) 3528 .bankedChild() 3529 .secure().exceptUserMode(); 3530 InitReg(MISCREG_HMAIR0) 3531 .hyp().monNonSecure(); 3532 InitReg(MISCREG_HMAIR1) 3533 .hyp().monNonSecure(); 3534 InitReg(MISCREG_HAMAIR0) 3535 .unimplemented() 3536 .warnNotFail() 3537 .hyp().monNonSecure(); 3538 InitReg(MISCREG_HAMAIR1) 3539 .unimplemented() 3540 .warnNotFail() 3541 .hyp().monNonSecure(); 3542 InitReg(MISCREG_VBAR) 3543 .banked(); 3544 InitReg(MISCREG_VBAR_NS) 3545 .bankedChild() 3546 .privSecure(!aarch32EL3) 3547 .nonSecure().exceptUserMode(); 3548 InitReg(MISCREG_VBAR_S) 3549 .bankedChild() 3550 .secure().exceptUserMode(); 3551 InitReg(MISCREG_MVBAR) 3552 .mon().secure() 3553 .hypRead(FullSystem && system->highestEL() == EL2) 3554 .privRead(FullSystem && system->highestEL() == EL1) 3555 .exceptUserMode(); 3556 InitReg(MISCREG_RMR) 3557 .unimplemented() 3558 .mon().secure().exceptUserMode(); 3559 InitReg(MISCREG_ISR) 3560 .allPrivileges().exceptUserMode().writes(0); 3561 InitReg(MISCREG_HVBAR) 3562 .hyp().monNonSecure() 3563 .res0(0x1f); 3564 InitReg(MISCREG_FCSEIDR) 3565 .unimplemented() 3566 .warnNotFail() 3567 .allPrivileges().exceptUserMode(); 3568 InitReg(MISCREG_CONTEXTIDR) 3569 .banked(); 3570 InitReg(MISCREG_CONTEXTIDR_NS) 3571 .bankedChild() 3572 .privSecure(!aarch32EL3) 3573 .nonSecure().exceptUserMode(); 3574 InitReg(MISCREG_CONTEXTIDR_S) 3575 .bankedChild() 3576 .secure().exceptUserMode(); 3577 InitReg(MISCREG_TPIDRURW) 3578 .banked(); 3579 InitReg(MISCREG_TPIDRURW_NS) 3580 .bankedChild() 3581 .allPrivileges() 3582 .privSecure(!aarch32EL3) 3583 .monSecure(0); 3584 InitReg(MISCREG_TPIDRURW_S) 3585 .bankedChild() 3586 .secure(); 3587 InitReg(MISCREG_TPIDRURO) 3588 .banked(); 3589 InitReg(MISCREG_TPIDRURO_NS) 3590 .bankedChild() 3591 .allPrivileges() 3592 .userNonSecureWrite(0).userSecureRead(1) 3593 .privSecure(!aarch32EL3) 3594 .monSecure(0); 3595 InitReg(MISCREG_TPIDRURO_S) 3596 .bankedChild() 3597 .secure().userSecureWrite(0); 3598 InitReg(MISCREG_TPIDRPRW) 3599 .banked(); 3600 InitReg(MISCREG_TPIDRPRW_NS) 3601 .bankedChild() 3602 .nonSecure().exceptUserMode() 3603 .privSecure(!aarch32EL3); 3604 InitReg(MISCREG_TPIDRPRW_S) 3605 .bankedChild() 3606 .secure().exceptUserMode(); 3607 InitReg(MISCREG_HTPIDR) 3608 .hyp().monNonSecure(); 3609 InitReg(MISCREG_CNTFRQ) 3610 .unverifiable() 3611 .reads(1).mon(); 3612 InitReg(MISCREG_CNTKCTL) 3613 .allPrivileges().exceptUserMode(); 3614 InitReg(MISCREG_CNTP_TVAL) 3615 .banked(); 3616 InitReg(MISCREG_CNTP_TVAL_NS) 3617 .bankedChild() 3618 .allPrivileges() 3619 .privSecure(!aarch32EL3) 3620 .monSecure(0); 3621 InitReg(MISCREG_CNTP_TVAL_S) 3622 .bankedChild() 3623 .secure().user(1); 3624 InitReg(MISCREG_CNTP_CTL) 3625 .banked(); 3626 InitReg(MISCREG_CNTP_CTL_NS) 3627 .bankedChild() 3628 .allPrivileges() 3629 .privSecure(!aarch32EL3) 3630 .monSecure(0); 3631 InitReg(MISCREG_CNTP_CTL_S) 3632 .bankedChild() 3633 .secure().user(1); 3634 InitReg(MISCREG_CNTV_TVAL) 3635 .allPrivileges(); 3636 InitReg(MISCREG_CNTV_CTL) 3637 .allPrivileges(); 3638 InitReg(MISCREG_CNTHCTL) 3639 .hypWrite().monNonSecureRead(); 3640 InitReg(MISCREG_CNTHP_TVAL) 3641 .hypWrite().monNonSecureRead(); 3642 InitReg(MISCREG_CNTHP_CTL) 3643 .hypWrite().monNonSecureRead(); 3644 InitReg(MISCREG_IL1DATA0) 3645 .unimplemented() 3646 .allPrivileges().exceptUserMode(); 3647 InitReg(MISCREG_IL1DATA1) 3648 .unimplemented() 3649 .allPrivileges().exceptUserMode(); 3650 InitReg(MISCREG_IL1DATA2) 3651 .unimplemented() 3652 .allPrivileges().exceptUserMode(); 3653 InitReg(MISCREG_IL1DATA3) 3654 .unimplemented() 3655 .allPrivileges().exceptUserMode(); 3656 InitReg(MISCREG_DL1DATA0) 3657 .unimplemented() 3658 .allPrivileges().exceptUserMode(); 3659 InitReg(MISCREG_DL1DATA1) 3660 .unimplemented() 3661 .allPrivileges().exceptUserMode(); 3662 InitReg(MISCREG_DL1DATA2) 3663 .unimplemented() 3664 .allPrivileges().exceptUserMode(); 3665 InitReg(MISCREG_DL1DATA3) 3666 .unimplemented() 3667 .allPrivileges().exceptUserMode(); 3668 InitReg(MISCREG_DL1DATA4) 3669 .unimplemented() 3670 .allPrivileges().exceptUserMode(); 3671 InitReg(MISCREG_RAMINDEX) 3672 .unimplemented() 3673 .writes(1).exceptUserMode(); 3674 InitReg(MISCREG_L2ACTLR) 3675 .unimplemented() 3676 .allPrivileges().exceptUserMode(); 3677 InitReg(MISCREG_CBAR) 3678 .unimplemented() 3679 .allPrivileges().exceptUserMode().writes(0); 3680 InitReg(MISCREG_HTTBR) 3681 .hyp().monNonSecure(); 3682 InitReg(MISCREG_VTTBR) 3683 .hyp().monNonSecure(); 3684 InitReg(MISCREG_CNTPCT) 3685 .reads(1); 3686 InitReg(MISCREG_CNTVCT) 3687 .unverifiable() 3688 .reads(1); 3689 InitReg(MISCREG_CNTP_CVAL) 3690 .banked(); 3691 InitReg(MISCREG_CNTP_CVAL_NS) 3692 .bankedChild() 3693 .allPrivileges() 3694 .privSecure(!aarch32EL3) 3695 .monSecure(0); 3696 InitReg(MISCREG_CNTP_CVAL_S) 3697 .bankedChild() 3698 .secure().user(1); 3699 InitReg(MISCREG_CNTV_CVAL) 3700 .allPrivileges(); 3701 InitReg(MISCREG_CNTVOFF) 3702 .hyp().monNonSecure(); 3703 InitReg(MISCREG_CNTHP_CVAL) 3704 .hypWrite().monNonSecureRead(); 3705 InitReg(MISCREG_CPUMERRSR) 3706 .unimplemented() 3707 .allPrivileges().exceptUserMode(); 3708 InitReg(MISCREG_L2MERRSR) 3709 .unimplemented() 3710 .warnNotFail() 3711 .allPrivileges().exceptUserMode(); 3712 3713 // AArch64 registers (Op0=2); 3714 InitReg(MISCREG_MDCCINT_EL1) 3715 .allPrivileges(); 3716 InitReg(MISCREG_OSDTRRX_EL1) 3717 .allPrivileges() 3718 .mapsTo(MISCREG_DBGDTRRXext); 3719 InitReg(MISCREG_MDSCR_EL1) 3720 .allPrivileges() 3721 .mapsTo(MISCREG_DBGDSCRext); 3722 InitReg(MISCREG_OSDTRTX_EL1) 3723 .allPrivileges() 3724 .mapsTo(MISCREG_DBGDTRTXext); 3725 InitReg(MISCREG_OSECCR_EL1) 3726 .allPrivileges() 3727 .mapsTo(MISCREG_DBGOSECCR); 3728 InitReg(MISCREG_DBGBVR0_EL1) 3729 .allPrivileges() 3730 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */); 3731 InitReg(MISCREG_DBGBVR1_EL1) 3732 .allPrivileges() 3733 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */); 3734 InitReg(MISCREG_DBGBVR2_EL1) 3735 .allPrivileges() 3736 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */); 3737 InitReg(MISCREG_DBGBVR3_EL1) 3738 .allPrivileges() 3739 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */); 3740 InitReg(MISCREG_DBGBVR4_EL1) 3741 .allPrivileges() 3742 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */); 3743 InitReg(MISCREG_DBGBVR5_EL1) 3744 .allPrivileges() 3745 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */); 3746 InitReg(MISCREG_DBGBCR0_EL1) 3747 .allPrivileges() 3748 .mapsTo(MISCREG_DBGBCR0); 3749 InitReg(MISCREG_DBGBCR1_EL1) 3750 .allPrivileges() 3751 .mapsTo(MISCREG_DBGBCR1); 3752 InitReg(MISCREG_DBGBCR2_EL1) 3753 .allPrivileges() 3754 .mapsTo(MISCREG_DBGBCR2); 3755 InitReg(MISCREG_DBGBCR3_EL1) 3756 .allPrivileges() 3757 .mapsTo(MISCREG_DBGBCR3); 3758 InitReg(MISCREG_DBGBCR4_EL1) 3759 .allPrivileges() 3760 .mapsTo(MISCREG_DBGBCR4); 3761 InitReg(MISCREG_DBGBCR5_EL1) 3762 .allPrivileges() 3763 .mapsTo(MISCREG_DBGBCR5); 3764 InitReg(MISCREG_DBGWVR0_EL1) 3765 .allPrivileges() 3766 .mapsTo(MISCREG_DBGWVR0); 3767 InitReg(MISCREG_DBGWVR1_EL1) 3768 .allPrivileges() 3769 .mapsTo(MISCREG_DBGWVR1); 3770 InitReg(MISCREG_DBGWVR2_EL1) 3771 .allPrivileges() 3772 .mapsTo(MISCREG_DBGWVR2); 3773 InitReg(MISCREG_DBGWVR3_EL1) 3774 .allPrivileges() 3775 .mapsTo(MISCREG_DBGWVR3); 3776 InitReg(MISCREG_DBGWCR0_EL1) 3777 .allPrivileges() 3778 .mapsTo(MISCREG_DBGWCR0); 3779 InitReg(MISCREG_DBGWCR1_EL1) 3780 .allPrivileges() 3781 .mapsTo(MISCREG_DBGWCR1); 3782 InitReg(MISCREG_DBGWCR2_EL1) 3783 .allPrivileges() 3784 .mapsTo(MISCREG_DBGWCR2); 3785 InitReg(MISCREG_DBGWCR3_EL1) 3786 .allPrivileges() 3787 .mapsTo(MISCREG_DBGWCR3); 3788 InitReg(MISCREG_MDCCSR_EL0) 3789 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3790 .mapsTo(MISCREG_DBGDSCRint); 3791 InitReg(MISCREG_MDDTR_EL0) 3792 .allPrivileges(); 3793 InitReg(MISCREG_MDDTRTX_EL0) 3794 .allPrivileges(); 3795 InitReg(MISCREG_MDDTRRX_EL0) 3796 .allPrivileges(); 3797 InitReg(MISCREG_DBGVCR32_EL2) 3798 .allPrivileges() 3799 .mapsTo(MISCREG_DBGVCR); 3800 InitReg(MISCREG_MDRAR_EL1) 3801 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3802 .mapsTo(MISCREG_DBGDRAR); 3803 InitReg(MISCREG_OSLAR_EL1) 3804 .allPrivileges().monSecureRead(0).monNonSecureRead(0) 3805 .mapsTo(MISCREG_DBGOSLAR); 3806 InitReg(MISCREG_OSLSR_EL1) 3807 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3808 .mapsTo(MISCREG_DBGOSLSR); 3809 InitReg(MISCREG_OSDLR_EL1) 3810 .allPrivileges() 3811 .mapsTo(MISCREG_DBGOSDLR); 3812 InitReg(MISCREG_DBGPRCR_EL1) 3813 .allPrivileges() 3814 .mapsTo(MISCREG_DBGPRCR); 3815 InitReg(MISCREG_DBGCLAIMSET_EL1) 3816 .allPrivileges() 3817 .mapsTo(MISCREG_DBGCLAIMSET); 3818 InitReg(MISCREG_DBGCLAIMCLR_EL1) 3819 .allPrivileges() 3820 .mapsTo(MISCREG_DBGCLAIMCLR); 3821 InitReg(MISCREG_DBGAUTHSTATUS_EL1) 3822 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0) 3823 .mapsTo(MISCREG_DBGAUTHSTATUS); 3824 InitReg(MISCREG_TEECR32_EL1); 3825 InitReg(MISCREG_TEEHBR32_EL1); 3826 3827 // AArch64 registers (Op0=1,3); 3828 InitReg(MISCREG_MIDR_EL1) 3829 .allPrivileges().exceptUserMode().writes(0); 3830 InitReg(MISCREG_MPIDR_EL1) 3831 .allPrivileges().exceptUserMode().writes(0); 3832 InitReg(MISCREG_REVIDR_EL1) 3833 .allPrivileges().exceptUserMode().writes(0); 3834 InitReg(MISCREG_ID_PFR0_EL1) 3835 .allPrivileges().exceptUserMode().writes(0) 3836 .mapsTo(MISCREG_ID_PFR0); 3837 InitReg(MISCREG_ID_PFR1_EL1) 3838 .allPrivileges().exceptUserMode().writes(0) 3839 .mapsTo(MISCREG_ID_PFR1); 3840 InitReg(MISCREG_ID_DFR0_EL1) 3841 .allPrivileges().exceptUserMode().writes(0) 3842 .mapsTo(MISCREG_ID_DFR0); 3843 InitReg(MISCREG_ID_AFR0_EL1) 3844 .allPrivileges().exceptUserMode().writes(0) 3845 .mapsTo(MISCREG_ID_AFR0); 3846 InitReg(MISCREG_ID_MMFR0_EL1) 3847 .allPrivileges().exceptUserMode().writes(0) 3848 .mapsTo(MISCREG_ID_MMFR0); 3849 InitReg(MISCREG_ID_MMFR1_EL1) 3850 .allPrivileges().exceptUserMode().writes(0) 3851 .mapsTo(MISCREG_ID_MMFR1); 3852 InitReg(MISCREG_ID_MMFR2_EL1) 3853 .allPrivileges().exceptUserMode().writes(0) 3854 .mapsTo(MISCREG_ID_MMFR2); 3855 InitReg(MISCREG_ID_MMFR3_EL1) 3856 .allPrivileges().exceptUserMode().writes(0) 3857 .mapsTo(MISCREG_ID_MMFR3); 3858 InitReg(MISCREG_ID_ISAR0_EL1) 3859 .allPrivileges().exceptUserMode().writes(0) 3860 .mapsTo(MISCREG_ID_ISAR0); 3861 InitReg(MISCREG_ID_ISAR1_EL1) 3862 .allPrivileges().exceptUserMode().writes(0) 3863 .mapsTo(MISCREG_ID_ISAR1); 3864 InitReg(MISCREG_ID_ISAR2_EL1) 3865 .allPrivileges().exceptUserMode().writes(0) 3866 .mapsTo(MISCREG_ID_ISAR2); 3867 InitReg(MISCREG_ID_ISAR3_EL1) 3868 .allPrivileges().exceptUserMode().writes(0) 3869 .mapsTo(MISCREG_ID_ISAR3); 3870 InitReg(MISCREG_ID_ISAR4_EL1) 3871 .allPrivileges().exceptUserMode().writes(0) 3872 .mapsTo(MISCREG_ID_ISAR4); 3873 InitReg(MISCREG_ID_ISAR5_EL1) 3874 .allPrivileges().exceptUserMode().writes(0) 3875 .mapsTo(MISCREG_ID_ISAR5); 3876 InitReg(MISCREG_MVFR0_EL1) 3877 .allPrivileges().exceptUserMode().writes(0); 3878 InitReg(MISCREG_MVFR1_EL1) 3879 .allPrivileges().exceptUserMode().writes(0); 3880 InitReg(MISCREG_MVFR2_EL1) 3881 .allPrivileges().exceptUserMode().writes(0); 3882 InitReg(MISCREG_ID_AA64PFR0_EL1) 3883 .allPrivileges().exceptUserMode().writes(0); 3884 InitReg(MISCREG_ID_AA64PFR1_EL1) 3885 .allPrivileges().exceptUserMode().writes(0); 3886 InitReg(MISCREG_ID_AA64DFR0_EL1) 3887 .allPrivileges().exceptUserMode().writes(0); 3888 InitReg(MISCREG_ID_AA64DFR1_EL1) 3889 .allPrivileges().exceptUserMode().writes(0); 3890 InitReg(MISCREG_ID_AA64AFR0_EL1) 3891 .allPrivileges().exceptUserMode().writes(0); 3892 InitReg(MISCREG_ID_AA64AFR1_EL1) 3893 .allPrivileges().exceptUserMode().writes(0); 3894 InitReg(MISCREG_ID_AA64ISAR0_EL1) 3895 .allPrivileges().exceptUserMode().writes(0); 3896 InitReg(MISCREG_ID_AA64ISAR1_EL1) 3897 .allPrivileges().exceptUserMode().writes(0); 3898 InitReg(MISCREG_ID_AA64MMFR0_EL1) 3899 .allPrivileges().exceptUserMode().writes(0); 3900 InitReg(MISCREG_ID_AA64MMFR1_EL1) 3901 .allPrivileges().exceptUserMode().writes(0); 3902 InitReg(MISCREG_ID_AA64MMFR2_EL1) 3903 .allPrivileges().exceptUserMode().writes(0); 3904 InitReg(MISCREG_CCSIDR_EL1) 3905 .allPrivileges().exceptUserMode().writes(0); 3906 InitReg(MISCREG_CLIDR_EL1) 3907 .allPrivileges().exceptUserMode().writes(0); 3908 InitReg(MISCREG_AIDR_EL1) 3909 .allPrivileges().exceptUserMode().writes(0); 3910 InitReg(MISCREG_CSSELR_EL1) 3911 .allPrivileges().exceptUserMode() 3912 .mapsTo(MISCREG_CSSELR_NS); 3913 InitReg(MISCREG_CTR_EL0) 3914 .reads(1); 3915 InitReg(MISCREG_DCZID_EL0) 3916 .reads(1); 3917 InitReg(MISCREG_VPIDR_EL2) 3918 .hyp().mon() 3919 .mapsTo(MISCREG_VPIDR); 3920 InitReg(MISCREG_VMPIDR_EL2) 3921 .hyp().mon() 3922 .mapsTo(MISCREG_VMPIDR); 3923 InitReg(MISCREG_SCTLR_EL1) 3924 .allPrivileges().exceptUserMode() 3925 .res0( 0x20440 | (EnDB ? 0 : 0x2000) 3926 | (IESB ? 0 : 0x200000) 3927 | (EnDA ? 0 : 0x8000000) 3928 | (EnIB ? 0 : 0x40000000) 3929 | (EnIA ? 0 : 0x80000000)) 3930 .res1(0x500800 | (SPAN ? 0 : 0x800000) 3931 | (nTLSMD ? 0 : 0x8000000) 3932 | (LSMAOE ? 0 : 0x10000000)) 3933 .mapsTo(MISCREG_SCTLR_NS); 3934 InitReg(MISCREG_ACTLR_EL1) 3935 .allPrivileges().exceptUserMode() 3936 .mapsTo(MISCREG_ACTLR_NS); 3937 InitReg(MISCREG_CPACR_EL1) 3938 .allPrivileges().exceptUserMode() 3939 .mapsTo(MISCREG_CPACR); 3940 InitReg(MISCREG_SCTLR_EL2) 3941 .hyp().mon() 3942 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000) 3943 | (IESB ? 0 : 0x200000) 3944 | (EnDA ? 0 : 0x8000000) 3945 | (EnIB ? 0 : 0x40000000) 3946 | (EnIA ? 0 : 0x80000000)) 3947 .res1(0x30c50830) 3948 .mapsTo(MISCREG_HSCTLR); 3949 InitReg(MISCREG_ACTLR_EL2) 3950 .hyp().mon() 3951 .mapsTo(MISCREG_HACTLR); 3952 InitReg(MISCREG_HCR_EL2) 3953 .hyp().mon() 3954 .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/); 3955 InitReg(MISCREG_MDCR_EL2) 3956 .hyp().mon() 3957 .mapsTo(MISCREG_HDCR); 3958 InitReg(MISCREG_CPTR_EL2) 3959 .hyp().mon() 3960 .mapsTo(MISCREG_HCPTR); 3961 InitReg(MISCREG_HSTR_EL2) 3962 .hyp().mon() 3963 .mapsTo(MISCREG_HSTR); 3964 InitReg(MISCREG_HACR_EL2) 3965 .hyp().mon() 3966 .mapsTo(MISCREG_HACR); 3967 InitReg(MISCREG_SCTLR_EL3) 3968 .mon() 3969 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000) 3970 | (IESB ? 0 : 0x200000) 3971 | (EnDA ? 0 : 0x8000000) 3972 | (EnIB ? 0 : 0x40000000) 3973 | (EnIA ? 0 : 0x80000000)) 3974 .res1(0x30c50830); 3975 InitReg(MISCREG_ACTLR_EL3) 3976 .mon(); 3977 InitReg(MISCREG_SCR_EL3) 3978 .mon() 3979 .mapsTo(MISCREG_SCR); // NAM D7-2005 3980 InitReg(MISCREG_SDER32_EL3) 3981 .mon() 3982 .mapsTo(MISCREG_SDER); 3983 InitReg(MISCREG_CPTR_EL3) 3984 .mon(); 3985 InitReg(MISCREG_MDCR_EL3) 3986 .mon(); 3987 InitReg(MISCREG_TTBR0_EL1) 3988 .allPrivileges().exceptUserMode() 3989 .mapsTo(MISCREG_TTBR0_NS); 3990 InitReg(MISCREG_TTBR1_EL1) 3991 .allPrivileges().exceptUserMode() 3992 .mapsTo(MISCREG_TTBR1_NS); 3993 InitReg(MISCREG_TCR_EL1) 3994 .allPrivileges().exceptUserMode() 3995 .mapsTo(MISCREG_TTBCR_NS); 3996 InitReg(MISCREG_TTBR0_EL2) 3997 .hyp().mon() 3998 .mapsTo(MISCREG_HTTBR); 3999 InitReg(MISCREG_TTBR1_EL2) 4000 .hyp().mon(); 4001 InitReg(MISCREG_TCR_EL2) 4002 .hyp().mon() 4003 .mapsTo(MISCREG_HTCR); 4004 InitReg(MISCREG_VTTBR_EL2) 4005 .hyp().mon() 4006 .mapsTo(MISCREG_VTTBR); 4007 InitReg(MISCREG_VTCR_EL2) 4008 .hyp().mon() 4009 .mapsTo(MISCREG_VTCR); 4010 InitReg(MISCREG_TTBR0_EL3) 4011 .mon(); 4012 InitReg(MISCREG_TCR_EL3) 4013 .mon(); 4014 InitReg(MISCREG_DACR32_EL2) 4015 .hyp().mon() 4016 .mapsTo(MISCREG_DACR_NS); 4017 InitReg(MISCREG_SPSR_EL1) 4018 .allPrivileges().exceptUserMode() 4019 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1 4020 InitReg(MISCREG_ELR_EL1) 4021 .allPrivileges().exceptUserMode(); 4022 InitReg(MISCREG_SP_EL0) 4023 .allPrivileges().exceptUserMode(); 4024 InitReg(MISCREG_SPSEL) 4025 .allPrivileges().exceptUserMode(); 4026 InitReg(MISCREG_CURRENTEL) 4027 .allPrivileges().exceptUserMode().writes(0); 4028 InitReg(MISCREG_NZCV) 4029 .allPrivileges(); 4030 InitReg(MISCREG_DAIF) 4031 .allPrivileges(); 4032 InitReg(MISCREG_FPCR) 4033 .allPrivileges(); 4034 InitReg(MISCREG_FPSR) 4035 .allPrivileges(); 4036 InitReg(MISCREG_DSPSR_EL0) 4037 .allPrivileges(); 4038 InitReg(MISCREG_DLR_EL0) 4039 .allPrivileges(); 4040 InitReg(MISCREG_SPSR_EL2) 4041 .hyp().mon() 4042 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2 4043 InitReg(MISCREG_ELR_EL2) 4044 .hyp().mon(); 4045 InitReg(MISCREG_SP_EL1) 4046 .hyp().mon(); 4047 InitReg(MISCREG_SPSR_IRQ_AA64) 4048 .hyp().mon(); 4049 InitReg(MISCREG_SPSR_ABT_AA64) 4050 .hyp().mon(); 4051 InitReg(MISCREG_SPSR_UND_AA64) 4052 .hyp().mon(); 4053 InitReg(MISCREG_SPSR_FIQ_AA64) 4054 .hyp().mon(); 4055 InitReg(MISCREG_SPSR_EL3) 4056 .mon() 4057 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3 4058 InitReg(MISCREG_ELR_EL3) 4059 .mon(); 4060 InitReg(MISCREG_SP_EL2) 4061 .mon(); 4062 InitReg(MISCREG_AFSR0_EL1) 4063 .allPrivileges().exceptUserMode() 4064 .mapsTo(MISCREG_ADFSR_NS); 4065 InitReg(MISCREG_AFSR1_EL1) 4066 .allPrivileges().exceptUserMode() 4067 .mapsTo(MISCREG_AIFSR_NS); 4068 InitReg(MISCREG_ESR_EL1) 4069 .allPrivileges().exceptUserMode(); 4070 InitReg(MISCREG_IFSR32_EL2) 4071 .hyp().mon() 4072 .mapsTo(MISCREG_IFSR_NS); 4073 InitReg(MISCREG_AFSR0_EL2) 4074 .hyp().mon() 4075 .mapsTo(MISCREG_HADFSR); 4076 InitReg(MISCREG_AFSR1_EL2) 4077 .hyp().mon() 4078 .mapsTo(MISCREG_HAIFSR); 4079 InitReg(MISCREG_ESR_EL2) 4080 .hyp().mon() 4081 .mapsTo(MISCREG_HSR); 4082 InitReg(MISCREG_FPEXC32_EL2) 4083 .hyp().mon().mapsTo(MISCREG_FPEXC); 4084 InitReg(MISCREG_AFSR0_EL3) 4085 .mon(); 4086 InitReg(MISCREG_AFSR1_EL3) 4087 .mon(); 4088 InitReg(MISCREG_ESR_EL3) 4089 .mon(); 4090 InitReg(MISCREG_FAR_EL1) 4091 .allPrivileges().exceptUserMode() 4092 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS); 4093 InitReg(MISCREG_FAR_EL2) 4094 .hyp().mon() 4095 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR); 4096 InitReg(MISCREG_HPFAR_EL2) 4097 .hyp().mon() 4098 .mapsTo(MISCREG_HPFAR); 4099 InitReg(MISCREG_FAR_EL3) 4100 .mon(); 4101 InitReg(MISCREG_IC_IALLUIS) 4102 .warnNotFail() 4103 .writes(1).exceptUserMode(); 4104 InitReg(MISCREG_PAR_EL1) 4105 .allPrivileges().exceptUserMode() 4106 .mapsTo(MISCREG_PAR_NS); 4107 InitReg(MISCREG_IC_IALLU) 4108 .warnNotFail() 4109 .writes(1).exceptUserMode(); 4110 InitReg(MISCREG_DC_IVAC_Xt) 4111 .warnNotFail() 4112 .writes(1).exceptUserMode(); 4113 InitReg(MISCREG_DC_ISW_Xt) 4114 .warnNotFail() 4115 .writes(1).exceptUserMode(); 4116 InitReg(MISCREG_AT_S1E1R_Xt) 4117 .writes(1).exceptUserMode(); 4118 InitReg(MISCREG_AT_S1E1W_Xt) 4119 .writes(1).exceptUserMode(); 4120 InitReg(MISCREG_AT_S1E0R_Xt) 4121 .writes(1).exceptUserMode(); 4122 InitReg(MISCREG_AT_S1E0W_Xt) 4123 .writes(1).exceptUserMode(); 4124 InitReg(MISCREG_DC_CSW_Xt) 4125 .warnNotFail() 4126 .writes(1).exceptUserMode(); 4127 InitReg(MISCREG_DC_CISW_Xt) 4128 .warnNotFail() 4129 .writes(1).exceptUserMode(); 4130 InitReg(MISCREG_DC_ZVA_Xt) 4131 .warnNotFail() 4132 .writes(1).userSecureWrite(0); 4133 InitReg(MISCREG_IC_IVAU_Xt) 4134 .writes(1); 4135 InitReg(MISCREG_DC_CVAC_Xt) 4136 .warnNotFail() 4137 .writes(1); 4138 InitReg(MISCREG_DC_CVAU_Xt) 4139 .warnNotFail() 4140 .writes(1); 4141 InitReg(MISCREG_DC_CIVAC_Xt) 4142 .warnNotFail() 4143 .writes(1); 4144 InitReg(MISCREG_AT_S1E2R_Xt) 4145 .monNonSecureWrite().hypWrite(); 4146 InitReg(MISCREG_AT_S1E2W_Xt) 4147 .monNonSecureWrite().hypWrite(); 4148 InitReg(MISCREG_AT_S12E1R_Xt) 4149 .hypWrite().monSecureWrite().monNonSecureWrite(); 4150 InitReg(MISCREG_AT_S12E1W_Xt) 4151 .hypWrite().monSecureWrite().monNonSecureWrite(); 4152 InitReg(MISCREG_AT_S12E0R_Xt) 4153 .hypWrite().monSecureWrite().monNonSecureWrite(); 4154 InitReg(MISCREG_AT_S12E0W_Xt) 4155 .hypWrite().monSecureWrite().monNonSecureWrite(); 4156 InitReg(MISCREG_AT_S1E3R_Xt) 4157 .monSecureWrite().monNonSecureWrite(); 4158 InitReg(MISCREG_AT_S1E3W_Xt) 4159 .monSecureWrite().monNonSecureWrite(); 4160 InitReg(MISCREG_TLBI_VMALLE1IS) 4161 .writes(1).exceptUserMode(); 4162 InitReg(MISCREG_TLBI_VAE1IS_Xt) 4163 .writes(1).exceptUserMode(); 4164 InitReg(MISCREG_TLBI_ASIDE1IS_Xt) 4165 .writes(1).exceptUserMode(); 4166 InitReg(MISCREG_TLBI_VAAE1IS_Xt) 4167 .writes(1).exceptUserMode(); 4168 InitReg(MISCREG_TLBI_VALE1IS_Xt) 4169 .writes(1).exceptUserMode(); 4170 InitReg(MISCREG_TLBI_VAALE1IS_Xt) 4171 .writes(1).exceptUserMode(); 4172 InitReg(MISCREG_TLBI_VMALLE1) 4173 .writes(1).exceptUserMode(); 4174 InitReg(MISCREG_TLBI_VAE1_Xt) 4175 .writes(1).exceptUserMode(); 4176 InitReg(MISCREG_TLBI_ASIDE1_Xt) 4177 .writes(1).exceptUserMode(); 4178 InitReg(MISCREG_TLBI_VAAE1_Xt) 4179 .writes(1).exceptUserMode(); 4180 InitReg(MISCREG_TLBI_VALE1_Xt) 4181 .writes(1).exceptUserMode(); 4182 InitReg(MISCREG_TLBI_VAALE1_Xt) 4183 .writes(1).exceptUserMode(); 4184 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt) 4185 .hypWrite().monSecureWrite().monNonSecureWrite(); 4186 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt) 4187 .hypWrite().monSecureWrite().monNonSecureWrite(); 4188 InitReg(MISCREG_TLBI_ALLE2IS) 4189 .monNonSecureWrite().hypWrite(); 4190 InitReg(MISCREG_TLBI_VAE2IS_Xt) 4191 .monNonSecureWrite().hypWrite(); 4192 InitReg(MISCREG_TLBI_ALLE1IS) 4193 .hypWrite().monSecureWrite().monNonSecureWrite(); 4194 InitReg(MISCREG_TLBI_VALE2IS_Xt) 4195 .monNonSecureWrite().hypWrite(); 4196 InitReg(MISCREG_TLBI_VMALLS12E1IS) 4197 .hypWrite().monSecureWrite().monNonSecureWrite(); 4198 InitReg(MISCREG_TLBI_IPAS2E1_Xt) 4199 .hypWrite().monSecureWrite().monNonSecureWrite(); 4200 InitReg(MISCREG_TLBI_IPAS2LE1_Xt) 4201 .hypWrite().monSecureWrite().monNonSecureWrite(); 4202 InitReg(MISCREG_TLBI_ALLE2) 4203 .monNonSecureWrite().hypWrite(); 4204 InitReg(MISCREG_TLBI_VAE2_Xt) 4205 .monNonSecureWrite().hypWrite(); 4206 InitReg(MISCREG_TLBI_ALLE1) 4207 .hypWrite().monSecureWrite().monNonSecureWrite(); 4208 InitReg(MISCREG_TLBI_VALE2_Xt) 4209 .monNonSecureWrite().hypWrite(); 4210 InitReg(MISCREG_TLBI_VMALLS12E1) 4211 .hypWrite().monSecureWrite().monNonSecureWrite(); 4212 InitReg(MISCREG_TLBI_ALLE3IS) 4213 .monSecureWrite().monNonSecureWrite(); 4214 InitReg(MISCREG_TLBI_VAE3IS_Xt) 4215 .monSecureWrite().monNonSecureWrite(); 4216 InitReg(MISCREG_TLBI_VALE3IS_Xt) 4217 .monSecureWrite().monNonSecureWrite(); 4218 InitReg(MISCREG_TLBI_ALLE3) 4219 .monSecureWrite().monNonSecureWrite(); 4220 InitReg(MISCREG_TLBI_VAE3_Xt) 4221 .monSecureWrite().monNonSecureWrite(); 4222 InitReg(MISCREG_TLBI_VALE3_Xt) 4223 .monSecureWrite().monNonSecureWrite(); 4224 InitReg(MISCREG_PMINTENSET_EL1) 4225 .allPrivileges().exceptUserMode() 4226 .mapsTo(MISCREG_PMINTENSET); 4227 InitReg(MISCREG_PMINTENCLR_EL1) 4228 .allPrivileges().exceptUserMode() 4229 .mapsTo(MISCREG_PMINTENCLR); 4230 InitReg(MISCREG_PMCR_EL0) 4231 .allPrivileges() 4232 .mapsTo(MISCREG_PMCR); 4233 InitReg(MISCREG_PMCNTENSET_EL0) 4234 .allPrivileges() 4235 .mapsTo(MISCREG_PMCNTENSET); 4236 InitReg(MISCREG_PMCNTENCLR_EL0) 4237 .allPrivileges() 4238 .mapsTo(MISCREG_PMCNTENCLR); 4239 InitReg(MISCREG_PMOVSCLR_EL0) 4240 .allPrivileges(); 4241// .mapsTo(MISCREG_PMOVSCLR); 4242 InitReg(MISCREG_PMSWINC_EL0) 4243 .writes(1).user() 4244 .mapsTo(MISCREG_PMSWINC); 4245 InitReg(MISCREG_PMSELR_EL0) 4246 .allPrivileges() 4247 .mapsTo(MISCREG_PMSELR); 4248 InitReg(MISCREG_PMCEID0_EL0) 4249 .reads(1).user() 4250 .mapsTo(MISCREG_PMCEID0); 4251 InitReg(MISCREG_PMCEID1_EL0) 4252 .reads(1).user() 4253 .mapsTo(MISCREG_PMCEID1); 4254 InitReg(MISCREG_PMCCNTR_EL0) 4255 .allPrivileges() 4256 .mapsTo(MISCREG_PMCCNTR); 4257 InitReg(MISCREG_PMXEVTYPER_EL0) 4258 .allPrivileges() 4259 .mapsTo(MISCREG_PMXEVTYPER); 4260 InitReg(MISCREG_PMCCFILTR_EL0) 4261 .allPrivileges(); 4262 InitReg(MISCREG_PMXEVCNTR_EL0) 4263 .allPrivileges() 4264 .mapsTo(MISCREG_PMXEVCNTR); 4265 InitReg(MISCREG_PMUSERENR_EL0) 4266 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0) 4267 .mapsTo(MISCREG_PMUSERENR); 4268 InitReg(MISCREG_PMOVSSET_EL0) 4269 .allPrivileges() 4270 .mapsTo(MISCREG_PMOVSSET); 4271 InitReg(MISCREG_MAIR_EL1) 4272 .allPrivileges().exceptUserMode() 4273 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS); 4274 InitReg(MISCREG_AMAIR_EL1) 4275 .allPrivileges().exceptUserMode() 4276 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS); 4277 InitReg(MISCREG_MAIR_EL2) 4278 .hyp().mon() 4279 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1); 4280 InitReg(MISCREG_AMAIR_EL2) 4281 .hyp().mon() 4282 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1); 4283 InitReg(MISCREG_MAIR_EL3) 4284 .mon(); 4285 InitReg(MISCREG_AMAIR_EL3) 4286 .mon(); 4287 InitReg(MISCREG_L2CTLR_EL1) 4288 .allPrivileges().exceptUserMode(); 4289 InitReg(MISCREG_L2ECTLR_EL1) 4290 .allPrivileges().exceptUserMode(); 4291 InitReg(MISCREG_VBAR_EL1) 4292 .allPrivileges().exceptUserMode() 4293 .mapsTo(MISCREG_VBAR_NS); 4294 InitReg(MISCREG_RVBAR_EL1) 4295 .allPrivileges().exceptUserMode().writes(0); 4296 InitReg(MISCREG_ISR_EL1) 4297 .allPrivileges().exceptUserMode().writes(0); 4298 InitReg(MISCREG_VBAR_EL2) 4299 .hyp().mon() 4300 .res0(0x7ff) 4301 .mapsTo(MISCREG_HVBAR); 4302 InitReg(MISCREG_RVBAR_EL2) 4303 .mon().hyp().writes(0); 4304 InitReg(MISCREG_VBAR_EL3) 4305 .mon(); 4306 InitReg(MISCREG_RVBAR_EL3) 4307 .mon().writes(0); 4308 InitReg(MISCREG_RMR_EL3) 4309 .mon(); 4310 InitReg(MISCREG_CONTEXTIDR_EL1) 4311 .allPrivileges().exceptUserMode() 4312 .mapsTo(MISCREG_CONTEXTIDR_NS); 4313 InitReg(MISCREG_TPIDR_EL1) 4314 .allPrivileges().exceptUserMode() 4315 .mapsTo(MISCREG_TPIDRPRW_NS); 4316 InitReg(MISCREG_TPIDR_EL0) 4317 .allPrivileges() 4318 .mapsTo(MISCREG_TPIDRURW_NS); 4319 InitReg(MISCREG_TPIDRRO_EL0) 4320 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0) 4321 .mapsTo(MISCREG_TPIDRURO_NS); 4322 InitReg(MISCREG_TPIDR_EL2) 4323 .hyp().mon() 4324 .mapsTo(MISCREG_HTPIDR); 4325 InitReg(MISCREG_TPIDR_EL3) 4326 .mon(); 4327 InitReg(MISCREG_CNTKCTL_EL1) 4328 .allPrivileges().exceptUserMode() 4329 .mapsTo(MISCREG_CNTKCTL); 4330 InitReg(MISCREG_CNTFRQ_EL0) 4331 .reads(1).mon() 4332 .mapsTo(MISCREG_CNTFRQ); 4333 InitReg(MISCREG_CNTPCT_EL0) 4334 .reads(1) 4335 .mapsTo(MISCREG_CNTPCT); /* 64b */ 4336 InitReg(MISCREG_CNTVCT_EL0) 4337 .unverifiable() 4338 .reads(1) 4339 .mapsTo(MISCREG_CNTVCT); /* 64b */ 4340 InitReg(MISCREG_CNTP_TVAL_EL0) 4341 .allPrivileges() 4342 .mapsTo(MISCREG_CNTP_TVAL_NS); 4343 InitReg(MISCREG_CNTP_CTL_EL0) 4344 .allPrivileges() 4345 .mapsTo(MISCREG_CNTP_CTL_NS); 4346 InitReg(MISCREG_CNTP_CVAL_EL0) 4347 .allPrivileges() 4348 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */ 4349 InitReg(MISCREG_CNTV_TVAL_EL0) 4350 .allPrivileges() 4351 .mapsTo(MISCREG_CNTV_TVAL); 4352 InitReg(MISCREG_CNTV_CTL_EL0) 4353 .allPrivileges() 4354 .mapsTo(MISCREG_CNTV_CTL); 4355 InitReg(MISCREG_CNTV_CVAL_EL0) 4356 .allPrivileges() 4357 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */ 4358 InitReg(MISCREG_PMEVCNTR0_EL0) 4359 .allPrivileges(); 4360// .mapsTo(MISCREG_PMEVCNTR0); 4361 InitReg(MISCREG_PMEVCNTR1_EL0) 4362 .allPrivileges(); 4363// .mapsTo(MISCREG_PMEVCNTR1); 4364 InitReg(MISCREG_PMEVCNTR2_EL0) 4365 .allPrivileges(); 4366// .mapsTo(MISCREG_PMEVCNTR2); 4367 InitReg(MISCREG_PMEVCNTR3_EL0) 4368 .allPrivileges(); 4369// .mapsTo(MISCREG_PMEVCNTR3); 4370 InitReg(MISCREG_PMEVCNTR4_EL0) 4371 .allPrivileges(); 4372// .mapsTo(MISCREG_PMEVCNTR4); 4373 InitReg(MISCREG_PMEVCNTR5_EL0) 4374 .allPrivileges(); 4375// .mapsTo(MISCREG_PMEVCNTR5); 4376 InitReg(MISCREG_PMEVTYPER0_EL0) 4377 .allPrivileges(); 4378// .mapsTo(MISCREG_PMEVTYPER0); 4379 InitReg(MISCREG_PMEVTYPER1_EL0) 4380 .allPrivileges(); 4381// .mapsTo(MISCREG_PMEVTYPER1); 4382 InitReg(MISCREG_PMEVTYPER2_EL0) 4383 .allPrivileges(); 4384// .mapsTo(MISCREG_PMEVTYPER2); 4385 InitReg(MISCREG_PMEVTYPER3_EL0) 4386 .allPrivileges(); 4387// .mapsTo(MISCREG_PMEVTYPER3); 4388 InitReg(MISCREG_PMEVTYPER4_EL0) 4389 .allPrivileges(); 4390// .mapsTo(MISCREG_PMEVTYPER4); 4391 InitReg(MISCREG_PMEVTYPER5_EL0) 4392 .allPrivileges(); 4393// .mapsTo(MISCREG_PMEVTYPER5); 4394 InitReg(MISCREG_CNTVOFF_EL2) 4395 .hyp().mon() 4396 .mapsTo(MISCREG_CNTVOFF); /* 64b */ 4397 InitReg(MISCREG_CNTHCTL_EL2) 4398 .mon().hyp() 4399 .mapsTo(MISCREG_CNTHCTL); 4400 InitReg(MISCREG_CNTHP_TVAL_EL2) 4401 .mon().hyp() 4402 .mapsTo(MISCREG_CNTHP_TVAL); 4403 InitReg(MISCREG_CNTHP_CTL_EL2) 4404 .mon().hyp() 4405 .mapsTo(MISCREG_CNTHP_CTL); 4406 InitReg(MISCREG_CNTHP_CVAL_EL2) 4407 .mon().hyp() 4408 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */ 4409 InitReg(MISCREG_CNTPS_TVAL_EL1) 4410 .mon().privSecure(); 4411 InitReg(MISCREG_CNTPS_CTL_EL1) 4412 .mon().privSecure(); 4413 InitReg(MISCREG_CNTPS_CVAL_EL1) 4414 .mon().privSecure(); 4415 InitReg(MISCREG_IL1DATA0_EL1) 4416 .allPrivileges().exceptUserMode(); 4417 InitReg(MISCREG_IL1DATA1_EL1) 4418 .allPrivileges().exceptUserMode(); 4419 InitReg(MISCREG_IL1DATA2_EL1) 4420 .allPrivileges().exceptUserMode(); 4421 InitReg(MISCREG_IL1DATA3_EL1) 4422 .allPrivileges().exceptUserMode(); 4423 InitReg(MISCREG_DL1DATA0_EL1) 4424 .allPrivileges().exceptUserMode(); 4425 InitReg(MISCREG_DL1DATA1_EL1) 4426 .allPrivileges().exceptUserMode(); 4427 InitReg(MISCREG_DL1DATA2_EL1) 4428 .allPrivileges().exceptUserMode(); 4429 InitReg(MISCREG_DL1DATA3_EL1) 4430 .allPrivileges().exceptUserMode(); 4431 InitReg(MISCREG_DL1DATA4_EL1) 4432 .allPrivileges().exceptUserMode(); 4433 InitReg(MISCREG_L2ACTLR_EL1) 4434 .allPrivileges().exceptUserMode(); 4435 InitReg(MISCREG_CPUACTLR_EL1) 4436 .allPrivileges().exceptUserMode(); 4437 InitReg(MISCREG_CPUECTLR_EL1) 4438 .allPrivileges().exceptUserMode(); 4439 InitReg(MISCREG_CPUMERRSR_EL1) 4440 .allPrivileges().exceptUserMode(); 4441 InitReg(MISCREG_L2MERRSR_EL1) 4442 .unimplemented() 4443 .warnNotFail() 4444 .allPrivileges().exceptUserMode(); 4445 InitReg(MISCREG_CBAR_EL1) 4446 .allPrivileges().exceptUserMode().writes(0); 4447 InitReg(MISCREG_CONTEXTIDR_EL2) 4448 .mon().hyp();
|
| 4449 4450 // GICv3 AArch64 4451 InitReg(MISCREG_ICC_PMR_EL1) 4452 .res0(0xffffff00) // [31:8] 4453 .allPrivileges().exceptUserMode() 4454 .mapsTo(MISCREG_ICC_PMR); 4455 InitReg(MISCREG_ICC_IAR0_EL1) 4456 .allPrivileges().exceptUserMode().writes(0) 4457 .mapsTo(MISCREG_ICC_IAR0); 4458 InitReg(MISCREG_ICC_EOIR0_EL1) 4459 .allPrivileges().exceptUserMode().reads(0) 4460 .mapsTo(MISCREG_ICC_EOIR0); 4461 InitReg(MISCREG_ICC_HPPIR0_EL1) 4462 .allPrivileges().exceptUserMode().writes(0) 4463 .mapsTo(MISCREG_ICC_HPPIR0); 4464 InitReg(MISCREG_ICC_BPR0_EL1) 4465 .res0(0xfffffff8) // [31:3] 4466 .allPrivileges().exceptUserMode() 4467 .mapsTo(MISCREG_ICC_BPR0); 4468 InitReg(MISCREG_ICC_AP0R0_EL1) 4469 .allPrivileges().exceptUserMode() 4470 .mapsTo(MISCREG_ICC_AP0R0); 4471 InitReg(MISCREG_ICC_AP0R1_EL1) 4472 .allPrivileges().exceptUserMode() 4473 .mapsTo(MISCREG_ICC_AP0R1); 4474 InitReg(MISCREG_ICC_AP0R2_EL1) 4475 .allPrivileges().exceptUserMode() 4476 .mapsTo(MISCREG_ICC_AP0R2); 4477 InitReg(MISCREG_ICC_AP0R3_EL1) 4478 .allPrivileges().exceptUserMode() 4479 .mapsTo(MISCREG_ICC_AP0R3); 4480 InitReg(MISCREG_ICC_AP1R0_EL1) 4481 .banked() 4482 .mapsTo(MISCREG_ICC_AP1R0); 4483 InitReg(MISCREG_ICC_AP1R0_EL1_NS) 4484 .bankedChild() 4485 .allPrivileges().exceptUserMode() 4486 .mapsTo(MISCREG_ICC_AP1R0_NS); 4487 InitReg(MISCREG_ICC_AP1R0_EL1_S) 4488 .bankedChild() 4489 .allPrivileges().exceptUserMode() 4490 .mapsTo(MISCREG_ICC_AP1R0_S); 4491 InitReg(MISCREG_ICC_AP1R1_EL1) 4492 .banked() 4493 .mapsTo(MISCREG_ICC_AP1R1); 4494 InitReg(MISCREG_ICC_AP1R1_EL1_NS) 4495 .bankedChild() 4496 .allPrivileges().exceptUserMode() 4497 .mapsTo(MISCREG_ICC_AP1R1_NS); 4498 InitReg(MISCREG_ICC_AP1R1_EL1_S) 4499 .bankedChild() 4500 .allPrivileges().exceptUserMode() 4501 .mapsTo(MISCREG_ICC_AP1R1_S); 4502 InitReg(MISCREG_ICC_AP1R2_EL1) 4503 .banked() 4504 .mapsTo(MISCREG_ICC_AP1R2); 4505 InitReg(MISCREG_ICC_AP1R2_EL1_NS) 4506 .bankedChild() 4507 .allPrivileges().exceptUserMode() 4508 .mapsTo(MISCREG_ICC_AP1R2_NS); 4509 InitReg(MISCREG_ICC_AP1R2_EL1_S) 4510 .bankedChild() 4511 .allPrivileges().exceptUserMode() 4512 .mapsTo(MISCREG_ICC_AP1R2_S); 4513 InitReg(MISCREG_ICC_AP1R3_EL1) 4514 .banked() 4515 .mapsTo(MISCREG_ICC_AP1R3); 4516 InitReg(MISCREG_ICC_AP1R3_EL1_NS) 4517 .bankedChild() 4518 .allPrivileges().exceptUserMode() 4519 .mapsTo(MISCREG_ICC_AP1R3_NS); 4520 InitReg(MISCREG_ICC_AP1R3_EL1_S) 4521 .bankedChild() 4522 .allPrivileges().exceptUserMode() 4523 .mapsTo(MISCREG_ICC_AP1R3_S); 4524 InitReg(MISCREG_ICC_DIR_EL1) 4525 .res0(0xFF000000) // [31:24] 4526 .allPrivileges().exceptUserMode().reads(0) 4527 .mapsTo(MISCREG_ICC_DIR); 4528 InitReg(MISCREG_ICC_RPR_EL1) 4529 .allPrivileges().exceptUserMode().writes(0) 4530 .mapsTo(MISCREG_ICC_RPR); 4531 InitReg(MISCREG_ICC_SGI1R_EL1) 4532 .allPrivileges().exceptUserMode().reads(0) 4533 .mapsTo(MISCREG_ICC_SGI1R); 4534 InitReg(MISCREG_ICC_ASGI1R_EL1) 4535 .allPrivileges().exceptUserMode().reads(0) 4536 .mapsTo(MISCREG_ICC_ASGI1R); 4537 InitReg(MISCREG_ICC_SGI0R_EL1) 4538 .allPrivileges().exceptUserMode().reads(0) 4539 .mapsTo(MISCREG_ICC_SGI0R); 4540 InitReg(MISCREG_ICC_IAR1_EL1) 4541 .allPrivileges().exceptUserMode().writes(0) 4542 .mapsTo(MISCREG_ICC_IAR1); 4543 InitReg(MISCREG_ICC_EOIR1_EL1) 4544 .res0(0xFF000000) // [31:24] 4545 .allPrivileges().exceptUserMode().reads(0) 4546 .mapsTo(MISCREG_ICC_EOIR1); 4547 InitReg(MISCREG_ICC_HPPIR1_EL1) 4548 .allPrivileges().exceptUserMode().writes(0) 4549 .mapsTo(MISCREG_ICC_HPPIR1); 4550 InitReg(MISCREG_ICC_BPR1_EL1) 4551 .banked() 4552 .mapsTo(MISCREG_ICC_BPR1); 4553 InitReg(MISCREG_ICC_BPR1_EL1_NS) 4554 .bankedChild() 4555 .res0(0xfffffff8) // [31:3] 4556 .allPrivileges().exceptUserMode() 4557 .mapsTo(MISCREG_ICC_BPR1_NS); 4558 InitReg(MISCREG_ICC_BPR1_EL1_S) 4559 .bankedChild() 4560 .res0(0xfffffff8) // [31:3] 4561 .secure().exceptUserMode() 4562 .mapsTo(MISCREG_ICC_BPR1_S); 4563 InitReg(MISCREG_ICC_CTLR_EL1) 4564 .banked() 4565 .mapsTo(MISCREG_ICC_CTLR); 4566 InitReg(MISCREG_ICC_CTLR_EL1_NS) 4567 .bankedChild() 4568 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2] 4569 .allPrivileges().exceptUserMode() 4570 .mapsTo(MISCREG_ICC_CTLR_NS); 4571 InitReg(MISCREG_ICC_CTLR_EL1_S) 4572 .bankedChild() 4573 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2] 4574 .secure().exceptUserMode() 4575 .mapsTo(MISCREG_ICC_CTLR_S); 4576 InitReg(MISCREG_ICC_SRE_EL1) 4577 .banked() 4578 .mapsTo(MISCREG_ICC_SRE); 4579 InitReg(MISCREG_ICC_SRE_EL1_NS) 4580 .bankedChild() 4581 .res0(0xFFFFFFF8) // [31:3] 4582 .allPrivileges().exceptUserMode() 4583 .mapsTo(MISCREG_ICC_SRE_NS); 4584 InitReg(MISCREG_ICC_SRE_EL1_S) 4585 .bankedChild() 4586 .res0(0xFFFFFFF8) // [31:3] 4587 .secure().exceptUserMode() 4588 .mapsTo(MISCREG_ICC_SRE_S); 4589 InitReg(MISCREG_ICC_IGRPEN0_EL1) 4590 .res0(0xFFFFFFFE) // [31:1] 4591 .allPrivileges().exceptUserMode() 4592 .mapsTo(MISCREG_ICC_IGRPEN0); 4593 InitReg(MISCREG_ICC_IGRPEN1_EL1) 4594 .banked() 4595 .mapsTo(MISCREG_ICC_IGRPEN1); 4596 InitReg(MISCREG_ICC_IGRPEN1_EL1_NS) 4597 .bankedChild() 4598 .res0(0xFFFFFFFE) // [31:1] 4599 .allPrivileges().exceptUserMode() 4600 .mapsTo(MISCREG_ICC_IGRPEN1_NS); 4601 InitReg(MISCREG_ICC_IGRPEN1_EL1_S) 4602 .bankedChild() 4603 .res0(0xFFFFFFFE) // [31:1] 4604 .secure().exceptUserMode() 4605 .mapsTo(MISCREG_ICC_IGRPEN1_S); 4606 InitReg(MISCREG_ICC_SRE_EL2) 4607 .hyp().mon() 4608 .mapsTo(MISCREG_ICC_HSRE); 4609 InitReg(MISCREG_ICC_CTLR_EL3) 4610 .allPrivileges().exceptUserMode() 4611 .mapsTo(MISCREG_ICC_MCTLR); 4612 InitReg(MISCREG_ICC_SRE_EL3) 4613 .allPrivileges().exceptUserMode() 4614 .mapsTo(MISCREG_ICC_MSRE); 4615 InitReg(MISCREG_ICC_IGRPEN1_EL3) 4616 .allPrivileges().exceptUserMode() 4617 .mapsTo(MISCREG_ICC_MGRPEN1); 4618 4619 InitReg(MISCREG_ICH_AP0R0_EL2) 4620 .hyp().mon() 4621 .mapsTo(MISCREG_ICH_AP0R0); 4622 InitReg(MISCREG_ICH_AP0R1_EL2) 4623 .hyp().mon() 4624 .unimplemented() 4625 .mapsTo(MISCREG_ICH_AP0R1); 4626 InitReg(MISCREG_ICH_AP0R2_EL2) 4627 .hyp().mon() 4628 .unimplemented() 4629 .mapsTo(MISCREG_ICH_AP0R2); 4630 InitReg(MISCREG_ICH_AP0R3_EL2) 4631 .hyp().mon() 4632 .unimplemented() 4633 .mapsTo(MISCREG_ICH_AP0R3); 4634 InitReg(MISCREG_ICH_AP1R0_EL2) 4635 .hyp().mon() 4636 .mapsTo(MISCREG_ICH_AP1R0); 4637 InitReg(MISCREG_ICH_AP1R1_EL2) 4638 .hyp().mon() 4639 .unimplemented() 4640 .mapsTo(MISCREG_ICH_AP1R1); 4641 InitReg(MISCREG_ICH_AP1R2_EL2) 4642 .hyp().mon() 4643 .unimplemented() 4644 .mapsTo(MISCREG_ICH_AP1R2); 4645 InitReg(MISCREG_ICH_AP1R3_EL2) 4646 .hyp().mon() 4647 .unimplemented() 4648 .mapsTo(MISCREG_ICH_AP1R3); 4649 InitReg(MISCREG_ICH_HCR_EL2) 4650 .hyp().mon() 4651 .mapsTo(MISCREG_ICH_HCR); 4652 InitReg(MISCREG_ICH_VTR_EL2) 4653 .hyp().mon().writes(0) 4654 .mapsTo(MISCREG_ICH_VTR); 4655 InitReg(MISCREG_ICH_MISR_EL2) 4656 .hyp().mon().writes(0) 4657 .mapsTo(MISCREG_ICH_MISR); 4658 InitReg(MISCREG_ICH_EISR_EL2) 4659 .hyp().mon().writes(0) 4660 .mapsTo(MISCREG_ICH_EISR); 4661 InitReg(MISCREG_ICH_ELRSR_EL2) 4662 .hyp().mon().writes(0) 4663 .mapsTo(MISCREG_ICH_ELRSR); 4664 InitReg(MISCREG_ICH_VMCR_EL2) 4665 .hyp().mon() 4666 .mapsTo(MISCREG_ICH_VMCR); 4667 InitReg(MISCREG_ICH_LR0_EL2) 4668 .hyp().mon() 4669 .allPrivileges().exceptUserMode(); 4670 InitReg(MISCREG_ICH_LR1_EL2) 4671 .hyp().mon() 4672 .allPrivileges().exceptUserMode(); 4673 InitReg(MISCREG_ICH_LR2_EL2) 4674 .hyp().mon() 4675 .allPrivileges().exceptUserMode(); 4676 InitReg(MISCREG_ICH_LR3_EL2) 4677 .hyp().mon() 4678 .allPrivileges().exceptUserMode(); 4679 InitReg(MISCREG_ICH_LR4_EL2) 4680 .hyp().mon() 4681 .allPrivileges().exceptUserMode(); 4682 InitReg(MISCREG_ICH_LR5_EL2) 4683 .hyp().mon() 4684 .allPrivileges().exceptUserMode(); 4685 InitReg(MISCREG_ICH_LR6_EL2) 4686 .hyp().mon() 4687 .allPrivileges().exceptUserMode(); 4688 InitReg(MISCREG_ICH_LR7_EL2) 4689 .hyp().mon() 4690 .allPrivileges().exceptUserMode(); 4691 InitReg(MISCREG_ICH_LR8_EL2) 4692 .hyp().mon() 4693 .allPrivileges().exceptUserMode(); 4694 InitReg(MISCREG_ICH_LR9_EL2) 4695 .hyp().mon() 4696 .allPrivileges().exceptUserMode(); 4697 InitReg(MISCREG_ICH_LR10_EL2) 4698 .hyp().mon() 4699 .allPrivileges().exceptUserMode(); 4700 InitReg(MISCREG_ICH_LR11_EL2) 4701 .hyp().mon() 4702 .allPrivileges().exceptUserMode(); 4703 InitReg(MISCREG_ICH_LR12_EL2) 4704 .hyp().mon() 4705 .allPrivileges().exceptUserMode(); 4706 InitReg(MISCREG_ICH_LR13_EL2) 4707 .hyp().mon() 4708 .allPrivileges().exceptUserMode(); 4709 InitReg(MISCREG_ICH_LR14_EL2) 4710 .hyp().mon() 4711 .allPrivileges().exceptUserMode(); 4712 InitReg(MISCREG_ICH_LR15_EL2) 4713 .hyp().mon() 4714 .allPrivileges().exceptUserMode(); 4715 4716 // GICv3 AArch32 4717 InitReg(MISCREG_ICC_AP0R0) 4718 .allPrivileges().exceptUserMode(); 4719 InitReg(MISCREG_ICC_AP0R1) 4720 .allPrivileges().exceptUserMode(); 4721 InitReg(MISCREG_ICC_AP0R2) 4722 .allPrivileges().exceptUserMode(); 4723 InitReg(MISCREG_ICC_AP0R3) 4724 .allPrivileges().exceptUserMode(); 4725 InitReg(MISCREG_ICC_AP1R0) 4726 .allPrivileges().exceptUserMode(); 4727 InitReg(MISCREG_ICC_AP1R0_NS) 4728 .allPrivileges().exceptUserMode(); 4729 InitReg(MISCREG_ICC_AP1R0_S) 4730 .allPrivileges().exceptUserMode(); 4731 InitReg(MISCREG_ICC_AP1R1) 4732 .allPrivileges().exceptUserMode(); 4733 InitReg(MISCREG_ICC_AP1R1_NS) 4734 .allPrivileges().exceptUserMode(); 4735 InitReg(MISCREG_ICC_AP1R1_S) 4736 .allPrivileges().exceptUserMode(); 4737 InitReg(MISCREG_ICC_AP1R2) 4738 .allPrivileges().exceptUserMode(); 4739 InitReg(MISCREG_ICC_AP1R2_NS) 4740 .allPrivileges().exceptUserMode(); 4741 InitReg(MISCREG_ICC_AP1R2_S) 4742 .allPrivileges().exceptUserMode(); 4743 InitReg(MISCREG_ICC_AP1R3) 4744 .allPrivileges().exceptUserMode(); 4745 InitReg(MISCREG_ICC_AP1R3_NS) 4746 .allPrivileges().exceptUserMode(); 4747 InitReg(MISCREG_ICC_AP1R3_S) 4748 .allPrivileges().exceptUserMode(); 4749 InitReg(MISCREG_ICC_ASGI1R) 4750 .allPrivileges().exceptUserMode().reads(0); 4751 InitReg(MISCREG_ICC_BPR0) 4752 .allPrivileges().exceptUserMode(); 4753 InitReg(MISCREG_ICC_BPR1) 4754 .allPrivileges().exceptUserMode(); 4755 InitReg(MISCREG_ICC_BPR1_NS) 4756 .allPrivileges().exceptUserMode(); 4757 InitReg(MISCREG_ICC_BPR1_S) 4758 .allPrivileges().exceptUserMode(); 4759 InitReg(MISCREG_ICC_CTLR) 4760 .allPrivileges().exceptUserMode(); 4761 InitReg(MISCREG_ICC_CTLR_NS) 4762 .allPrivileges().exceptUserMode(); 4763 InitReg(MISCREG_ICC_CTLR_S) 4764 .allPrivileges().exceptUserMode(); 4765 InitReg(MISCREG_ICC_DIR) 4766 .allPrivileges().exceptUserMode().reads(0); 4767 InitReg(MISCREG_ICC_EOIR0) 4768 .allPrivileges().exceptUserMode().reads(0); 4769 InitReg(MISCREG_ICC_EOIR1) 4770 .allPrivileges().exceptUserMode().reads(0); 4771 InitReg(MISCREG_ICC_HPPIR0) 4772 .allPrivileges().exceptUserMode().writes(0); 4773 InitReg(MISCREG_ICC_HPPIR1) 4774 .allPrivileges().exceptUserMode().writes(0); 4775 InitReg(MISCREG_ICC_HSRE) 4776 .allPrivileges().exceptUserMode(); 4777 InitReg(MISCREG_ICC_IAR0) 4778 .allPrivileges().exceptUserMode().writes(0); 4779 InitReg(MISCREG_ICC_IAR1) 4780 .allPrivileges().exceptUserMode().writes(0); 4781 InitReg(MISCREG_ICC_IGRPEN0) 4782 .allPrivileges().exceptUserMode(); 4783 InitReg(MISCREG_ICC_IGRPEN1) 4784 .allPrivileges().exceptUserMode(); 4785 InitReg(MISCREG_ICC_IGRPEN1_NS) 4786 .allPrivileges().exceptUserMode(); 4787 InitReg(MISCREG_ICC_IGRPEN1_S) 4788 .allPrivileges().exceptUserMode(); 4789 InitReg(MISCREG_ICC_MCTLR) 4790 .allPrivileges().exceptUserMode(); 4791 InitReg(MISCREG_ICC_MGRPEN1) 4792 .allPrivileges().exceptUserMode(); 4793 InitReg(MISCREG_ICC_MSRE) 4794 .allPrivileges().exceptUserMode(); 4795 InitReg(MISCREG_ICC_PMR) 4796 .allPrivileges().exceptUserMode(); 4797 InitReg(MISCREG_ICC_RPR) 4798 .allPrivileges().exceptUserMode().writes(0); 4799 InitReg(MISCREG_ICC_SGI0R) 4800 .allPrivileges().exceptUserMode().reads(0); 4801 InitReg(MISCREG_ICC_SGI1R) 4802 .allPrivileges().exceptUserMode().reads(0); 4803 InitReg(MISCREG_ICC_SRE) 4804 .allPrivileges().exceptUserMode(); 4805 InitReg(MISCREG_ICC_SRE_NS) 4806 .allPrivileges().exceptUserMode(); 4807 InitReg(MISCREG_ICC_SRE_S) 4808 .allPrivileges().exceptUserMode(); 4809 4810 InitReg(MISCREG_ICH_AP0R0) 4811 .hyp().mon(); 4812 InitReg(MISCREG_ICH_AP0R1) 4813 .hyp().mon(); 4814 InitReg(MISCREG_ICH_AP0R2) 4815 .hyp().mon(); 4816 InitReg(MISCREG_ICH_AP0R3) 4817 .hyp().mon(); 4818 InitReg(MISCREG_ICH_AP1R0) 4819 .hyp().mon(); 4820 InitReg(MISCREG_ICH_AP1R1) 4821 .hyp().mon(); 4822 InitReg(MISCREG_ICH_AP1R2) 4823 .hyp().mon(); 4824 InitReg(MISCREG_ICH_AP1R3) 4825 .hyp().mon(); 4826 InitReg(MISCREG_ICH_HCR) 4827 .hyp().mon(); 4828 InitReg(MISCREG_ICH_VTR) 4829 .hyp().mon().writes(0); 4830 InitReg(MISCREG_ICH_MISR) 4831 .hyp().mon().writes(0); 4832 InitReg(MISCREG_ICH_EISR) 4833 .hyp().mon().writes(0); 4834 InitReg(MISCREG_ICH_ELRSR) 4835 .hyp().mon().writes(0); 4836 InitReg(MISCREG_ICH_VMCR) 4837 .hyp().mon(); 4838 InitReg(MISCREG_ICH_LR0) 4839 .hyp().mon(); 4840 InitReg(MISCREG_ICH_LR1) 4841 .hyp().mon(); 4842 InitReg(MISCREG_ICH_LR2) 4843 .hyp().mon(); 4844 InitReg(MISCREG_ICH_LR3) 4845 .hyp().mon(); 4846 InitReg(MISCREG_ICH_LR4) 4847 .hyp().mon(); 4848 InitReg(MISCREG_ICH_LR5) 4849 .hyp().mon(); 4850 InitReg(MISCREG_ICH_LR6) 4851 .hyp().mon(); 4852 InitReg(MISCREG_ICH_LR7) 4853 .hyp().mon(); 4854 InitReg(MISCREG_ICH_LR8) 4855 .hyp().mon(); 4856 InitReg(MISCREG_ICH_LR9) 4857 .hyp().mon(); 4858 InitReg(MISCREG_ICH_LR10) 4859 .hyp().mon(); 4860 InitReg(MISCREG_ICH_LR11) 4861 .hyp().mon(); 4862 InitReg(MISCREG_ICH_LR12) 4863 .hyp().mon(); 4864 InitReg(MISCREG_ICH_LR13) 4865 .hyp().mon(); 4866 InitReg(MISCREG_ICH_LR14) 4867 .hyp().mon(); 4868 InitReg(MISCREG_ICH_LR15) 4869 .hyp().mon(); 4870 InitReg(MISCREG_ICH_LRC0) 4871 .mapsTo(MISCREG_ICH_LR0) 4872 .hyp().mon(); 4873 InitReg(MISCREG_ICH_LRC1) 4874 .mapsTo(MISCREG_ICH_LR1) 4875 .hyp().mon(); 4876 InitReg(MISCREG_ICH_LRC2) 4877 .mapsTo(MISCREG_ICH_LR2) 4878 .hyp().mon(); 4879 InitReg(MISCREG_ICH_LRC3) 4880 .mapsTo(MISCREG_ICH_LR3) 4881 .hyp().mon(); 4882 InitReg(MISCREG_ICH_LRC4) 4883 .mapsTo(MISCREG_ICH_LR4) 4884 .hyp().mon(); 4885 InitReg(MISCREG_ICH_LRC5) 4886 .mapsTo(MISCREG_ICH_LR5) 4887 .hyp().mon(); 4888 InitReg(MISCREG_ICH_LRC6) 4889 .mapsTo(MISCREG_ICH_LR6) 4890 .hyp().mon(); 4891 InitReg(MISCREG_ICH_LRC7) 4892 .mapsTo(MISCREG_ICH_LR7) 4893 .hyp().mon(); 4894 InitReg(MISCREG_ICH_LRC8) 4895 .mapsTo(MISCREG_ICH_LR8) 4896 .hyp().mon(); 4897 InitReg(MISCREG_ICH_LRC9) 4898 .mapsTo(MISCREG_ICH_LR9) 4899 .hyp().mon(); 4900 InitReg(MISCREG_ICH_LRC10) 4901 .mapsTo(MISCREG_ICH_LR10) 4902 .hyp().mon(); 4903 InitReg(MISCREG_ICH_LRC11) 4904 .mapsTo(MISCREG_ICH_LR11) 4905 .hyp().mon(); 4906 InitReg(MISCREG_ICH_LRC12) 4907 .mapsTo(MISCREG_ICH_LR12) 4908 .hyp().mon(); 4909 InitReg(MISCREG_ICH_LRC13) 4910 .mapsTo(MISCREG_ICH_LR13) 4911 .hyp().mon(); 4912 InitReg(MISCREG_ICH_LRC14) 4913 .mapsTo(MISCREG_ICH_LR14) 4914 .hyp().mon(); 4915 InitReg(MISCREG_ICH_LRC15) 4916 .mapsTo(MISCREG_ICH_LR15) 4917 .hyp().mon(); 4918
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4097 InitReg(MISCREG_CNTHV_CTL_EL2) 4098 .mon().hyp(); 4099 InitReg(MISCREG_CNTHV_CVAL_EL2) 4100 .mon().hyp(); 4101 InitReg(MISCREG_CNTHV_TVAL_EL2) 4102 .mon().hyp(); 4103 4104 // Dummy registers 4105 InitReg(MISCREG_NOP) 4106 .allPrivileges(); 4107 InitReg(MISCREG_RAZ) 4108 .allPrivileges().exceptUserMode().writes(0); 4109 InitReg(MISCREG_CP14_UNIMPL) 4110 .unimplemented() 4111 .warnNotFail(); 4112 InitReg(MISCREG_CP15_UNIMPL) 4113 .unimplemented() 4114 .warnNotFail(); 4115 InitReg(MISCREG_UNKNOWN); 4116 InitReg(MISCREG_IMPDEF_UNIMPL) 4117 .unimplemented() 4118 .warnNotFail(impdefAsNop); 4119 4120 // RAS extension (unimplemented) 4121 InitReg(MISCREG_ERRIDR_EL1) 4122 .unimplemented() 4123 .warnNotFail(); 4124 InitReg(MISCREG_ERRSELR_EL1) 4125 .unimplemented() 4126 .warnNotFail(); 4127 InitReg(MISCREG_ERXFR_EL1) 4128 .unimplemented() 4129 .warnNotFail(); 4130 InitReg(MISCREG_ERXCTLR_EL1) 4131 .unimplemented() 4132 .warnNotFail(); 4133 InitReg(MISCREG_ERXSTATUS_EL1) 4134 .unimplemented() 4135 .warnNotFail(); 4136 InitReg(MISCREG_ERXADDR_EL1) 4137 .unimplemented() 4138 .warnNotFail(); 4139 InitReg(MISCREG_ERXMISC0_EL1) 4140 .unimplemented() 4141 .warnNotFail(); 4142 InitReg(MISCREG_ERXMISC1_EL1) 4143 .unimplemented() 4144 .warnNotFail(); 4145 InitReg(MISCREG_DISR_EL1) 4146 .unimplemented() 4147 .warnNotFail(); 4148 InitReg(MISCREG_VSESR_EL2) 4149 .unimplemented() 4150 .warnNotFail(); 4151 InitReg(MISCREG_VDISR_EL2) 4152 .unimplemented() 4153 .warnNotFail(); 4154 4155 // Register mappings for some unimplemented registers: 4156 // ESR_EL1 -> DFSR 4157 // RMR_EL1 -> RMR 4158 // RMR_EL2 -> HRMR 4159 // DBGDTR_EL0 -> DBGDTR{R or T}Xint 4160 // DBGDTRRX_EL0 -> DBGDTRRXint 4161 // DBGDTRTX_EL0 -> DBGDTRRXint 4162 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5) 4163 4164 completed = true; 4165} 4166 4167} // namespace ArmISA
| 4919 InitReg(MISCREG_CNTHV_CTL_EL2) 4920 .mon().hyp(); 4921 InitReg(MISCREG_CNTHV_CVAL_EL2) 4922 .mon().hyp(); 4923 InitReg(MISCREG_CNTHV_TVAL_EL2) 4924 .mon().hyp(); 4925 4926 // Dummy registers 4927 InitReg(MISCREG_NOP) 4928 .allPrivileges(); 4929 InitReg(MISCREG_RAZ) 4930 .allPrivileges().exceptUserMode().writes(0); 4931 InitReg(MISCREG_CP14_UNIMPL) 4932 .unimplemented() 4933 .warnNotFail(); 4934 InitReg(MISCREG_CP15_UNIMPL) 4935 .unimplemented() 4936 .warnNotFail(); 4937 InitReg(MISCREG_UNKNOWN); 4938 InitReg(MISCREG_IMPDEF_UNIMPL) 4939 .unimplemented() 4940 .warnNotFail(impdefAsNop); 4941 4942 // RAS extension (unimplemented) 4943 InitReg(MISCREG_ERRIDR_EL1) 4944 .unimplemented() 4945 .warnNotFail(); 4946 InitReg(MISCREG_ERRSELR_EL1) 4947 .unimplemented() 4948 .warnNotFail(); 4949 InitReg(MISCREG_ERXFR_EL1) 4950 .unimplemented() 4951 .warnNotFail(); 4952 InitReg(MISCREG_ERXCTLR_EL1) 4953 .unimplemented() 4954 .warnNotFail(); 4955 InitReg(MISCREG_ERXSTATUS_EL1) 4956 .unimplemented() 4957 .warnNotFail(); 4958 InitReg(MISCREG_ERXADDR_EL1) 4959 .unimplemented() 4960 .warnNotFail(); 4961 InitReg(MISCREG_ERXMISC0_EL1) 4962 .unimplemented() 4963 .warnNotFail(); 4964 InitReg(MISCREG_ERXMISC1_EL1) 4965 .unimplemented() 4966 .warnNotFail(); 4967 InitReg(MISCREG_DISR_EL1) 4968 .unimplemented() 4969 .warnNotFail(); 4970 InitReg(MISCREG_VSESR_EL2) 4971 .unimplemented() 4972 .warnNotFail(); 4973 InitReg(MISCREG_VDISR_EL2) 4974 .unimplemented() 4975 .warnNotFail(); 4976 4977 // Register mappings for some unimplemented registers: 4978 // ESR_EL1 -> DFSR 4979 // RMR_EL1 -> RMR 4980 // RMR_EL2 -> HRMR 4981 // DBGDTR_EL0 -> DBGDTR{R or T}Xint 4982 // DBGDTRRX_EL0 -> DBGDTRRXint 4983 // DBGDTRTX_EL0 -> DBGDTRRXint 4984 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5) 4985 4986 completed = true; 4987} 4988 4989} // namespace ArmISA
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