miscregs.cc (12576:e55d2103ccac) | miscregs.cc (12577:5cafe57f87e5) |
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1/* 2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 474 unchanged lines hidden (view full) --- 483 case 5: 484 return MISCREG_TLBIMVAL; 485 case 7: 486 return MISCREG_TLBIMVAAL; 487 } 488 break; 489 } 490 } else if (opc1 == 4) { | 1/* 2 * Copyright (c) 2010-2013, 2015-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 474 unchanged lines hidden (view full) --- 483 case 5: 484 return MISCREG_TLBIMVAL; 485 case 7: 486 return MISCREG_TLBIMVAAL; 487 } 488 break; 489 } 490 } else if (opc1 == 4) { |
491 if (crm == 3) { | 491 if (crm == 0) { |
492 switch (opc2) { | 492 switch (opc2) { |
493 case 1: 494 return MISCREG_TLBIIPAS2IS; 495 case 5: 496 return MISCREG_TLBIIPAS2LIS; 497 } 498 } else if (crm == 3) { 499 switch (opc2) { |
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493 case 0: 494 return MISCREG_TLBIALLHIS; 495 case 1: 496 return MISCREG_TLBIMVAHIS; 497 case 4: 498 return MISCREG_TLBIALLNSNHIS; 499 case 5: 500 return MISCREG_TLBIMVALHIS; 501 } | 500 case 0: 501 return MISCREG_TLBIALLHIS; 502 case 1: 503 return MISCREG_TLBIMVAHIS; 504 case 4: 505 return MISCREG_TLBIALLNSNHIS; 506 case 5: 507 return MISCREG_TLBIMVALHIS; 508 } |
509 } else if (crm == 4) { 510 switch (opc2) { 511 case 1: 512 return MISCREG_TLBIIPAS2; 513 case 5: 514 return MISCREG_TLBIIPAS2L; 515 } |
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502 } else if (crm == 7) { 503 switch (opc2) { 504 case 0: 505 return MISCREG_TLBIALLH; 506 case 1: 507 return MISCREG_TLBIMVAH; 508 case 4: 509 return MISCREG_TLBIALLNSNH; --- 2417 unchanged lines hidden (view full) --- 2927 .writes(1).exceptUserMode(); 2928 InitReg(MISCREG_TLBIMVAA) 2929 .writes(1).exceptUserMode(); 2930 InitReg(MISCREG_TLBIMVAL) 2931 .writes(1).exceptUserMode(); 2932 InitReg(MISCREG_TLBIMVAAL) 2933 .writes(1).exceptUserMode(); 2934 InitReg(MISCREG_TLBIIPAS2IS) | 516 } else if (crm == 7) { 517 switch (opc2) { 518 case 0: 519 return MISCREG_TLBIALLH; 520 case 1: 521 return MISCREG_TLBIMVAH; 522 case 4: 523 return MISCREG_TLBIALLNSNH; --- 2417 unchanged lines hidden (view full) --- 2941 .writes(1).exceptUserMode(); 2942 InitReg(MISCREG_TLBIMVAA) 2943 .writes(1).exceptUserMode(); 2944 InitReg(MISCREG_TLBIMVAL) 2945 .writes(1).exceptUserMode(); 2946 InitReg(MISCREG_TLBIMVAAL) 2947 .writes(1).exceptUserMode(); 2948 InitReg(MISCREG_TLBIIPAS2IS) |
2935 .unimplemented() | |
2936 .monNonSecureWrite().hypWrite(); 2937 InitReg(MISCREG_TLBIIPAS2LIS) | 2949 .monNonSecureWrite().hypWrite(); 2950 InitReg(MISCREG_TLBIIPAS2LIS) |
2938 .unimplemented() | |
2939 .monNonSecureWrite().hypWrite(); 2940 InitReg(MISCREG_TLBIALLHIS) 2941 .monNonSecureWrite().hypWrite(); 2942 InitReg(MISCREG_TLBIMVAHIS) 2943 .monNonSecureWrite().hypWrite(); 2944 InitReg(MISCREG_TLBIALLNSNHIS) 2945 .monNonSecureWrite().hypWrite(); 2946 InitReg(MISCREG_TLBIMVALHIS) 2947 .monNonSecureWrite().hypWrite(); 2948 InitReg(MISCREG_TLBIIPAS2) | 2951 .monNonSecureWrite().hypWrite(); 2952 InitReg(MISCREG_TLBIALLHIS) 2953 .monNonSecureWrite().hypWrite(); 2954 InitReg(MISCREG_TLBIMVAHIS) 2955 .monNonSecureWrite().hypWrite(); 2956 InitReg(MISCREG_TLBIALLNSNHIS) 2957 .monNonSecureWrite().hypWrite(); 2958 InitReg(MISCREG_TLBIMVALHIS) 2959 .monNonSecureWrite().hypWrite(); 2960 InitReg(MISCREG_TLBIIPAS2) |
2949 .unimplemented() | |
2950 .monNonSecureWrite().hypWrite(); 2951 InitReg(MISCREG_TLBIIPAS2L) | 2961 .monNonSecureWrite().hypWrite(); 2962 InitReg(MISCREG_TLBIIPAS2L) |
2952 .unimplemented() | |
2953 .monNonSecureWrite().hypWrite(); 2954 InitReg(MISCREG_TLBIALLH) 2955 .monNonSecureWrite().hypWrite(); 2956 InitReg(MISCREG_TLBIMVAH) 2957 .monNonSecureWrite().hypWrite(); 2958 InitReg(MISCREG_TLBIALLNSNH) 2959 .monNonSecureWrite().hypWrite(); 2960 InitReg(MISCREG_TLBIMVALH) --- 995 unchanged lines hidden --- | 2963 .monNonSecureWrite().hypWrite(); 2964 InitReg(MISCREG_TLBIALLH) 2965 .monNonSecureWrite().hypWrite(); 2966 InitReg(MISCREG_TLBIMVAH) 2967 .monNonSecureWrite().hypWrite(); 2968 InitReg(MISCREG_TLBIALLNSNH) 2969 .monNonSecureWrite().hypWrite(); 2970 InitReg(MISCREG_TLBIMVALH) --- 995 unchanged lines hidden --- |