1/*
2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 * Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include <tuple>
45
46#include "arch/arm/isa.hh"
47#include "base/logging.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51namespace ArmISA
52{
53
54MiscRegIndex
55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56{
57 switch(crn) {
58 case 0:
59 switch (opc1) {
60 case 0:
61 switch (opc2) {
62 case 0:
63 switch (crm) {
64 case 0:
65 return MISCREG_DBGDIDR;
66 case 1:
67 return MISCREG_DBGDSCRint;
68 }
69 break;
70 }
71 break;
72 case 7:
73 switch (opc2) {
74 case 0:
75 switch (crm) {
76 case 0:
77 return MISCREG_JIDR;
78 }
79 break;
80 }
81 break;
82 }
83 break;
84 case 1:
85 switch (opc1) {
86 case 6:
87 switch (crm) {
88 case 0:
89 switch (opc2) {
90 case 0:
91 return MISCREG_TEEHBR;
92 }
93 break;
94 }
95 break;
96 case 7:
97 switch (crm) {
98 case 0:
99 switch (opc2) {
100 case 0:
101 return MISCREG_JOSCR;
102 }
103 break;
104 }
105 break;
106 }
107 break;
108 case 2:
109 switch (opc1) {
110 case 7:
111 switch (crm) {
112 case 0:
113 switch (opc2) {
114 case 0:
115 return MISCREG_JMCR;
116 }
117 break;
118 }
119 break;
120 }
121 break;
122 }
123 // If we get here then it must be a register that we haven't implemented
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn, opc1, crm, opc2);
126 return MISCREG_CP14_UNIMPL;
127}
128
129using namespace std;
130
131MiscRegIndex
132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133{
134 switch (crn) {
135 case 0:
136 switch (opc1) {
137 case 0:
138 switch (crm) {
139 case 0:
140 switch (opc2) {
141 case 1:
142 return MISCREG_CTR;
143 case 2:
144 return MISCREG_TCMTR;
145 case 3:
146 return MISCREG_TLBTR;
147 case 5:
148 return MISCREG_MPIDR;
149 case 6:
150 return MISCREG_REVIDR;
151 default:
152 return MISCREG_MIDR;
153 }
154 break;
155 case 1:
156 switch (opc2) {
157 case 0:
158 return MISCREG_ID_PFR0;
159 case 1:
160 return MISCREG_ID_PFR1;
161 case 2:
162 return MISCREG_ID_DFR0;
163 case 3:
164 return MISCREG_ID_AFR0;
165 case 4:
166 return MISCREG_ID_MMFR0;
167 case 5:
168 return MISCREG_ID_MMFR1;
169 case 6:
170 return MISCREG_ID_MMFR2;
171 case 7:
172 return MISCREG_ID_MMFR3;
173 }
174 break;
175 case 2:
176 switch (opc2) {
177 case 0:
178 return MISCREG_ID_ISAR0;
179 case 1:
180 return MISCREG_ID_ISAR1;
181 case 2:
182 return MISCREG_ID_ISAR2;
183 case 3:
184 return MISCREG_ID_ISAR3;
185 case 4:
186 return MISCREG_ID_ISAR4;
187 case 5:
188 return MISCREG_ID_ISAR5;
189 case 6:
190 case 7:
191 return MISCREG_RAZ; // read as zero
192 }
193 break;
194 default:
195 return MISCREG_RAZ; // read as zero
196 }
197 break;
198 case 1:
199 if (crm == 0) {
200 switch (opc2) {
201 case 0:
202 return MISCREG_CCSIDR;
203 case 1:
204 return MISCREG_CLIDR;
205 case 7:
206 return MISCREG_AIDR;
207 }
208 }
209 break;
210 case 2:
211 if (crm == 0 && opc2 == 0) {
212 return MISCREG_CSSELR;
213 }
214 break;
215 case 4:
216 if (crm == 0) {
217 if (opc2 == 0)
218 return MISCREG_VPIDR;
219 else if (opc2 == 5)
220 return MISCREG_VMPIDR;
221 }
222 break;
223 }
224 break;
225 case 1:
226 if (opc1 == 0) {
227 if (crm == 0) {
228 switch (opc2) {
229 case 0:
230 return MISCREG_SCTLR;
231 case 1:
232 return MISCREG_ACTLR;
233 case 0x2:
234 return MISCREG_CPACR;
235 }
236 } else if (crm == 1) {
237 switch (opc2) {
238 case 0:
239 return MISCREG_SCR;
240 case 1:
241 return MISCREG_SDER;
242 case 2:
243 return MISCREG_NSACR;
244 }
245 }
246 } else if (opc1 == 4) {
247 if (crm == 0) {
248 if (opc2 == 0)
249 return MISCREG_HSCTLR;
250 else if (opc2 == 1)
251 return MISCREG_HACTLR;
252 } else if (crm == 1) {
253 switch (opc2) {
254 case 0:
255 return MISCREG_HCR;
256 case 1:
257 return MISCREG_HDCR;
258 case 2:
259 return MISCREG_HCPTR;
260 case 3:
261 return MISCREG_HSTR;
262 case 7:
263 return MISCREG_HACR;
264 }
265 }
266 }
267 break;
268 case 2:
269 if (opc1 == 0 && crm == 0) {
270 switch (opc2) {
271 case 0:
272 return MISCREG_TTBR0;
273 case 1:
274 return MISCREG_TTBR1;
275 case 2:
276 return MISCREG_TTBCR;
277 }
278 } else if (opc1 == 4) {
279 if (crm == 0 && opc2 == 2)
280 return MISCREG_HTCR;
281 else if (crm == 1 && opc2 == 2)
282 return MISCREG_VTCR;
283 }
284 break;
285 case 3:
286 if (opc1 == 0 && crm == 0 && opc2 == 0) {
287 return MISCREG_DACR;
288 }
289 break;
290 case 5:
291 if (opc1 == 0) {
292 if (crm == 0) {
293 if (opc2 == 0) {
294 return MISCREG_DFSR;
295 } else if (opc2 == 1) {
296 return MISCREG_IFSR;
297 }
298 } else if (crm == 1) {
299 if (opc2 == 0) {
300 return MISCREG_ADFSR;
301 } else if (opc2 == 1) {
302 return MISCREG_AIFSR;
303 }
304 }
305 } else if (opc1 == 4) {
306 if (crm == 1) {
307 if (opc2 == 0)
308 return MISCREG_HADFSR;
309 else if (opc2 == 1)
310 return MISCREG_HAIFSR;
311 } else if (crm == 2 && opc2 == 0) {
312 return MISCREG_HSR;
313 }
314 }
315 break;
316 case 6:
317 if (opc1 == 0 && crm == 0) {
318 switch (opc2) {
319 case 0:
320 return MISCREG_DFAR;
321 case 2:
322 return MISCREG_IFAR;
323 }
324 } else if (opc1 == 4 && crm == 0) {
325 switch (opc2) {
326 case 0:
327 return MISCREG_HDFAR;
328 case 2:
329 return MISCREG_HIFAR;
330 case 4:
331 return MISCREG_HPFAR;
332 }
333 }
334 break;
335 case 7:
336 if (opc1 == 0) {
337 switch (crm) {
338 case 0:
339 if (opc2 == 4) {
340 return MISCREG_NOP;
341 }
342 break;
343 case 1:
344 switch (opc2) {
345 case 0:
346 return MISCREG_ICIALLUIS;
347 case 6:
348 return MISCREG_BPIALLIS;
349 }
350 break;
351 case 4:
352 if (opc2 == 0) {
353 return MISCREG_PAR;
354 }
355 break;
356 case 5:
357 switch (opc2) {
358 case 0:
359 return MISCREG_ICIALLU;
360 case 1:
361 return MISCREG_ICIMVAU;
362 case 4:
363 return MISCREG_CP15ISB;
364 case 6:
365 return MISCREG_BPIALL;
366 case 7:
367 return MISCREG_BPIMVA;
368 }
369 break;
370 case 6:
371 if (opc2 == 1) {
372 return MISCREG_DCIMVAC;
373 } else if (opc2 == 2) {
374 return MISCREG_DCISW;
375 }
376 break;
377 case 8:
378 switch (opc2) {
379 case 0:
380 return MISCREG_ATS1CPR;
381 case 1:
382 return MISCREG_ATS1CPW;
383 case 2:
384 return MISCREG_ATS1CUR;
385 case 3:
386 return MISCREG_ATS1CUW;
387 case 4:
388 return MISCREG_ATS12NSOPR;
389 case 5:
390 return MISCREG_ATS12NSOPW;
391 case 6:
392 return MISCREG_ATS12NSOUR;
393 case 7:
394 return MISCREG_ATS12NSOUW;
395 }
396 break;
397 case 10:
398 switch (opc2) {
399 case 1:
400 return MISCREG_DCCMVAC;
401 case 2:
402 return MISCREG_DCCSW;
403 case 4:
404 return MISCREG_CP15DSB;
405 case 5:
406 return MISCREG_CP15DMB;
407 }
408 break;
409 case 11:
410 if (opc2 == 1) {
411 return MISCREG_DCCMVAU;
412 }
413 break;
414 case 13:
415 if (opc2 == 1) {
416 return MISCREG_NOP;
417 }
418 break;
419 case 14:
420 if (opc2 == 1) {
421 return MISCREG_DCCIMVAC;
422 } else if (opc2 == 2) {
423 return MISCREG_DCCISW;
424 }
425 break;
426 }
427 } else if (opc1 == 4 && crm == 8) {
428 if (opc2 == 0)
429 return MISCREG_ATS1HR;
430 else if (opc2 == 1)
431 return MISCREG_ATS1HW;
432 }
433 break;
434 case 8:
435 if (opc1 == 0) {
436 switch (crm) {
437 case 3:
438 switch (opc2) {
439 case 0:
440 return MISCREG_TLBIALLIS;
441 case 1:
442 return MISCREG_TLBIMVAIS;
443 case 2:
444 return MISCREG_TLBIASIDIS;
445 case 3:
446 return MISCREG_TLBIMVAAIS;
447 case 5:
448 return MISCREG_TLBIMVALIS;
449 case 7:
450 return MISCREG_TLBIMVAALIS;
451 }
452 break;
453 case 5:
454 switch (opc2) {
455 case 0:
456 return MISCREG_ITLBIALL;
457 case 1:
458 return MISCREG_ITLBIMVA;
459 case 2:
460 return MISCREG_ITLBIASID;
461 }
462 break;
463 case 6:
464 switch (opc2) {
465 case 0:
466 return MISCREG_DTLBIALL;
467 case 1:
468 return MISCREG_DTLBIMVA;
469 case 2:
470 return MISCREG_DTLBIASID;
471 }
472 break;
473 case 7:
474 switch (opc2) {
475 case 0:
476 return MISCREG_TLBIALL;
477 case 1:
478 return MISCREG_TLBIMVA;
479 case 2:
480 return MISCREG_TLBIASID;
481 case 3:
482 return MISCREG_TLBIMVAA;
483 case 5:
484 return MISCREG_TLBIMVAL;
485 case 7:
486 return MISCREG_TLBIMVAAL;
487 }
488 break;
489 }
490 } else if (opc1 == 4) {
491 if (crm == 0) {
492 switch (opc2) {
493 case 1:
494 return MISCREG_TLBIIPAS2IS;
495 case 5:
496 return MISCREG_TLBIIPAS2LIS;
497 }
498 } else if (crm == 3) {
499 switch (opc2) {
500 case 0:
501 return MISCREG_TLBIALLHIS;
502 case 1:
503 return MISCREG_TLBIMVAHIS;
504 case 4:
505 return MISCREG_TLBIALLNSNHIS;
506 case 5:
507 return MISCREG_TLBIMVALHIS;
508 }
509 } else if (crm == 4) {
510 switch (opc2) {
511 case 1:
512 return MISCREG_TLBIIPAS2;
513 case 5:
514 return MISCREG_TLBIIPAS2L;
515 }
516 } else if (crm == 7) {
517 switch (opc2) {
518 case 0:
519 return MISCREG_TLBIALLH;
520 case 1:
521 return MISCREG_TLBIMVAH;
522 case 4:
523 return MISCREG_TLBIALLNSNH;
524 case 5:
525 return MISCREG_TLBIMVALH;
526 }
527 }
528 }
529 break;
530 case 9:
531 // Every cop register with CRn = 9 and CRm in
532 // {0-2}, {5-8} is implementation defined regardless
533 // of opc1 and opc2.
534 switch (crm) {
535 case 0:
536 case 1:
537 case 2:
538 case 5:
539 case 6:
540 case 7:
541 case 8:
542 return MISCREG_IMPDEF_UNIMPL;
543 }
544 if (opc1 == 0) {
545 switch (crm) {
546 case 12:
547 switch (opc2) {
548 case 0:
549 return MISCREG_PMCR;
550 case 1:
551 return MISCREG_PMCNTENSET;
552 case 2:
553 return MISCREG_PMCNTENCLR;
554 case 3:
555 return MISCREG_PMOVSR;
556 case 4:
557 return MISCREG_PMSWINC;
558 case 5:
559 return MISCREG_PMSELR;
560 case 6:
561 return MISCREG_PMCEID0;
562 case 7:
563 return MISCREG_PMCEID1;
564 }
565 break;
566 case 13:
567 switch (opc2) {
568 case 0:
569 return MISCREG_PMCCNTR;
570 case 1:
571 // Selector is PMSELR.SEL
572 return MISCREG_PMXEVTYPER_PMCCFILTR;
573 case 2:
574 return MISCREG_PMXEVCNTR;
575 }
576 break;
577 case 14:
578 switch (opc2) {
579 case 0:
580 return MISCREG_PMUSERENR;
581 case 1:
582 return MISCREG_PMINTENSET;
583 case 2:
584 return MISCREG_PMINTENCLR;
585 case 3:
586 return MISCREG_PMOVSSET;
587 }
588 break;
589 }
590 } else if (opc1 == 1) {
591 switch (crm) {
592 case 0:
593 switch (opc2) {
594 case 2: // L2CTLR, L2 Control Register
595 return MISCREG_L2CTLR;
596 case 3:
597 return MISCREG_L2ECTLR;
598 }
599 break;
600 break;
601 }
602 }
603 break;
604 case 10:
605 if (opc1 == 0) {
606 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
607 if (crm < 2) {
608 return MISCREG_IMPDEF_UNIMPL;
609 } else if (crm == 2) { // TEX Remap Registers
610 if (opc2 == 0) {
611 // Selector is TTBCR.EAE
612 return MISCREG_PRRR_MAIR0;
613 } else if (opc2 == 1) {
614 // Selector is TTBCR.EAE
615 return MISCREG_NMRR_MAIR1;
616 }
617 } else if (crm == 3) {
618 if (opc2 == 0) {
619 return MISCREG_AMAIR0;
620 } else if (opc2 == 1) {
621 return MISCREG_AMAIR1;
622 }
623 }
624 } else if (opc1 == 4) {
625 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
626 if (crm == 2) {
627 if (opc2 == 0)
628 return MISCREG_HMAIR0;
629 else if (opc2 == 1)
630 return MISCREG_HMAIR1;
631 } else if (crm == 3) {
632 if (opc2 == 0)
633 return MISCREG_HAMAIR0;
634 else if (opc2 == 1)
635 return MISCREG_HAMAIR1;
636 }
637 }
638 break;
639 case 11:
640 if (opc1 <=7) {
641 switch (crm) {
642 case 0:
643 case 1:
644 case 2:
645 case 3:
646 case 4:
647 case 5:
648 case 6:
649 case 7:
650 case 8:
651 case 15:
652 // Reserved for DMA operations for TCM access
653 return MISCREG_IMPDEF_UNIMPL;
654 default:
655 break;
656 }
657 }
658 break;
659 case 12:
660 if (opc1 == 0) {
661 if (crm == 0) {
662 if (opc2 == 0) {
663 return MISCREG_VBAR;
664 } else if (opc2 == 1) {
665 return MISCREG_MVBAR;
666 }
667 } else if (crm == 1) {
668 if (opc2 == 0) {
669 return MISCREG_ISR;
670 }
671 }
672 } else if (opc1 == 4) {
673 if (crm == 0 && opc2 == 0)
674 return MISCREG_HVBAR;
675 }
676 break;
677 case 13:
678 if (opc1 == 0) {
679 if (crm == 0) {
680 switch (opc2) {
681 case 0:
682 return MISCREG_FCSEIDR;
683 case 1:
684 return MISCREG_CONTEXTIDR;
685 case 2:
686 return MISCREG_TPIDRURW;
687 case 3:
688 return MISCREG_TPIDRURO;
689 case 4:
690 return MISCREG_TPIDRPRW;
691 }
692 }
693 } else if (opc1 == 4) {
694 if (crm == 0 && opc2 == 2)
695 return MISCREG_HTPIDR;
696 }
697 break;
698 case 14:
699 if (opc1 == 0) {
700 switch (crm) {
701 case 0:
702 if (opc2 == 0)
703 return MISCREG_CNTFRQ;
704 break;
705 case 1:
706 if (opc2 == 0)
707 return MISCREG_CNTKCTL;
708 break;
709 case 2:
710 if (opc2 == 0)
711 return MISCREG_CNTP_TVAL;
712 else if (opc2 == 1)
713 return MISCREG_CNTP_CTL;
714 break;
715 case 3:
716 if (opc2 == 0)
717 return MISCREG_CNTV_TVAL;
718 else if (opc2 == 1)
719 return MISCREG_CNTV_CTL;
720 break;
721 }
722 } else if (opc1 == 4) {
723 if (crm == 1 && opc2 == 0) {
724 return MISCREG_CNTHCTL;
725 } else if (crm == 2) {
726 if (opc2 == 0)
727 return MISCREG_CNTHP_TVAL;
728 else if (opc2 == 1)
729 return MISCREG_CNTHP_CTL;
730 }
731 }
732 break;
733 case 15:
734 // Implementation defined
735 return MISCREG_IMPDEF_UNIMPL;
736 }
737 // Unrecognized register
738 return MISCREG_CP15_UNIMPL;
739}
740
741MiscRegIndex
742decodeCP15Reg64(unsigned crm, unsigned opc1)
743{
744 switch (crm) {
745 case 2:
746 switch (opc1) {
747 case 0:
748 return MISCREG_TTBR0;
749 case 1:
750 return MISCREG_TTBR1;
751 case 4:
752 return MISCREG_HTTBR;
753 case 6:
754 return MISCREG_VTTBR;
755 }
756 break;
757 case 7:
758 if (opc1 == 0)
759 return MISCREG_PAR;
760 break;
761 case 14:
762 switch (opc1) {
763 case 0:
764 return MISCREG_CNTPCT;
765 case 1:
766 return MISCREG_CNTVCT;
767 case 2:
768 return MISCREG_CNTP_CVAL;
769 case 3:
770 return MISCREG_CNTV_CVAL;
771 case 4:
772 return MISCREG_CNTVOFF;
773 case 6:
774 return MISCREG_CNTHP_CVAL;
775 }
776 break;
777 case 15:
778 if (opc1 == 0)
779 return MISCREG_CPUMERRSR;
780 else if (opc1 == 1)
781 return MISCREG_L2MERRSR;
782 break;
783 }
784 // Unrecognized register
785 return MISCREG_CP15_UNIMPL;
786}
787
788std::tuple<bool, bool>
789canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
790{
791 bool secure = !scr.ns;
792 bool canRead = false;
793 bool undefined = false;
794
795 switch (cpsr.mode) {
796 case MODE_USER:
797 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
798 miscRegInfo[reg][MISCREG_USR_NS_RD];
799 break;
800 case MODE_FIQ:
801 case MODE_IRQ:
802 case MODE_SVC:
803 case MODE_ABORT:
804 case MODE_UNDEFINED:
805 case MODE_SYSTEM:
806 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
807 miscRegInfo[reg][MISCREG_PRI_NS_RD];
808 break;
809 case MODE_MON:
810 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
811 miscRegInfo[reg][MISCREG_MON_NS1_RD];
812 break;
813 case MODE_HYP:
814 canRead = miscRegInfo[reg][MISCREG_HYP_RD];
815 break;
816 default:
817 undefined = true;
818 }
819 // can't do permissions checkes on the root of a banked pair of regs
820 assert(!miscRegInfo[reg][MISCREG_BANKED]);
821 return std::make_tuple(canRead, undefined);
822}
823
824std::tuple<bool, bool>
825canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
826{
827 bool secure = !scr.ns;
828 bool canWrite = false;
829 bool undefined = false;
830
831 switch (cpsr.mode) {
832 case MODE_USER:
833 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
834 miscRegInfo[reg][MISCREG_USR_NS_WR];
835 break;
836 case MODE_FIQ:
837 case MODE_IRQ:
838 case MODE_SVC:
839 case MODE_ABORT:
840 case MODE_UNDEFINED:
841 case MODE_SYSTEM:
842 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
843 miscRegInfo[reg][MISCREG_PRI_NS_WR];
844 break;
845 case MODE_MON:
846 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
847 miscRegInfo[reg][MISCREG_MON_NS1_WR];
848 break;
849 case MODE_HYP:
850 canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
851 break;
852 default:
853 undefined = true;
854 }
855 // can't do permissions checkes on the root of a banked pair of regs
856 assert(!miscRegInfo[reg][MISCREG_BANKED]);
857 return std::make_tuple(canWrite, undefined);
858}
859
860int
861snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
862{
863 SCR scr = tc->readMiscReg(MISCREG_SCR);
864 return snsBankedIndex(reg, tc, scr.ns);
865}
866
867int
868snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
869{
870 int reg_as_int = static_cast<int>(reg);
871 if (miscRegInfo[reg][MISCREG_BANKED]) {
872 reg_as_int += (ArmSystem::haveSecurity(tc) &&
873 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
874 }
875 return reg_as_int;
876}
877
878
879/**
880 * If the reg is a child reg of a banked set, then the parent is the last
881 * banked one in the list. This is messy, and the wish is to eventually have
882 * the bitmap replaced with a better data structure. the preUnflatten function
883 * initializes a lookup table to speed up the search for these banked
884 * registers.
885 */
886
887int unflattenResultMiscReg[NUM_MISCREGS];
888
889void
890preUnflattenMiscReg()
891{
892 int reg = -1;
893 for (int i = 0 ; i < NUM_MISCREGS; i++){
894 if (miscRegInfo[i][MISCREG_BANKED])
895 reg = i;
896 if (miscRegInfo[i][MISCREG_BANKED_CHILD])
897 unflattenResultMiscReg[i] = reg;
898 else
899 unflattenResultMiscReg[i] = i;
900 // if this assert fails, no parent was found, and something is broken
901 assert(unflattenResultMiscReg[i] > -1);
902 }
903}
904
905int
906unflattenMiscReg(int reg)
907{
908 return unflattenResultMiscReg[reg];
909}
910
911bool
912canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
913{
914 // Check for SP_EL0 access while SPSEL == 0
915 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
916 return false;
917
918 // Check for RVBAR access
919 if (reg == MISCREG_RVBAR_EL1) {
920 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
921 if (highest_el == EL2 || highest_el == EL3)
922 return false;
923 }
924 if (reg == MISCREG_RVBAR_EL2) {
925 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
926 if (highest_el == EL3)
927 return false;
928 }
929
930 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
931
932 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
933 case EL0:
934 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
935 miscRegInfo[reg][MISCREG_USR_NS_RD];
936 case EL1:
937 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
938 miscRegInfo[reg][MISCREG_PRI_NS_RD];
939 case EL2:
940 return miscRegInfo[reg][MISCREG_HYP_RD];
941 case EL3:
942 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
943 miscRegInfo[reg][MISCREG_MON_NS1_RD];
944 default:
945 panic("Invalid exception level");
946 }
947}
948
949bool
950canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
951{
952 // Check for SP_EL0 access while SPSEL == 0
953 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
954 return false;
955 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
956 if (reg == MISCREG_DAIF) {
957 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
958 if (el == EL0 && !sctlr.uma)
959 return false;
960 }
961 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
962 // In syscall-emulation mode, this test is skipped and DCZVA is always
963 // allowed at EL0
964 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
965 if (el == EL0 && !sctlr.dze)
966 return false;
967 }
968 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
969 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
970 if (el == EL0 && !sctlr.uci)
971 return false;
972 }
973
974 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
975
976 switch (el) {
977 case EL0:
978 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
979 miscRegInfo[reg][MISCREG_USR_NS_WR];
980 case EL1:
981 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
982 miscRegInfo[reg][MISCREG_PRI_NS_WR];
983 case EL2:
984 return miscRegInfo[reg][MISCREG_HYP_WR];
985 case EL3:
986 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
987 miscRegInfo[reg][MISCREG_MON_NS1_WR];
988 default:
989 panic("Invalid exception level");
990 }
991}
992
993MiscRegIndex
994decodeAArch64SysReg(unsigned op0, unsigned op1,
995 unsigned crn, unsigned crm,
996 unsigned op2)
997{
998 switch (op0) {
999 case 1:
1000 switch (crn) {
1001 case 7:
1002 switch (op1) {
1003 case 0:
1004 switch (crm) {
1005 case 1:
1006 switch (op2) {
1007 case 0:
1008 return MISCREG_IC_IALLUIS;
1009 }
1010 break;
1011 case 5:
1012 switch (op2) {
1013 case 0:
1014 return MISCREG_IC_IALLU;
1015 }
1016 break;
1017 case 6:
1018 switch (op2) {
1019 case 1:
1020 return MISCREG_DC_IVAC_Xt;
1021 case 2:
1022 return MISCREG_DC_ISW_Xt;
1023 }
1024 break;
1025 case 8:
1026 switch (op2) {
1027 case 0:
1028 return MISCREG_AT_S1E1R_Xt;
1029 case 1:
1030 return MISCREG_AT_S1E1W_Xt;
1031 case 2:
1032 return MISCREG_AT_S1E0R_Xt;
1033 case 3:
1034 return MISCREG_AT_S1E0W_Xt;
1035 }
1036 break;
1037 case 10:
1038 switch (op2) {
1039 case 2:
1040 return MISCREG_DC_CSW_Xt;
1041 }
1042 break;
1043 case 14:
1044 switch (op2) {
1045 case 2:
1046 return MISCREG_DC_CISW_Xt;
1047 }
1048 break;
1049 }
1050 break;
1051 case 3:
1052 switch (crm) {
1053 case 4:
1054 switch (op2) {
1055 case 1:
1056 return MISCREG_DC_ZVA_Xt;
1057 }
1058 break;
1059 case 5:
1060 switch (op2) {
1061 case 1:
1062 return MISCREG_IC_IVAU_Xt;
1063 }
1064 break;
1065 case 10:
1066 switch (op2) {
1067 case 1:
1068 return MISCREG_DC_CVAC_Xt;
1069 }
1070 break;
1071 case 11:
1072 switch (op2) {
1073 case 1:
1074 return MISCREG_DC_CVAU_Xt;
1075 }
1076 break;
1077 case 14:
1078 switch (op2) {
1079 case 1:
1080 return MISCREG_DC_CIVAC_Xt;
1081 }
1082 break;
1083 }
1084 break;
1085 case 4:
1086 switch (crm) {
1087 case 8:
1088 switch (op2) {
1089 case 0:
1090 return MISCREG_AT_S1E2R_Xt;
1091 case 1:
1092 return MISCREG_AT_S1E2W_Xt;
1093 case 4:
1094 return MISCREG_AT_S12E1R_Xt;
1095 case 5:
1096 return MISCREG_AT_S12E1W_Xt;
1097 case 6:
1098 return MISCREG_AT_S12E0R_Xt;
1099 case 7:
1100 return MISCREG_AT_S12E0W_Xt;
1101 }
1102 break;
1103 }
1104 break;
1105 case 6:
1106 switch (crm) {
1107 case 8:
1108 switch (op2) {
1109 case 0:
1110 return MISCREG_AT_S1E3R_Xt;
1111 case 1:
1112 return MISCREG_AT_S1E3W_Xt;
1113 }
1114 break;
1115 }
1116 break;
1117 }
1118 break;
1119 case 8:
1120 switch (op1) {
1121 case 0:
1122 switch (crm) {
1123 case 3:
1124 switch (op2) {
1125 case 0:
1126 return MISCREG_TLBI_VMALLE1IS;
1127 case 1:
1128 return MISCREG_TLBI_VAE1IS_Xt;
1129 case 2:
1130 return MISCREG_TLBI_ASIDE1IS_Xt;
1131 case 3:
1132 return MISCREG_TLBI_VAAE1IS_Xt;
1133 case 5:
1134 return MISCREG_TLBI_VALE1IS_Xt;
1135 case 7:
1136 return MISCREG_TLBI_VAALE1IS_Xt;
1137 }
1138 break;
1139 case 7:
1140 switch (op2) {
1141 case 0:
1142 return MISCREG_TLBI_VMALLE1;
1143 case 1:
1144 return MISCREG_TLBI_VAE1_Xt;
1145 case 2:
1146 return MISCREG_TLBI_ASIDE1_Xt;
1147 case 3:
1148 return MISCREG_TLBI_VAAE1_Xt;
1149 case 5:
1150 return MISCREG_TLBI_VALE1_Xt;
1151 case 7:
1152 return MISCREG_TLBI_VAALE1_Xt;
1153 }
1154 break;
1155 }
1156 break;
1157 case 4:
1158 switch (crm) {
1159 case 0:
1160 switch (op2) {
1161 case 1:
1162 return MISCREG_TLBI_IPAS2E1IS_Xt;
1163 case 5:
1164 return MISCREG_TLBI_IPAS2LE1IS_Xt;
1165 }
1166 break;
1167 case 3:
1168 switch (op2) {
1169 case 0:
1170 return MISCREG_TLBI_ALLE2IS;
1171 case 1:
1172 return MISCREG_TLBI_VAE2IS_Xt;
1173 case 4:
1174 return MISCREG_TLBI_ALLE1IS;
1175 case 5:
1176 return MISCREG_TLBI_VALE2IS_Xt;
1177 case 6:
1178 return MISCREG_TLBI_VMALLS12E1IS;
1179 }
1180 break;
1181 case 4:
1182 switch (op2) {
1183 case 1:
1184 return MISCREG_TLBI_IPAS2E1_Xt;
1185 case 5:
1186 return MISCREG_TLBI_IPAS2LE1_Xt;
1187 }
1188 break;
1189 case 7:
1190 switch (op2) {
1191 case 0:
1192 return MISCREG_TLBI_ALLE2;
1193 case 1:
1194 return MISCREG_TLBI_VAE2_Xt;
1195 case 4:
1196 return MISCREG_TLBI_ALLE1;
1197 case 5:
1198 return MISCREG_TLBI_VALE2_Xt;
1199 case 6:
1200 return MISCREG_TLBI_VMALLS12E1;
1201 }
1202 break;
1203 }
1204 break;
1205 case 6:
1206 switch (crm) {
1207 case 3:
1208 switch (op2) {
1209 case 0:
1210 return MISCREG_TLBI_ALLE3IS;
1211 case 1:
1212 return MISCREG_TLBI_VAE3IS_Xt;
1213 case 5:
1214 return MISCREG_TLBI_VALE3IS_Xt;
1215 }
1216 break;
1217 case 7:
1218 switch (op2) {
1219 case 0:
1220 return MISCREG_TLBI_ALLE3;
1221 case 1:
1222 return MISCREG_TLBI_VAE3_Xt;
1223 case 5:
1224 return MISCREG_TLBI_VALE3_Xt;
1225 }
1226 break;
1227 }
1228 break;
1229 }
1230 break;
1231 case 11:
1232 case 15:
1233 // SYS Instruction with CRn = { 11, 15 }
1234 // (Trappable by HCR_EL2.TIDCP)
1235 return MISCREG_IMPDEF_UNIMPL;
1236 }
1237 break;
1238 case 2:
1239 switch (crn) {
1240 case 0:
1241 switch (op1) {
1242 case 0:
1243 switch (crm) {
1244 case 0:
1245 switch (op2) {
1246 case 2:
1247 return MISCREG_OSDTRRX_EL1;
1248 case 4:
1249 return MISCREG_DBGBVR0_EL1;
1250 case 5:
1251 return MISCREG_DBGBCR0_EL1;
1252 case 6:
1253 return MISCREG_DBGWVR0_EL1;
1254 case 7:
1255 return MISCREG_DBGWCR0_EL1;
1256 }
1257 break;
1258 case 1:
1259 switch (op2) {
1260 case 4:
1261 return MISCREG_DBGBVR1_EL1;
1262 case 5:
1263 return MISCREG_DBGBCR1_EL1;
1264 case 6:
1265 return MISCREG_DBGWVR1_EL1;
1266 case 7:
1267 return MISCREG_DBGWCR1_EL1;
1268 }
1269 break;
1270 case 2:
1271 switch (op2) {
1272 case 0:
1273 return MISCREG_MDCCINT_EL1;
1274 case 2:
1275 return MISCREG_MDSCR_EL1;
1276 case 4:
1277 return MISCREG_DBGBVR2_EL1;
1278 case 5:
1279 return MISCREG_DBGBCR2_EL1;
1280 case 6:
1281 return MISCREG_DBGWVR2_EL1;
1282 case 7:
1283 return MISCREG_DBGWCR2_EL1;
1284 }
1285 break;
1286 case 3:
1287 switch (op2) {
1288 case 2:
1289 return MISCREG_OSDTRTX_EL1;
1290 case 4:
1291 return MISCREG_DBGBVR3_EL1;
1292 case 5:
1293 return MISCREG_DBGBCR3_EL1;
1294 case 6:
1295 return MISCREG_DBGWVR3_EL1;
1296 case 7:
1297 return MISCREG_DBGWCR3_EL1;
1298 }
1299 break;
1300 case 4:
1301 switch (op2) {
1302 case 4:
1303 return MISCREG_DBGBVR4_EL1;
1304 case 5:
1305 return MISCREG_DBGBCR4_EL1;
1306 }
1307 break;
1308 case 5:
1309 switch (op2) {
1310 case 4:
1311 return MISCREG_DBGBVR5_EL1;
1312 case 5:
1313 return MISCREG_DBGBCR5_EL1;
1314 }
1315 break;
1316 case 6:
1317 switch (op2) {
1318 case 2:
1319 return MISCREG_OSECCR_EL1;
1320 }
1321 break;
1322 }
1323 break;
1324 case 2:
1325 switch (crm) {
1326 case 0:
1327 switch (op2) {
1328 case 0:
1329 return MISCREG_TEECR32_EL1;
1330 }
1331 break;
1332 }
1333 break;
1334 case 3:
1335 switch (crm) {
1336 case 1:
1337 switch (op2) {
1338 case 0:
1339 return MISCREG_MDCCSR_EL0;
1340 }
1341 break;
1342 case 4:
1343 switch (op2) {
1344 case 0:
1345 return MISCREG_MDDTR_EL0;
1346 }
1347 break;
1348 case 5:
1349 switch (op2) {
1350 case 0:
1351 return MISCREG_MDDTRRX_EL0;
1352 }
1353 break;
1354 }
1355 break;
1356 case 4:
1357 switch (crm) {
1358 case 7:
1359 switch (op2) {
1360 case 0:
1361 return MISCREG_DBGVCR32_EL2;
1362 }
1363 break;
1364 }
1365 break;
1366 }
1367 break;
1368 case 1:
1369 switch (op1) {
1370 case 0:
1371 switch (crm) {
1372 case 0:
1373 switch (op2) {
1374 case 0:
1375 return MISCREG_MDRAR_EL1;
1376 case 4:
1377 return MISCREG_OSLAR_EL1;
1378 }
1379 break;
1380 case 1:
1381 switch (op2) {
1382 case 4:
1383 return MISCREG_OSLSR_EL1;
1384 }
1385 break;
1386 case 3:
1387 switch (op2) {
1388 case 4:
1389 return MISCREG_OSDLR_EL1;
1390 }
1391 break;
1392 case 4:
1393 switch (op2) {
1394 case 4:
1395 return MISCREG_DBGPRCR_EL1;
1396 }
1397 break;
1398 }
1399 break;
1400 case 2:
1401 switch (crm) {
1402 case 0:
1403 switch (op2) {
1404 case 0:
1405 return MISCREG_TEEHBR32_EL1;
1406 }
1407 break;
1408 }
1409 break;
1410 }
1411 break;
1412 case 7:
1413 switch (op1) {
1414 case 0:
1415 switch (crm) {
1416 case 8:
1417 switch (op2) {
1418 case 6:
1419 return MISCREG_DBGCLAIMSET_EL1;
1420 }
1421 break;
1422 case 9:
1423 switch (op2) {
1424 case 6:
1425 return MISCREG_DBGCLAIMCLR_EL1;
1426 }
1427 break;
1428 case 14:
1429 switch (op2) {
1430 case 6:
1431 return MISCREG_DBGAUTHSTATUS_EL1;
1432 }
1433 break;
1434 }
1435 break;
1436 }
1437 break;
1438 }
1439 break;
1440 case 3:
1441 switch (crn) {
1442 case 0:
1443 switch (op1) {
1444 case 0:
1445 switch (crm) {
1446 case 0:
1447 switch (op2) {
1448 case 0:
1449 return MISCREG_MIDR_EL1;
1450 case 5:
1451 return MISCREG_MPIDR_EL1;
1452 case 6:
1453 return MISCREG_REVIDR_EL1;
1454 }
1455 break;
1456 case 1:
1457 switch (op2) {
1458 case 0:
1459 return MISCREG_ID_PFR0_EL1;
1460 case 1:
1461 return MISCREG_ID_PFR1_EL1;
1462 case 2:
1463 return MISCREG_ID_DFR0_EL1;
1464 case 3:
1465 return MISCREG_ID_AFR0_EL1;
1466 case 4:
1467 return MISCREG_ID_MMFR0_EL1;
1468 case 5:
1469 return MISCREG_ID_MMFR1_EL1;
1470 case 6:
1471 return MISCREG_ID_MMFR2_EL1;
1472 case 7:
1473 return MISCREG_ID_MMFR3_EL1;
1474 }
1475 break;
1476 case 2:
1477 switch (op2) {
1478 case 0:
1479 return MISCREG_ID_ISAR0_EL1;
1480 case 1:
1481 return MISCREG_ID_ISAR1_EL1;
1482 case 2:
1483 return MISCREG_ID_ISAR2_EL1;
1484 case 3:
1485 return MISCREG_ID_ISAR3_EL1;
1486 case 4:
1487 return MISCREG_ID_ISAR4_EL1;
1488 case 5:
1489 return MISCREG_ID_ISAR5_EL1;
1490 }
1491 break;
1492 case 3:
1493 switch (op2) {
1494 case 0:
1495 return MISCREG_MVFR0_EL1;
1496 case 1:
1497 return MISCREG_MVFR1_EL1;
1498 case 2:
1499 return MISCREG_MVFR2_EL1;
1500 case 3 ... 7:
1501 return MISCREG_RAZ;
1502 }
1503 break;
1504 case 4:
1505 switch (op2) {
1506 case 0:
1507 return MISCREG_ID_AA64PFR0_EL1;
1508 case 1:
1509 return MISCREG_ID_AA64PFR1_EL1;
1510 case 2 ... 7:
1511 return MISCREG_RAZ;
1512 }
1513 break;
1514 case 5:
1515 switch (op2) {
1516 case 0:
1517 return MISCREG_ID_AA64DFR0_EL1;
1518 case 1:
1519 return MISCREG_ID_AA64DFR1_EL1;
1520 case 4:
1521 return MISCREG_ID_AA64AFR0_EL1;
1522 case 5:
1523 return MISCREG_ID_AA64AFR1_EL1;
1524 case 2:
1525 case 3:
1526 case 6:
1527 case 7:
1528 return MISCREG_RAZ;
1529 }
1530 break;
1531 case 6:
1532 switch (op2) {
1533 case 0:
1534 return MISCREG_ID_AA64ISAR0_EL1;
1535 case 1:
1536 return MISCREG_ID_AA64ISAR1_EL1;
1537 case 2 ... 7:
1538 return MISCREG_RAZ;
1539 }
1540 break;
1541 case 7:
1542 switch (op2) {
1543 case 0:
1544 return MISCREG_ID_AA64MMFR0_EL1;
1545 case 1:
1546 return MISCREG_ID_AA64MMFR1_EL1;
1547 case 2:
1548 return MISCREG_ID_AA64MMFR2_EL1;
1549 case 3 ... 7:
1550 return MISCREG_RAZ;
1551 }
1552 break;
1553 }
1554 break;
1555 case 1:
1556 switch (crm) {
1557 case 0:
1558 switch (op2) {
1559 case 0:
1560 return MISCREG_CCSIDR_EL1;
1561 case 1:
1562 return MISCREG_CLIDR_EL1;
1563 case 7:
1564 return MISCREG_AIDR_EL1;
1565 }
1566 break;
1567 }
1568 break;
1569 case 2:
1570 switch (crm) {
1571 case 0:
1572 switch (op2) {
1573 case 0:
1574 return MISCREG_CSSELR_EL1;
1575 }
1576 break;
1577 }
1578 break;
1579 case 3:
1580 switch (crm) {
1581 case 0:
1582 switch (op2) {
1583 case 1:
1584 return MISCREG_CTR_EL0;
1585 case 7:
1586 return MISCREG_DCZID_EL0;
1587 }
1588 break;
1589 }
1590 break;
1591 case 4:
1592 switch (crm) {
1593 case 0:
1594 switch (op2) {
1595 case 0:
1596 return MISCREG_VPIDR_EL2;
1597 case 5:
1598 return MISCREG_VMPIDR_EL2;
1599 }
1600 break;
1601 }
1602 break;
1603 }
1604 break;
1605 case 1:
1606 switch (op1) {
1607 case 0:
1608 switch (crm) {
1609 case 0:
1610 switch (op2) {
1611 case 0:
1612 return MISCREG_SCTLR_EL1;
1613 case 1:
1614 return MISCREG_ACTLR_EL1;
1615 case 2:
1616 return MISCREG_CPACR_EL1;
1617 }
1618 break;
1619 }
1620 break;
1621 case 4:
1622 switch (crm) {
1623 case 0:
1624 switch (op2) {
1625 case 0:
1626 return MISCREG_SCTLR_EL2;
1627 case 1:
1628 return MISCREG_ACTLR_EL2;
1629 }
1630 break;
1631 case 1:
1632 switch (op2) {
1633 case 0:
1634 return MISCREG_HCR_EL2;
1635 case 1:
1636 return MISCREG_MDCR_EL2;
1637 case 2:
1638 return MISCREG_CPTR_EL2;
1639 case 3:
1640 return MISCREG_HSTR_EL2;
1641 case 7:
1642 return MISCREG_HACR_EL2;
1643 }
1644 break;
1645 }
1646 break;
1647 case 6:
1648 switch (crm) {
1649 case 0:
1650 switch (op2) {
1651 case 0:
1652 return MISCREG_SCTLR_EL3;
1653 case 1:
1654 return MISCREG_ACTLR_EL3;
1655 }
1656 break;
1657 case 1:
1658 switch (op2) {
1659 case 0:
1660 return MISCREG_SCR_EL3;
1661 case 1:
1662 return MISCREG_SDER32_EL3;
1663 case 2:
1664 return MISCREG_CPTR_EL3;
1665 }
1666 break;
1667 case 3:
1668 switch (op2) {
1669 case 1:
1670 return MISCREG_MDCR_EL3;
1671 }
1672 break;
1673 }
1674 break;
1675 }
1676 break;
1677 case 2:
1678 switch (op1) {
1679 case 0:
1680 switch (crm) {
1681 case 0:
1682 switch (op2) {
1683 case 0:
1684 return MISCREG_TTBR0_EL1;
1685 case 1:
1686 return MISCREG_TTBR1_EL1;
1687 case 2:
1688 return MISCREG_TCR_EL1;
1689 }
1690 break;
1691 }
1692 break;
1693 case 4:
1694 switch (crm) {
1695 case 0:
1696 switch (op2) {
1697 case 0:
1698 return MISCREG_TTBR0_EL2;
1699 case 1:
1700 return MISCREG_TTBR1_EL2;
1701 case 2:
1702 return MISCREG_TCR_EL2;
1703 }
1704 break;
1705 case 1:
1706 switch (op2) {
1707 case 0:
1708 return MISCREG_VTTBR_EL2;
1709 case 2:
1710 return MISCREG_VTCR_EL2;
1711 }
1712 break;
1713 }
1714 break;
1715 case 6:
1716 switch (crm) {
1717 case 0:
1718 switch (op2) {
1719 case 0:
1720 return MISCREG_TTBR0_EL3;
1721 case 2:
1722 return MISCREG_TCR_EL3;
1723 }
1724 break;
1725 }
1726 break;
1727 }
1728 break;
1729 case 3:
1730 switch (op1) {
1731 case 4:
1732 switch (crm) {
1733 case 0:
1734 switch (op2) {
1735 case 0:
1736 return MISCREG_DACR32_EL2;
1737 }
1738 break;
1739 }
1740 break;
1741 }
1742 break;
1743 case 4:
1744 switch (op1) {
1745 case 0:
1746 switch (crm) {
1747 case 0:
1748 switch (op2) {
1749 case 0:
1750 return MISCREG_SPSR_EL1;
1751 case 1:
1752 return MISCREG_ELR_EL1;
1753 }
1754 break;
1755 case 1:
1756 switch (op2) {
1757 case 0:
1758 return MISCREG_SP_EL0;
1759 }
1760 break;
1761 case 2:
1762 switch (op2) {
1763 case 0:
1764 return MISCREG_SPSEL;
1765 case 2:
1766 return MISCREG_CURRENTEL;
1767 }
1768 break;
1769 }
1770 break;
1771 case 3:
1772 switch (crm) {
1773 case 2:
1774 switch (op2) {
1775 case 0:
1776 return MISCREG_NZCV;
1777 case 1:
1778 return MISCREG_DAIF;
1779 }
1780 break;
1781 case 4:
1782 switch (op2) {
1783 case 0:
1784 return MISCREG_FPCR;
1785 case 1:
1786 return MISCREG_FPSR;
1787 }
1788 break;
1789 case 5:
1790 switch (op2) {
1791 case 0:
1792 return MISCREG_DSPSR_EL0;
1793 case 1:
1794 return MISCREG_DLR_EL0;
1795 }
1796 break;
1797 }
1798 break;
1799 case 4:
1800 switch (crm) {
1801 case 0:
1802 switch (op2) {
1803 case 0:
1804 return MISCREG_SPSR_EL2;
1805 case 1:
1806 return MISCREG_ELR_EL2;
1807 }
1808 break;
1809 case 1:
1810 switch (op2) {
1811 case 0:
1812 return MISCREG_SP_EL1;
1813 }
1814 break;
1815 case 3:
1816 switch (op2) {
1817 case 0:
1818 return MISCREG_SPSR_IRQ_AA64;
1819 case 1:
1820 return MISCREG_SPSR_ABT_AA64;
1821 case 2:
1822 return MISCREG_SPSR_UND_AA64;
1823 case 3:
1824 return MISCREG_SPSR_FIQ_AA64;
1825 }
1826 break;
1827 }
1828 break;
1829 case 6:
1830 switch (crm) {
1831 case 0:
1832 switch (op2) {
1833 case 0:
1834 return MISCREG_SPSR_EL3;
1835 case 1:
1836 return MISCREG_ELR_EL3;
1837 }
1838 break;
1839 case 1:
1840 switch (op2) {
1841 case 0:
1842 return MISCREG_SP_EL2;
1843 }
1844 break;
1845 }
1846 break;
1847 }
1848 break;
1849 case 5:
1850 switch (op1) {
1851 case 0:
1852 switch (crm) {
1853 case 1:
1854 switch (op2) {
1855 case 0:
1856 return MISCREG_AFSR0_EL1;
1857 case 1:
1858 return MISCREG_AFSR1_EL1;
1859 }
1860 break;
1861 case 2:
1862 switch (op2) {
1863 case 0:
1864 return MISCREG_ESR_EL1;
1865 }
1866 break;
1867 case 3:
1868 switch (op2) {
1869 case 0:
1870 return MISCREG_ERRIDR_EL1;
1871 case 1:
1872 return MISCREG_ERRSELR_EL1;
1873 }
1874 break;
1875 case 4:
1876 switch (op2) {
1877 case 0:
1878 return MISCREG_ERXFR_EL1;
1879 case 1:
1880 return MISCREG_ERXCTLR_EL1;
1881 case 2:
1882 return MISCREG_ERXSTATUS_EL1;
1883 case 3:
1884 return MISCREG_ERXADDR_EL1;
1885 }
1886 break;
1887 case 5:
1888 switch (op2) {
1889 case 0:
1890 return MISCREG_ERXMISC0_EL1;
1891 case 1:
1892 return MISCREG_ERXMISC1_EL1;
1893 }
1894 break;
1895 }
1896 break;
1897 case 4:
1898 switch (crm) {
1899 case 0:
1900 switch (op2) {
1901 case 1:
1902 return MISCREG_IFSR32_EL2;
1903 }
1904 break;
1905 case 1:
1906 switch (op2) {
1907 case 0:
1908 return MISCREG_AFSR0_EL2;
1909 case 1:
1910 return MISCREG_AFSR1_EL2;
1911 }
1912 break;
1913 case 2:
1914 switch (op2) {
1915 case 0:
1916 return MISCREG_ESR_EL2;
1917 case 3:
1918 return MISCREG_VSESR_EL2;
1919 }
1920 break;
1921 case 3:
1922 switch (op2) {
1923 case 0:
1924 return MISCREG_FPEXC32_EL2;
1925 }
1926 break;
1927 }
1928 break;
1929 case 6:
1930 switch (crm) {
1931 case 1:
1932 switch (op2) {
1933 case 0:
1934 return MISCREG_AFSR0_EL3;
1935 case 1:
1936 return MISCREG_AFSR1_EL3;
1937 }
1938 break;
1939 case 2:
1940 switch (op2) {
1941 case 0:
1942 return MISCREG_ESR_EL3;
1943 }
1944 break;
1945 }
1946 break;
1947 }
1948 break;
1949 case 6:
1950 switch (op1) {
1951 case 0:
1952 switch (crm) {
1953 case 0:
1954 switch (op2) {
1955 case 0:
1956 return MISCREG_FAR_EL1;
1957 }
1958 break;
1959 }
1960 break;
1961 case 4:
1962 switch (crm) {
1963 case 0:
1964 switch (op2) {
1965 case 0:
1966 return MISCREG_FAR_EL2;
1967 case 4:
1968 return MISCREG_HPFAR_EL2;
1969 }
1970 break;
1971 }
1972 break;
1973 case 6:
1974 switch (crm) {
1975 case 0:
1976 switch (op2) {
1977 case 0:
1978 return MISCREG_FAR_EL3;
1979 }
1980 break;
1981 }
1982 break;
1983 }
1984 break;
1985 case 7:
1986 switch (op1) {
1987 case 0:
1988 switch (crm) {
1989 case 4:
1990 switch (op2) {
1991 case 0:
1992 return MISCREG_PAR_EL1;
1993 }
1994 break;
1995 }
1996 break;
1997 }
1998 break;
1999 case 9:
2000 switch (op1) {
2001 case 0:
2002 switch (crm) {
2003 case 14:
2004 switch (op2) {
2005 case 1:
2006 return MISCREG_PMINTENSET_EL1;
2007 case 2:
2008 return MISCREG_PMINTENCLR_EL1;
2009 }
2010 break;
2011 }
2012 break;
2013 case 3:
2014 switch (crm) {
2015 case 12:
2016 switch (op2) {
2017 case 0:
2018 return MISCREG_PMCR_EL0;
2019 case 1:
2020 return MISCREG_PMCNTENSET_EL0;
2021 case 2:
2022 return MISCREG_PMCNTENCLR_EL0;
2023 case 3:
2024 return MISCREG_PMOVSCLR_EL0;
2025 case 4:
2026 return MISCREG_PMSWINC_EL0;
2027 case 5:
2028 return MISCREG_PMSELR_EL0;
2029 case 6:
2030 return MISCREG_PMCEID0_EL0;
2031 case 7:
2032 return MISCREG_PMCEID1_EL0;
2033 }
2034 break;
2035 case 13:
2036 switch (op2) {
2037 case 0:
2038 return MISCREG_PMCCNTR_EL0;
2039 case 1:
2040 return MISCREG_PMXEVTYPER_EL0;
2041 case 2:
2042 return MISCREG_PMXEVCNTR_EL0;
2043 }
2044 break;
2045 case 14:
2046 switch (op2) {
2047 case 0:
2048 return MISCREG_PMUSERENR_EL0;
2049 case 3:
2050 return MISCREG_PMOVSSET_EL0;
2051 }
2052 break;
2053 }
2054 break;
2055 }
2056 break;
2057 case 10:
2058 switch (op1) {
2059 case 0:
2060 switch (crm) {
2061 case 2:
2062 switch (op2) {
2063 case 0:
2064 return MISCREG_MAIR_EL1;
2065 }
2066 break;
2067 case 3:
2068 switch (op2) {
2069 case 0:
2070 return MISCREG_AMAIR_EL1;
2071 }
2072 break;
2073 }
2074 break;
2075 case 4:
2076 switch (crm) {
2077 case 2:
2078 switch (op2) {
2079 case 0:
2080 return MISCREG_MAIR_EL2;
2081 }
2082 break;
2083 case 3:
2084 switch (op2) {
2085 case 0:
2086 return MISCREG_AMAIR_EL2;
2087 }
2088 break;
2089 }
2090 break;
2091 case 6:
2092 switch (crm) {
2093 case 2:
2094 switch (op2) {
2095 case 0:
2096 return MISCREG_MAIR_EL3;
2097 }
2098 break;
2099 case 3:
2100 switch (op2) {
2101 case 0:
2102 return MISCREG_AMAIR_EL3;
2103 }
2104 break;
2105 }
2106 break;
2107 }
2108 break;
2109 case 11:
2110 switch (op1) {
2111 case 1:
2112 switch (crm) {
2113 case 0:
2114 switch (op2) {
2115 case 2:
2116 return MISCREG_L2CTLR_EL1;
2117 case 3:
2118 return MISCREG_L2ECTLR_EL1;
2119 }
2120 break;
2121 }
2122 M5_FALLTHROUGH;
2123 default:
2124 // S3_<op1>_11_<Cm>_<op2>
2125 return MISCREG_IMPDEF_UNIMPL;
2126 }
2127 M5_UNREACHABLE;
2128 case 12:
2129 switch (op1) {
2130 case 0:
2131 switch (crm) {
2132 case 0:
2133 switch (op2) {
2134 case 0:
2135 return MISCREG_VBAR_EL1;
2136 case 1:
2137 return MISCREG_RVBAR_EL1;
2138 }
2139 break;
2140 case 1:
2141 switch (op2) {
2142 case 0:
2143 return MISCREG_ISR_EL1;
2144 case 1:
2145 return MISCREG_DISR_EL1;
2146 }
2147 break;
2148 }
2149 break;
2150 case 4:
2151 switch (crm) {
2152 case 0:
2153 switch (op2) {
2154 case 0:
2155 return MISCREG_VBAR_EL2;
2156 case 1:
2157 return MISCREG_RVBAR_EL2;
2158 }
2159 break;
2160 case 1:
2161 switch (op2) {
2162 case 1:
2163 return MISCREG_VDISR_EL2;
2164 }
2165 break;
2166 }
2167 break;
2168 case 6:
2169 switch (crm) {
2170 case 0:
2171 switch (op2) {
2172 case 0:
2173 return MISCREG_VBAR_EL3;
2174 case 1:
2175 return MISCREG_RVBAR_EL3;
2176 case 2:
2177 return MISCREG_RMR_EL3;
2178 }
2179 break;
2180 }
2181 break;
2182 }
2183 break;
2184 case 13:
2185 switch (op1) {
2186 case 0:
2187 switch (crm) {
2188 case 0:
2189 switch (op2) {
2190 case 1:
2191 return MISCREG_CONTEXTIDR_EL1;
2192 case 4:
2193 return MISCREG_TPIDR_EL1;
2194 }
2195 break;
2196 }
2197 break;
2198 case 3:
2199 switch (crm) {
2200 case 0:
2201 switch (op2) {
2202 case 2:
2203 return MISCREG_TPIDR_EL0;
2204 case 3:
2205 return MISCREG_TPIDRRO_EL0;
2206 }
2207 break;
2208 }
2209 break;
2210 case 4:
2211 switch (crm) {
2212 case 0:
2213 switch (op2) {
2214 case 1:
2215 return MISCREG_CONTEXTIDR_EL2;
2216 case 2:
2217 return MISCREG_TPIDR_EL2;
2218 }
2219 break;
2220 }
2221 break;
2222 case 6:
2223 switch (crm) {
2224 case 0:
2225 switch (op2) {
2226 case 2:
2227 return MISCREG_TPIDR_EL3;
2228 }
2229 break;
2230 }
2231 break;
2232 }
2233 break;
2234 case 14:
2235 switch (op1) {
2236 case 0:
2237 switch (crm) {
2238 case 1:
2239 switch (op2) {
2240 case 0:
2241 return MISCREG_CNTKCTL_EL1;
2242 }
2243 break;
2244 }
2245 break;
2246 case 3:
2247 switch (crm) {
2248 case 0:
2249 switch (op2) {
2250 case 0:
2251 return MISCREG_CNTFRQ_EL0;
2252 case 1:
2253 return MISCREG_CNTPCT_EL0;
2254 case 2:
2255 return MISCREG_CNTVCT_EL0;
2256 }
2257 break;
2258 case 2:
2259 switch (op2) {
2260 case 0:
2261 return MISCREG_CNTP_TVAL_EL0;
2262 case 1:
2263 return MISCREG_CNTP_CTL_EL0;
2264 case 2:
2265 return MISCREG_CNTP_CVAL_EL0;
2266 }
2267 break;
2268 case 3:
2269 switch (op2) {
2270 case 0:
2271 return MISCREG_CNTV_TVAL_EL0;
2272 case 1:
2273 return MISCREG_CNTV_CTL_EL0;
2274 case 2:
2275 return MISCREG_CNTV_CVAL_EL0;
2276 }
2277 break;
2278 case 8:
2279 switch (op2) {
2280 case 0:
2281 return MISCREG_PMEVCNTR0_EL0;
2282 case 1:
2283 return MISCREG_PMEVCNTR1_EL0;
2284 case 2:
2285 return MISCREG_PMEVCNTR2_EL0;
2286 case 3:
2287 return MISCREG_PMEVCNTR3_EL0;
2288 case 4:
2289 return MISCREG_PMEVCNTR4_EL0;
2290 case 5:
2291 return MISCREG_PMEVCNTR5_EL0;
2292 }
2293 break;
2294 case 12:
2295 switch (op2) {
2296 case 0:
2297 return MISCREG_PMEVTYPER0_EL0;
2298 case 1:
2299 return MISCREG_PMEVTYPER1_EL0;
2300 case 2:
2301 return MISCREG_PMEVTYPER2_EL0;
2302 case 3:
2303 return MISCREG_PMEVTYPER3_EL0;
2304 case 4:
2305 return MISCREG_PMEVTYPER4_EL0;
2306 case 5:
2307 return MISCREG_PMEVTYPER5_EL0;
2308 }
2309 break;
2310 case 15:
2311 switch (op2) {
2312 case 7:
2313 return MISCREG_PMCCFILTR_EL0;
2314 }
2315 }
2316 break;
2317 case 4:
2318 switch (crm) {
2319 case 0:
2320 switch (op2) {
2321 case 3:
2322 return MISCREG_CNTVOFF_EL2;
2323 }
2324 break;
2325 case 1:
2326 switch (op2) {
2327 case 0:
2328 return MISCREG_CNTHCTL_EL2;
2329 }
2330 break;
2331 case 2:
2332 switch (op2) {
2333 case 0:
2334 return MISCREG_CNTHP_TVAL_EL2;
2335 case 1:
2336 return MISCREG_CNTHP_CTL_EL2;
2337 case 2:
2338 return MISCREG_CNTHP_CVAL_EL2;
2339 }
2340 break;
2341 case 3:
2342 switch (op2) {
2343 case 0:
2344 return MISCREG_CNTHV_TVAL_EL2;
2345 case 1:
2346 return MISCREG_CNTHV_CTL_EL2;
2347 case 2:
2348 return MISCREG_CNTHV_CVAL_EL2;
2349 }
2350 break;
2351 }
2352 break;
2353 case 7:
2354 switch (crm) {
2355 case 2:
2356 switch (op2) {
2357 case 0:
2358 return MISCREG_CNTPS_TVAL_EL1;
2359 case 1:
2360 return MISCREG_CNTPS_CTL_EL1;
2361 case 2:
2362 return MISCREG_CNTPS_CVAL_EL1;
2363 }
2364 break;
2365 }
2366 break;
2367 }
2368 break;
2369 case 15:
2370 switch (op1) {
2371 case 0:
2372 switch (crm) {
2373 case 0:
2374 switch (op2) {
2375 case 0:
2376 return MISCREG_IL1DATA0_EL1;
2377 case 1:
2378 return MISCREG_IL1DATA1_EL1;
2379 case 2:
2380 return MISCREG_IL1DATA2_EL1;
2381 case 3:
2382 return MISCREG_IL1DATA3_EL1;
2383 }
2384 break;
2385 case 1:
2386 switch (op2) {
2387 case 0:
2388 return MISCREG_DL1DATA0_EL1;
2389 case 1:
2390 return MISCREG_DL1DATA1_EL1;
2391 case 2:
2392 return MISCREG_DL1DATA2_EL1;
2393 case 3:
2394 return MISCREG_DL1DATA3_EL1;
2395 case 4:
2396 return MISCREG_DL1DATA4_EL1;
2397 }
2398 break;
2399 }
2400 break;
2401 case 1:
2402 switch (crm) {
2403 case 0:
2404 switch (op2) {
2405 case 0:
2406 return MISCREG_L2ACTLR_EL1;
2407 }
2408 break;
2409 case 2:
2410 switch (op2) {
2411 case 0:
2412 return MISCREG_CPUACTLR_EL1;
2413 case 1:
2414 return MISCREG_CPUECTLR_EL1;
2415 case 2:
2416 return MISCREG_CPUMERRSR_EL1;
2417 case 3:
2418 return MISCREG_L2MERRSR_EL1;
2419 }
2420 break;
2421 case 3:
2422 switch (op2) {
2423 case 0:
2424 return MISCREG_CBAR_EL1;
2425
2426 }
2427 break;
2428 }
2429 break;
2430 }
2431 // S3_<op1>_15_<Cm>_<op2>
2432 return MISCREG_IMPDEF_UNIMPL;
2433 }
2434 break;
2435 }
2436
2437 return MISCREG_UNKNOWN;
2438}
2439
2440bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2441
2442void
2443ISA::initializeMiscRegMetadata()
2444{
2445 // the MiscReg metadata tables are shared across all instances of the
2446 // ISA object, so there's no need to initialize them multiple times.
2447 static bool completed = false;
2448 if (completed)
2449 return;
2450
2451 // This boolean variable specifies if the system is running in aarch32 at
2452 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2453 // is running in aarch64 (aarch32EL3 = false)
2454 bool aarch32EL3 = haveSecurity && !highestELIs64;
2455
2456 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
2457 // unsupported
2458 bool SPAN = false;
2459
2460 // Implicit error synchronization event enable (Arm 8.2+), unsupported
2461 bool IESB = false;
2462
2463 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
2464 // unsupported
2465 bool LSMAOE = false;
2466
2467 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
2468 bool nTLSMD = false;
2469
2470 // Pointer authentication (Arm 8.3+), unsupported
2471 bool EnDA = false; // using APDAKey_EL1 key of instr addrs in ELs 0,1
2472 bool EnDB = false; // using APDBKey_EL1 key of instr addrs in ELs 0,1
2473 bool EnIA = false; // using APIAKey_EL1 key of instr addrs in ELs 0,1
2474 bool EnIB = false; // using APIBKey_EL1 key of instr addrs in ELs 0,1
2475
2476 /**
2477 * Some registers alias with others, and therefore need to be translated.
2478 * When two mapping registers are given, they are the 32b lower and
2479 * upper halves, respectively, of the 64b register being mapped.
2480 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2481 *
2482 * NAM = "not architecturally mandated",
2483 * from ARM DDI 0487A.i, template text
2484 * "AArch64 System register ___ can be mapped to
2485 * AArch32 System register ___, but this is not
2486 * architecturally mandated."
2487 */
2488
2489 InitReg(MISCREG_CPSR)
2490 .allPrivileges();
2491 InitReg(MISCREG_SPSR)
2492 .allPrivileges();
2493 InitReg(MISCREG_SPSR_FIQ)
2494 .allPrivileges();
2495 InitReg(MISCREG_SPSR_IRQ)
2496 .allPrivileges();
2497 InitReg(MISCREG_SPSR_SVC)
2498 .allPrivileges();
2499 InitReg(MISCREG_SPSR_MON)
2500 .allPrivileges();
2501 InitReg(MISCREG_SPSR_ABT)
2502 .allPrivileges();
2503 InitReg(MISCREG_SPSR_HYP)
2504 .allPrivileges();
2505 InitReg(MISCREG_SPSR_UND)
2506 .allPrivileges();
2507 InitReg(MISCREG_ELR_HYP)
2508 .allPrivileges();
2509 InitReg(MISCREG_FPSID)
2510 .allPrivileges();
2511 InitReg(MISCREG_FPSCR)
2512 .allPrivileges();
2513 InitReg(MISCREG_MVFR1)
2514 .allPrivileges();
2515 InitReg(MISCREG_MVFR0)
2516 .allPrivileges();
2517 InitReg(MISCREG_FPEXC)
2518 .allPrivileges();
2519
2520 // Helper registers
2521 InitReg(MISCREG_CPSR_MODE)
2522 .allPrivileges();
2523 InitReg(MISCREG_CPSR_Q)
2524 .allPrivileges();
2525 InitReg(MISCREG_FPSCR_EXC)
2526 .allPrivileges();
2527 InitReg(MISCREG_FPSCR_QC)
2528 .allPrivileges();
2529 InitReg(MISCREG_LOCKADDR)
2530 .allPrivileges();
2531 InitReg(MISCREG_LOCKFLAG)
2532 .allPrivileges();
2533 InitReg(MISCREG_PRRR_MAIR0)
2534 .mutex()
2535 .banked();
2536 InitReg(MISCREG_PRRR_MAIR0_NS)
2537 .mutex()
2538 .privSecure(!aarch32EL3)
2539 .bankedChild();
2540 InitReg(MISCREG_PRRR_MAIR0_S)
2541 .mutex()
2542 .bankedChild();
2543 InitReg(MISCREG_NMRR_MAIR1)
2544 .mutex()
2545 .banked();
2546 InitReg(MISCREG_NMRR_MAIR1_NS)
2547 .mutex()
2548 .privSecure(!aarch32EL3)
2549 .bankedChild();
2550 InitReg(MISCREG_NMRR_MAIR1_S)
2551 .mutex()
2552 .bankedChild();
2553 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2554 .mutex();
2555 InitReg(MISCREG_SCTLR_RST)
2556 .allPrivileges();
2557 InitReg(MISCREG_SEV_MAILBOX)
2558 .allPrivileges();
2559
2560 // AArch32 CP14 registers
2561 InitReg(MISCREG_DBGDIDR)
2562 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2563 InitReg(MISCREG_DBGDSCRint)
2564 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2565 InitReg(MISCREG_DBGDCCINT)
2566 .unimplemented()
2567 .allPrivileges();
2568 InitReg(MISCREG_DBGDTRTXint)
2569 .unimplemented()
2570 .allPrivileges();
2571 InitReg(MISCREG_DBGDTRRXint)
2572 .unimplemented()
2573 .allPrivileges();
2574 InitReg(MISCREG_DBGWFAR)
2575 .unimplemented()
2576 .allPrivileges();
2577 InitReg(MISCREG_DBGVCR)
2578 .unimplemented()
2579 .allPrivileges();
2580 InitReg(MISCREG_DBGDTRRXext)
2581 .unimplemented()
2582 .allPrivileges();
2583 InitReg(MISCREG_DBGDSCRext)
2584 .unimplemented()
2585 .warnNotFail()
2586 .allPrivileges();
2587 InitReg(MISCREG_DBGDTRTXext)
2588 .unimplemented()
2589 .allPrivileges();
2590 InitReg(MISCREG_DBGOSECCR)
2591 .unimplemented()
2592 .allPrivileges();
2593 InitReg(MISCREG_DBGBVR0)
2594 .unimplemented()
2595 .allPrivileges();
2596 InitReg(MISCREG_DBGBVR1)
2597 .unimplemented()
2598 .allPrivileges();
2599 InitReg(MISCREG_DBGBVR2)
2600 .unimplemented()
2601 .allPrivileges();
2602 InitReg(MISCREG_DBGBVR3)
2603 .unimplemented()
2604 .allPrivileges();
2605 InitReg(MISCREG_DBGBVR4)
2606 .unimplemented()
2607 .allPrivileges();
2608 InitReg(MISCREG_DBGBVR5)
2609 .unimplemented()
2610 .allPrivileges();
2611 InitReg(MISCREG_DBGBCR0)
2612 .unimplemented()
2613 .allPrivileges();
2614 InitReg(MISCREG_DBGBCR1)
2615 .unimplemented()
2616 .allPrivileges();
2617 InitReg(MISCREG_DBGBCR2)
2618 .unimplemented()
2619 .allPrivileges();
2620 InitReg(MISCREG_DBGBCR3)
2621 .unimplemented()
2622 .allPrivileges();
2623 InitReg(MISCREG_DBGBCR4)
2624 .unimplemented()
2625 .allPrivileges();
2626 InitReg(MISCREG_DBGBCR5)
2627 .unimplemented()
2628 .allPrivileges();
2629 InitReg(MISCREG_DBGWVR0)
2630 .unimplemented()
2631 .allPrivileges();
2632 InitReg(MISCREG_DBGWVR1)
2633 .unimplemented()
2634 .allPrivileges();
2635 InitReg(MISCREG_DBGWVR2)
2636 .unimplemented()
2637 .allPrivileges();
2638 InitReg(MISCREG_DBGWVR3)
2639 .unimplemented()
2640 .allPrivileges();
2641 InitReg(MISCREG_DBGWCR0)
2642 .unimplemented()
2643 .allPrivileges();
2644 InitReg(MISCREG_DBGWCR1)
2645 .unimplemented()
2646 .allPrivileges();
2647 InitReg(MISCREG_DBGWCR2)
2648 .unimplemented()
2649 .allPrivileges();
2650 InitReg(MISCREG_DBGWCR3)
2651 .unimplemented()
2652 .allPrivileges();
2653 InitReg(MISCREG_DBGDRAR)
2654 .unimplemented()
2655 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2656 InitReg(MISCREG_DBGBXVR4)
2657 .unimplemented()
2658 .allPrivileges();
2659 InitReg(MISCREG_DBGBXVR5)
2660 .unimplemented()
2661 .allPrivileges();
2662 InitReg(MISCREG_DBGOSLAR)
2663 .unimplemented()
2664 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
2665 InitReg(MISCREG_DBGOSLSR)
2666 .unimplemented()
2667 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2668 InitReg(MISCREG_DBGOSDLR)
2669 .unimplemented()
2670 .allPrivileges();
2671 InitReg(MISCREG_DBGPRCR)
2672 .unimplemented()
2673 .allPrivileges();
2674 InitReg(MISCREG_DBGDSAR)
2675 .unimplemented()
2676 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2677 InitReg(MISCREG_DBGCLAIMSET)
2678 .unimplemented()
2679 .allPrivileges();
2680 InitReg(MISCREG_DBGCLAIMCLR)
2681 .unimplemented()
2682 .allPrivileges();
2683 InitReg(MISCREG_DBGAUTHSTATUS)
2684 .unimplemented()
2685 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2686 InitReg(MISCREG_DBGDEVID2)
2687 .unimplemented()
2688 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2689 InitReg(MISCREG_DBGDEVID1)
2690 .unimplemented()
2691 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2692 InitReg(MISCREG_DBGDEVID0)
2693 .unimplemented()
2694 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2695 InitReg(MISCREG_TEECR)
2696 .unimplemented()
2697 .allPrivileges();
2698 InitReg(MISCREG_JIDR)
2699 .allPrivileges();
2700 InitReg(MISCREG_TEEHBR)
2701 .allPrivileges();
2702 InitReg(MISCREG_JOSCR)
2703 .allPrivileges();
2704 InitReg(MISCREG_JMCR)
2705 .allPrivileges();
2706
2707 // AArch32 CP15 registers
2708 InitReg(MISCREG_MIDR)
2709 .allPrivileges().exceptUserMode().writes(0);
2710 InitReg(MISCREG_CTR)
2711 .allPrivileges().exceptUserMode().writes(0);
2712 InitReg(MISCREG_TCMTR)
2713 .allPrivileges().exceptUserMode().writes(0);
2714 InitReg(MISCREG_TLBTR)
2715 .allPrivileges().exceptUserMode().writes(0);
2716 InitReg(MISCREG_MPIDR)
2717 .allPrivileges().exceptUserMode().writes(0);
2718 InitReg(MISCREG_REVIDR)
2719 .unimplemented()
2720 .warnNotFail()
2721 .allPrivileges().exceptUserMode().writes(0);
2722 InitReg(MISCREG_ID_PFR0)
2723 .allPrivileges().exceptUserMode().writes(0);
2724 InitReg(MISCREG_ID_PFR1)
2725 .allPrivileges().exceptUserMode().writes(0);
2726 InitReg(MISCREG_ID_DFR0)
2727 .allPrivileges().exceptUserMode().writes(0);
2728 InitReg(MISCREG_ID_AFR0)
2729 .allPrivileges().exceptUserMode().writes(0);
2730 InitReg(MISCREG_ID_MMFR0)
2731 .allPrivileges().exceptUserMode().writes(0);
2732 InitReg(MISCREG_ID_MMFR1)
2733 .allPrivileges().exceptUserMode().writes(0);
2734 InitReg(MISCREG_ID_MMFR2)
2735 .allPrivileges().exceptUserMode().writes(0);
2736 InitReg(MISCREG_ID_MMFR3)
2737 .allPrivileges().exceptUserMode().writes(0);
2738 InitReg(MISCREG_ID_ISAR0)
2739 .allPrivileges().exceptUserMode().writes(0);
2740 InitReg(MISCREG_ID_ISAR1)
2741 .allPrivileges().exceptUserMode().writes(0);
2742 InitReg(MISCREG_ID_ISAR2)
2743 .allPrivileges().exceptUserMode().writes(0);
2744 InitReg(MISCREG_ID_ISAR3)
2745 .allPrivileges().exceptUserMode().writes(0);
2746 InitReg(MISCREG_ID_ISAR4)
2747 .allPrivileges().exceptUserMode().writes(0);
2748 InitReg(MISCREG_ID_ISAR5)
2749 .allPrivileges().exceptUserMode().writes(0);
2750 InitReg(MISCREG_CCSIDR)
2751 .allPrivileges().exceptUserMode().writes(0);
2752 InitReg(MISCREG_CLIDR)
2753 .allPrivileges().exceptUserMode().writes(0);
2754 InitReg(MISCREG_AIDR)
2755 .allPrivileges().exceptUserMode().writes(0);
2756 InitReg(MISCREG_CSSELR)
2757 .banked();
2758 InitReg(MISCREG_CSSELR_NS)
2759 .bankedChild()
2760 .privSecure(!aarch32EL3)
2761 .nonSecure().exceptUserMode();
2762 InitReg(MISCREG_CSSELR_S)
2763 .bankedChild()
2764 .secure().exceptUserMode();
2765 InitReg(MISCREG_VPIDR)
2766 .hyp().monNonSecure();
2767 InitReg(MISCREG_VMPIDR)
2768 .hyp().monNonSecure();
2769 InitReg(MISCREG_SCTLR)
2770 .banked()
2771 // readMiscRegNoEffect() uses this metadata
2772 // despite using children (below) as backing store
2773 .res0(0x8d22c600)
2774 .res1(0x00400800 | (SPAN ? 0 : 0x800000)
2775 | (LSMAOE ? 0 : 0x10)
2776 | (nTLSMD ? 0 : 0x8));
2777 InitReg(MISCREG_SCTLR_NS)
2778 .bankedChild()
2779 .privSecure(!aarch32EL3)
2780 .nonSecure().exceptUserMode();
2781 InitReg(MISCREG_SCTLR_S)
2782 .bankedChild()
2783 .secure().exceptUserMode();
2784 InitReg(MISCREG_ACTLR)
2785 .banked();
2786 InitReg(MISCREG_ACTLR_NS)
2787 .bankedChild()
2788 .privSecure(!aarch32EL3)
2789 .nonSecure().exceptUserMode();
2790 InitReg(MISCREG_ACTLR_S)
2791 .bankedChild()
2792 .secure().exceptUserMode();
2793 InitReg(MISCREG_CPACR)
2794 .allPrivileges().exceptUserMode();
2795 InitReg(MISCREG_SCR)
2796 .mon().secure().exceptUserMode()
2797 .res0(0xff40) // [31:16], [6]
2798 .res1(0x0030); // [5:4]
2799 InitReg(MISCREG_SDER)
2800 .mon();
2801 InitReg(MISCREG_NSACR)
2802 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2803 InitReg(MISCREG_HSCTLR)
2804 .hyp().monNonSecure()
2805 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
2806 | (IESB ? 0 : 0x200000)
2807 | (EnDA ? 0 : 0x8000000)
2808 | (EnIB ? 0 : 0x40000000)
2809 | (EnIA ? 0 : 0x80000000))
2810 .res1(0x30c50830);
2811 InitReg(MISCREG_HACTLR)
2812 .hyp().monNonSecure();
2813 InitReg(MISCREG_HCR)
2814 .hyp().monNonSecure();
2815 InitReg(MISCREG_HDCR)
2816 .hyp().monNonSecure();
2817 InitReg(MISCREG_HCPTR)
2818 .hyp().monNonSecure();
2819 InitReg(MISCREG_HSTR)
2820 .hyp().monNonSecure();
2821 InitReg(MISCREG_HACR)
2822 .unimplemented()
2823 .warnNotFail()
2824 .hyp().monNonSecure();
2825 InitReg(MISCREG_TTBR0)
2826 .banked();
2827 InitReg(MISCREG_TTBR0_NS)
2828 .bankedChild()
2829 .privSecure(!aarch32EL3)
2830 .nonSecure().exceptUserMode();
2831 InitReg(MISCREG_TTBR0_S)
2832 .bankedChild()
2833 .secure().exceptUserMode();
2834 InitReg(MISCREG_TTBR1)
2835 .banked();
2836 InitReg(MISCREG_TTBR1_NS)
2837 .bankedChild()
2838 .privSecure(!aarch32EL3)
2839 .nonSecure().exceptUserMode();
2840 InitReg(MISCREG_TTBR1_S)
2841 .bankedChild()
2842 .secure().exceptUserMode();
2843 InitReg(MISCREG_TTBCR)
2844 .banked();
2845 InitReg(MISCREG_TTBCR_NS)
2846 .bankedChild()
2847 .privSecure(!aarch32EL3)
2848 .nonSecure().exceptUserMode();
2849 InitReg(MISCREG_TTBCR_S)
2850 .bankedChild()
2851 .secure().exceptUserMode();
2852 InitReg(MISCREG_HTCR)
2853 .hyp().monNonSecure();
2854 InitReg(MISCREG_VTCR)
2855 .hyp().monNonSecure();
2856 InitReg(MISCREG_DACR)
2857 .banked();
2858 InitReg(MISCREG_DACR_NS)
2859 .bankedChild()
2860 .privSecure(!aarch32EL3)
2861 .nonSecure().exceptUserMode();
2862 InitReg(MISCREG_DACR_S)
2863 .bankedChild()
2864 .secure().exceptUserMode();
2865 InitReg(MISCREG_DFSR)
2866 .banked();
2867 InitReg(MISCREG_DFSR_NS)
2868 .bankedChild()
2869 .privSecure(!aarch32EL3)
2870 .nonSecure().exceptUserMode();
2871 InitReg(MISCREG_DFSR_S)
2872 .bankedChild()
2873 .secure().exceptUserMode();
2874 InitReg(MISCREG_IFSR)
2875 .banked();
2876 InitReg(MISCREG_IFSR_NS)
2877 .bankedChild()
2878 .privSecure(!aarch32EL3)
2879 .nonSecure().exceptUserMode();
2880 InitReg(MISCREG_IFSR_S)
2881 .bankedChild()
2882 .secure().exceptUserMode();
2883 InitReg(MISCREG_ADFSR)
2884 .unimplemented()
2885 .warnNotFail()
2886 .banked();
2887 InitReg(MISCREG_ADFSR_NS)
2888 .unimplemented()
2889 .warnNotFail()
2890 .bankedChild()
2891 .privSecure(!aarch32EL3)
2892 .nonSecure().exceptUserMode();
2893 InitReg(MISCREG_ADFSR_S)
2894 .unimplemented()
2895 .warnNotFail()
2896 .bankedChild()
2897 .secure().exceptUserMode();
2898 InitReg(MISCREG_AIFSR)
2899 .unimplemented()
2900 .warnNotFail()
2901 .banked();
2902 InitReg(MISCREG_AIFSR_NS)
2903 .unimplemented()
2904 .warnNotFail()
2905 .bankedChild()
2906 .privSecure(!aarch32EL3)
2907 .nonSecure().exceptUserMode();
2908 InitReg(MISCREG_AIFSR_S)
2909 .unimplemented()
2910 .warnNotFail()
2911 .bankedChild()
2912 .secure().exceptUserMode();
2913 InitReg(MISCREG_HADFSR)
2914 .hyp().monNonSecure();
2915 InitReg(MISCREG_HAIFSR)
2916 .hyp().monNonSecure();
2917 InitReg(MISCREG_HSR)
2918 .hyp().monNonSecure();
2919 InitReg(MISCREG_DFAR)
2920 .banked();
2921 InitReg(MISCREG_DFAR_NS)
2922 .bankedChild()
2923 .privSecure(!aarch32EL3)
2924 .nonSecure().exceptUserMode();
2925 InitReg(MISCREG_DFAR_S)
2926 .bankedChild()
2927 .secure().exceptUserMode();
2928 InitReg(MISCREG_IFAR)
2929 .banked();
2930 InitReg(MISCREG_IFAR_NS)
2931 .bankedChild()
2932 .privSecure(!aarch32EL3)
2933 .nonSecure().exceptUserMode();
2934 InitReg(MISCREG_IFAR_S)
2935 .bankedChild()
2936 .secure().exceptUserMode();
2937 InitReg(MISCREG_HDFAR)
2938 .hyp().monNonSecure();
2939 InitReg(MISCREG_HIFAR)
2940 .hyp().monNonSecure();
2941 InitReg(MISCREG_HPFAR)
2942 .hyp().monNonSecure();
2943 InitReg(MISCREG_ICIALLUIS)
2944 .unimplemented()
2945 .warnNotFail()
2946 .writes(1).exceptUserMode();
2947 InitReg(MISCREG_BPIALLIS)
2948 .unimplemented()
2949 .warnNotFail()
2950 .writes(1).exceptUserMode();
2951 InitReg(MISCREG_PAR)
2952 .banked();
2953 InitReg(MISCREG_PAR_NS)
2954 .bankedChild()
2955 .privSecure(!aarch32EL3)
2956 .nonSecure().exceptUserMode();
2957 InitReg(MISCREG_PAR_S)
2958 .bankedChild()
2959 .secure().exceptUserMode();
2960 InitReg(MISCREG_ICIALLU)
2961 .writes(1).exceptUserMode();
2962 InitReg(MISCREG_ICIMVAU)
2963 .unimplemented()
2964 .warnNotFail()
2965 .writes(1).exceptUserMode();
2966 InitReg(MISCREG_CP15ISB)
2967 .writes(1);
2968 InitReg(MISCREG_BPIALL)
2969 .unimplemented()
2970 .warnNotFail()
2971 .writes(1).exceptUserMode();
2972 InitReg(MISCREG_BPIMVA)
2973 .unimplemented()
2974 .warnNotFail()
2975 .writes(1).exceptUserMode();
2976 InitReg(MISCREG_DCIMVAC)
2977 .unimplemented()
2978 .warnNotFail()
2979 .writes(1).exceptUserMode();
2980 InitReg(MISCREG_DCISW)
2981 .unimplemented()
2982 .warnNotFail()
2983 .writes(1).exceptUserMode();
2984 InitReg(MISCREG_ATS1CPR)
2985 .writes(1).exceptUserMode();
2986 InitReg(MISCREG_ATS1CPW)
2987 .writes(1).exceptUserMode();
2988 InitReg(MISCREG_ATS1CUR)
2989 .writes(1).exceptUserMode();
2990 InitReg(MISCREG_ATS1CUW)
2991 .writes(1).exceptUserMode();
2992 InitReg(MISCREG_ATS12NSOPR)
2993 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2994 InitReg(MISCREG_ATS12NSOPW)
2995 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2996 InitReg(MISCREG_ATS12NSOUR)
2997 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2998 InitReg(MISCREG_ATS12NSOUW)
2999 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3000 InitReg(MISCREG_DCCMVAC)
3001 .writes(1).exceptUserMode();
3002 InitReg(MISCREG_DCCSW)
3003 .unimplemented()
3004 .warnNotFail()
3005 .writes(1).exceptUserMode();
3006 InitReg(MISCREG_CP15DSB)
3007 .writes(1);
3008 InitReg(MISCREG_CP15DMB)
3009 .writes(1);
3010 InitReg(MISCREG_DCCMVAU)
3011 .unimplemented()
3012 .warnNotFail()
3013 .writes(1).exceptUserMode();
3014 InitReg(MISCREG_DCCIMVAC)
3015 .unimplemented()
3016 .warnNotFail()
3017 .writes(1).exceptUserMode();
3018 InitReg(MISCREG_DCCISW)
3019 .unimplemented()
3020 .warnNotFail()
3021 .writes(1).exceptUserMode();
3022 InitReg(MISCREG_ATS1HR)
3023 .monNonSecureWrite().hypWrite();
3024 InitReg(MISCREG_ATS1HW)
3025 .monNonSecureWrite().hypWrite();
3026 InitReg(MISCREG_TLBIALLIS)
3027 .writes(1).exceptUserMode();
3028 InitReg(MISCREG_TLBIMVAIS)
3029 .writes(1).exceptUserMode();
3030 InitReg(MISCREG_TLBIASIDIS)
3031 .writes(1).exceptUserMode();
3032 InitReg(MISCREG_TLBIMVAAIS)
3033 .writes(1).exceptUserMode();
3034 InitReg(MISCREG_TLBIMVALIS)
3035 .writes(1).exceptUserMode();
3036 InitReg(MISCREG_TLBIMVAALIS)
3037 .writes(1).exceptUserMode();
3038 InitReg(MISCREG_ITLBIALL)
3039 .writes(1).exceptUserMode();
3040 InitReg(MISCREG_ITLBIMVA)
3041 .writes(1).exceptUserMode();
3042 InitReg(MISCREG_ITLBIASID)
3043 .writes(1).exceptUserMode();
3044 InitReg(MISCREG_DTLBIALL)
3045 .writes(1).exceptUserMode();
3046 InitReg(MISCREG_DTLBIMVA)
3047 .writes(1).exceptUserMode();
3048 InitReg(MISCREG_DTLBIASID)
3049 .writes(1).exceptUserMode();
3050 InitReg(MISCREG_TLBIALL)
3051 .writes(1).exceptUserMode();
3052 InitReg(MISCREG_TLBIMVA)
3053 .writes(1).exceptUserMode();
3054 InitReg(MISCREG_TLBIASID)
3055 .writes(1).exceptUserMode();
3056 InitReg(MISCREG_TLBIMVAA)
3057 .writes(1).exceptUserMode();
3058 InitReg(MISCREG_TLBIMVAL)
3059 .writes(1).exceptUserMode();
3060 InitReg(MISCREG_TLBIMVAAL)
3061 .writes(1).exceptUserMode();
3062 InitReg(MISCREG_TLBIIPAS2IS)
3063 .monNonSecureWrite().hypWrite();
3064 InitReg(MISCREG_TLBIIPAS2LIS)
3065 .monNonSecureWrite().hypWrite();
3066 InitReg(MISCREG_TLBIALLHIS)
3067 .monNonSecureWrite().hypWrite();
3068 InitReg(MISCREG_TLBIMVAHIS)
3069 .monNonSecureWrite().hypWrite();
3070 InitReg(MISCREG_TLBIALLNSNHIS)
3071 .monNonSecureWrite().hypWrite();
3072 InitReg(MISCREG_TLBIMVALHIS)
3073 .monNonSecureWrite().hypWrite();
3074 InitReg(MISCREG_TLBIIPAS2)
3075 .monNonSecureWrite().hypWrite();
3076 InitReg(MISCREG_TLBIIPAS2L)
3077 .monNonSecureWrite().hypWrite();
3078 InitReg(MISCREG_TLBIALLH)
3079 .monNonSecureWrite().hypWrite();
3080 InitReg(MISCREG_TLBIMVAH)
3081 .monNonSecureWrite().hypWrite();
3082 InitReg(MISCREG_TLBIALLNSNH)
3083 .monNonSecureWrite().hypWrite();
3084 InitReg(MISCREG_TLBIMVALH)
3085 .monNonSecureWrite().hypWrite();
3086 InitReg(MISCREG_PMCR)
3087 .allPrivileges();
3088 InitReg(MISCREG_PMCNTENSET)
3089 .allPrivileges();
3090 InitReg(MISCREG_PMCNTENCLR)
3091 .allPrivileges();
3092 InitReg(MISCREG_PMOVSR)
3093 .allPrivileges();
3094 InitReg(MISCREG_PMSWINC)
3095 .allPrivileges();
3096 InitReg(MISCREG_PMSELR)
3097 .allPrivileges();
3098 InitReg(MISCREG_PMCEID0)
3099 .allPrivileges();
3100 InitReg(MISCREG_PMCEID1)
3101 .allPrivileges();
3102 InitReg(MISCREG_PMCCNTR)
3103 .allPrivileges();
3104 InitReg(MISCREG_PMXEVTYPER)
3105 .allPrivileges();
3106 InitReg(MISCREG_PMCCFILTR)
3107 .allPrivileges();
3108 InitReg(MISCREG_PMXEVCNTR)
3109 .allPrivileges();
3110 InitReg(MISCREG_PMUSERENR)
3111 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3112 InitReg(MISCREG_PMINTENSET)
3113 .allPrivileges().exceptUserMode();
3114 InitReg(MISCREG_PMINTENCLR)
3115 .allPrivileges().exceptUserMode();
3116 InitReg(MISCREG_PMOVSSET)
3117 .unimplemented()
3118 .allPrivileges();
3119 InitReg(MISCREG_L2CTLR)
3120 .allPrivileges().exceptUserMode();
3121 InitReg(MISCREG_L2ECTLR)
3122 .unimplemented()
3123 .allPrivileges().exceptUserMode();
3124 InitReg(MISCREG_PRRR)
3125 .banked();
3126 InitReg(MISCREG_PRRR_NS)
3127 .bankedChild()
3128 .privSecure(!aarch32EL3)
3129 .nonSecure().exceptUserMode();
3130 InitReg(MISCREG_PRRR_S)
3131 .bankedChild()
3132 .secure().exceptUserMode();
3133 InitReg(MISCREG_MAIR0)
3134 .banked();
3135 InitReg(MISCREG_MAIR0_NS)
3136 .bankedChild()
3137 .privSecure(!aarch32EL3)
3138 .nonSecure().exceptUserMode();
3139 InitReg(MISCREG_MAIR0_S)
3140 .bankedChild()
3141 .secure().exceptUserMode();
3142 InitReg(MISCREG_NMRR)
3143 .banked();
3144 InitReg(MISCREG_NMRR_NS)
3145 .bankedChild()
3146 .privSecure(!aarch32EL3)
3147 .nonSecure().exceptUserMode();
3148 InitReg(MISCREG_NMRR_S)
3149 .bankedChild()
3150 .secure().exceptUserMode();
3151 InitReg(MISCREG_MAIR1)
3152 .banked();
3153 InitReg(MISCREG_MAIR1_NS)
3154 .bankedChild()
3155 .privSecure(!aarch32EL3)
3156 .nonSecure().exceptUserMode();
3157 InitReg(MISCREG_MAIR1_S)
3158 .bankedChild()
3159 .secure().exceptUserMode();
3160 InitReg(MISCREG_AMAIR0)
3161 .banked();
3162 InitReg(MISCREG_AMAIR0_NS)
3163 .bankedChild()
3164 .privSecure(!aarch32EL3)
3165 .nonSecure().exceptUserMode();
3166 InitReg(MISCREG_AMAIR0_S)
3167 .bankedChild()
3168 .secure().exceptUserMode();
3169 InitReg(MISCREG_AMAIR1)
3170 .banked();
3171 InitReg(MISCREG_AMAIR1_NS)
3172 .bankedChild()
3173 .privSecure(!aarch32EL3)
3174 .nonSecure().exceptUserMode();
3175 InitReg(MISCREG_AMAIR1_S)
3176 .bankedChild()
3177 .secure().exceptUserMode();
3178 InitReg(MISCREG_HMAIR0)
3179 .hyp().monNonSecure();
3180 InitReg(MISCREG_HMAIR1)
3181 .hyp().monNonSecure();
3182 InitReg(MISCREG_HAMAIR0)
3183 .unimplemented()
3184 .warnNotFail()
3185 .hyp().monNonSecure();
3186 InitReg(MISCREG_HAMAIR1)
3187 .unimplemented()
3188 .warnNotFail()
3189 .hyp().monNonSecure();
3190 InitReg(MISCREG_VBAR)
3191 .banked();
3192 InitReg(MISCREG_VBAR_NS)
3193 .bankedChild()
3194 .privSecure(!aarch32EL3)
3195 .nonSecure().exceptUserMode();
3196 InitReg(MISCREG_VBAR_S)
3197 .bankedChild()
3198 .secure().exceptUserMode();
3199 InitReg(MISCREG_MVBAR)
3200 .mon().secure()
3201 .hypRead(FullSystem && system->highestEL() == EL2)
3202 .privRead(FullSystem && system->highestEL() == EL1)
3203 .exceptUserMode();
3204 InitReg(MISCREG_RMR)
3205 .unimplemented()
3206 .mon().secure().exceptUserMode();
3207 InitReg(MISCREG_ISR)
3208 .allPrivileges().exceptUserMode().writes(0);
3209 InitReg(MISCREG_HVBAR)
3210 .hyp().monNonSecure()
3211 .res0(0x1f);
3212 InitReg(MISCREG_FCSEIDR)
3213 .unimplemented()
3214 .warnNotFail()
3215 .allPrivileges().exceptUserMode();
3216 InitReg(MISCREG_CONTEXTIDR)
3217 .banked();
3218 InitReg(MISCREG_CONTEXTIDR_NS)
3219 .bankedChild()
3220 .privSecure(!aarch32EL3)
3221 .nonSecure().exceptUserMode();
3222 InitReg(MISCREG_CONTEXTIDR_S)
3223 .bankedChild()
3224 .secure().exceptUserMode();
3225 InitReg(MISCREG_TPIDRURW)
3226 .banked();
3227 InitReg(MISCREG_TPIDRURW_NS)
3228 .bankedChild()
3229 .allPrivileges()
3230 .privSecure(!aarch32EL3)
3231 .monSecure(0);
3232 InitReg(MISCREG_TPIDRURW_S)
3233 .bankedChild()
3234 .secure();
3235 InitReg(MISCREG_TPIDRURO)
3236 .banked();
3237 InitReg(MISCREG_TPIDRURO_NS)
3238 .bankedChild()
3239 .allPrivileges()
3240 .userNonSecureWrite(0).userSecureRead(1)
3241 .privSecure(!aarch32EL3)
3242 .monSecure(0);
3243 InitReg(MISCREG_TPIDRURO_S)
3244 .bankedChild()
3245 .secure().userSecureWrite(0);
3246 InitReg(MISCREG_TPIDRPRW)
3247 .banked();
3248 InitReg(MISCREG_TPIDRPRW_NS)
3249 .bankedChild()
3250 .nonSecure().exceptUserMode()
3251 .privSecure(!aarch32EL3);
3252 InitReg(MISCREG_TPIDRPRW_S)
3253 .bankedChild()
3254 .secure().exceptUserMode();
3255 InitReg(MISCREG_HTPIDR)
3256 .hyp().monNonSecure();
3257 InitReg(MISCREG_CNTFRQ)
3258 .unverifiable()
3259 .reads(1).mon();
3260 InitReg(MISCREG_CNTKCTL)
3261 .allPrivileges().exceptUserMode();
3262 InitReg(MISCREG_CNTP_TVAL)
3263 .banked();
3264 InitReg(MISCREG_CNTP_TVAL_NS)
3265 .bankedChild()
3266 .allPrivileges()
3267 .privSecure(!aarch32EL3)
3268 .monSecure(0);
3269 InitReg(MISCREG_CNTP_TVAL_S)
3270 .bankedChild()
3271 .secure().user(1);
3272 InitReg(MISCREG_CNTP_CTL)
3273 .banked();
3274 InitReg(MISCREG_CNTP_CTL_NS)
3275 .bankedChild()
3276 .allPrivileges()
3277 .privSecure(!aarch32EL3)
3278 .monSecure(0);
3279 InitReg(MISCREG_CNTP_CTL_S)
3280 .bankedChild()
3281 .secure().user(1);
3282 InitReg(MISCREG_CNTV_TVAL)
3283 .allPrivileges();
3284 InitReg(MISCREG_CNTV_CTL)
3285 .allPrivileges();
3286 InitReg(MISCREG_CNTHCTL)
3287 .hypWrite().monNonSecureRead();
3288 InitReg(MISCREG_CNTHP_TVAL)
3289 .hypWrite().monNonSecureRead();
3290 InitReg(MISCREG_CNTHP_CTL)
3291 .hypWrite().monNonSecureRead();
3292 InitReg(MISCREG_IL1DATA0)
3293 .unimplemented()
3294 .allPrivileges().exceptUserMode();
3295 InitReg(MISCREG_IL1DATA1)
3296 .unimplemented()
3297 .allPrivileges().exceptUserMode();
3298 InitReg(MISCREG_IL1DATA2)
3299 .unimplemented()
3300 .allPrivileges().exceptUserMode();
3301 InitReg(MISCREG_IL1DATA3)
3302 .unimplemented()
3303 .allPrivileges().exceptUserMode();
3304 InitReg(MISCREG_DL1DATA0)
3305 .unimplemented()
3306 .allPrivileges().exceptUserMode();
3307 InitReg(MISCREG_DL1DATA1)
3308 .unimplemented()
3309 .allPrivileges().exceptUserMode();
3310 InitReg(MISCREG_DL1DATA2)
3311 .unimplemented()
3312 .allPrivileges().exceptUserMode();
3313 InitReg(MISCREG_DL1DATA3)
3314 .unimplemented()
3315 .allPrivileges().exceptUserMode();
3316 InitReg(MISCREG_DL1DATA4)
3317 .unimplemented()
3318 .allPrivileges().exceptUserMode();
3319 InitReg(MISCREG_RAMINDEX)
3320 .unimplemented()
3321 .writes(1).exceptUserMode();
3322 InitReg(MISCREG_L2ACTLR)
3323 .unimplemented()
3324 .allPrivileges().exceptUserMode();
3325 InitReg(MISCREG_CBAR)
3326 .unimplemented()
3327 .allPrivileges().exceptUserMode().writes(0);
3328 InitReg(MISCREG_HTTBR)
3329 .hyp().monNonSecure();
3330 InitReg(MISCREG_VTTBR)
3331 .hyp().monNonSecure();
3332 InitReg(MISCREG_CNTPCT)
3333 .reads(1);
3334 InitReg(MISCREG_CNTVCT)
3335 .unverifiable()
3336 .reads(1);
3337 InitReg(MISCREG_CNTP_CVAL)
3338 .banked();
3339 InitReg(MISCREG_CNTP_CVAL_NS)
3340 .bankedChild()
3341 .allPrivileges()
3342 .privSecure(!aarch32EL3)
3343 .monSecure(0);
3344 InitReg(MISCREG_CNTP_CVAL_S)
3345 .bankedChild()
3346 .secure().user(1);
3347 InitReg(MISCREG_CNTV_CVAL)
3348 .allPrivileges();
3349 InitReg(MISCREG_CNTVOFF)
3350 .hyp().monNonSecure();
3351 InitReg(MISCREG_CNTHP_CVAL)
3352 .hypWrite().monNonSecureRead();
3353 InitReg(MISCREG_CPUMERRSR)
3354 .unimplemented()
3355 .allPrivileges().exceptUserMode();
3356 InitReg(MISCREG_L2MERRSR)
3357 .unimplemented()
3358 .warnNotFail()
3359 .allPrivileges().exceptUserMode();
3360
3361 // AArch64 registers (Op0=2);
3362 InitReg(MISCREG_MDCCINT_EL1)
3363 .allPrivileges();
3364 InitReg(MISCREG_OSDTRRX_EL1)
3365 .allPrivileges()
3366 .mapsTo(MISCREG_DBGDTRRXext);
3367 InitReg(MISCREG_MDSCR_EL1)
3368 .allPrivileges()
3369 .mapsTo(MISCREG_DBGDSCRext);
3370 InitReg(MISCREG_OSDTRTX_EL1)
3371 .allPrivileges()
3372 .mapsTo(MISCREG_DBGDTRTXext);
3373 InitReg(MISCREG_OSECCR_EL1)
3374 .allPrivileges()
3375 .mapsTo(MISCREG_DBGOSECCR);
3376 InitReg(MISCREG_DBGBVR0_EL1)
3377 .allPrivileges()
3378 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3379 InitReg(MISCREG_DBGBVR1_EL1)
3380 .allPrivileges()
3381 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3382 InitReg(MISCREG_DBGBVR2_EL1)
3383 .allPrivileges()
3384 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3385 InitReg(MISCREG_DBGBVR3_EL1)
3386 .allPrivileges()
3387 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3388 InitReg(MISCREG_DBGBVR4_EL1)
3389 .allPrivileges()
3390 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3391 InitReg(MISCREG_DBGBVR5_EL1)
3392 .allPrivileges()
3393 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3394 InitReg(MISCREG_DBGBCR0_EL1)
3395 .allPrivileges()
3396 .mapsTo(MISCREG_DBGBCR0);
3397 InitReg(MISCREG_DBGBCR1_EL1)
3398 .allPrivileges()
3399 .mapsTo(MISCREG_DBGBCR1);
3400 InitReg(MISCREG_DBGBCR2_EL1)
3401 .allPrivileges()
3402 .mapsTo(MISCREG_DBGBCR2);
3403 InitReg(MISCREG_DBGBCR3_EL1)
3404 .allPrivileges()
3405 .mapsTo(MISCREG_DBGBCR3);
3406 InitReg(MISCREG_DBGBCR4_EL1)
3407 .allPrivileges()
3408 .mapsTo(MISCREG_DBGBCR4);
3409 InitReg(MISCREG_DBGBCR5_EL1)
3410 .allPrivileges()
3411 .mapsTo(MISCREG_DBGBCR5);
3412 InitReg(MISCREG_DBGWVR0_EL1)
3413 .allPrivileges()
3414 .mapsTo(MISCREG_DBGWVR0);
3415 InitReg(MISCREG_DBGWVR1_EL1)
3416 .allPrivileges()
3417 .mapsTo(MISCREG_DBGWVR1);
3418 InitReg(MISCREG_DBGWVR2_EL1)
3419 .allPrivileges()
3420 .mapsTo(MISCREG_DBGWVR2);
3421 InitReg(MISCREG_DBGWVR3_EL1)
3422 .allPrivileges()
3423 .mapsTo(MISCREG_DBGWVR3);
3424 InitReg(MISCREG_DBGWCR0_EL1)
3425 .allPrivileges()
3426 .mapsTo(MISCREG_DBGWCR0);
3427 InitReg(MISCREG_DBGWCR1_EL1)
3428 .allPrivileges()
3429 .mapsTo(MISCREG_DBGWCR1);
3430 InitReg(MISCREG_DBGWCR2_EL1)
3431 .allPrivileges()
3432 .mapsTo(MISCREG_DBGWCR2);
3433 InitReg(MISCREG_DBGWCR3_EL1)
3434 .allPrivileges()
3435 .mapsTo(MISCREG_DBGWCR3);
3436 InitReg(MISCREG_MDCCSR_EL0)
3437 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3438 .mapsTo(MISCREG_DBGDSCRint);
3439 InitReg(MISCREG_MDDTR_EL0)
3440 .allPrivileges();
3441 InitReg(MISCREG_MDDTRTX_EL0)
3442 .allPrivileges();
3443 InitReg(MISCREG_MDDTRRX_EL0)
3444 .allPrivileges();
3445 InitReg(MISCREG_DBGVCR32_EL2)
3446 .allPrivileges()
3447 .mapsTo(MISCREG_DBGVCR);
3448 InitReg(MISCREG_MDRAR_EL1)
3449 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3450 .mapsTo(MISCREG_DBGDRAR);
3451 InitReg(MISCREG_OSLAR_EL1)
3452 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3453 .mapsTo(MISCREG_DBGOSLAR);
3454 InitReg(MISCREG_OSLSR_EL1)
3455 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3456 .mapsTo(MISCREG_DBGOSLSR);
3457 InitReg(MISCREG_OSDLR_EL1)
3458 .allPrivileges()
3459 .mapsTo(MISCREG_DBGOSDLR);
3460 InitReg(MISCREG_DBGPRCR_EL1)
3461 .allPrivileges()
3462 .mapsTo(MISCREG_DBGPRCR);
3463 InitReg(MISCREG_DBGCLAIMSET_EL1)
3464 .allPrivileges()
3465 .mapsTo(MISCREG_DBGCLAIMSET);
3466 InitReg(MISCREG_DBGCLAIMCLR_EL1)
3467 .allPrivileges()
3468 .mapsTo(MISCREG_DBGCLAIMCLR);
3469 InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3470 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3471 .mapsTo(MISCREG_DBGAUTHSTATUS);
3472 InitReg(MISCREG_TEECR32_EL1);
3473 InitReg(MISCREG_TEEHBR32_EL1);
3474
3475 // AArch64 registers (Op0=1,3);
3476 InitReg(MISCREG_MIDR_EL1)
3477 .allPrivileges().exceptUserMode().writes(0);
3478 InitReg(MISCREG_MPIDR_EL1)
3479 .allPrivileges().exceptUserMode().writes(0);
3480 InitReg(MISCREG_REVIDR_EL1)
3481 .allPrivileges().exceptUserMode().writes(0);
3482 InitReg(MISCREG_ID_PFR0_EL1)
3483 .allPrivileges().exceptUserMode().writes(0)
3484 .mapsTo(MISCREG_ID_PFR0);
3485 InitReg(MISCREG_ID_PFR1_EL1)
3486 .allPrivileges().exceptUserMode().writes(0)
3487 .mapsTo(MISCREG_ID_PFR1);
3488 InitReg(MISCREG_ID_DFR0_EL1)
3489 .allPrivileges().exceptUserMode().writes(0)
3490 .mapsTo(MISCREG_ID_DFR0);
3491 InitReg(MISCREG_ID_AFR0_EL1)
3492 .allPrivileges().exceptUserMode().writes(0)
3493 .mapsTo(MISCREG_ID_AFR0);
3494 InitReg(MISCREG_ID_MMFR0_EL1)
3495 .allPrivileges().exceptUserMode().writes(0)
3496 .mapsTo(MISCREG_ID_MMFR0);
3497 InitReg(MISCREG_ID_MMFR1_EL1)
3498 .allPrivileges().exceptUserMode().writes(0)
3499 .mapsTo(MISCREG_ID_MMFR1);
3500 InitReg(MISCREG_ID_MMFR2_EL1)
3501 .allPrivileges().exceptUserMode().writes(0)
3502 .mapsTo(MISCREG_ID_MMFR2);
3503 InitReg(MISCREG_ID_MMFR3_EL1)
3504 .allPrivileges().exceptUserMode().writes(0)
3505 .mapsTo(MISCREG_ID_MMFR3);
3506 InitReg(MISCREG_ID_ISAR0_EL1)
3507 .allPrivileges().exceptUserMode().writes(0)
3508 .mapsTo(MISCREG_ID_ISAR0);
3509 InitReg(MISCREG_ID_ISAR1_EL1)
3510 .allPrivileges().exceptUserMode().writes(0)
3511 .mapsTo(MISCREG_ID_ISAR1);
3512 InitReg(MISCREG_ID_ISAR2_EL1)
3513 .allPrivileges().exceptUserMode().writes(0)
3514 .mapsTo(MISCREG_ID_ISAR2);
3515 InitReg(MISCREG_ID_ISAR3_EL1)
3516 .allPrivileges().exceptUserMode().writes(0)
3517 .mapsTo(MISCREG_ID_ISAR3);
3518 InitReg(MISCREG_ID_ISAR4_EL1)
3519 .allPrivileges().exceptUserMode().writes(0)
3520 .mapsTo(MISCREG_ID_ISAR4);
3521 InitReg(MISCREG_ID_ISAR5_EL1)
3522 .allPrivileges().exceptUserMode().writes(0)
3523 .mapsTo(MISCREG_ID_ISAR5);
3524 InitReg(MISCREG_MVFR0_EL1)
3525 .allPrivileges().exceptUserMode().writes(0);
3526 InitReg(MISCREG_MVFR1_EL1)
3527 .allPrivileges().exceptUserMode().writes(0);
3528 InitReg(MISCREG_MVFR2_EL1)
3529 .allPrivileges().exceptUserMode().writes(0);
3530 InitReg(MISCREG_ID_AA64PFR0_EL1)
3531 .allPrivileges().exceptUserMode().writes(0);
3532 InitReg(MISCREG_ID_AA64PFR1_EL1)
3533 .allPrivileges().exceptUserMode().writes(0);
3534 InitReg(MISCREG_ID_AA64DFR0_EL1)
3535 .allPrivileges().exceptUserMode().writes(0);
3536 InitReg(MISCREG_ID_AA64DFR1_EL1)
3537 .allPrivileges().exceptUserMode().writes(0);
3538 InitReg(MISCREG_ID_AA64AFR0_EL1)
3539 .allPrivileges().exceptUserMode().writes(0);
3540 InitReg(MISCREG_ID_AA64AFR1_EL1)
3541 .allPrivileges().exceptUserMode().writes(0);
3542 InitReg(MISCREG_ID_AA64ISAR0_EL1)
3543 .allPrivileges().exceptUserMode().writes(0);
3544 InitReg(MISCREG_ID_AA64ISAR1_EL1)
3545 .allPrivileges().exceptUserMode().writes(0);
3546 InitReg(MISCREG_ID_AA64MMFR0_EL1)
3547 .allPrivileges().exceptUserMode().writes(0);
3548 InitReg(MISCREG_ID_AA64MMFR1_EL1)
3549 .allPrivileges().exceptUserMode().writes(0);
3550 InitReg(MISCREG_ID_AA64MMFR2_EL1)
3551 .allPrivileges().exceptUserMode().writes(0);
3552 InitReg(MISCREG_CCSIDR_EL1)
3553 .allPrivileges().exceptUserMode().writes(0);
3554 InitReg(MISCREG_CLIDR_EL1)
3555 .allPrivileges().exceptUserMode().writes(0);
3556 InitReg(MISCREG_AIDR_EL1)
3557 .allPrivileges().exceptUserMode().writes(0);
3558 InitReg(MISCREG_CSSELR_EL1)
3559 .allPrivileges().exceptUserMode()
3560 .mapsTo(MISCREG_CSSELR_NS);
3561 InitReg(MISCREG_CTR_EL0)
3562 .reads(1);
3563 InitReg(MISCREG_DCZID_EL0)
3564 .reads(1);
3565 InitReg(MISCREG_VPIDR_EL2)
3566 .hyp().mon()
3567 .mapsTo(MISCREG_VPIDR);
3568 InitReg(MISCREG_VMPIDR_EL2)
3569 .hyp().mon()
3570 .mapsTo(MISCREG_VMPIDR);
3571 InitReg(MISCREG_SCTLR_EL1)
3572 .allPrivileges().exceptUserMode()
3573 .res0( 0x20440 | (EnDB ? 0 : 0x2000)
3574 | (IESB ? 0 : 0x200000)
3575 | (EnDA ? 0 : 0x8000000)
3576 | (EnIB ? 0 : 0x40000000)
3577 | (EnIA ? 0 : 0x80000000))
3578 .res1(0x500800 | (SPAN ? 0 : 0x800000)
3579 | (nTLSMD ? 0 : 0x8000000)
3580 | (LSMAOE ? 0 : 0x10000000))
3581 .mapsTo(MISCREG_SCTLR_NS);
3582 InitReg(MISCREG_ACTLR_EL1)
3583 .allPrivileges().exceptUserMode()
3584 .mapsTo(MISCREG_ACTLR_NS);
3585 InitReg(MISCREG_CPACR_EL1)
3586 .allPrivileges().exceptUserMode()
3587 .mapsTo(MISCREG_CPACR);
3588 InitReg(MISCREG_SCTLR_EL2)
3589 .hyp().mon()
3590 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3591 | (IESB ? 0 : 0x200000)
3592 | (EnDA ? 0 : 0x8000000)
3593 | (EnIB ? 0 : 0x40000000)
3594 | (EnIA ? 0 : 0x80000000))
3595 .res1(0x30c50830)
3596 .mapsTo(MISCREG_HSCTLR);
3597 InitReg(MISCREG_ACTLR_EL2)
3598 .hyp().mon()
3599 .mapsTo(MISCREG_HACTLR);
3600 InitReg(MISCREG_HCR_EL2)
3601 .hyp().mon()
3602 .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
3603 InitReg(MISCREG_MDCR_EL2)
3604 .hyp().mon()
3605 .mapsTo(MISCREG_HDCR);
3606 InitReg(MISCREG_CPTR_EL2)
3607 .hyp().mon()
3608 .mapsTo(MISCREG_HCPTR);
3609 InitReg(MISCREG_HSTR_EL2)
3610 .hyp().mon()
3611 .mapsTo(MISCREG_HSTR);
3612 InitReg(MISCREG_HACR_EL2)
3613 .hyp().mon()
3614 .mapsTo(MISCREG_HACR);
3615 InitReg(MISCREG_SCTLR_EL3)
3616 .mon()
3617 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3618 | (IESB ? 0 : 0x200000)
3619 | (EnDA ? 0 : 0x8000000)
3620 | (EnIB ? 0 : 0x40000000)
3621 | (EnIA ? 0 : 0x80000000))
3622 .res1(0x30c50830);
3623 InitReg(MISCREG_ACTLR_EL3)
3624 .mon();
3625 InitReg(MISCREG_SCR_EL3)
3626 .mon()
3627 .mapsTo(MISCREG_SCR); // NAM D7-2005
3628 InitReg(MISCREG_SDER32_EL3)
3629 .mon()
3630 .mapsTo(MISCREG_SDER);
3631 InitReg(MISCREG_CPTR_EL3)
3632 .mon();
3633 InitReg(MISCREG_MDCR_EL3)
3634 .mon();
3635 InitReg(MISCREG_TTBR0_EL1)
3636 .allPrivileges().exceptUserMode()
3637 .mapsTo(MISCREG_TTBR0_NS);
3638 InitReg(MISCREG_TTBR1_EL1)
3639 .allPrivileges().exceptUserMode()
3640 .mapsTo(MISCREG_TTBR1_NS);
3641 InitReg(MISCREG_TCR_EL1)
3642 .allPrivileges().exceptUserMode()
3643 .mapsTo(MISCREG_TTBCR_NS);
3644 InitReg(MISCREG_TTBR0_EL2)
3645 .hyp().mon()
3646 .mapsTo(MISCREG_HTTBR);
3647 InitReg(MISCREG_TTBR1_EL2)
3648 .hyp().mon();
3649 InitReg(MISCREG_TCR_EL2)
3650 .hyp().mon()
3651 .mapsTo(MISCREG_HTCR);
3652 InitReg(MISCREG_VTTBR_EL2)
3653 .hyp().mon()
3654 .mapsTo(MISCREG_VTTBR);
3655 InitReg(MISCREG_VTCR_EL2)
3656 .hyp().mon()
3657 .mapsTo(MISCREG_VTCR);
3658 InitReg(MISCREG_TTBR0_EL3)
3659 .mon();
3660 InitReg(MISCREG_TCR_EL3)
3661 .mon();
3662 InitReg(MISCREG_DACR32_EL2)
3663 .hyp().mon()
3664 .mapsTo(MISCREG_DACR_NS);
3665 InitReg(MISCREG_SPSR_EL1)
3666 .allPrivileges().exceptUserMode()
3667 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
3668 InitReg(MISCREG_ELR_EL1)
3669 .allPrivileges().exceptUserMode();
3670 InitReg(MISCREG_SP_EL0)
3671 .allPrivileges().exceptUserMode();
3672 InitReg(MISCREG_SPSEL)
3673 .allPrivileges().exceptUserMode();
3674 InitReg(MISCREG_CURRENTEL)
3675 .allPrivileges().exceptUserMode().writes(0);
3676 InitReg(MISCREG_NZCV)
3677 .allPrivileges();
3678 InitReg(MISCREG_DAIF)
3679 .allPrivileges();
3680 InitReg(MISCREG_FPCR)
3681 .allPrivileges();
3682 InitReg(MISCREG_FPSR)
3683 .allPrivileges();
3684 InitReg(MISCREG_DSPSR_EL0)
3685 .allPrivileges();
3686 InitReg(MISCREG_DLR_EL0)
3687 .allPrivileges();
3688 InitReg(MISCREG_SPSR_EL2)
3689 .hyp().mon()
3690 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
3691 InitReg(MISCREG_ELR_EL2)
3692 .hyp().mon();
3693 InitReg(MISCREG_SP_EL1)
3694 .hyp().mon();
3695 InitReg(MISCREG_SPSR_IRQ_AA64)
3696 .hyp().mon();
3697 InitReg(MISCREG_SPSR_ABT_AA64)
3698 .hyp().mon();
3699 InitReg(MISCREG_SPSR_UND_AA64)
3700 .hyp().mon();
3701 InitReg(MISCREG_SPSR_FIQ_AA64)
3702 .hyp().mon();
3703 InitReg(MISCREG_SPSR_EL3)
3704 .mon()
3705 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
3706 InitReg(MISCREG_ELR_EL3)
3707 .mon();
3708 InitReg(MISCREG_SP_EL2)
3709 .mon();
3710 InitReg(MISCREG_AFSR0_EL1)
3711 .allPrivileges().exceptUserMode()
3712 .mapsTo(MISCREG_ADFSR_NS);
3713 InitReg(MISCREG_AFSR1_EL1)
3714 .allPrivileges().exceptUserMode()
3715 .mapsTo(MISCREG_AIFSR_NS);
3716 InitReg(MISCREG_ESR_EL1)
3717 .allPrivileges().exceptUserMode();
3718 InitReg(MISCREG_IFSR32_EL2)
3719 .hyp().mon()
3720 .mapsTo(MISCREG_IFSR_NS);
3721 InitReg(MISCREG_AFSR0_EL2)
3722 .hyp().mon()
3723 .mapsTo(MISCREG_HADFSR);
3724 InitReg(MISCREG_AFSR1_EL2)
3725 .hyp().mon()
3726 .mapsTo(MISCREG_HAIFSR);
3727 InitReg(MISCREG_ESR_EL2)
3728 .hyp().mon()
3729 .mapsTo(MISCREG_HSR);
3730 InitReg(MISCREG_FPEXC32_EL2)
3731 .hyp().mon().mapsTo(MISCREG_FPEXC);
3732 InitReg(MISCREG_AFSR0_EL3)
3733 .mon();
3734 InitReg(MISCREG_AFSR1_EL3)
3735 .mon();
3736 InitReg(MISCREG_ESR_EL3)
3737 .mon();
3738 InitReg(MISCREG_FAR_EL1)
3739 .allPrivileges().exceptUserMode()
3740 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
3741 InitReg(MISCREG_FAR_EL2)
3742 .hyp().mon()
3743 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
3744 InitReg(MISCREG_HPFAR_EL2)
3745 .hyp().mon()
3746 .mapsTo(MISCREG_HPFAR);
3747 InitReg(MISCREG_FAR_EL3)
3748 .mon();
3749 InitReg(MISCREG_IC_IALLUIS)
3750 .warnNotFail()
3751 .writes(1).exceptUserMode();
3752 InitReg(MISCREG_PAR_EL1)
3753 .allPrivileges().exceptUserMode()
3754 .mapsTo(MISCREG_PAR_NS);
3755 InitReg(MISCREG_IC_IALLU)
3756 .warnNotFail()
3757 .writes(1).exceptUserMode();
3758 InitReg(MISCREG_DC_IVAC_Xt)
3759 .warnNotFail()
3760 .writes(1).exceptUserMode();
3761 InitReg(MISCREG_DC_ISW_Xt)
3762 .warnNotFail()
3763 .writes(1).exceptUserMode();
3764 InitReg(MISCREG_AT_S1E1R_Xt)
3765 .writes(1).exceptUserMode();
3766 InitReg(MISCREG_AT_S1E1W_Xt)
3767 .writes(1).exceptUserMode();
3768 InitReg(MISCREG_AT_S1E0R_Xt)
3769 .writes(1).exceptUserMode();
3770 InitReg(MISCREG_AT_S1E0W_Xt)
3771 .writes(1).exceptUserMode();
3772 InitReg(MISCREG_DC_CSW_Xt)
3773 .warnNotFail()
3774 .writes(1).exceptUserMode();
3775 InitReg(MISCREG_DC_CISW_Xt)
3776 .warnNotFail()
3777 .writes(1).exceptUserMode();
3778 InitReg(MISCREG_DC_ZVA_Xt)
3779 .warnNotFail()
3780 .writes(1).userSecureWrite(0);
3781 InitReg(MISCREG_IC_IVAU_Xt)
3782 .writes(1);
3783 InitReg(MISCREG_DC_CVAC_Xt)
3784 .warnNotFail()
3785 .writes(1);
3786 InitReg(MISCREG_DC_CVAU_Xt)
3787 .warnNotFail()
3788 .writes(1);
3789 InitReg(MISCREG_DC_CIVAC_Xt)
3790 .warnNotFail()
3791 .writes(1);
3792 InitReg(MISCREG_AT_S1E2R_Xt)
3793 .monNonSecureWrite().hypWrite();
3794 InitReg(MISCREG_AT_S1E2W_Xt)
3795 .monNonSecureWrite().hypWrite();
3796 InitReg(MISCREG_AT_S12E1R_Xt)
3797 .hypWrite().monSecureWrite().monNonSecureWrite();
3798 InitReg(MISCREG_AT_S12E1W_Xt)
3799 .hypWrite().monSecureWrite().monNonSecureWrite();
3800 InitReg(MISCREG_AT_S12E0R_Xt)
3801 .hypWrite().monSecureWrite().monNonSecureWrite();
3802 InitReg(MISCREG_AT_S12E0W_Xt)
3803 .hypWrite().monSecureWrite().monNonSecureWrite();
3804 InitReg(MISCREG_AT_S1E3R_Xt)
3805 .monSecureWrite().monNonSecureWrite();
3806 InitReg(MISCREG_AT_S1E3W_Xt)
3807 .monSecureWrite().monNonSecureWrite();
3808 InitReg(MISCREG_TLBI_VMALLE1IS)
3809 .writes(1).exceptUserMode();
3810 InitReg(MISCREG_TLBI_VAE1IS_Xt)
3811 .writes(1).exceptUserMode();
3812 InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
3813 .writes(1).exceptUserMode();
3814 InitReg(MISCREG_TLBI_VAAE1IS_Xt)
3815 .writes(1).exceptUserMode();
3816 InitReg(MISCREG_TLBI_VALE1IS_Xt)
3817 .writes(1).exceptUserMode();
3818 InitReg(MISCREG_TLBI_VAALE1IS_Xt)
3819 .writes(1).exceptUserMode();
3820 InitReg(MISCREG_TLBI_VMALLE1)
3821 .writes(1).exceptUserMode();
3822 InitReg(MISCREG_TLBI_VAE1_Xt)
3823 .writes(1).exceptUserMode();
3824 InitReg(MISCREG_TLBI_ASIDE1_Xt)
3825 .writes(1).exceptUserMode();
3826 InitReg(MISCREG_TLBI_VAAE1_Xt)
3827 .writes(1).exceptUserMode();
3828 InitReg(MISCREG_TLBI_VALE1_Xt)
3829 .writes(1).exceptUserMode();
3830 InitReg(MISCREG_TLBI_VAALE1_Xt)
3831 .writes(1).exceptUserMode();
3832 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
3833 .hypWrite().monSecureWrite().monNonSecureWrite();
3834 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
3835 .hypWrite().monSecureWrite().monNonSecureWrite();
3836 InitReg(MISCREG_TLBI_ALLE2IS)
3837 .monNonSecureWrite().hypWrite();
3838 InitReg(MISCREG_TLBI_VAE2IS_Xt)
3839 .monNonSecureWrite().hypWrite();
3840 InitReg(MISCREG_TLBI_ALLE1IS)
3841 .hypWrite().monSecureWrite().monNonSecureWrite();
3842 InitReg(MISCREG_TLBI_VALE2IS_Xt)
3843 .monNonSecureWrite().hypWrite();
3844 InitReg(MISCREG_TLBI_VMALLS12E1IS)
3845 .hypWrite().monSecureWrite().monNonSecureWrite();
3846 InitReg(MISCREG_TLBI_IPAS2E1_Xt)
3847 .hypWrite().monSecureWrite().monNonSecureWrite();
3848 InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
3849 .hypWrite().monSecureWrite().monNonSecureWrite();
3850 InitReg(MISCREG_TLBI_ALLE2)
3851 .monNonSecureWrite().hypWrite();
3852 InitReg(MISCREG_TLBI_VAE2_Xt)
3853 .monNonSecureWrite().hypWrite();
3854 InitReg(MISCREG_TLBI_ALLE1)
3855 .hypWrite().monSecureWrite().monNonSecureWrite();
3856 InitReg(MISCREG_TLBI_VALE2_Xt)
3857 .monNonSecureWrite().hypWrite();
3858 InitReg(MISCREG_TLBI_VMALLS12E1)
3859 .hypWrite().monSecureWrite().monNonSecureWrite();
3860 InitReg(MISCREG_TLBI_ALLE3IS)
3861 .monSecureWrite().monNonSecureWrite();
3862 InitReg(MISCREG_TLBI_VAE3IS_Xt)
3863 .monSecureWrite().monNonSecureWrite();
3864 InitReg(MISCREG_TLBI_VALE3IS_Xt)
3865 .monSecureWrite().monNonSecureWrite();
3866 InitReg(MISCREG_TLBI_ALLE3)
3867 .monSecureWrite().monNonSecureWrite();
3868 InitReg(MISCREG_TLBI_VAE3_Xt)
3869 .monSecureWrite().monNonSecureWrite();
3870 InitReg(MISCREG_TLBI_VALE3_Xt)
3871 .monSecureWrite().monNonSecureWrite();
3872 InitReg(MISCREG_PMINTENSET_EL1)
3873 .allPrivileges().exceptUserMode()
3874 .mapsTo(MISCREG_PMINTENSET);
3875 InitReg(MISCREG_PMINTENCLR_EL1)
3876 .allPrivileges().exceptUserMode()
3877 .mapsTo(MISCREG_PMINTENCLR);
3878 InitReg(MISCREG_PMCR_EL0)
3879 .allPrivileges()
3880 .mapsTo(MISCREG_PMCR);
3881 InitReg(MISCREG_PMCNTENSET_EL0)
3882 .allPrivileges()
3883 .mapsTo(MISCREG_PMCNTENSET);
3884 InitReg(MISCREG_PMCNTENCLR_EL0)
3885 .allPrivileges()
3886 .mapsTo(MISCREG_PMCNTENCLR);
3887 InitReg(MISCREG_PMOVSCLR_EL0)
3888 .allPrivileges();
3889// .mapsTo(MISCREG_PMOVSCLR);
3890 InitReg(MISCREG_PMSWINC_EL0)
3891 .writes(1).user()
3892 .mapsTo(MISCREG_PMSWINC);
3893 InitReg(MISCREG_PMSELR_EL0)
3894 .allPrivileges()
3895 .mapsTo(MISCREG_PMSELR);
3896 InitReg(MISCREG_PMCEID0_EL0)
3897 .reads(1).user()
3898 .mapsTo(MISCREG_PMCEID0);
3899 InitReg(MISCREG_PMCEID1_EL0)
3900 .reads(1).user()
3901 .mapsTo(MISCREG_PMCEID1);
3902 InitReg(MISCREG_PMCCNTR_EL0)
3903 .allPrivileges()
3904 .mapsTo(MISCREG_PMCCNTR);
3905 InitReg(MISCREG_PMXEVTYPER_EL0)
3906 .allPrivileges()
3907 .mapsTo(MISCREG_PMXEVTYPER);
3908 InitReg(MISCREG_PMCCFILTR_EL0)
3909 .allPrivileges();
3910 InitReg(MISCREG_PMXEVCNTR_EL0)
3911 .allPrivileges()
3912 .mapsTo(MISCREG_PMXEVCNTR);
3913 InitReg(MISCREG_PMUSERENR_EL0)
3914 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3915 .mapsTo(MISCREG_PMUSERENR);
3916 InitReg(MISCREG_PMOVSSET_EL0)
3917 .allPrivileges()
3918 .mapsTo(MISCREG_PMOVSSET);
3919 InitReg(MISCREG_MAIR_EL1)
3920 .allPrivileges().exceptUserMode()
3921 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
3922 InitReg(MISCREG_AMAIR_EL1)
3923 .allPrivileges().exceptUserMode()
3924 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
3925 InitReg(MISCREG_MAIR_EL2)
3926 .hyp().mon()
3927 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
3928 InitReg(MISCREG_AMAIR_EL2)
3929 .hyp().mon()
3930 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
3931 InitReg(MISCREG_MAIR_EL3)
3932 .mon();
3933 InitReg(MISCREG_AMAIR_EL3)
3934 .mon();
3935 InitReg(MISCREG_L2CTLR_EL1)
3936 .allPrivileges().exceptUserMode();
3937 InitReg(MISCREG_L2ECTLR_EL1)
3938 .allPrivileges().exceptUserMode();
3939 InitReg(MISCREG_VBAR_EL1)
3940 .allPrivileges().exceptUserMode()
3941 .mapsTo(MISCREG_VBAR_NS);
3942 InitReg(MISCREG_RVBAR_EL1)
3943 .allPrivileges().exceptUserMode().writes(0);
3944 InitReg(MISCREG_ISR_EL1)
3945 .allPrivileges().exceptUserMode().writes(0);
3946 InitReg(MISCREG_VBAR_EL2)
3947 .hyp().mon()
3948 .res0(0x7ff)
3949 .mapsTo(MISCREG_HVBAR);
3950 InitReg(MISCREG_RVBAR_EL2)
3951 .mon().hyp().writes(0);
3952 InitReg(MISCREG_VBAR_EL3)
3953 .mon();
3954 InitReg(MISCREG_RVBAR_EL3)
3955 .mon().writes(0);
3956 InitReg(MISCREG_RMR_EL3)
3957 .mon();
3958 InitReg(MISCREG_CONTEXTIDR_EL1)
3959 .allPrivileges().exceptUserMode()
3960 .mapsTo(MISCREG_CONTEXTIDR_NS);
3961 InitReg(MISCREG_TPIDR_EL1)
3962 .allPrivileges().exceptUserMode()
3963 .mapsTo(MISCREG_TPIDRPRW_NS);
3964 InitReg(MISCREG_TPIDR_EL0)
3965 .allPrivileges()
3966 .mapsTo(MISCREG_TPIDRURW_NS);
3967 InitReg(MISCREG_TPIDRRO_EL0)
3968 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3969 .mapsTo(MISCREG_TPIDRURO_NS);
3970 InitReg(MISCREG_TPIDR_EL2)
3971 .hyp().mon()
3972 .mapsTo(MISCREG_HTPIDR);
3973 InitReg(MISCREG_TPIDR_EL3)
3974 .mon();
3975 InitReg(MISCREG_CNTKCTL_EL1)
3976 .allPrivileges().exceptUserMode()
3977 .mapsTo(MISCREG_CNTKCTL);
3978 InitReg(MISCREG_CNTFRQ_EL0)
3979 .reads(1).mon()
3980 .mapsTo(MISCREG_CNTFRQ);
3981 InitReg(MISCREG_CNTPCT_EL0)
3982 .reads(1)
3983 .mapsTo(MISCREG_CNTPCT); /* 64b */
3984 InitReg(MISCREG_CNTVCT_EL0)
3985 .unverifiable()
3986 .reads(1)
3987 .mapsTo(MISCREG_CNTVCT); /* 64b */
3988 InitReg(MISCREG_CNTP_TVAL_EL0)
3989 .allPrivileges()
3990 .mapsTo(MISCREG_CNTP_TVAL_NS);
3991 InitReg(MISCREG_CNTP_CTL_EL0)
3992 .allPrivileges()
3993 .mapsTo(MISCREG_CNTP_CTL_NS);
3994 InitReg(MISCREG_CNTP_CVAL_EL0)
3995 .allPrivileges()
3996 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
3997 InitReg(MISCREG_CNTV_TVAL_EL0)
3998 .allPrivileges()
3999 .mapsTo(MISCREG_CNTV_TVAL);
4000 InitReg(MISCREG_CNTV_CTL_EL0)
4001 .allPrivileges()
4002 .mapsTo(MISCREG_CNTV_CTL);
4003 InitReg(MISCREG_CNTV_CVAL_EL0)
4004 .allPrivileges()
4005 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
4006 InitReg(MISCREG_PMEVCNTR0_EL0)
4007 .allPrivileges();
4008// .mapsTo(MISCREG_PMEVCNTR0);
4009 InitReg(MISCREG_PMEVCNTR1_EL0)
4010 .allPrivileges();
4011// .mapsTo(MISCREG_PMEVCNTR1);
4012 InitReg(MISCREG_PMEVCNTR2_EL0)
4013 .allPrivileges();
4014// .mapsTo(MISCREG_PMEVCNTR2);
4015 InitReg(MISCREG_PMEVCNTR3_EL0)
4016 .allPrivileges();
4017// .mapsTo(MISCREG_PMEVCNTR3);
4018 InitReg(MISCREG_PMEVCNTR4_EL0)
4019 .allPrivileges();
4020// .mapsTo(MISCREG_PMEVCNTR4);
4021 InitReg(MISCREG_PMEVCNTR5_EL0)
4022 .allPrivileges();
4023// .mapsTo(MISCREG_PMEVCNTR5);
4024 InitReg(MISCREG_PMEVTYPER0_EL0)
4025 .allPrivileges();
4026// .mapsTo(MISCREG_PMEVTYPER0);
4027 InitReg(MISCREG_PMEVTYPER1_EL0)
4028 .allPrivileges();
4029// .mapsTo(MISCREG_PMEVTYPER1);
4030 InitReg(MISCREG_PMEVTYPER2_EL0)
4031 .allPrivileges();
4032// .mapsTo(MISCREG_PMEVTYPER2);
4033 InitReg(MISCREG_PMEVTYPER3_EL0)
4034 .allPrivileges();
4035// .mapsTo(MISCREG_PMEVTYPER3);
4036 InitReg(MISCREG_PMEVTYPER4_EL0)
4037 .allPrivileges();
4038// .mapsTo(MISCREG_PMEVTYPER4);
4039 InitReg(MISCREG_PMEVTYPER5_EL0)
4040 .allPrivileges();
4041// .mapsTo(MISCREG_PMEVTYPER5);
4042 InitReg(MISCREG_CNTVOFF_EL2)
4043 .hyp().mon()
4044 .mapsTo(MISCREG_CNTVOFF); /* 64b */
4045 InitReg(MISCREG_CNTHCTL_EL2)
4046 .mon().hyp()
4047 .mapsTo(MISCREG_CNTHCTL);
4048 InitReg(MISCREG_CNTHP_TVAL_EL2)
4049 .mon().hyp()
4050 .mapsTo(MISCREG_CNTHP_TVAL);
4051 InitReg(MISCREG_CNTHP_CTL_EL2)
4052 .mon().hyp()
4053 .mapsTo(MISCREG_CNTHP_CTL);
4054 InitReg(MISCREG_CNTHP_CVAL_EL2)
4055 .mon().hyp()
4056 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
4057 InitReg(MISCREG_CNTPS_TVAL_EL1)
4058 .mon().privSecure();
4059 InitReg(MISCREG_CNTPS_CTL_EL1)
4060 .mon().privSecure();
4061 InitReg(MISCREG_CNTPS_CVAL_EL1)
4062 .mon().privSecure();
4063 InitReg(MISCREG_IL1DATA0_EL1)
4064 .allPrivileges().exceptUserMode();
4065 InitReg(MISCREG_IL1DATA1_EL1)
4066 .allPrivileges().exceptUserMode();
4067 InitReg(MISCREG_IL1DATA2_EL1)
4068 .allPrivileges().exceptUserMode();
4069 InitReg(MISCREG_IL1DATA3_EL1)
4070 .allPrivileges().exceptUserMode();
4071 InitReg(MISCREG_DL1DATA0_EL1)
4072 .allPrivileges().exceptUserMode();
4073 InitReg(MISCREG_DL1DATA1_EL1)
4074 .allPrivileges().exceptUserMode();
4075 InitReg(MISCREG_DL1DATA2_EL1)
4076 .allPrivileges().exceptUserMode();
4077 InitReg(MISCREG_DL1DATA3_EL1)
4078 .allPrivileges().exceptUserMode();
4079 InitReg(MISCREG_DL1DATA4_EL1)
4080 .allPrivileges().exceptUserMode();
4081 InitReg(MISCREG_L2ACTLR_EL1)
4082 .allPrivileges().exceptUserMode();
4083 InitReg(MISCREG_CPUACTLR_EL1)
4084 .allPrivileges().exceptUserMode();
4085 InitReg(MISCREG_CPUECTLR_EL1)
4086 .allPrivileges().exceptUserMode();
4087 InitReg(MISCREG_CPUMERRSR_EL1)
4088 .allPrivileges().exceptUserMode();
4089 InitReg(MISCREG_L2MERRSR_EL1)
4090 .unimplemented()
4091 .warnNotFail()
4092 .allPrivileges().exceptUserMode();
4093 InitReg(MISCREG_CBAR_EL1)
4094 .allPrivileges().exceptUserMode().writes(0);
4095 InitReg(MISCREG_CONTEXTIDR_EL2)
4096 .mon().hyp();
4097 InitReg(MISCREG_CNTHV_CTL_EL2)
4098 .mon().hyp();
4099 InitReg(MISCREG_CNTHV_CVAL_EL2)
4100 .mon().hyp();
4101 InitReg(MISCREG_CNTHV_TVAL_EL2)
4102 .mon().hyp();
4103
4104 // Dummy registers
4105 InitReg(MISCREG_NOP)
4106 .allPrivileges();
4107 InitReg(MISCREG_RAZ)
4108 .allPrivileges().exceptUserMode().writes(0);
4109 InitReg(MISCREG_CP14_UNIMPL)
4110 .unimplemented()
4111 .warnNotFail();
4112 InitReg(MISCREG_CP15_UNIMPL)
4113 .unimplemented()
4114 .warnNotFail();
4115 InitReg(MISCREG_UNKNOWN);
4116 InitReg(MISCREG_IMPDEF_UNIMPL)
4117 .unimplemented()
4118 .warnNotFail(impdefAsNop);
4119
4120 // RAS extension (unimplemented)
4121 InitReg(MISCREG_ERRIDR_EL1)
4122 .unimplemented()
4123 .warnNotFail();
4124 InitReg(MISCREG_ERRSELR_EL1)
4125 .unimplemented()
4126 .warnNotFail();
4127 InitReg(MISCREG_ERXFR_EL1)
4128 .unimplemented()
4129 .warnNotFail();
4130 InitReg(MISCREG_ERXCTLR_EL1)
4131 .unimplemented()
4132 .warnNotFail();
4133 InitReg(MISCREG_ERXSTATUS_EL1)
4134 .unimplemented()
4135 .warnNotFail();
4136 InitReg(MISCREG_ERXADDR_EL1)
4137 .unimplemented()
4138 .warnNotFail();
4139 InitReg(MISCREG_ERXMISC0_EL1)
4140 .unimplemented()
4141 .warnNotFail();
4142 InitReg(MISCREG_ERXMISC1_EL1)
4143 .unimplemented()
4144 .warnNotFail();
4145 InitReg(MISCREG_DISR_EL1)
4146 .unimplemented()
4147 .warnNotFail();
4148 InitReg(MISCREG_VSESR_EL2)
4149 .unimplemented()
4150 .warnNotFail();
4151 InitReg(MISCREG_VDISR_EL2)
4152 .unimplemented()
4153 .warnNotFail();
4154
4155 // Register mappings for some unimplemented registers:
4156 // ESR_EL1 -> DFSR
4157 // RMR_EL1 -> RMR
4158 // RMR_EL2 -> HRMR
4159 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
4160 // DBGDTRRX_EL0 -> DBGDTRRXint
4161 // DBGDTRTX_EL0 -> DBGDTRRXint
4162 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
4163
4164 completed = true;
4165}
4166
4167} // namespace ArmISA