1/*
2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 * Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include <tuple>
45
46#include "arch/arm/isa.hh"
47#include "base/logging.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51namespace ArmISA
52{
53
54MiscRegIndex
55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56{
57 switch(crn) {
58 case 0:
59 switch (opc1) {
60 case 0:
61 switch (opc2) {
62 case 0:
63 switch (crm) {
64 case 0:
65 return MISCREG_DBGDIDR;
66 case 1:
67 return MISCREG_DBGDSCRint;
68 }
69 break;
70 }
71 break;
72 case 7:
73 switch (opc2) {
74 case 0:
75 switch (crm) {
76 case 0:
77 return MISCREG_JIDR;
78 }
79 break;
80 }
81 break;
82 }
83 break;
84 case 1:
85 switch (opc1) {
86 case 6:
87 switch (crm) {
88 case 0:
89 switch (opc2) {
90 case 0:
91 return MISCREG_TEEHBR;
92 }
93 break;
94 }
95 break;
96 case 7:
97 switch (crm) {
98 case 0:
99 switch (opc2) {
100 case 0:
101 return MISCREG_JOSCR;
102 }
103 break;
104 }
105 break;
106 }
107 break;
108 case 2:
109 switch (opc1) {
110 case 7:
111 switch (crm) {
112 case 0:
113 switch (opc2) {
114 case 0:
115 return MISCREG_JMCR;
116 }
117 break;
118 }
119 break;
120 }
121 break;
122 }
123 // If we get here then it must be a register that we haven't implemented
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn, opc1, crm, opc2);
126 return MISCREG_CP14_UNIMPL;
127}
128
129using namespace std;
130
131MiscRegIndex
132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133{
134 switch (crn) {
135 case 0:
136 switch (opc1) {
137 case 0:
138 switch (crm) {
139 case 0:
140 switch (opc2) {
141 case 1:
142 return MISCREG_CTR;
143 case 2:
144 return MISCREG_TCMTR;
145 case 3:
146 return MISCREG_TLBTR;
147 case 5:
148 return MISCREG_MPIDR;
149 case 6:
150 return MISCREG_REVIDR;
151 default:
152 return MISCREG_MIDR;
153 }
154 break;
155 case 1:
156 switch (opc2) {
157 case 0:
158 return MISCREG_ID_PFR0;
159 case 1:
160 return MISCREG_ID_PFR1;
161 case 2:
162 return MISCREG_ID_DFR0;
163 case 3:
164 return MISCREG_ID_AFR0;
165 case 4:
166 return MISCREG_ID_MMFR0;
167 case 5:
168 return MISCREG_ID_MMFR1;
169 case 6:
170 return MISCREG_ID_MMFR2;
171 case 7:
172 return MISCREG_ID_MMFR3;
173 }
174 break;
175 case 2:
176 switch (opc2) {
177 case 0:
178 return MISCREG_ID_ISAR0;
179 case 1:
180 return MISCREG_ID_ISAR1;
181 case 2:
182 return MISCREG_ID_ISAR2;
183 case 3:
184 return MISCREG_ID_ISAR3;
185 case 4:
186 return MISCREG_ID_ISAR4;
187 case 5:
188 return MISCREG_ID_ISAR5;
189 case 6:
190 case 7:
191 return MISCREG_RAZ; // read as zero
192 }
193 break;
194 default:
195 return MISCREG_RAZ; // read as zero
196 }
197 break;
198 case 1:
199 if (crm == 0) {
200 switch (opc2) {
201 case 0:
202 return MISCREG_CCSIDR;
203 case 1:
204 return MISCREG_CLIDR;
205 case 7:
206 return MISCREG_AIDR;
207 }
208 }
209 break;
210 case 2:
211 if (crm == 0 && opc2 == 0) {
212 return MISCREG_CSSELR;
213 }
214 break;
215 case 4:
216 if (crm == 0) {
217 if (opc2 == 0)
218 return MISCREG_VPIDR;
219 else if (opc2 == 5)
220 return MISCREG_VMPIDR;
221 }
222 break;
223 }
224 break;
225 case 1:
226 if (opc1 == 0) {
227 if (crm == 0) {
228 switch (opc2) {
229 case 0:
230 return MISCREG_SCTLR;
231 case 1:
232 return MISCREG_ACTLR;
233 case 0x2:
234 return MISCREG_CPACR;
235 }
236 } else if (crm == 1) {
237 switch (opc2) {
238 case 0:
239 return MISCREG_SCR;
240 case 1:
241 return MISCREG_SDER;
242 case 2:
243 return MISCREG_NSACR;
244 }
245 }
246 } else if (opc1 == 4) {
247 if (crm == 0) {
248 if (opc2 == 0)
249 return MISCREG_HSCTLR;
250 else if (opc2 == 1)
251 return MISCREG_HACTLR;
252 } else if (crm == 1) {
253 switch (opc2) {
254 case 0:
255 return MISCREG_HCR;
256 case 1:
257 return MISCREG_HDCR;
258 case 2:
259 return MISCREG_HCPTR;
260 case 3:
261 return MISCREG_HSTR;
262 case 7:
263 return MISCREG_HACR;
264 }
265 }
266 }
267 break;
268 case 2:
269 if (opc1 == 0 && crm == 0) {
270 switch (opc2) {
271 case 0:
272 return MISCREG_TTBR0;
273 case 1:
274 return MISCREG_TTBR1;
275 case 2:
276 return MISCREG_TTBCR;
277 }
278 } else if (opc1 == 4) {
279 if (crm == 0 && opc2 == 2)
280 return MISCREG_HTCR;
281 else if (crm == 1 && opc2 == 2)
282 return MISCREG_VTCR;
283 }
284 break;
285 case 3:
286 if (opc1 == 0 && crm == 0 && opc2 == 0) {
287 return MISCREG_DACR;
288 }
289 break;
290 case 5:
291 if (opc1 == 0) {
292 if (crm == 0) {
293 if (opc2 == 0) {
294 return MISCREG_DFSR;
295 } else if (opc2 == 1) {
296 return MISCREG_IFSR;
297 }
298 } else if (crm == 1) {
299 if (opc2 == 0) {
300 return MISCREG_ADFSR;
301 } else if (opc2 == 1) {
302 return MISCREG_AIFSR;
303 }
304 }
305 } else if (opc1 == 4) {
306 if (crm == 1) {
307 if (opc2 == 0)
308 return MISCREG_HADFSR;
309 else if (opc2 == 1)
310 return MISCREG_HAIFSR;
311 } else if (crm == 2 && opc2 == 0) {
312 return MISCREG_HSR;
313 }
314 }
315 break;
316 case 6:
317 if (opc1 == 0 && crm == 0) {
318 switch (opc2) {
319 case 0:
320 return MISCREG_DFAR;
321 case 2:
322 return MISCREG_IFAR;
323 }
324 } else if (opc1 == 4 && crm == 0) {
325 switch (opc2) {
326 case 0:
327 return MISCREG_HDFAR;
328 case 2:
329 return MISCREG_HIFAR;
330 case 4:
331 return MISCREG_HPFAR;
332 }
333 }
334 break;
335 case 7:
336 if (opc1 == 0) {
337 switch (crm) {
338 case 0:
339 if (opc2 == 4) {
340 return MISCREG_NOP;
341 }
342 break;
343 case 1:
344 switch (opc2) {
345 case 0:
346 return MISCREG_ICIALLUIS;
347 case 6:
348 return MISCREG_BPIALLIS;
349 }
350 break;
351 case 4:
352 if (opc2 == 0) {
353 return MISCREG_PAR;
354 }
355 break;
356 case 5:
357 switch (opc2) {
358 case 0:
359 return MISCREG_ICIALLU;
360 case 1:
361 return MISCREG_ICIMVAU;
362 case 4:
363 return MISCREG_CP15ISB;
364 case 6:
365 return MISCREG_BPIALL;
366 case 7:
367 return MISCREG_BPIMVA;
368 }
369 break;
370 case 6:
371 if (opc2 == 1) {
372 return MISCREG_DCIMVAC;
373 } else if (opc2 == 2) {
374 return MISCREG_DCISW;
375 }
376 break;
377 case 8:
378 switch (opc2) {
379 case 0:
380 return MISCREG_ATS1CPR;
381 case 1:
382 return MISCREG_ATS1CPW;
383 case 2:
384 return MISCREG_ATS1CUR;
385 case 3:
386 return MISCREG_ATS1CUW;
387 case 4:
388 return MISCREG_ATS12NSOPR;
389 case 5:
390 return MISCREG_ATS12NSOPW;
391 case 6:
392 return MISCREG_ATS12NSOUR;
393 case 7:
394 return MISCREG_ATS12NSOUW;
395 }
396 break;
397 case 10:
398 switch (opc2) {
399 case 1:
400 return MISCREG_DCCMVAC;
401 case 2:
402 return MISCREG_DCCSW;
403 case 4:
404 return MISCREG_CP15DSB;
405 case 5:
406 return MISCREG_CP15DMB;
407 }
408 break;
409 case 11:
410 if (opc2 == 1) {
411 return MISCREG_DCCMVAU;
412 }
413 break;
414 case 13:
415 if (opc2 == 1) {
416 return MISCREG_NOP;
417 }
418 break;
419 case 14:
420 if (opc2 == 1) {
421 return MISCREG_DCCIMVAC;
422 } else if (opc2 == 2) {
423 return MISCREG_DCCISW;
424 }
425 break;
426 }
427 } else if (opc1 == 4 && crm == 8) {
428 if (opc2 == 0)
429 return MISCREG_ATS1HR;
430 else if (opc2 == 1)
431 return MISCREG_ATS1HW;
432 }
433 break;
434 case 8:
435 if (opc1 == 0) {
436 switch (crm) {
437 case 3:
438 switch (opc2) {
439 case 0:
440 return MISCREG_TLBIALLIS;
441 case 1:
442 return MISCREG_TLBIMVAIS;
443 case 2:
444 return MISCREG_TLBIASIDIS;
445 case 3:
446 return MISCREG_TLBIMVAAIS;
447 case 5:
448 return MISCREG_TLBIMVALIS;
449 case 7:
450 return MISCREG_TLBIMVAALIS;
451 }
452 break;
453 case 5:
454 switch (opc2) {
455 case 0:
456 return MISCREG_ITLBIALL;
457 case 1:
458 return MISCREG_ITLBIMVA;
459 case 2:
460 return MISCREG_ITLBIASID;
461 }
462 break;
463 case 6:
464 switch (opc2) {
465 case 0:
466 return MISCREG_DTLBIALL;
467 case 1:
468 return MISCREG_DTLBIMVA;
469 case 2:
470 return MISCREG_DTLBIASID;
471 }
472 break;
473 case 7:
474 switch (opc2) {
475 case 0:
476 return MISCREG_TLBIALL;
477 case 1:
478 return MISCREG_TLBIMVA;
479 case 2:
480 return MISCREG_TLBIASID;
481 case 3:
482 return MISCREG_TLBIMVAA;
483 case 5:
484 return MISCREG_TLBIMVAL;
485 case 7:
486 return MISCREG_TLBIMVAAL;
487 }
488 break;
489 }
490 } else if (opc1 == 4) {
491 if (crm == 0) {
492 switch (opc2) {
493 case 1:
494 return MISCREG_TLBIIPAS2IS;
495 case 5:
496 return MISCREG_TLBIIPAS2LIS;
497 }
498 } else if (crm == 3) {
499 switch (opc2) {
500 case 0:
501 return MISCREG_TLBIALLHIS;
502 case 1:
503 return MISCREG_TLBIMVAHIS;
504 case 4:
505 return MISCREG_TLBIALLNSNHIS;
506 case 5:
507 return MISCREG_TLBIMVALHIS;
508 }
509 } else if (crm == 4) {
510 switch (opc2) {
511 case 1:
512 return MISCREG_TLBIIPAS2;
513 case 5:
514 return MISCREG_TLBIIPAS2L;
515 }
516 } else if (crm == 7) {
517 switch (opc2) {
518 case 0:
519 return MISCREG_TLBIALLH;
520 case 1:
521 return MISCREG_TLBIMVAH;
522 case 4:
523 return MISCREG_TLBIALLNSNH;
524 case 5:
525 return MISCREG_TLBIMVALH;
526 }
527 }
528 }
529 break;
530 case 9:
531 // Every cop register with CRn = 9 and CRm in
532 // {0-2}, {5-8} is implementation defined regardless
533 // of opc1 and opc2.
534 switch (crm) {
535 case 0:
536 case 1:
537 case 2:
538 case 5:
539 case 6:
540 case 7:
541 case 8:
542 return MISCREG_IMPDEF_UNIMPL;
543 }
544 if (opc1 == 0) {
545 switch (crm) {
546 case 12:
547 switch (opc2) {
548 case 0:
549 return MISCREG_PMCR;
550 case 1:
551 return MISCREG_PMCNTENSET;
552 case 2:
553 return MISCREG_PMCNTENCLR;
554 case 3:
555 return MISCREG_PMOVSR;
556 case 4:
557 return MISCREG_PMSWINC;
558 case 5:
559 return MISCREG_PMSELR;
560 case 6:
561 return MISCREG_PMCEID0;
562 case 7:
563 return MISCREG_PMCEID1;
564 }
565 break;
566 case 13:
567 switch (opc2) {
568 case 0:
569 return MISCREG_PMCCNTR;
570 case 1:
571 // Selector is PMSELR.SEL
572 return MISCREG_PMXEVTYPER_PMCCFILTR;
573 case 2:
574 return MISCREG_PMXEVCNTR;
575 }
576 break;
577 case 14:
578 switch (opc2) {
579 case 0:
580 return MISCREG_PMUSERENR;
581 case 1:
582 return MISCREG_PMINTENSET;
583 case 2:
584 return MISCREG_PMINTENCLR;
585 case 3:
586 return MISCREG_PMOVSSET;
587 }
588 break;
589 }
590 } else if (opc1 == 1) {
591 switch (crm) {
592 case 0:
593 switch (opc2) {
594 case 2: // L2CTLR, L2 Control Register
595 return MISCREG_L2CTLR;
596 case 3:
597 return MISCREG_L2ECTLR;
598 }
599 break;
600 break;
601 }
602 }
603 break;
604 case 10:
605 if (opc1 == 0) {
606 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
607 if (crm < 2) {
608 return MISCREG_IMPDEF_UNIMPL;
609 } else if (crm == 2) { // TEX Remap Registers
610 if (opc2 == 0) {
611 // Selector is TTBCR.EAE
612 return MISCREG_PRRR_MAIR0;
613 } else if (opc2 == 1) {
614 // Selector is TTBCR.EAE
615 return MISCREG_NMRR_MAIR1;
616 }
617 } else if (crm == 3) {
618 if (opc2 == 0) {
619 return MISCREG_AMAIR0;
620 } else if (opc2 == 1) {
621 return MISCREG_AMAIR1;
622 }
623 }
624 } else if (opc1 == 4) {
625 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
626 if (crm == 2) {
627 if (opc2 == 0)
628 return MISCREG_HMAIR0;
629 else if (opc2 == 1)
630 return MISCREG_HMAIR1;
631 } else if (crm == 3) {
632 if (opc2 == 0)
633 return MISCREG_HAMAIR0;
634 else if (opc2 == 1)
635 return MISCREG_HAMAIR1;
636 }
637 }
638 break;
639 case 11:
640 if (opc1 <=7) {
641 switch (crm) {
642 case 0:
643 case 1:
644 case 2:
645 case 3:
646 case 4:
647 case 5:
648 case 6:
649 case 7:
650 case 8:
651 case 15:
652 // Reserved for DMA operations for TCM access
653 return MISCREG_IMPDEF_UNIMPL;
654 default:
655 break;
656 }
657 }
658 break;
659 case 12:
660 if (opc1 == 0) {
661 if (crm == 0) {
662 if (opc2 == 0) {
663 return MISCREG_VBAR;
664 } else if (opc2 == 1) {
665 return MISCREG_MVBAR;
666 }
667 } else if (crm == 1) {
668 if (opc2 == 0) {
669 return MISCREG_ISR;
670 }
671 }
672 } else if (opc1 == 4) {
673 if (crm == 0 && opc2 == 0)
674 return MISCREG_HVBAR;
675 }
676 break;
677 case 13:
678 if (opc1 == 0) {
679 if (crm == 0) {
680 switch (opc2) {
681 case 0:
682 return MISCREG_FCSEIDR;
683 case 1:
684 return MISCREG_CONTEXTIDR;
685 case 2:
686 return MISCREG_TPIDRURW;
687 case 3:
688 return MISCREG_TPIDRURO;
689 case 4:
690 return MISCREG_TPIDRPRW;
691 }
692 }
693 } else if (opc1 == 4) {
694 if (crm == 0 && opc2 == 2)
695 return MISCREG_HTPIDR;
696 }
697 break;
698 case 14:
699 if (opc1 == 0) {
700 switch (crm) {
701 case 0:
702 if (opc2 == 0)
703 return MISCREG_CNTFRQ;
704 break;
705 case 1:
706 if (opc2 == 0)
707 return MISCREG_CNTKCTL;
708 break;
709 case 2:
710 if (opc2 == 0)
711 return MISCREG_CNTP_TVAL;
712 else if (opc2 == 1)
713 return MISCREG_CNTP_CTL;
714 break;
715 case 3:
716 if (opc2 == 0)
717 return MISCREG_CNTV_TVAL;
718 else if (opc2 == 1)
719 return MISCREG_CNTV_CTL;
720 break;
721 }
722 } else if (opc1 == 4) {
723 if (crm == 1 && opc2 == 0) {
724 return MISCREG_CNTHCTL;
725 } else if (crm == 2) {
726 if (opc2 == 0)
727 return MISCREG_CNTHP_TVAL;
728 else if (opc2 == 1)
729 return MISCREG_CNTHP_CTL;
730 }
731 }
732 break;
733 case 15:
734 // Implementation defined
735 return MISCREG_IMPDEF_UNIMPL;
736 }
737 // Unrecognized register
738 return MISCREG_CP15_UNIMPL;
739}
740
741MiscRegIndex
742decodeCP15Reg64(unsigned crm, unsigned opc1)
743{
744 switch (crm) {
745 case 2:
746 switch (opc1) {
747 case 0:
748 return MISCREG_TTBR0;
749 case 1:
750 return MISCREG_TTBR1;
751 case 4:
752 return MISCREG_HTTBR;
753 case 6:
754 return MISCREG_VTTBR;
755 }
756 break;
757 case 7:
758 if (opc1 == 0)
759 return MISCREG_PAR;
760 break;
761 case 14:
762 switch (opc1) {
763 case 0:
764 return MISCREG_CNTPCT;
765 case 1:
766 return MISCREG_CNTVCT;
767 case 2:
768 return MISCREG_CNTP_CVAL;
769 case 3:
770 return MISCREG_CNTV_CVAL;
771 case 4:
772 return MISCREG_CNTVOFF;
773 case 6:
774 return MISCREG_CNTHP_CVAL;
775 }
776 break;
777 case 15:
778 if (opc1 == 0)
779 return MISCREG_CPUMERRSR;
780 else if (opc1 == 1)
781 return MISCREG_L2MERRSR;
782 break;
783 }
784 // Unrecognized register
785 return MISCREG_CP15_UNIMPL;
786}
787
788std::tuple<bool, bool>
789canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
790{
791 bool secure = !scr.ns;
792 bool canRead = false;
793 bool undefined = false;
794
795 switch (cpsr.mode) {
796 case MODE_USER:
797 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
798 miscRegInfo[reg][MISCREG_USR_NS_RD];
799 break;
800 case MODE_FIQ:
801 case MODE_IRQ:
802 case MODE_SVC:
803 case MODE_ABORT:
804 case MODE_UNDEFINED:
805 case MODE_SYSTEM:
806 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
807 miscRegInfo[reg][MISCREG_PRI_NS_RD];
808 break;
809 case MODE_MON:
810 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
811 miscRegInfo[reg][MISCREG_MON_NS1_RD];
812 break;
813 case MODE_HYP:
814 canRead = miscRegInfo[reg][MISCREG_HYP_RD];
815 break;
816 default:
817 undefined = true;
818 }
819 // can't do permissions checkes on the root of a banked pair of regs
820 assert(!miscRegInfo[reg][MISCREG_BANKED]);
821 return std::make_tuple(canRead, undefined);
822}
823
824std::tuple<bool, bool>
825canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
826{
827 bool secure = !scr.ns;
828 bool canWrite = false;
829 bool undefined = false;
830
831 switch (cpsr.mode) {
832 case MODE_USER:
833 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
834 miscRegInfo[reg][MISCREG_USR_NS_WR];
835 break;
836 case MODE_FIQ:
837 case MODE_IRQ:
838 case MODE_SVC:
839 case MODE_ABORT:
840 case MODE_UNDEFINED:
841 case MODE_SYSTEM:
842 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
843 miscRegInfo[reg][MISCREG_PRI_NS_WR];
844 break;
845 case MODE_MON:
846 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
847 miscRegInfo[reg][MISCREG_MON_NS1_WR];
848 break;
849 case MODE_HYP:
850 canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
851 break;
852 default:
853 undefined = true;
854 }
855 // can't do permissions checkes on the root of a banked pair of regs
856 assert(!miscRegInfo[reg][MISCREG_BANKED]);
857 return std::make_tuple(canWrite, undefined);
858}
859
860int
861snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
862{
863 SCR scr = tc->readMiscReg(MISCREG_SCR);
864 return snsBankedIndex(reg, tc, scr.ns);
865}
866
867int
868snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
869{
870 int reg_as_int = static_cast<int>(reg);
871 if (miscRegInfo[reg][MISCREG_BANKED]) {
872 reg_as_int += (ArmSystem::haveSecurity(tc) &&
873 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
874 }
875 return reg_as_int;
876}
877
878
879/**
880 * If the reg is a child reg of a banked set, then the parent is the last
881 * banked one in the list. This is messy, and the wish is to eventually have
882 * the bitmap replaced with a better data structure. the preUnflatten function
883 * initializes a lookup table to speed up the search for these banked
884 * registers.
885 */
886
887int unflattenResultMiscReg[NUM_MISCREGS];
888
889void
890preUnflattenMiscReg()
891{
892 int reg = -1;
893 for (int i = 0 ; i < NUM_MISCREGS; i++){
894 if (miscRegInfo[i][MISCREG_BANKED])
895 reg = i;
896 if (miscRegInfo[i][MISCREG_BANKED_CHILD])
897 unflattenResultMiscReg[i] = reg;
898 else
899 unflattenResultMiscReg[i] = i;
900 // if this assert fails, no parent was found, and something is broken
901 assert(unflattenResultMiscReg[i] > -1);
902 }
903}
904
905int
906unflattenMiscReg(int reg)
907{
908 return unflattenResultMiscReg[reg];
909}
910
911bool
912canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
913{
914 // Check for SP_EL0 access while SPSEL == 0
915 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
916 return false;
917
918 // Check for RVBAR access
919 if (reg == MISCREG_RVBAR_EL1) {
920 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
921 if (highest_el == EL2 || highest_el == EL3)
922 return false;
923 }
924 if (reg == MISCREG_RVBAR_EL2) {
925 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
926 if (highest_el == EL3)
927 return false;
928 }
929
930 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
931
932 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
933 case EL0:
934 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
935 miscRegInfo[reg][MISCREG_USR_NS_RD];
936 case EL1:
937 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
938 miscRegInfo[reg][MISCREG_PRI_NS_RD];
939 case EL2:
940 return miscRegInfo[reg][MISCREG_HYP_RD];
941 case EL3:
942 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
943 miscRegInfo[reg][MISCREG_MON_NS1_RD];
944 default:
945 panic("Invalid exception level");
946 }
947}
948
949bool
950canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
951{
952 // Check for SP_EL0 access while SPSEL == 0
953 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
954 return false;
955 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
956 if (reg == MISCREG_DAIF) {
957 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
958 if (el == EL0 && !sctlr.uma)
959 return false;
960 }
961 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
962 // In syscall-emulation mode, this test is skipped and DCZVA is always
963 // allowed at EL0
964 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
965 if (el == EL0 && !sctlr.dze)
966 return false;
967 }
968 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
969 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
970 if (el == EL0 && !sctlr.uci)
971 return false;
972 }
973
974 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
975
976 switch (el) {
977 case EL0:
978 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
979 miscRegInfo[reg][MISCREG_USR_NS_WR];
980 case EL1:
981 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
982 miscRegInfo[reg][MISCREG_PRI_NS_WR];
983 case EL2:
984 return miscRegInfo[reg][MISCREG_HYP_WR];
985 case EL3:
986 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
987 miscRegInfo[reg][MISCREG_MON_NS1_WR];
988 default:
989 panic("Invalid exception level");
990 }
991}
992
993MiscRegIndex
994decodeAArch64SysReg(unsigned op0, unsigned op1,
995 unsigned crn, unsigned crm,
996 unsigned op2)
997{
998 switch (op0) {
999 case 1:
1000 switch (crn) {
1001 case 7:
1002 switch (op1) {
1003 case 0:
1004 switch (crm) {
1005 case 1:
1006 switch (op2) {
1007 case 0:
1008 return MISCREG_IC_IALLUIS;
1009 }
1010 break;
1011 case 5:
1012 switch (op2) {
1013 case 0:
1014 return MISCREG_IC_IALLU;
1015 }
1016 break;
1017 case 6:
1018 switch (op2) {
1019 case 1:
1020 return MISCREG_DC_IVAC_Xt;
1021 case 2:
1022 return MISCREG_DC_ISW_Xt;
1023 }
1024 break;
1025 case 8:
1026 switch (op2) {
1027 case 0:
1028 return MISCREG_AT_S1E1R_Xt;
1029 case 1:
1030 return MISCREG_AT_S1E1W_Xt;
1031 case 2:
1032 return MISCREG_AT_S1E0R_Xt;
1033 case 3:
1034 return MISCREG_AT_S1E0W_Xt;
1035 }
1036 break;
1037 case 10:
1038 switch (op2) {
1039 case 2:
1040 return MISCREG_DC_CSW_Xt;
1041 }
1042 break;
1043 case 14:
1044 switch (op2) {
1045 case 2:
1046 return MISCREG_DC_CISW_Xt;
1047 }
1048 break;
1049 }
1050 break;
1051 case 3:
1052 switch (crm) {
1053 case 4:
1054 switch (op2) {
1055 case 1:
1056 return MISCREG_DC_ZVA_Xt;
1057 }
1058 break;
1059 case 5:
1060 switch (op2) {
1061 case 1:
1062 return MISCREG_IC_IVAU_Xt;
1063 }
1064 break;
1065 case 10:
1066 switch (op2) {
1067 case 1:
1068 return MISCREG_DC_CVAC_Xt;
1069 }
1070 break;
1071 case 11:
1072 switch (op2) {
1073 case 1:
1074 return MISCREG_DC_CVAU_Xt;
1075 }
1076 break;
1077 case 14:
1078 switch (op2) {
1079 case 1:
1080 return MISCREG_DC_CIVAC_Xt;
1081 }
1082 break;
1083 }
1084 break;
1085 case 4:
1086 switch (crm) {
1087 case 8:
1088 switch (op2) {
1089 case 0:
1090 return MISCREG_AT_S1E2R_Xt;
1091 case 1:
1092 return MISCREG_AT_S1E2W_Xt;
1093 case 4:
1094 return MISCREG_AT_S12E1R_Xt;
1095 case 5:
1096 return MISCREG_AT_S12E1W_Xt;
1097 case 6:
1098 return MISCREG_AT_S12E0R_Xt;
1099 case 7:
1100 return MISCREG_AT_S12E0W_Xt;
1101 }
1102 break;
1103 }
1104 break;
1105 case 6:
1106 switch (crm) {
1107 case 8:
1108 switch (op2) {
1109 case 0:
1110 return MISCREG_AT_S1E3R_Xt;
1111 case 1:
1112 return MISCREG_AT_S1E3W_Xt;
1113 }
1114 break;
1115 }
1116 break;
1117 }
1118 break;
1119 case 8:
1120 switch (op1) {
1121 case 0:
1122 switch (crm) {
1123 case 3:
1124 switch (op2) {
1125 case 0:
1126 return MISCREG_TLBI_VMALLE1IS;
1127 case 1:
1128 return MISCREG_TLBI_VAE1IS_Xt;
1129 case 2:
1130 return MISCREG_TLBI_ASIDE1IS_Xt;
1131 case 3:
1132 return MISCREG_TLBI_VAAE1IS_Xt;
1133 case 5:
1134 return MISCREG_TLBI_VALE1IS_Xt;
1135 case 7:
1136 return MISCREG_TLBI_VAALE1IS_Xt;
1137 }
1138 break;
1139 case 7:
1140 switch (op2) {
1141 case 0:
1142 return MISCREG_TLBI_VMALLE1;
1143 case 1:
1144 return MISCREG_TLBI_VAE1_Xt;
1145 case 2:
1146 return MISCREG_TLBI_ASIDE1_Xt;
1147 case 3:
1148 return MISCREG_TLBI_VAAE1_Xt;
1149 case 5:
1150 return MISCREG_TLBI_VALE1_Xt;
1151 case 7:
1152 return MISCREG_TLBI_VAALE1_Xt;
1153 }
1154 break;
1155 }
1156 break;
1157 case 4:
1158 switch (crm) {
1159 case 0:
1160 switch (op2) {
1161 case 1:
1162 return MISCREG_TLBI_IPAS2E1IS_Xt;
1163 case 5:
1164 return MISCREG_TLBI_IPAS2LE1IS_Xt;
1165 }
1166 break;
1167 case 3:
1168 switch (op2) {
1169 case 0:
1170 return MISCREG_TLBI_ALLE2IS;
1171 case 1:
1172 return MISCREG_TLBI_VAE2IS_Xt;
1173 case 4:
1174 return MISCREG_TLBI_ALLE1IS;
1175 case 5:
1176 return MISCREG_TLBI_VALE2IS_Xt;
1177 case 6:
1178 return MISCREG_TLBI_VMALLS12E1IS;
1179 }
1180 break;
1181 case 4:
1182 switch (op2) {
1183 case 1:
1184 return MISCREG_TLBI_IPAS2E1_Xt;
1185 case 5:
1186 return MISCREG_TLBI_IPAS2LE1_Xt;
1187 }
1188 break;
1189 case 7:
1190 switch (op2) {
1191 case 0:
1192 return MISCREG_TLBI_ALLE2;
1193 case 1:
1194 return MISCREG_TLBI_VAE2_Xt;
1195 case 4:
1196 return MISCREG_TLBI_ALLE1;
1197 case 5:
1198 return MISCREG_TLBI_VALE2_Xt;
1199 case 6:
1200 return MISCREG_TLBI_VMALLS12E1;
1201 }
1202 break;
1203 }
1204 break;
1205 case 6:
1206 switch (crm) {
1207 case 3:
1208 switch (op2) {
1209 case 0:
1210 return MISCREG_TLBI_ALLE3IS;
1211 case 1:
1212 return MISCREG_TLBI_VAE3IS_Xt;
1213 case 5:
1214 return MISCREG_TLBI_VALE3IS_Xt;
1215 }
1216 break;
1217 case 7:
1218 switch (op2) {
1219 case 0:
1220 return MISCREG_TLBI_ALLE3;
1221 case 1:
1222 return MISCREG_TLBI_VAE3_Xt;
1223 case 5:
1224 return MISCREG_TLBI_VALE3_Xt;
1225 }
1226 break;
1227 }
1228 break;
1229 }
1230 break;
1231 }
1232 break;
1233 case 2:
1234 switch (crn) {
1235 case 0:
1236 switch (op1) {
1237 case 0:
1238 switch (crm) {
1239 case 0:
1240 switch (op2) {
1241 case 2:
1242 return MISCREG_OSDTRRX_EL1;
1243 case 4:
1244 return MISCREG_DBGBVR0_EL1;
1245 case 5:
1246 return MISCREG_DBGBCR0_EL1;
1247 case 6:
1248 return MISCREG_DBGWVR0_EL1;
1249 case 7:
1250 return MISCREG_DBGWCR0_EL1;
1251 }
1252 break;
1253 case 1:
1254 switch (op2) {
1255 case 4:
1256 return MISCREG_DBGBVR1_EL1;
1257 case 5:
1258 return MISCREG_DBGBCR1_EL1;
1259 case 6:
1260 return MISCREG_DBGWVR1_EL1;
1261 case 7:
1262 return MISCREG_DBGWCR1_EL1;
1263 }
1264 break;
1265 case 2:
1266 switch (op2) {
1267 case 0:
1268 return MISCREG_MDCCINT_EL1;
1269 case 2:
1270 return MISCREG_MDSCR_EL1;
1271 case 4:
1272 return MISCREG_DBGBVR2_EL1;
1273 case 5:
1274 return MISCREG_DBGBCR2_EL1;
1275 case 6:
1276 return MISCREG_DBGWVR2_EL1;
1277 case 7:
1278 return MISCREG_DBGWCR2_EL1;
1279 }
1280 break;
1281 case 3:
1282 switch (op2) {
1283 case 2:
1284 return MISCREG_OSDTRTX_EL1;
1285 case 4:
1286 return MISCREG_DBGBVR3_EL1;
1287 case 5:
1288 return MISCREG_DBGBCR3_EL1;
1289 case 6:
1290 return MISCREG_DBGWVR3_EL1;
1291 case 7:
1292 return MISCREG_DBGWCR3_EL1;
1293 }
1294 break;
1295 case 4:
1296 switch (op2) {
1297 case 4:
1298 return MISCREG_DBGBVR4_EL1;
1299 case 5:
1300 return MISCREG_DBGBCR4_EL1;
1301 }
1302 break;
1303 case 5:
1304 switch (op2) {
1305 case 4:
1306 return MISCREG_DBGBVR5_EL1;
1307 case 5:
1308 return MISCREG_DBGBCR5_EL1;
1309 }
1310 break;
1311 case 6:
1312 switch (op2) {
1313 case 2:
1314 return MISCREG_OSECCR_EL1;
1315 }
1316 break;
1317 }
1318 break;
1319 case 2:
1320 switch (crm) {
1321 case 0:
1322 switch (op2) {
1323 case 0:
1324 return MISCREG_TEECR32_EL1;
1325 }
1326 break;
1327 }
1328 break;
1329 case 3:
1330 switch (crm) {
1331 case 1:
1332 switch (op2) {
1333 case 0:
1334 return MISCREG_MDCCSR_EL0;
1335 }
1336 break;
1337 case 4:
1338 switch (op2) {
1339 case 0:
1340 return MISCREG_MDDTR_EL0;
1341 }
1342 break;
1343 case 5:
1344 switch (op2) {
1345 case 0:
1346 return MISCREG_MDDTRRX_EL0;
1347 }
1348 break;
1349 }
1350 break;
1351 case 4:
1352 switch (crm) {
1353 case 7:
1354 switch (op2) {
1355 case 0:
1356 return MISCREG_DBGVCR32_EL2;
1357 }
1358 break;
1359 }
1360 break;
1361 }
1362 break;
1363 case 1:
1364 switch (op1) {
1365 case 0:
1366 switch (crm) {
1367 case 0:
1368 switch (op2) {
1369 case 0:
1370 return MISCREG_MDRAR_EL1;
1371 case 4:
1372 return MISCREG_OSLAR_EL1;
1373 }
1374 break;
1375 case 1:
1376 switch (op2) {
1377 case 4:
1378 return MISCREG_OSLSR_EL1;
1379 }
1380 break;
1381 case 3:
1382 switch (op2) {
1383 case 4:
1384 return MISCREG_OSDLR_EL1;
1385 }
1386 break;
1387 case 4:
1388 switch (op2) {
1389 case 4:
1390 return MISCREG_DBGPRCR_EL1;
1391 }
1392 break;
1393 }
1394 break;
1395 case 2:
1396 switch (crm) {
1397 case 0:
1398 switch (op2) {
1399 case 0:
1400 return MISCREG_TEEHBR32_EL1;
1401 }
1402 break;
1403 }
1404 break;
1405 }
1406 break;
1407 case 7:
1408 switch (op1) {
1409 case 0:
1410 switch (crm) {
1411 case 8:
1412 switch (op2) {
1413 case 6:
1414 return MISCREG_DBGCLAIMSET_EL1;
1415 }
1416 break;
1417 case 9:
1418 switch (op2) {
1419 case 6:
1420 return MISCREG_DBGCLAIMCLR_EL1;
1421 }
1422 break;
1423 case 14:
1424 switch (op2) {
1425 case 6:
1426 return MISCREG_DBGAUTHSTATUS_EL1;
1427 }
1428 break;
1429 }
1430 break;
1431 }
1432 break;
1433 }
1434 break;
1435 case 3:
1436 switch (crn) {
1437 case 0:
1438 switch (op1) {
1439 case 0:
1440 switch (crm) {
1441 case 0:
1442 switch (op2) {
1443 case 0:
1444 return MISCREG_MIDR_EL1;
1445 case 5:
1446 return MISCREG_MPIDR_EL1;
1447 case 6:
1448 return MISCREG_REVIDR_EL1;
1449 }
1450 break;
1451 case 1:
1452 switch (op2) {
1453 case 0:
1454 return MISCREG_ID_PFR0_EL1;
1455 case 1:
1456 return MISCREG_ID_PFR1_EL1;
1457 case 2:
1458 return MISCREG_ID_DFR0_EL1;
1459 case 3:
1460 return MISCREG_ID_AFR0_EL1;
1461 case 4:
1462 return MISCREG_ID_MMFR0_EL1;
1463 case 5:
1464 return MISCREG_ID_MMFR1_EL1;
1465 case 6:
1466 return MISCREG_ID_MMFR2_EL1;
1467 case 7:
1468 return MISCREG_ID_MMFR3_EL1;
1469 }
1470 break;
1471 case 2:
1472 switch (op2) {
1473 case 0:
1474 return MISCREG_ID_ISAR0_EL1;
1475 case 1:
1476 return MISCREG_ID_ISAR1_EL1;
1477 case 2:
1478 return MISCREG_ID_ISAR2_EL1;
1479 case 3:
1480 return MISCREG_ID_ISAR3_EL1;
1481 case 4:
1482 return MISCREG_ID_ISAR4_EL1;
1483 case 5:
1484 return MISCREG_ID_ISAR5_EL1;
1485 }
1486 break;
1487 case 3:
1488 switch (op2) {
1489 case 0:
1490 return MISCREG_MVFR0_EL1;
1491 case 1:
1492 return MISCREG_MVFR1_EL1;
1493 case 2:
1494 return MISCREG_MVFR2_EL1;
1495 case 3 ... 7:
1496 return MISCREG_RAZ;
1497 }
1498 break;
1499 case 4:
1500 switch (op2) {
1501 case 0:
1502 return MISCREG_ID_AA64PFR0_EL1;
1503 case 1:
1504 return MISCREG_ID_AA64PFR1_EL1;
1505 case 2 ... 7:
1506 return MISCREG_RAZ;
1507 }
1508 break;
1509 case 5:
1510 switch (op2) {
1511 case 0:
1512 return MISCREG_ID_AA64DFR0_EL1;
1513 case 1:
1514 return MISCREG_ID_AA64DFR1_EL1;
1515 case 4:
1516 return MISCREG_ID_AA64AFR0_EL1;
1517 case 5:
1518 return MISCREG_ID_AA64AFR1_EL1;
1519 case 2:
1520 case 3:
1521 case 6:
1522 case 7:
1523 return MISCREG_RAZ;
1524 }
1525 break;
1526 case 6:
1527 switch (op2) {
1528 case 0:
1529 return MISCREG_ID_AA64ISAR0_EL1;
1530 case 1:
1531 return MISCREG_ID_AA64ISAR1_EL1;
1532 case 2 ... 7:
1533 return MISCREG_RAZ;
1534 }
1535 break;
1536 case 7:
1537 switch (op2) {
1538 case 0:
1539 return MISCREG_ID_AA64MMFR0_EL1;
1540 case 1:
1541 return MISCREG_ID_AA64MMFR1_EL1;
1542 case 2 ... 7:
1543 return MISCREG_RAZ;
1544 }
1545 break;
1546 }
1547 break;
1548 case 1:
1549 switch (crm) {
1550 case 0:
1551 switch (op2) {
1552 case 0:
1553 return MISCREG_CCSIDR_EL1;
1554 case 1:
1555 return MISCREG_CLIDR_EL1;
1556 case 7:
1557 return MISCREG_AIDR_EL1;
1558 }
1559 break;
1560 }
1561 break;
1562 case 2:
1563 switch (crm) {
1564 case 0:
1565 switch (op2) {
1566 case 0:
1567 return MISCREG_CSSELR_EL1;
1568 }
1569 break;
1570 }
1571 break;
1572 case 3:
1573 switch (crm) {
1574 case 0:
1575 switch (op2) {
1576 case 1:
1577 return MISCREG_CTR_EL0;
1578 case 7:
1579 return MISCREG_DCZID_EL0;
1580 }
1581 break;
1582 }
1583 break;
1584 case 4:
1585 switch (crm) {
1586 case 0:
1587 switch (op2) {
1588 case 0:
1589 return MISCREG_VPIDR_EL2;
1590 case 5:
1591 return MISCREG_VMPIDR_EL2;
1592 }
1593 break;
1594 }
1595 break;
1596 }
1597 break;
1598 case 1:
1599 switch (op1) {
1600 case 0:
1601 switch (crm) {
1602 case 0:
1603 switch (op2) {
1604 case 0:
1605 return MISCREG_SCTLR_EL1;
1606 case 1:
1607 return MISCREG_ACTLR_EL1;
1608 case 2:
1609 return MISCREG_CPACR_EL1;
1610 }
1611 break;
1612 }
1613 break;
1614 case 4:
1615 switch (crm) {
1616 case 0:
1617 switch (op2) {
1618 case 0:
1619 return MISCREG_SCTLR_EL2;
1620 case 1:
1621 return MISCREG_ACTLR_EL2;
1622 }
1623 break;
1624 case 1:
1625 switch (op2) {
1626 case 0:
1627 return MISCREG_HCR_EL2;
1628 case 1:
1629 return MISCREG_MDCR_EL2;
1630 case 2:
1631 return MISCREG_CPTR_EL2;
1632 case 3:
1633 return MISCREG_HSTR_EL2;
1634 case 7:
1635 return MISCREG_HACR_EL2;
1636 }
1637 break;
1638 }
1639 break;
1640 case 6:
1641 switch (crm) {
1642 case 0:
1643 switch (op2) {
1644 case 0:
1645 return MISCREG_SCTLR_EL3;
1646 case 1:
1647 return MISCREG_ACTLR_EL3;
1648 }
1649 break;
1650 case 1:
1651 switch (op2) {
1652 case 0:
1653 return MISCREG_SCR_EL3;
1654 case 1:
1655 return MISCREG_SDER32_EL3;
1656 case 2:
1657 return MISCREG_CPTR_EL3;
1658 }
1659 break;
1660 case 3:
1661 switch (op2) {
1662 case 1:
1663 return MISCREG_MDCR_EL3;
1664 }
1665 break;
1666 }
1667 break;
1668 }
1669 break;
1670 case 2:
1671 switch (op1) {
1672 case 0:
1673 switch (crm) {
1674 case 0:
1675 switch (op2) {
1676 case 0:
1677 return MISCREG_TTBR0_EL1;
1678 case 1:
1679 return MISCREG_TTBR1_EL1;
1680 case 2:
1681 return MISCREG_TCR_EL1;
1682 }
1683 break;
1684 }
1685 break;
1686 case 4:
1687 switch (crm) {
1688 case 0:
1689 switch (op2) {
1690 case 0:
1691 return MISCREG_TTBR0_EL2;
1692 case 1:
1693 return MISCREG_TTBR1_EL2;
1694 case 2:
1695 return MISCREG_TCR_EL2;
1696 }
1697 break;
1698 case 1:
1699 switch (op2) {
1700 case 0:
1701 return MISCREG_VTTBR_EL2;
1702 case 2:
1703 return MISCREG_VTCR_EL2;
1704 }
1705 break;
1706 }
1707 break;
1708 case 6:
1709 switch (crm) {
1710 case 0:
1711 switch (op2) {
1712 case 0:
1713 return MISCREG_TTBR0_EL3;
1714 case 2:
1715 return MISCREG_TCR_EL3;
1716 }
1717 break;
1718 }
1719 break;
1720 }
1721 break;
1722 case 3:
1723 switch (op1) {
1724 case 4:
1725 switch (crm) {
1726 case 0:
1727 switch (op2) {
1728 case 0:
1729 return MISCREG_DACR32_EL2;
1730 }
1731 break;
1732 }
1733 break;
1734 }
1735 break;
1736 case 4:
1737 switch (op1) {
1738 case 0:
1739 switch (crm) {
1740 case 0:
1741 switch (op2) {
1742 case 0:
1743 return MISCREG_SPSR_EL1;
1744 case 1:
1745 return MISCREG_ELR_EL1;
1746 }
1747 break;
1748 case 1:
1749 switch (op2) {
1750 case 0:
1751 return MISCREG_SP_EL0;
1752 }
1753 break;
1754 case 2:
1755 switch (op2) {
1756 case 0:
1757 return MISCREG_SPSEL;
1758 case 2:
1759 return MISCREG_CURRENTEL;
1760 }
1761 break;
1762 }
1763 break;
1764 case 3:
1765 switch (crm) {
1766 case 2:
1767 switch (op2) {
1768 case 0:
1769 return MISCREG_NZCV;
1770 case 1:
1771 return MISCREG_DAIF;
1772 }
1773 break;
1774 case 4:
1775 switch (op2) {
1776 case 0:
1777 return MISCREG_FPCR;
1778 case 1:
1779 return MISCREG_FPSR;
1780 }
1781 break;
1782 case 5:
1783 switch (op2) {
1784 case 0:
1785 return MISCREG_DSPSR_EL0;
1786 case 1:
1787 return MISCREG_DLR_EL0;
1788 }
1789 break;
1790 }
1791 break;
1792 case 4:
1793 switch (crm) {
1794 case 0:
1795 switch (op2) {
1796 case 0:
1797 return MISCREG_SPSR_EL2;
1798 case 1:
1799 return MISCREG_ELR_EL2;
1800 }
1801 break;
1802 case 1:
1803 switch (op2) {
1804 case 0:
1805 return MISCREG_SP_EL1;
1806 }
1807 break;
1808 case 3:
1809 switch (op2) {
1810 case 0:
1811 return MISCREG_SPSR_IRQ_AA64;
1812 case 1:
1813 return MISCREG_SPSR_ABT_AA64;
1814 case 2:
1815 return MISCREG_SPSR_UND_AA64;
1816 case 3:
1817 return MISCREG_SPSR_FIQ_AA64;
1818 }
1819 break;
1820 }
1821 break;
1822 case 6:
1823 switch (crm) {
1824 case 0:
1825 switch (op2) {
1826 case 0:
1827 return MISCREG_SPSR_EL3;
1828 case 1:
1829 return MISCREG_ELR_EL3;
1830 }
1831 break;
1832 case 1:
1833 switch (op2) {
1834 case 0:
1835 return MISCREG_SP_EL2;
1836 }
1837 break;
1838 }
1839 break;
1840 }
1841 break;
1842 case 5:
1843 switch (op1) {
1844 case 0:
1845 switch (crm) {
1846 case 1:
1847 switch (op2) {
1848 case 0:
1849 return MISCREG_AFSR0_EL1;
1850 case 1:
1851 return MISCREG_AFSR1_EL1;
1852 }
1853 break;
1854 case 2:
1855 switch (op2) {
1856 case 0:
1857 return MISCREG_ESR_EL1;
1858 }
1859 break;
1860 }
1861 break;
1862 case 4:
1863 switch (crm) {
1864 case 0:
1865 switch (op2) {
1866 case 1:
1867 return MISCREG_IFSR32_EL2;
1868 }
1869 break;
1870 case 1:
1871 switch (op2) {
1872 case 0:
1873 return MISCREG_AFSR0_EL2;
1874 case 1:
1875 return MISCREG_AFSR1_EL2;
1876 }
1877 break;
1878 case 2:
1879 switch (op2) {
1880 case 0:
1881 return MISCREG_ESR_EL2;
1882 }
1883 break;
1884 case 3:
1885 switch (op2) {
1886 case 0:
1887 return MISCREG_FPEXC32_EL2;
1888 }
1889 break;
1890 }
1891 break;
1892 case 6:
1893 switch (crm) {
1894 case 1:
1895 switch (op2) {
1896 case 0:
1897 return MISCREG_AFSR0_EL3;
1898 case 1:
1899 return MISCREG_AFSR1_EL3;
1900 }
1901 break;
1902 case 2:
1903 switch (op2) {
1904 case 0:
1905 return MISCREG_ESR_EL3;
1906 }
1907 break;
1908 }
1909 break;
1910 }
1911 break;
1912 case 6:
1913 switch (op1) {
1914 case 0:
1915 switch (crm) {
1916 case 0:
1917 switch (op2) {
1918 case 0:
1919 return MISCREG_FAR_EL1;
1920 }
1921 break;
1922 }
1923 break;
1924 case 4:
1925 switch (crm) {
1926 case 0:
1927 switch (op2) {
1928 case 0:
1929 return MISCREG_FAR_EL2;
1930 case 4:
1931 return MISCREG_HPFAR_EL2;
1932 }
1933 break;
1934 }
1935 break;
1936 case 6:
1937 switch (crm) {
1938 case 0:
1939 switch (op2) {
1940 case 0:
1941 return MISCREG_FAR_EL3;
1942 }
1943 break;
1944 }
1945 break;
1946 }
1947 break;
1948 case 7:
1949 switch (op1) {
1950 case 0:
1951 switch (crm) {
1952 case 4:
1953 switch (op2) {
1954 case 0:
1955 return MISCREG_PAR_EL1;
1956 }
1957 break;
1958 }
1959 break;
1960 }
1961 break;
1962 case 9:
1963 switch (op1) {
1964 case 0:
1965 switch (crm) {
1966 case 14:
1967 switch (op2) {
1968 case 1:
1969 return MISCREG_PMINTENSET_EL1;
1970 case 2:
1971 return MISCREG_PMINTENCLR_EL1;
1972 }
1973 break;
1974 }
1975 break;
1976 case 3:
1977 switch (crm) {
1978 case 12:
1979 switch (op2) {
1980 case 0:
1981 return MISCREG_PMCR_EL0;
1982 case 1:
1983 return MISCREG_PMCNTENSET_EL0;
1984 case 2:
1985 return MISCREG_PMCNTENCLR_EL0;
1986 case 3:
1987 return MISCREG_PMOVSCLR_EL0;
1988 case 4:
1989 return MISCREG_PMSWINC_EL0;
1990 case 5:
1991 return MISCREG_PMSELR_EL0;
1992 case 6:
1993 return MISCREG_PMCEID0_EL0;
1994 case 7:
1995 return MISCREG_PMCEID1_EL0;
1996 }
1997 break;
1998 case 13:
1999 switch (op2) {
2000 case 0:
2001 return MISCREG_PMCCNTR_EL0;
2002 case 1:
2003 return MISCREG_PMXEVTYPER_EL0;
2004 case 2:
2005 return MISCREG_PMXEVCNTR_EL0;
2006 }
2007 break;
2008 case 14:
2009 switch (op2) {
2010 case 0:
2011 return MISCREG_PMUSERENR_EL0;
2012 case 3:
2013 return MISCREG_PMOVSSET_EL0;
2014 }
2015 break;
2016 }
2017 break;
2018 }
2019 break;
2020 case 10:
2021 switch (op1) {
2022 case 0:
2023 switch (crm) {
2024 case 2:
2025 switch (op2) {
2026 case 0:
2027 return MISCREG_MAIR_EL1;
2028 }
2029 break;
2030 case 3:
2031 switch (op2) {
2032 case 0:
2033 return MISCREG_AMAIR_EL1;
2034 }
2035 break;
2036 }
2037 break;
2038 case 4:
2039 switch (crm) {
2040 case 2:
2041 switch (op2) {
2042 case 0:
2043 return MISCREG_MAIR_EL2;
2044 }
2045 break;
2046 case 3:
2047 switch (op2) {
2048 case 0:
2049 return MISCREG_AMAIR_EL2;
2050 }
2051 break;
2052 }
2053 break;
2054 case 6:
2055 switch (crm) {
2056 case 2:
2057 switch (op2) {
2058 case 0:
2059 return MISCREG_MAIR_EL3;
2060 }
2061 break;
2062 case 3:
2063 switch (op2) {
2064 case 0:
2065 return MISCREG_AMAIR_EL3;
2066 }
2067 break;
2068 }
2069 break;
2070 }
2071 break;
2072 case 11:
2073 switch (op1) {
2074 case 1:
2075 switch (crm) {
2076 case 0:
2077 switch (op2) {
2078 case 2:
2079 return MISCREG_L2CTLR_EL1;
2080 case 3:
2081 return MISCREG_L2ECTLR_EL1;
2082 }
2083 break;
2084 }
2085 M5_FALLTHROUGH;
2086 default:
2087 // S3_<op1>_11_<Cm>_<op2>
2088 return MISCREG_IMPDEF_UNIMPL;
2089 }
2090 M5_UNREACHABLE;
2091 case 12:
2092 switch (op1) {
2093 case 0:
2094 switch (crm) {
2095 case 0:
2096 switch (op2) {
2097 case 0:
2098 return MISCREG_VBAR_EL1;
2099 case 1:
2100 return MISCREG_RVBAR_EL1;
2101 }
2102 break;
2103 case 1:
2104 switch (op2) {
2105 case 0:
2106 return MISCREG_ISR_EL1;
2107 }
2108 break;
2109 }
2110 break;
2111 case 4:
2112 switch (crm) {
2113 case 0:
2114 switch (op2) {
2115 case 0:
2116 return MISCREG_VBAR_EL2;
2117 case 1:
2118 return MISCREG_RVBAR_EL2;
2119 }
2120 break;
2121 }
2122 break;
2123 case 6:
2124 switch (crm) {
2125 case 0:
2126 switch (op2) {
2127 case 0:
2128 return MISCREG_VBAR_EL3;
2129 case 1:
2130 return MISCREG_RVBAR_EL3;
2131 case 2:
2132 return MISCREG_RMR_EL3;
2133 }
2134 break;
2135 }
2136 break;
2137 }
2138 break;
2139 case 13:
2140 switch (op1) {
2141 case 0:
2142 switch (crm) {
2143 case 0:
2144 switch (op2) {
2145 case 1:
2146 return MISCREG_CONTEXTIDR_EL1;
2147 case 4:
2148 return MISCREG_TPIDR_EL1;
2149 }
2150 break;
2151 }
2152 break;
2153 case 3:
2154 switch (crm) {
2155 case 0:
2156 switch (op2) {
2157 case 2:
2158 return MISCREG_TPIDR_EL0;
2159 case 3:
2160 return MISCREG_TPIDRRO_EL0;
2161 }
2162 break;
2163 }
2164 break;
2165 case 4:
2166 switch (crm) {
2167 case 0:
2168 switch (op2) {
2169 case 1:
2170 return MISCREG_CONTEXTIDR_EL2;
2171 case 2:
2172 return MISCREG_TPIDR_EL2;
2173 }
2174 break;
2175 }
2176 break;
2177 case 6:
2178 switch (crm) {
2179 case 0:
2180 switch (op2) {
2181 case 2:
2182 return MISCREG_TPIDR_EL3;
2183 }
2184 break;
2185 }
2186 break;
2187 }
2188 break;
2189 case 14:
2190 switch (op1) {
2191 case 0:
2192 switch (crm) {
2193 case 1:
2194 switch (op2) {
2195 case 0:
2196 return MISCREG_CNTKCTL_EL1;
2197 }
2198 break;
2199 }
2200 break;
2201 case 3:
2202 switch (crm) {
2203 case 0:
2204 switch (op2) {
2205 case 0:
2206 return MISCREG_CNTFRQ_EL0;
2207 case 1:
2208 return MISCREG_CNTPCT_EL0;
2209 case 2:
2210 return MISCREG_CNTVCT_EL0;
2211 }
2212 break;
2213 case 2:
2214 switch (op2) {
2215 case 0:
2216 return MISCREG_CNTP_TVAL_EL0;
2217 case 1:
2218 return MISCREG_CNTP_CTL_EL0;
2219 case 2:
2220 return MISCREG_CNTP_CVAL_EL0;
2221 }
2222 break;
2223 case 3:
2224 switch (op2) {
2225 case 0:
2226 return MISCREG_CNTV_TVAL_EL0;
2227 case 1:
2228 return MISCREG_CNTV_CTL_EL0;
2229 case 2:
2230 return MISCREG_CNTV_CVAL_EL0;
2231 }
2232 break;
2233 case 8:
2234 switch (op2) {
2235 case 0:
2236 return MISCREG_PMEVCNTR0_EL0;
2237 case 1:
2238 return MISCREG_PMEVCNTR1_EL0;
2239 case 2:
2240 return MISCREG_PMEVCNTR2_EL0;
2241 case 3:
2242 return MISCREG_PMEVCNTR3_EL0;
2243 case 4:
2244 return MISCREG_PMEVCNTR4_EL0;
2245 case 5:
2246 return MISCREG_PMEVCNTR5_EL0;
2247 }
2248 break;
2249 case 12:
2250 switch (op2) {
2251 case 0:
2252 return MISCREG_PMEVTYPER0_EL0;
2253 case 1:
2254 return MISCREG_PMEVTYPER1_EL0;
2255 case 2:
2256 return MISCREG_PMEVTYPER2_EL0;
2257 case 3:
2258 return MISCREG_PMEVTYPER3_EL0;
2259 case 4:
2260 return MISCREG_PMEVTYPER4_EL0;
2261 case 5:
2262 return MISCREG_PMEVTYPER5_EL0;
2263 }
2264 break;
2265 case 15:
2266 switch (op2) {
2267 case 7:
2268 return MISCREG_PMCCFILTR_EL0;
2269 }
2270 }
2271 break;
2272 case 4:
2273 switch (crm) {
2274 case 0:
2275 switch (op2) {
2276 case 3:
2277 return MISCREG_CNTVOFF_EL2;
2278 }
2279 break;
2280 case 1:
2281 switch (op2) {
2282 case 0:
2283 return MISCREG_CNTHCTL_EL2;
2284 }
2285 break;
2286 case 2:
2287 switch (op2) {
2288 case 0:
2289 return MISCREG_CNTHP_TVAL_EL2;
2290 case 1:
2291 return MISCREG_CNTHP_CTL_EL2;
2292 case 2:
2293 return MISCREG_CNTHP_CVAL_EL2;
2294 }
2295 break;
2296 }
2297 break;
2298 case 7:
2299 switch (crm) {
2300 case 2:
2301 switch (op2) {
2302 case 0:
2303 return MISCREG_CNTPS_TVAL_EL1;
2304 case 1:
2305 return MISCREG_CNTPS_CTL_EL1;
2306 case 2:
2307 return MISCREG_CNTPS_CVAL_EL1;
2308 }
2309 break;
2310 }
2311 break;
2312 }
2313 break;
2314 case 15:
2315 switch (op1) {
2316 case 0:
2317 switch (crm) {
2318 case 0:
2319 switch (op2) {
2320 case 0:
2321 return MISCREG_IL1DATA0_EL1;
2322 case 1:
2323 return MISCREG_IL1DATA1_EL1;
2324 case 2:
2325 return MISCREG_IL1DATA2_EL1;
2326 case 3:
2327 return MISCREG_IL1DATA3_EL1;
2328 }
2329 break;
2330 case 1:
2331 switch (op2) {
2332 case 0:
2333 return MISCREG_DL1DATA0_EL1;
2334 case 1:
2335 return MISCREG_DL1DATA1_EL1;
2336 case 2:
2337 return MISCREG_DL1DATA2_EL1;
2338 case 3:
2339 return MISCREG_DL1DATA3_EL1;
2340 case 4:
2341 return MISCREG_DL1DATA4_EL1;
2342 }
2343 break;
2344 }
2345 break;
2346 case 1:
2347 switch (crm) {
2348 case 0:
2349 switch (op2) {
2350 case 0:
2351 return MISCREG_L2ACTLR_EL1;
2352 }
2353 break;
2354 case 2:
2355 switch (op2) {
2356 case 0:
2357 return MISCREG_CPUACTLR_EL1;
2358 case 1:
2359 return MISCREG_CPUECTLR_EL1;
2360 case 2:
2361 return MISCREG_CPUMERRSR_EL1;
2362 case 3:
2363 return MISCREG_L2MERRSR_EL1;
2364 }
2365 break;
2366 case 3:
2367 switch (op2) {
2368 case 0:
2369 return MISCREG_CBAR_EL1;
2370
2371 }
2372 break;
2373 }
2374 break;
2375 }
2376 // S3_<op1>_15_<Cm>_<op2>
2377 return MISCREG_IMPDEF_UNIMPL;
2378 }
2379 break;
2380 }
2381
2382 return MISCREG_UNKNOWN;
2383}
2384
2385bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2386
2387void
2388ISA::initializeMiscRegMetadata()
2389{
2390 // the MiscReg metadata tables are shared across all instances of the
2391 // ISA object, so there's no need to initialize them multiple times.
2392 static bool completed = false;
2393 if (completed)
2394 return;
2395
2396 // This boolean variable specifies if the system is running in aarch32 at
2397 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2398 // is running in aarch64 (aarch32EL3 = false)
2399 bool aarch32EL3 = haveSecurity && !highestELIs64;
2400
2401 /**
2402 * Some registers alias with others, and therefore need to be translated.
2403 * When two mapping registers are given, they are the 32b lower and
2404 * upper halves, respectively, of the 64b register being mapped.
2405 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2406 *
2407 * NAM = "not architecturally mandated",
2408 * from ARM DDI 0487A.i, template text
2409 * "AArch64 System register ___ can be mapped to
2410 * AArch32 System register ___, but this is not
2411 * architecturally mandated."
2412 */
2413
2414 InitReg(MISCREG_CPSR)
2415 .allPrivileges();
2416 InitReg(MISCREG_SPSR)
2417 .allPrivileges();
2418 InitReg(MISCREG_SPSR_FIQ)
2419 .allPrivileges();
2420 InitReg(MISCREG_SPSR_IRQ)
2421 .allPrivileges();
2422 InitReg(MISCREG_SPSR_SVC)
2423 .allPrivileges();
2424 InitReg(MISCREG_SPSR_MON)
2425 .allPrivileges();
2426 InitReg(MISCREG_SPSR_ABT)
2427 .allPrivileges();
2428 InitReg(MISCREG_SPSR_HYP)
2429 .allPrivileges();
2430 InitReg(MISCREG_SPSR_UND)
2431 .allPrivileges();
2432 InitReg(MISCREG_ELR_HYP)
2433 .allPrivileges();
2434 InitReg(MISCREG_FPSID)
2435 .allPrivileges();
2436 InitReg(MISCREG_FPSCR)
2437 .allPrivileges();
2438 InitReg(MISCREG_MVFR1)
2439 .allPrivileges();
2440 InitReg(MISCREG_MVFR0)
2441 .allPrivileges();
2442 InitReg(MISCREG_FPEXC)
2443 .allPrivileges();
2444
2445 // Helper registers
2446 InitReg(MISCREG_CPSR_MODE)
2447 .allPrivileges();
2448 InitReg(MISCREG_CPSR_Q)
2449 .allPrivileges();
2450 InitReg(MISCREG_FPSCR_EXC)
2451 .allPrivileges();
2452 InitReg(MISCREG_FPSCR_QC)
2453 .allPrivileges();
2454 InitReg(MISCREG_LOCKADDR)
2455 .allPrivileges();
2456 InitReg(MISCREG_LOCKFLAG)
2457 .allPrivileges();
2458 InitReg(MISCREG_PRRR_MAIR0)
2459 .mutex()
2460 .banked();
2461 InitReg(MISCREG_PRRR_MAIR0_NS)
2462 .mutex()
2463 .privSecure(!aarch32EL3)
2464 .bankedChild();
2465 InitReg(MISCREG_PRRR_MAIR0_S)
2466 .mutex()
2467 .bankedChild();
2468 InitReg(MISCREG_NMRR_MAIR1)
2469 .mutex()
2470 .banked();
2471 InitReg(MISCREG_NMRR_MAIR1_NS)
2472 .mutex()
2473 .privSecure(!aarch32EL3)
2474 .bankedChild();
2475 InitReg(MISCREG_NMRR_MAIR1_S)
2476 .mutex()
2477 .bankedChild();
2478 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2479 .mutex();
2480 InitReg(MISCREG_SCTLR_RST)
2481 .allPrivileges();
2482 InitReg(MISCREG_SEV_MAILBOX)
2483 .allPrivileges();
2484
2485 // AArch32 CP14 registers
2486 InitReg(MISCREG_DBGDIDR)
2487 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2488 InitReg(MISCREG_DBGDSCRint)
2489 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2490 InitReg(MISCREG_DBGDCCINT)
2491 .unimplemented()
2492 .allPrivileges();
2493 InitReg(MISCREG_DBGDTRTXint)
2494 .unimplemented()
2495 .allPrivileges();
2496 InitReg(MISCREG_DBGDTRRXint)
2497 .unimplemented()
2498 .allPrivileges();
2499 InitReg(MISCREG_DBGWFAR)
2500 .unimplemented()
2501 .allPrivileges();
2502 InitReg(MISCREG_DBGVCR)
2503 .unimplemented()
2504 .allPrivileges();
2505 InitReg(MISCREG_DBGDTRRXext)
2506 .unimplemented()
2507 .allPrivileges();
2508 InitReg(MISCREG_DBGDSCRext)
2509 .unimplemented()
2510 .warnNotFail()
2511 .allPrivileges();
2512 InitReg(MISCREG_DBGDTRTXext)
2513 .unimplemented()
2514 .allPrivileges();
2515 InitReg(MISCREG_DBGOSECCR)
2516 .unimplemented()
2517 .allPrivileges();
2518 InitReg(MISCREG_DBGBVR0)
2519 .unimplemented()
2520 .allPrivileges();
2521 InitReg(MISCREG_DBGBVR1)
2522 .unimplemented()
2523 .allPrivileges();
2524 InitReg(MISCREG_DBGBVR2)
2525 .unimplemented()
2526 .allPrivileges();
2527 InitReg(MISCREG_DBGBVR3)
2528 .unimplemented()
2529 .allPrivileges();
2530 InitReg(MISCREG_DBGBVR4)
2531 .unimplemented()
2532 .allPrivileges();
2533 InitReg(MISCREG_DBGBVR5)
2534 .unimplemented()
2535 .allPrivileges();
2536 InitReg(MISCREG_DBGBCR0)
2537 .unimplemented()
2538 .allPrivileges();
2539 InitReg(MISCREG_DBGBCR1)
2540 .unimplemented()
2541 .allPrivileges();
2542 InitReg(MISCREG_DBGBCR2)
2543 .unimplemented()
2544 .allPrivileges();
2545 InitReg(MISCREG_DBGBCR3)
2546 .unimplemented()
2547 .allPrivileges();
2548 InitReg(MISCREG_DBGBCR4)
2549 .unimplemented()
2550 .allPrivileges();
2551 InitReg(MISCREG_DBGBCR5)
2552 .unimplemented()
2553 .allPrivileges();
2554 InitReg(MISCREG_DBGWVR0)
2555 .unimplemented()
2556 .allPrivileges();
2557 InitReg(MISCREG_DBGWVR1)
2558 .unimplemented()
2559 .allPrivileges();
2560 InitReg(MISCREG_DBGWVR2)
2561 .unimplemented()
2562 .allPrivileges();
2563 InitReg(MISCREG_DBGWVR3)
2564 .unimplemented()
2565 .allPrivileges();
2566 InitReg(MISCREG_DBGWCR0)
2567 .unimplemented()
2568 .allPrivileges();
2569 InitReg(MISCREG_DBGWCR1)
2570 .unimplemented()
2571 .allPrivileges();
2572 InitReg(MISCREG_DBGWCR2)
2573 .unimplemented()
2574 .allPrivileges();
2575 InitReg(MISCREG_DBGWCR3)
2576 .unimplemented()
2577 .allPrivileges();
2578 InitReg(MISCREG_DBGDRAR)
2579 .unimplemented()
2580 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2581 InitReg(MISCREG_DBGBXVR4)
2582 .unimplemented()
2583 .allPrivileges();
2584 InitReg(MISCREG_DBGBXVR5)
2585 .unimplemented()
2586 .allPrivileges();
2587 InitReg(MISCREG_DBGOSLAR)
2588 .unimplemented()
2589 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
2590 InitReg(MISCREG_DBGOSLSR)
2591 .unimplemented()
2592 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2593 InitReg(MISCREG_DBGOSDLR)
2594 .unimplemented()
2595 .allPrivileges();
2596 InitReg(MISCREG_DBGPRCR)
2597 .unimplemented()
2598 .allPrivileges();
2599 InitReg(MISCREG_DBGDSAR)
2600 .unimplemented()
2601 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2602 InitReg(MISCREG_DBGCLAIMSET)
2603 .unimplemented()
2604 .allPrivileges();
2605 InitReg(MISCREG_DBGCLAIMCLR)
2606 .unimplemented()
2607 .allPrivileges();
2608 InitReg(MISCREG_DBGAUTHSTATUS)
2609 .unimplemented()
2610 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2611 InitReg(MISCREG_DBGDEVID2)
2612 .unimplemented()
2613 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2614 InitReg(MISCREG_DBGDEVID1)
2615 .unimplemented()
2616 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2617 InitReg(MISCREG_DBGDEVID0)
2618 .unimplemented()
2619 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2620 InitReg(MISCREG_TEECR)
2621 .unimplemented()
2622 .allPrivileges();
2623 InitReg(MISCREG_JIDR)
2624 .allPrivileges();
2625 InitReg(MISCREG_TEEHBR)
2626 .allPrivileges();
2627 InitReg(MISCREG_JOSCR)
2628 .allPrivileges();
2629 InitReg(MISCREG_JMCR)
2630 .allPrivileges();
2631
2632 // AArch32 CP15 registers
2633 InitReg(MISCREG_MIDR)
2634 .allPrivileges().exceptUserMode().writes(0);
2635 InitReg(MISCREG_CTR)
2636 .allPrivileges().exceptUserMode().writes(0);
2637 InitReg(MISCREG_TCMTR)
2638 .allPrivileges().exceptUserMode().writes(0);
2639 InitReg(MISCREG_TLBTR)
2640 .allPrivileges().exceptUserMode().writes(0);
2641 InitReg(MISCREG_MPIDR)
2642 .allPrivileges().exceptUserMode().writes(0);
2643 InitReg(MISCREG_REVIDR)
2644 .unimplemented()
2645 .warnNotFail()
2646 .allPrivileges().exceptUserMode().writes(0);
2647 InitReg(MISCREG_ID_PFR0)
2648 .allPrivileges().exceptUserMode().writes(0);
2649 InitReg(MISCREG_ID_PFR1)
2650 .allPrivileges().exceptUserMode().writes(0);
2651 InitReg(MISCREG_ID_DFR0)
2652 .allPrivileges().exceptUserMode().writes(0);
2653 InitReg(MISCREG_ID_AFR0)
2654 .allPrivileges().exceptUserMode().writes(0);
2655 InitReg(MISCREG_ID_MMFR0)
2656 .allPrivileges().exceptUserMode().writes(0);
2657 InitReg(MISCREG_ID_MMFR1)
2658 .allPrivileges().exceptUserMode().writes(0);
2659 InitReg(MISCREG_ID_MMFR2)
2660 .allPrivileges().exceptUserMode().writes(0);
2661 InitReg(MISCREG_ID_MMFR3)
2662 .allPrivileges().exceptUserMode().writes(0);
2663 InitReg(MISCREG_ID_ISAR0)
2664 .allPrivileges().exceptUserMode().writes(0);
2665 InitReg(MISCREG_ID_ISAR1)
2666 .allPrivileges().exceptUserMode().writes(0);
2667 InitReg(MISCREG_ID_ISAR2)
2668 .allPrivileges().exceptUserMode().writes(0);
2669 InitReg(MISCREG_ID_ISAR3)
2670 .allPrivileges().exceptUserMode().writes(0);
2671 InitReg(MISCREG_ID_ISAR4)
2672 .allPrivileges().exceptUserMode().writes(0);
2673 InitReg(MISCREG_ID_ISAR5)
2674 .allPrivileges().exceptUserMode().writes(0);
2675 InitReg(MISCREG_CCSIDR)
2676 .allPrivileges().exceptUserMode().writes(0);
2677 InitReg(MISCREG_CLIDR)
2678 .allPrivileges().exceptUserMode().writes(0);
2679 InitReg(MISCREG_AIDR)
2680 .allPrivileges().exceptUserMode().writes(0);
2681 InitReg(MISCREG_CSSELR)
2682 .banked();
2683 InitReg(MISCREG_CSSELR_NS)
2684 .bankedChild()
2685 .privSecure(!aarch32EL3)
2686 .nonSecure().exceptUserMode();
2687 InitReg(MISCREG_CSSELR_S)
2688 .bankedChild()
2689 .secure().exceptUserMode();
2690 InitReg(MISCREG_VPIDR)
2691 .hyp().monNonSecure();
2692 InitReg(MISCREG_VMPIDR)
2693 .hyp().monNonSecure();
2694 InitReg(MISCREG_SCTLR)
2695 .banked();
2696 InitReg(MISCREG_SCTLR_NS)
2697 .bankedChild()
2698 .privSecure(!aarch32EL3)
2699 .nonSecure().exceptUserMode();
2700 InitReg(MISCREG_SCTLR_S)
2701 .bankedChild()
2702 .secure().exceptUserMode();
2703 InitReg(MISCREG_ACTLR)
2704 .banked();
2705 InitReg(MISCREG_ACTLR_NS)
2706 .bankedChild()
2707 .privSecure(!aarch32EL3)
2708 .nonSecure().exceptUserMode();
2709 InitReg(MISCREG_ACTLR_S)
2710 .bankedChild()
2711 .secure().exceptUserMode();
2712 InitReg(MISCREG_CPACR)
2713 .allPrivileges().exceptUserMode();
2714 InitReg(MISCREG_SCR)
2715 .mon().secure().exceptUserMode()
2716 .res0(0xff40) // [31:16], [6]
2717 .res1(0x0030); // [5:4]
2718 InitReg(MISCREG_SDER)
2719 .mon();
2720 InitReg(MISCREG_NSACR)
2721 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2722 InitReg(MISCREG_HSCTLR)
2723 .hyp().monNonSecure();
2724 InitReg(MISCREG_HACTLR)
2725 .hyp().monNonSecure();
2726 InitReg(MISCREG_HCR)
2727 .hyp().monNonSecure();
2728 InitReg(MISCREG_HDCR)
2729 .hyp().monNonSecure();
2730 InitReg(MISCREG_HCPTR)
2731 .hyp().monNonSecure();
2732 InitReg(MISCREG_HSTR)
2733 .hyp().monNonSecure();
2734 InitReg(MISCREG_HACR)
2735 .unimplemented()
2736 .warnNotFail()
2737 .hyp().monNonSecure();
2738 InitReg(MISCREG_TTBR0)
2739 .banked();
2740 InitReg(MISCREG_TTBR0_NS)
2741 .bankedChild()
2742 .privSecure(!aarch32EL3)
2743 .nonSecure().exceptUserMode();
2744 InitReg(MISCREG_TTBR0_S)
2745 .bankedChild()
2746 .secure().exceptUserMode();
2747 InitReg(MISCREG_TTBR1)
2748 .banked();
2749 InitReg(MISCREG_TTBR1_NS)
2750 .bankedChild()
2751 .privSecure(!aarch32EL3)
2752 .nonSecure().exceptUserMode();
2753 InitReg(MISCREG_TTBR1_S)
2754 .bankedChild()
2755 .secure().exceptUserMode();
2756 InitReg(MISCREG_TTBCR)
2757 .banked();
2758 InitReg(MISCREG_TTBCR_NS)
2759 .bankedChild()
2760 .privSecure(!aarch32EL3)
2761 .nonSecure().exceptUserMode();
2762 InitReg(MISCREG_TTBCR_S)
2763 .bankedChild()
2764 .secure().exceptUserMode();
2765 InitReg(MISCREG_HTCR)
2766 .hyp().monNonSecure();
2767 InitReg(MISCREG_VTCR)
2768 .hyp().monNonSecure();
2769 InitReg(MISCREG_DACR)
2770 .banked();
2771 InitReg(MISCREG_DACR_NS)
2772 .bankedChild()
2773 .privSecure(!aarch32EL3)
2774 .nonSecure().exceptUserMode();
2775 InitReg(MISCREG_DACR_S)
2776 .bankedChild()
2777 .secure().exceptUserMode();
2778 InitReg(MISCREG_DFSR)
2779 .banked();
2780 InitReg(MISCREG_DFSR_NS)
2781 .bankedChild()
2782 .privSecure(!aarch32EL3)
2783 .nonSecure().exceptUserMode();
2784 InitReg(MISCREG_DFSR_S)
2785 .bankedChild()
2786 .secure().exceptUserMode();
2787 InitReg(MISCREG_IFSR)
2788 .banked();
2789 InitReg(MISCREG_IFSR_NS)
2790 .bankedChild()
2791 .privSecure(!aarch32EL3)
2792 .nonSecure().exceptUserMode();
2793 InitReg(MISCREG_IFSR_S)
2794 .bankedChild()
2795 .secure().exceptUserMode();
2796 InitReg(MISCREG_ADFSR)
2797 .unimplemented()
2798 .warnNotFail()
2799 .banked();
2800 InitReg(MISCREG_ADFSR_NS)
2801 .unimplemented()
2802 .warnNotFail()
2803 .bankedChild()
2804 .privSecure(!aarch32EL3)
2805 .nonSecure().exceptUserMode();
2806 InitReg(MISCREG_ADFSR_S)
2807 .unimplemented()
2808 .warnNotFail()
2809 .bankedChild()
2810 .secure().exceptUserMode();
2811 InitReg(MISCREG_AIFSR)
2812 .unimplemented()
2813 .warnNotFail()
2814 .banked();
2815 InitReg(MISCREG_AIFSR_NS)
2816 .unimplemented()
2817 .warnNotFail()
2818 .bankedChild()
2819 .privSecure(!aarch32EL3)
2820 .nonSecure().exceptUserMode();
2821 InitReg(MISCREG_AIFSR_S)
2822 .unimplemented()
2823 .warnNotFail()
2824 .bankedChild()
2825 .secure().exceptUserMode();
2826 InitReg(MISCREG_HADFSR)
2827 .hyp().monNonSecure();
2828 InitReg(MISCREG_HAIFSR)
2829 .hyp().monNonSecure();
2830 InitReg(MISCREG_HSR)
2831 .hyp().monNonSecure();
2832 InitReg(MISCREG_DFAR)
2833 .banked();
2834 InitReg(MISCREG_DFAR_NS)
2835 .bankedChild()
2836 .privSecure(!aarch32EL3)
2837 .nonSecure().exceptUserMode();
2838 InitReg(MISCREG_DFAR_S)
2839 .bankedChild()
2840 .secure().exceptUserMode();
2841 InitReg(MISCREG_IFAR)
2842 .banked();
2843 InitReg(MISCREG_IFAR_NS)
2844 .bankedChild()
2845 .privSecure(!aarch32EL3)
2846 .nonSecure().exceptUserMode();
2847 InitReg(MISCREG_IFAR_S)
2848 .bankedChild()
2849 .secure().exceptUserMode();
2850 InitReg(MISCREG_HDFAR)
2851 .hyp().monNonSecure();
2852 InitReg(MISCREG_HIFAR)
2853 .hyp().monNonSecure();
2854 InitReg(MISCREG_HPFAR)
2855 .hyp().monNonSecure();
2856 InitReg(MISCREG_ICIALLUIS)
2857 .unimplemented()
2858 .warnNotFail()
2859 .writes(1).exceptUserMode();
2860 InitReg(MISCREG_BPIALLIS)
2861 .unimplemented()
2862 .warnNotFail()
2863 .writes(1).exceptUserMode();
2864 InitReg(MISCREG_PAR)
2865 .banked();
2866 InitReg(MISCREG_PAR_NS)
2867 .bankedChild()
2868 .privSecure(!aarch32EL3)
2869 .nonSecure().exceptUserMode();
2870 InitReg(MISCREG_PAR_S)
2871 .bankedChild()
2872 .secure().exceptUserMode();
2873 InitReg(MISCREG_ICIALLU)
2874 .writes(1).exceptUserMode();
2875 InitReg(MISCREG_ICIMVAU)
2876 .unimplemented()
2877 .warnNotFail()
2878 .writes(1).exceptUserMode();
2879 InitReg(MISCREG_CP15ISB)
2880 .writes(1);
2881 InitReg(MISCREG_BPIALL)
2882 .unimplemented()
2883 .warnNotFail()
2884 .writes(1).exceptUserMode();
2885 InitReg(MISCREG_BPIMVA)
2886 .unimplemented()
2887 .warnNotFail()
2888 .writes(1).exceptUserMode();
2889 InitReg(MISCREG_DCIMVAC)
2890 .unimplemented()
2891 .warnNotFail()
2892 .writes(1).exceptUserMode();
2893 InitReg(MISCREG_DCISW)
2894 .unimplemented()
2895 .warnNotFail()
2896 .writes(1).exceptUserMode();
2897 InitReg(MISCREG_ATS1CPR)
2898 .writes(1).exceptUserMode();
2899 InitReg(MISCREG_ATS1CPW)
2900 .writes(1).exceptUserMode();
2901 InitReg(MISCREG_ATS1CUR)
2902 .writes(1).exceptUserMode();
2903 InitReg(MISCREG_ATS1CUW)
2904 .writes(1).exceptUserMode();
2905 InitReg(MISCREG_ATS12NSOPR)
2906 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2907 InitReg(MISCREG_ATS12NSOPW)
2908 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2909 InitReg(MISCREG_ATS12NSOUR)
2910 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2911 InitReg(MISCREG_ATS12NSOUW)
2912 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2913 InitReg(MISCREG_DCCMVAC)
2914 .writes(1).exceptUserMode();
2915 InitReg(MISCREG_DCCSW)
2916 .unimplemented()
2917 .warnNotFail()
2918 .writes(1).exceptUserMode();
2919 InitReg(MISCREG_CP15DSB)
2920 .writes(1);
2921 InitReg(MISCREG_CP15DMB)
2922 .writes(1);
2923 InitReg(MISCREG_DCCMVAU)
2924 .unimplemented()
2925 .warnNotFail()
2926 .writes(1).exceptUserMode();
2927 InitReg(MISCREG_DCCIMVAC)
2928 .unimplemented()
2929 .warnNotFail()
2930 .writes(1).exceptUserMode();
2931 InitReg(MISCREG_DCCISW)
2932 .unimplemented()
2933 .warnNotFail()
2934 .writes(1).exceptUserMode();
2935 InitReg(MISCREG_ATS1HR)
2936 .monNonSecureWrite().hypWrite();
2937 InitReg(MISCREG_ATS1HW)
2938 .monNonSecureWrite().hypWrite();
2939 InitReg(MISCREG_TLBIALLIS)
2940 .writes(1).exceptUserMode();
2941 InitReg(MISCREG_TLBIMVAIS)
2942 .writes(1).exceptUserMode();
2943 InitReg(MISCREG_TLBIASIDIS)
2944 .writes(1).exceptUserMode();
2945 InitReg(MISCREG_TLBIMVAAIS)
2946 .writes(1).exceptUserMode();
2947 InitReg(MISCREG_TLBIMVALIS)
2948 .writes(1).exceptUserMode();
2949 InitReg(MISCREG_TLBIMVAALIS)
2950 .writes(1).exceptUserMode();
2951 InitReg(MISCREG_ITLBIALL)
2952 .writes(1).exceptUserMode();
2953 InitReg(MISCREG_ITLBIMVA)
2954 .writes(1).exceptUserMode();
2955 InitReg(MISCREG_ITLBIASID)
2956 .writes(1).exceptUserMode();
2957 InitReg(MISCREG_DTLBIALL)
2958 .writes(1).exceptUserMode();
2959 InitReg(MISCREG_DTLBIMVA)
2960 .writes(1).exceptUserMode();
2961 InitReg(MISCREG_DTLBIASID)
2962 .writes(1).exceptUserMode();
2963 InitReg(MISCREG_TLBIALL)
2964 .writes(1).exceptUserMode();
2965 InitReg(MISCREG_TLBIMVA)
2966 .writes(1).exceptUserMode();
2967 InitReg(MISCREG_TLBIASID)
2968 .writes(1).exceptUserMode();
2969 InitReg(MISCREG_TLBIMVAA)
2970 .writes(1).exceptUserMode();
2971 InitReg(MISCREG_TLBIMVAL)
2972 .writes(1).exceptUserMode();
2973 InitReg(MISCREG_TLBIMVAAL)
2974 .writes(1).exceptUserMode();
2975 InitReg(MISCREG_TLBIIPAS2IS)
2976 .monNonSecureWrite().hypWrite();
2977 InitReg(MISCREG_TLBIIPAS2LIS)
2978 .monNonSecureWrite().hypWrite();
2979 InitReg(MISCREG_TLBIALLHIS)
2980 .monNonSecureWrite().hypWrite();
2981 InitReg(MISCREG_TLBIMVAHIS)
2982 .monNonSecureWrite().hypWrite();
2983 InitReg(MISCREG_TLBIALLNSNHIS)
2984 .monNonSecureWrite().hypWrite();
2985 InitReg(MISCREG_TLBIMVALHIS)
2986 .monNonSecureWrite().hypWrite();
2987 InitReg(MISCREG_TLBIIPAS2)
2988 .monNonSecureWrite().hypWrite();
2989 InitReg(MISCREG_TLBIIPAS2L)
2990 .monNonSecureWrite().hypWrite();
2991 InitReg(MISCREG_TLBIALLH)
2992 .monNonSecureWrite().hypWrite();
2993 InitReg(MISCREG_TLBIMVAH)
2994 .monNonSecureWrite().hypWrite();
2995 InitReg(MISCREG_TLBIALLNSNH)
2996 .monNonSecureWrite().hypWrite();
2997 InitReg(MISCREG_TLBIMVALH)
2998 .monNonSecureWrite().hypWrite();
2999 InitReg(MISCREG_PMCR)
3000 .allPrivileges();
3001 InitReg(MISCREG_PMCNTENSET)
3002 .allPrivileges();
3003 InitReg(MISCREG_PMCNTENCLR)
3004 .allPrivileges();
3005 InitReg(MISCREG_PMOVSR)
3006 .allPrivileges();
3007 InitReg(MISCREG_PMSWINC)
3008 .allPrivileges();
3009 InitReg(MISCREG_PMSELR)
3010 .allPrivileges();
3011 InitReg(MISCREG_PMCEID0)
3012 .allPrivileges();
3013 InitReg(MISCREG_PMCEID1)
3014 .allPrivileges();
3015 InitReg(MISCREG_PMCCNTR)
3016 .allPrivileges();
3017 InitReg(MISCREG_PMXEVTYPER)
3018 .allPrivileges();
3019 InitReg(MISCREG_PMCCFILTR)
3020 .allPrivileges();
3021 InitReg(MISCREG_PMXEVCNTR)
3022 .allPrivileges();
3023 InitReg(MISCREG_PMUSERENR)
3024 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3025 InitReg(MISCREG_PMINTENSET)
3026 .allPrivileges().exceptUserMode();
3027 InitReg(MISCREG_PMINTENCLR)
3028 .allPrivileges().exceptUserMode();
3029 InitReg(MISCREG_PMOVSSET)
3030 .unimplemented()
3031 .allPrivileges();
3032 InitReg(MISCREG_L2CTLR)
3033 .allPrivileges().exceptUserMode();
3034 InitReg(MISCREG_L2ECTLR)
3035 .unimplemented()
3036 .allPrivileges().exceptUserMode();
3037 InitReg(MISCREG_PRRR)
3038 .banked();
3039 InitReg(MISCREG_PRRR_NS)
3040 .bankedChild()
3041 .privSecure(!aarch32EL3)
3042 .nonSecure().exceptUserMode();
3043 InitReg(MISCREG_PRRR_S)
3044 .bankedChild()
3045 .secure().exceptUserMode();
3046 InitReg(MISCREG_MAIR0)
3047 .banked();
3048 InitReg(MISCREG_MAIR0_NS)
3049 .bankedChild()
3050 .privSecure(!aarch32EL3)
3051 .nonSecure().exceptUserMode();
3052 InitReg(MISCREG_MAIR0_S)
3053 .bankedChild()
3054 .secure().exceptUserMode();
3055 InitReg(MISCREG_NMRR)
3056 .banked();
3057 InitReg(MISCREG_NMRR_NS)
3058 .bankedChild()
3059 .privSecure(!aarch32EL3)
3060 .nonSecure().exceptUserMode();
3061 InitReg(MISCREG_NMRR_S)
3062 .bankedChild()
3063 .secure().exceptUserMode();
3064 InitReg(MISCREG_MAIR1)
3065 .banked();
3066 InitReg(MISCREG_MAIR1_NS)
3067 .bankedChild()
3068 .privSecure(!aarch32EL3)
3069 .nonSecure().exceptUserMode();
3070 InitReg(MISCREG_MAIR1_S)
3071 .bankedChild()
3072 .secure().exceptUserMode();
3073 InitReg(MISCREG_AMAIR0)
3074 .banked();
3075 InitReg(MISCREG_AMAIR0_NS)
3076 .bankedChild()
3077 .privSecure(!aarch32EL3)
3078 .nonSecure().exceptUserMode();
3079 InitReg(MISCREG_AMAIR0_S)
3080 .bankedChild()
3081 .secure().exceptUserMode();
3082 InitReg(MISCREG_AMAIR1)
3083 .banked();
3084 InitReg(MISCREG_AMAIR1_NS)
3085 .bankedChild()
3086 .privSecure(!aarch32EL3)
3087 .nonSecure().exceptUserMode();
3088 InitReg(MISCREG_AMAIR1_S)
3089 .bankedChild()
3090 .secure().exceptUserMode();
3091 InitReg(MISCREG_HMAIR0)
3092 .hyp().monNonSecure();
3093 InitReg(MISCREG_HMAIR1)
3094 .hyp().monNonSecure();
3095 InitReg(MISCREG_HAMAIR0)
3096 .unimplemented()
3097 .warnNotFail()
3098 .hyp().monNonSecure();
3099 InitReg(MISCREG_HAMAIR1)
3100 .unimplemented()
3101 .warnNotFail()
3102 .hyp().monNonSecure();
3103 InitReg(MISCREG_VBAR)
3104 .banked();
3105 InitReg(MISCREG_VBAR_NS)
3106 .bankedChild()
3107 .privSecure(!aarch32EL3)
3108 .nonSecure().exceptUserMode();
3109 InitReg(MISCREG_VBAR_S)
3110 .bankedChild()
3111 .secure().exceptUserMode();
3112 InitReg(MISCREG_MVBAR)
3113 .mon().secure().exceptUserMode();
3114 InitReg(MISCREG_RMR)
3115 .unimplemented()
3116 .mon().secure().exceptUserMode();
3117 InitReg(MISCREG_ISR)
3118 .allPrivileges().exceptUserMode().writes(0);
3119 InitReg(MISCREG_HVBAR)
3120 .hyp().monNonSecure();
3121 InitReg(MISCREG_FCSEIDR)
3122 .unimplemented()
3123 .warnNotFail()
3124 .allPrivileges().exceptUserMode();
3125 InitReg(MISCREG_CONTEXTIDR)
3126 .banked();
3127 InitReg(MISCREG_CONTEXTIDR_NS)
3128 .bankedChild()
3129 .privSecure(!aarch32EL3)
3130 .nonSecure().exceptUserMode();
3131 InitReg(MISCREG_CONTEXTIDR_S)
3132 .bankedChild()
3133 .secure().exceptUserMode();
3134 InitReg(MISCREG_TPIDRURW)
3135 .banked();
3136 InitReg(MISCREG_TPIDRURW_NS)
3137 .bankedChild()
3138 .allPrivileges()
3139 .privSecure(!aarch32EL3)
3140 .monSecure(0);
3141 InitReg(MISCREG_TPIDRURW_S)
3142 .bankedChild()
3143 .secure();
3144 InitReg(MISCREG_TPIDRURO)
3145 .banked();
3146 InitReg(MISCREG_TPIDRURO_NS)
3147 .bankedChild()
3148 .allPrivileges()
3149 .userNonSecureWrite(0).userSecureRead(1)
3150 .privSecure(!aarch32EL3)
3151 .monSecure(0);
3152 InitReg(MISCREG_TPIDRURO_S)
3153 .bankedChild()
3154 .secure().userSecureWrite(0);
3155 InitReg(MISCREG_TPIDRPRW)
3156 .banked();
3157 InitReg(MISCREG_TPIDRPRW_NS)
3158 .bankedChild()
3159 .nonSecure().exceptUserMode()
3160 .privSecure(!aarch32EL3);
3161 InitReg(MISCREG_TPIDRPRW_S)
3162 .bankedChild()
3163 .secure().exceptUserMode();
3164 InitReg(MISCREG_HTPIDR)
3165 .hyp().monNonSecure();
3166 InitReg(MISCREG_CNTFRQ)
3167 .unverifiable()
3168 .reads(1).mon();
3169 InitReg(MISCREG_CNTKCTL)
3170 .allPrivileges().exceptUserMode();
3171 InitReg(MISCREG_CNTP_TVAL)
3172 .banked();
3173 InitReg(MISCREG_CNTP_TVAL_NS)
3174 .bankedChild()
3175 .allPrivileges()
3176 .privSecure(!aarch32EL3)
3177 .monSecure(0);
3178 InitReg(MISCREG_CNTP_TVAL_S)
3179 .unimplemented()
3180 .bankedChild()
3181 .secure().user(1);
3182 InitReg(MISCREG_CNTP_CTL)
3183 .banked();
3184 InitReg(MISCREG_CNTP_CTL_NS)
3185 .bankedChild()
3186 .allPrivileges()
3187 .privSecure(!aarch32EL3)
3188 .monSecure(0);
3189 InitReg(MISCREG_CNTP_CTL_S)
3190 .unimplemented()
3191 .bankedChild()
3192 .secure().user(1);
3193 InitReg(MISCREG_CNTV_TVAL)
3194 .allPrivileges();
3195 InitReg(MISCREG_CNTV_CTL)
3196 .allPrivileges();
3197 InitReg(MISCREG_CNTHCTL)
3198 .unimplemented()
3199 .hypWrite().monNonSecureRead();
3200 InitReg(MISCREG_CNTHP_TVAL)
3201 .unimplemented()
3202 .hypWrite().monNonSecureRead();
3203 InitReg(MISCREG_CNTHP_CTL)
3204 .unimplemented()
3205 .hypWrite().monNonSecureRead();
3206 InitReg(MISCREG_IL1DATA0)
3207 .unimplemented()
3208 .allPrivileges().exceptUserMode();
3209 InitReg(MISCREG_IL1DATA1)
3210 .unimplemented()
3211 .allPrivileges().exceptUserMode();
3212 InitReg(MISCREG_IL1DATA2)
3213 .unimplemented()
3214 .allPrivileges().exceptUserMode();
3215 InitReg(MISCREG_IL1DATA3)
3216 .unimplemented()
3217 .allPrivileges().exceptUserMode();
3218 InitReg(MISCREG_DL1DATA0)
3219 .unimplemented()
3220 .allPrivileges().exceptUserMode();
3221 InitReg(MISCREG_DL1DATA1)
3222 .unimplemented()
3223 .allPrivileges().exceptUserMode();
3224 InitReg(MISCREG_DL1DATA2)
3225 .unimplemented()
3226 .allPrivileges().exceptUserMode();
3227 InitReg(MISCREG_DL1DATA3)
3228 .unimplemented()
3229 .allPrivileges().exceptUserMode();
3230 InitReg(MISCREG_DL1DATA4)
3231 .unimplemented()
3232 .allPrivileges().exceptUserMode();
3233 InitReg(MISCREG_RAMINDEX)
3234 .unimplemented()
3235 .writes(1).exceptUserMode();
3236 InitReg(MISCREG_L2ACTLR)
3237 .unimplemented()
3238 .allPrivileges().exceptUserMode();
3239 InitReg(MISCREG_CBAR)
3240 .unimplemented()
3241 .allPrivileges().exceptUserMode().writes(0);
3242 InitReg(MISCREG_HTTBR)
3243 .hyp().monNonSecure();
3244 InitReg(MISCREG_VTTBR)
3245 .hyp().monNonSecure();
3246 InitReg(MISCREG_CNTPCT)
3247 .reads(1);
3248 InitReg(MISCREG_CNTVCT)
3249 .unverifiable()
3250 .reads(1);
3251 InitReg(MISCREG_CNTP_CVAL)
3252 .banked();
3253 InitReg(MISCREG_CNTP_CVAL_NS)
3254 .bankedChild()
3255 .allPrivileges()
3256 .privSecure(!aarch32EL3)
3257 .monSecure(0);
3258 InitReg(MISCREG_CNTP_CVAL_S)
3259 .unimplemented()
3260 .bankedChild()
3261 .secure().user(1);
3262 InitReg(MISCREG_CNTV_CVAL)
3263 .allPrivileges();
3264 InitReg(MISCREG_CNTVOFF)
3265 .hyp().monNonSecure();
3266 InitReg(MISCREG_CNTHP_CVAL)
3267 .unimplemented()
3268 .hypWrite().monNonSecureRead();
3269 InitReg(MISCREG_CPUMERRSR)
3270 .unimplemented()
3271 .allPrivileges().exceptUserMode();
3272 InitReg(MISCREG_L2MERRSR)
3273 .unimplemented()
3274 .warnNotFail()
3275 .allPrivileges().exceptUserMode();
3276
3277 // AArch64 registers (Op0=2);
3278 InitReg(MISCREG_MDCCINT_EL1)
3279 .allPrivileges();
3280 InitReg(MISCREG_OSDTRRX_EL1)
3281 .allPrivileges()
3282 .mapsTo(MISCREG_DBGDTRRXext);
3283 InitReg(MISCREG_MDSCR_EL1)
3284 .allPrivileges()
3285 .mapsTo(MISCREG_DBGDSCRext);
3286 InitReg(MISCREG_OSDTRTX_EL1)
3287 .allPrivileges()
3288 .mapsTo(MISCREG_DBGDTRTXext);
3289 InitReg(MISCREG_OSECCR_EL1)
3290 .allPrivileges()
3291 .mapsTo(MISCREG_DBGOSECCR);
3292 InitReg(MISCREG_DBGBVR0_EL1)
3293 .allPrivileges()
3294 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3295 InitReg(MISCREG_DBGBVR1_EL1)
3296 .allPrivileges()
3297 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3298 InitReg(MISCREG_DBGBVR2_EL1)
3299 .allPrivileges()
3300 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3301 InitReg(MISCREG_DBGBVR3_EL1)
3302 .allPrivileges()
3303 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3304 InitReg(MISCREG_DBGBVR4_EL1)
3305 .allPrivileges()
3306 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3307 InitReg(MISCREG_DBGBVR5_EL1)
3308 .allPrivileges()
3309 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3310 InitReg(MISCREG_DBGBCR0_EL1)
3311 .allPrivileges()
3312 .mapsTo(MISCREG_DBGBCR0);
3313 InitReg(MISCREG_DBGBCR1_EL1)
3314 .allPrivileges()
3315 .mapsTo(MISCREG_DBGBCR1);
3316 InitReg(MISCREG_DBGBCR2_EL1)
3317 .allPrivileges()
3318 .mapsTo(MISCREG_DBGBCR2);
3319 InitReg(MISCREG_DBGBCR3_EL1)
3320 .allPrivileges()
3321 .mapsTo(MISCREG_DBGBCR3);
3322 InitReg(MISCREG_DBGBCR4_EL1)
3323 .allPrivileges()
3324 .mapsTo(MISCREG_DBGBCR4);
3325 InitReg(MISCREG_DBGBCR5_EL1)
3326 .allPrivileges()
3327 .mapsTo(MISCREG_DBGBCR5);
3328 InitReg(MISCREG_DBGWVR0_EL1)
3329 .allPrivileges()
3330 .mapsTo(MISCREG_DBGWVR0);
3331 InitReg(MISCREG_DBGWVR1_EL1)
3332 .allPrivileges()
3333 .mapsTo(MISCREG_DBGWVR1);
3334 InitReg(MISCREG_DBGWVR2_EL1)
3335 .allPrivileges()
3336 .mapsTo(MISCREG_DBGWVR2);
3337 InitReg(MISCREG_DBGWVR3_EL1)
3338 .allPrivileges()
3339 .mapsTo(MISCREG_DBGWVR3);
3340 InitReg(MISCREG_DBGWCR0_EL1)
3341 .allPrivileges()
3342 .mapsTo(MISCREG_DBGWCR0);
3343 InitReg(MISCREG_DBGWCR1_EL1)
3344 .allPrivileges()
3345 .mapsTo(MISCREG_DBGWCR1);
3346 InitReg(MISCREG_DBGWCR2_EL1)
3347 .allPrivileges()
3348 .mapsTo(MISCREG_DBGWCR2);
3349 InitReg(MISCREG_DBGWCR3_EL1)
3350 .allPrivileges()
3351 .mapsTo(MISCREG_DBGWCR3);
3352 InitReg(MISCREG_MDCCSR_EL0)
3353 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3354 .mapsTo(MISCREG_DBGDSCRint);
3355 InitReg(MISCREG_MDDTR_EL0)
3356 .allPrivileges();
3357 InitReg(MISCREG_MDDTRTX_EL0)
3358 .allPrivileges();
3359 InitReg(MISCREG_MDDTRRX_EL0)
3360 .allPrivileges();
3361 InitReg(MISCREG_DBGVCR32_EL2)
3362 .allPrivileges()
3363 .mapsTo(MISCREG_DBGVCR);
3364 InitReg(MISCREG_MDRAR_EL1)
3365 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3366 .mapsTo(MISCREG_DBGDRAR);
3367 InitReg(MISCREG_OSLAR_EL1)
3368 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3369 .mapsTo(MISCREG_DBGOSLAR);
3370 InitReg(MISCREG_OSLSR_EL1)
3371 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3372 .mapsTo(MISCREG_DBGOSLSR);
3373 InitReg(MISCREG_OSDLR_EL1)
3374 .allPrivileges()
3375 .mapsTo(MISCREG_DBGOSDLR);
3376 InitReg(MISCREG_DBGPRCR_EL1)
3377 .allPrivileges()
3378 .mapsTo(MISCREG_DBGPRCR);
3379 InitReg(MISCREG_DBGCLAIMSET_EL1)
3380 .allPrivileges()
3381 .mapsTo(MISCREG_DBGCLAIMSET);
3382 InitReg(MISCREG_DBGCLAIMCLR_EL1)
3383 .allPrivileges()
3384 .mapsTo(MISCREG_DBGCLAIMCLR);
3385 InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3386 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3387 .mapsTo(MISCREG_DBGAUTHSTATUS);
3388 InitReg(MISCREG_TEECR32_EL1);
3389 InitReg(MISCREG_TEEHBR32_EL1);
3390
3391 // AArch64 registers (Op0=1,3);
3392 InitReg(MISCREG_MIDR_EL1)
3393 .allPrivileges().exceptUserMode().writes(0);
3394 InitReg(MISCREG_MPIDR_EL1)
3395 .allPrivileges().exceptUserMode().writes(0);
3396 InitReg(MISCREG_REVIDR_EL1)
3397 .allPrivileges().exceptUserMode().writes(0);
3398 InitReg(MISCREG_ID_PFR0_EL1)
3399 .allPrivileges().exceptUserMode().writes(0)
3400 .mapsTo(MISCREG_ID_PFR0);
3401 InitReg(MISCREG_ID_PFR1_EL1)
3402 .allPrivileges().exceptUserMode().writes(0)
3403 .mapsTo(MISCREG_ID_PFR1);
3404 InitReg(MISCREG_ID_DFR0_EL1)
3405 .allPrivileges().exceptUserMode().writes(0)
3406 .mapsTo(MISCREG_ID_DFR0);
3407 InitReg(MISCREG_ID_AFR0_EL1)
3408 .allPrivileges().exceptUserMode().writes(0)
3409 .mapsTo(MISCREG_ID_AFR0);
3410 InitReg(MISCREG_ID_MMFR0_EL1)
3411 .allPrivileges().exceptUserMode().writes(0)
3412 .mapsTo(MISCREG_ID_MMFR0);
3413 InitReg(MISCREG_ID_MMFR1_EL1)
3414 .allPrivileges().exceptUserMode().writes(0)
3415 .mapsTo(MISCREG_ID_MMFR1);
3416 InitReg(MISCREG_ID_MMFR2_EL1)
3417 .allPrivileges().exceptUserMode().writes(0)
3418 .mapsTo(MISCREG_ID_MMFR2);
3419 InitReg(MISCREG_ID_MMFR3_EL1)
3420 .allPrivileges().exceptUserMode().writes(0)
3421 .mapsTo(MISCREG_ID_MMFR3);
3422 InitReg(MISCREG_ID_ISAR0_EL1)
3423 .allPrivileges().exceptUserMode().writes(0)
3424 .mapsTo(MISCREG_ID_ISAR0);
3425 InitReg(MISCREG_ID_ISAR1_EL1)
3426 .allPrivileges().exceptUserMode().writes(0)
3427 .mapsTo(MISCREG_ID_ISAR1);
3428 InitReg(MISCREG_ID_ISAR2_EL1)
3429 .allPrivileges().exceptUserMode().writes(0)
3430 .mapsTo(MISCREG_ID_ISAR2);
3431 InitReg(MISCREG_ID_ISAR3_EL1)
3432 .allPrivileges().exceptUserMode().writes(0)
3433 .mapsTo(MISCREG_ID_ISAR3);
3434 InitReg(MISCREG_ID_ISAR4_EL1)
3435 .allPrivileges().exceptUserMode().writes(0)
3436 .mapsTo(MISCREG_ID_ISAR4);
3437 InitReg(MISCREG_ID_ISAR5_EL1)
3438 .allPrivileges().exceptUserMode().writes(0)
3439 .mapsTo(MISCREG_ID_ISAR5);
3440 InitReg(MISCREG_MVFR0_EL1)
3441 .allPrivileges().exceptUserMode().writes(0);
3442 InitReg(MISCREG_MVFR1_EL1)
3443 .allPrivileges().exceptUserMode().writes(0);
3444 InitReg(MISCREG_MVFR2_EL1)
3445 .allPrivileges().exceptUserMode().writes(0);
3446 InitReg(MISCREG_ID_AA64PFR0_EL1)
3447 .allPrivileges().exceptUserMode().writes(0);
3448 InitReg(MISCREG_ID_AA64PFR1_EL1)
3449 .allPrivileges().exceptUserMode().writes(0);
3450 InitReg(MISCREG_ID_AA64DFR0_EL1)
3451 .allPrivileges().exceptUserMode().writes(0);
3452 InitReg(MISCREG_ID_AA64DFR1_EL1)
3453 .allPrivileges().exceptUserMode().writes(0);
3454 InitReg(MISCREG_ID_AA64AFR0_EL1)
3455 .allPrivileges().exceptUserMode().writes(0);
3456 InitReg(MISCREG_ID_AA64AFR1_EL1)
3457 .allPrivileges().exceptUserMode().writes(0);
3458 InitReg(MISCREG_ID_AA64ISAR0_EL1)
3459 .allPrivileges().exceptUserMode().writes(0);
3460 InitReg(MISCREG_ID_AA64ISAR1_EL1)
3461 .allPrivileges().exceptUserMode().writes(0);
3462 InitReg(MISCREG_ID_AA64MMFR0_EL1)
3463 .allPrivileges().exceptUserMode().writes(0);
3464 InitReg(MISCREG_ID_AA64MMFR1_EL1)
3465 .allPrivileges().exceptUserMode().writes(0);
3466 InitReg(MISCREG_CCSIDR_EL1)
3467 .allPrivileges().exceptUserMode().writes(0);
3468 InitReg(MISCREG_CLIDR_EL1)
3469 .allPrivileges().exceptUserMode().writes(0);
3470 InitReg(MISCREG_AIDR_EL1)
3471 .allPrivileges().exceptUserMode().writes(0);
3472 InitReg(MISCREG_CSSELR_EL1)
3473 .allPrivileges().exceptUserMode()
3474 .mapsTo(MISCREG_CSSELR_NS);
3475 InitReg(MISCREG_CTR_EL0)
3476 .reads(1);
3477 InitReg(MISCREG_DCZID_EL0)
3478 .reads(1);
3479 InitReg(MISCREG_VPIDR_EL2)
3480 .hyp().mon()
3481 .mapsTo(MISCREG_VPIDR);
3482 InitReg(MISCREG_VMPIDR_EL2)
3483 .hyp().mon()
3484 .mapsTo(MISCREG_VMPIDR);
3485 InitReg(MISCREG_SCTLR_EL1)
3486 .allPrivileges().exceptUserMode()
3487 .mapsTo(MISCREG_SCTLR_NS);
3488 InitReg(MISCREG_ACTLR_EL1)
3489 .allPrivileges().exceptUserMode()
3490 .mapsTo(MISCREG_ACTLR_NS);
3491 InitReg(MISCREG_CPACR_EL1)
3492 .allPrivileges().exceptUserMode()
3493 .mapsTo(MISCREG_CPACR);
3494 InitReg(MISCREG_SCTLR_EL2)
3495 .hyp().mon()
3496 .mapsTo(MISCREG_HSCTLR);
3497 InitReg(MISCREG_ACTLR_EL2)
3498 .hyp().mon()
3499 .mapsTo(MISCREG_HACTLR);
3500 InitReg(MISCREG_HCR_EL2)
3501 .hyp().mon()
3502 .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
3503 InitReg(MISCREG_MDCR_EL2)
3504 .hyp().mon()
3505 .mapsTo(MISCREG_HDCR);
3506 InitReg(MISCREG_CPTR_EL2)
3507 .hyp().mon()
3508 .mapsTo(MISCREG_HCPTR);
3509 InitReg(MISCREG_HSTR_EL2)
3510 .hyp().mon()
3511 .mapsTo(MISCREG_HSTR);
3512 InitReg(MISCREG_HACR_EL2)
3513 .hyp().mon()
3514 .mapsTo(MISCREG_HACR);
3515 InitReg(MISCREG_SCTLR_EL3)
3516 .mon();
3517 InitReg(MISCREG_ACTLR_EL3)
3518 .mon();
3519 InitReg(MISCREG_SCR_EL3)
3520 .mon()
3521 .mapsTo(MISCREG_SCR); // NAM D7-2005
3522 InitReg(MISCREG_SDER32_EL3)
3523 .mon()
3524 .mapsTo(MISCREG_SDER);
3525 InitReg(MISCREG_CPTR_EL3)
3526 .mon();
3527 InitReg(MISCREG_MDCR_EL3)
3528 .mon();
3529 InitReg(MISCREG_TTBR0_EL1)
3530 .allPrivileges().exceptUserMode()
3531 .mapsTo(MISCREG_TTBR0_NS);
3532 InitReg(MISCREG_TTBR1_EL1)
3533 .allPrivileges().exceptUserMode()
3534 .mapsTo(MISCREG_TTBR1_NS);
3535 InitReg(MISCREG_TCR_EL1)
3536 .allPrivileges().exceptUserMode()
3537 .mapsTo(MISCREG_TTBCR_NS);
3538 InitReg(MISCREG_TTBR0_EL2)
3539 .hyp().mon()
3540 .mapsTo(MISCREG_HTTBR);
3541 InitReg(MISCREG_TTBR1_EL2)
3542 .hyp().mon();
3543 InitReg(MISCREG_TCR_EL2)
3544 .hyp().mon()
3545 .mapsTo(MISCREG_HTCR);
3546 InitReg(MISCREG_VTTBR_EL2)
3547 .hyp().mon()
3548 .mapsTo(MISCREG_VTTBR);
3549 InitReg(MISCREG_VTCR_EL2)
3550 .hyp().mon()
3551 .mapsTo(MISCREG_VTCR);
3552 InitReg(MISCREG_TTBR0_EL3)
3553 .mon();
3554 InitReg(MISCREG_TCR_EL3)
3555 .mon();
3556 InitReg(MISCREG_DACR32_EL2)
3557 .hyp().mon()
3558 .mapsTo(MISCREG_DACR_NS);
3559 InitReg(MISCREG_SPSR_EL1)
3560 .allPrivileges().exceptUserMode()
3561 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
3562 InitReg(MISCREG_ELR_EL1)
3563 .allPrivileges().exceptUserMode();
3564 InitReg(MISCREG_SP_EL0)
3565 .allPrivileges().exceptUserMode();
3566 InitReg(MISCREG_SPSEL)
3567 .allPrivileges().exceptUserMode();
3568 InitReg(MISCREG_CURRENTEL)
3569 .allPrivileges().exceptUserMode().writes(0);
3570 InitReg(MISCREG_NZCV)
3571 .allPrivileges();
3572 InitReg(MISCREG_DAIF)
3573 .allPrivileges();
3574 InitReg(MISCREG_FPCR)
3575 .allPrivileges();
3576 InitReg(MISCREG_FPSR)
3577 .allPrivileges();
3578 InitReg(MISCREG_DSPSR_EL0)
3579 .allPrivileges();
3580 InitReg(MISCREG_DLR_EL0)
3581 .allPrivileges();
3582 InitReg(MISCREG_SPSR_EL2)
3583 .hyp().mon()
3584 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
3585 InitReg(MISCREG_ELR_EL2)
3586 .hyp().mon();
3587 InitReg(MISCREG_SP_EL1)
3588 .hyp().mon();
3589 InitReg(MISCREG_SPSR_IRQ_AA64)
3590 .hyp().mon();
3591 InitReg(MISCREG_SPSR_ABT_AA64)
3592 .hyp().mon();
3593 InitReg(MISCREG_SPSR_UND_AA64)
3594 .hyp().mon();
3595 InitReg(MISCREG_SPSR_FIQ_AA64)
3596 .hyp().mon();
3597 InitReg(MISCREG_SPSR_EL3)
3598 .mon()
3599 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
3600 InitReg(MISCREG_ELR_EL3)
3601 .mon();
3602 InitReg(MISCREG_SP_EL2)
3603 .mon();
3604 InitReg(MISCREG_AFSR0_EL1)
3605 .allPrivileges().exceptUserMode()
3606 .mapsTo(MISCREG_ADFSR_NS);
3607 InitReg(MISCREG_AFSR1_EL1)
3608 .allPrivileges().exceptUserMode()
3609 .mapsTo(MISCREG_AIFSR_NS);
3610 InitReg(MISCREG_ESR_EL1)
3611 .allPrivileges().exceptUserMode();
3612 InitReg(MISCREG_IFSR32_EL2)
3613 .hyp().mon()
3614 .mapsTo(MISCREG_IFSR_NS);
3615 InitReg(MISCREG_AFSR0_EL2)
3616 .hyp().mon()
3617 .mapsTo(MISCREG_HADFSR);
3618 InitReg(MISCREG_AFSR1_EL2)
3619 .hyp().mon()
3620 .mapsTo(MISCREG_HAIFSR);
3621 InitReg(MISCREG_ESR_EL2)
3622 .hyp().mon()
3623 .mapsTo(MISCREG_HSR);
3624 InitReg(MISCREG_FPEXC32_EL2)
3625 .hyp().mon().mapsTo(MISCREG_FPEXC);
3626 InitReg(MISCREG_AFSR0_EL3)
3627 .mon();
3628 InitReg(MISCREG_AFSR1_EL3)
3629 .mon();
3630 InitReg(MISCREG_ESR_EL3)
3631 .mon();
3632 InitReg(MISCREG_FAR_EL1)
3633 .allPrivileges().exceptUserMode()
3634 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
3635 InitReg(MISCREG_FAR_EL2)
3636 .hyp().mon()
3637 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
3638 InitReg(MISCREG_HPFAR_EL2)
3639 .hyp().mon()
3640 .mapsTo(MISCREG_HPFAR);
3641 InitReg(MISCREG_FAR_EL3)
3642 .mon();
3643 InitReg(MISCREG_IC_IALLUIS)
3644 .warnNotFail()
3645 .writes(1).exceptUserMode();
3646 InitReg(MISCREG_PAR_EL1)
3647 .allPrivileges().exceptUserMode()
3648 .mapsTo(MISCREG_PAR_NS);
3649 InitReg(MISCREG_IC_IALLU)
3650 .warnNotFail()
3651 .writes(1).exceptUserMode();
3652 InitReg(MISCREG_DC_IVAC_Xt)
3653 .warnNotFail()
3654 .writes(1).exceptUserMode();
3655 InitReg(MISCREG_DC_ISW_Xt)
3656 .warnNotFail()
3657 .writes(1).exceptUserMode();
3658 InitReg(MISCREG_AT_S1E1R_Xt)
3659 .writes(1).exceptUserMode();
3660 InitReg(MISCREG_AT_S1E1W_Xt)
3661 .writes(1).exceptUserMode();
3662 InitReg(MISCREG_AT_S1E0R_Xt)
3663 .writes(1).exceptUserMode();
3664 InitReg(MISCREG_AT_S1E0W_Xt)
3665 .writes(1).exceptUserMode();
3666 InitReg(MISCREG_DC_CSW_Xt)
3667 .warnNotFail()
3668 .writes(1).exceptUserMode();
3669 InitReg(MISCREG_DC_CISW_Xt)
3670 .warnNotFail()
3671 .writes(1).exceptUserMode();
3672 InitReg(MISCREG_DC_ZVA_Xt)
3673 .warnNotFail()
3674 .writes(1).userSecureWrite(0);
3675 InitReg(MISCREG_IC_IVAU_Xt)
3676 .writes(1);
3677 InitReg(MISCREG_DC_CVAC_Xt)
3678 .warnNotFail()
3679 .writes(1);
3680 InitReg(MISCREG_DC_CVAU_Xt)
3681 .warnNotFail()
3682 .writes(1);
3683 InitReg(MISCREG_DC_CIVAC_Xt)
3684 .warnNotFail()
3685 .writes(1);
3686 InitReg(MISCREG_AT_S1E2R_Xt)
3687 .monNonSecureWrite().hypWrite();
3688 InitReg(MISCREG_AT_S1E2W_Xt)
3689 .monNonSecureWrite().hypWrite();
3690 InitReg(MISCREG_AT_S12E1R_Xt)
3691 .hypWrite().monSecureWrite().monNonSecureWrite();
3692 InitReg(MISCREG_AT_S12E1W_Xt)
3693 .hypWrite().monSecureWrite().monNonSecureWrite();
3694 InitReg(MISCREG_AT_S12E0R_Xt)
3695 .hypWrite().monSecureWrite().monNonSecureWrite();
3696 InitReg(MISCREG_AT_S12E0W_Xt)
3697 .hypWrite().monSecureWrite().monNonSecureWrite();
3698 InitReg(MISCREG_AT_S1E3R_Xt)
3699 .monSecureWrite().monNonSecureWrite();
3700 InitReg(MISCREG_AT_S1E3W_Xt)
3701 .monSecureWrite().monNonSecureWrite();
3702 InitReg(MISCREG_TLBI_VMALLE1IS)
3703 .writes(1).exceptUserMode();
3704 InitReg(MISCREG_TLBI_VAE1IS_Xt)
3705 .writes(1).exceptUserMode();
3706 InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
3707 .writes(1).exceptUserMode();
3708 InitReg(MISCREG_TLBI_VAAE1IS_Xt)
3709 .writes(1).exceptUserMode();
3710 InitReg(MISCREG_TLBI_VALE1IS_Xt)
3711 .writes(1).exceptUserMode();
3712 InitReg(MISCREG_TLBI_VAALE1IS_Xt)
3713 .writes(1).exceptUserMode();
3714 InitReg(MISCREG_TLBI_VMALLE1)
3715 .writes(1).exceptUserMode();
3716 InitReg(MISCREG_TLBI_VAE1_Xt)
3717 .writes(1).exceptUserMode();
3718 InitReg(MISCREG_TLBI_ASIDE1_Xt)
3719 .writes(1).exceptUserMode();
3720 InitReg(MISCREG_TLBI_VAAE1_Xt)
3721 .writes(1).exceptUserMode();
3722 InitReg(MISCREG_TLBI_VALE1_Xt)
3723 .writes(1).exceptUserMode();
3724 InitReg(MISCREG_TLBI_VAALE1_Xt)
3725 .writes(1).exceptUserMode();
3726 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
3727 .hypWrite().monSecureWrite().monNonSecureWrite();
3728 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
3729 .hypWrite().monSecureWrite().monNonSecureWrite();
3730 InitReg(MISCREG_TLBI_ALLE2IS)
3731 .monNonSecureWrite().hypWrite();
3732 InitReg(MISCREG_TLBI_VAE2IS_Xt)
3733 .monNonSecureWrite().hypWrite();
3734 InitReg(MISCREG_TLBI_ALLE1IS)
3735 .hypWrite().monSecureWrite().monNonSecureWrite();
3736 InitReg(MISCREG_TLBI_VALE2IS_Xt)
3737 .monNonSecureWrite().hypWrite();
3738 InitReg(MISCREG_TLBI_VMALLS12E1IS)
3739 .hypWrite().monSecureWrite().monNonSecureWrite();
3740 InitReg(MISCREG_TLBI_IPAS2E1_Xt)
3741 .hypWrite().monSecureWrite().monNonSecureWrite();
3742 InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
3743 .hypWrite().monSecureWrite().monNonSecureWrite();
3744 InitReg(MISCREG_TLBI_ALLE2)
3745 .monNonSecureWrite().hypWrite();
3746 InitReg(MISCREG_TLBI_VAE2_Xt)
3747 .monNonSecureWrite().hypWrite();
3748 InitReg(MISCREG_TLBI_ALLE1)
3749 .hypWrite().monSecureWrite().monNonSecureWrite();
3750 InitReg(MISCREG_TLBI_VALE2_Xt)
3751 .monNonSecureWrite().hypWrite();
3752 InitReg(MISCREG_TLBI_VMALLS12E1)
3753 .hypWrite().monSecureWrite().monNonSecureWrite();
3754 InitReg(MISCREG_TLBI_ALLE3IS)
3755 .monSecureWrite().monNonSecureWrite();
3756 InitReg(MISCREG_TLBI_VAE3IS_Xt)
3757 .monSecureWrite().monNonSecureWrite();
3758 InitReg(MISCREG_TLBI_VALE3IS_Xt)
3759 .monSecureWrite().monNonSecureWrite();
3760 InitReg(MISCREG_TLBI_ALLE3)
3761 .monSecureWrite().monNonSecureWrite();
3762 InitReg(MISCREG_TLBI_VAE3_Xt)
3763 .monSecureWrite().monNonSecureWrite();
3764 InitReg(MISCREG_TLBI_VALE3_Xt)
3765 .monSecureWrite().monNonSecureWrite();
3766 InitReg(MISCREG_PMINTENSET_EL1)
3767 .allPrivileges().exceptUserMode()
3768 .mapsTo(MISCREG_PMINTENSET);
3769 InitReg(MISCREG_PMINTENCLR_EL1)
3770 .allPrivileges().exceptUserMode()
3771 .mapsTo(MISCREG_PMINTENCLR);
3772 InitReg(MISCREG_PMCR_EL0)
3773 .allPrivileges()
3774 .mapsTo(MISCREG_PMCR);
3775 InitReg(MISCREG_PMCNTENSET_EL0)
3776 .allPrivileges()
3777 .mapsTo(MISCREG_PMCNTENSET);
3778 InitReg(MISCREG_PMCNTENCLR_EL0)
3779 .allPrivileges()
3780 .mapsTo(MISCREG_PMCNTENCLR);
3781 InitReg(MISCREG_PMOVSCLR_EL0)
3782 .allPrivileges();
3783// .mapsTo(MISCREG_PMOVSCLR);
3784 InitReg(MISCREG_PMSWINC_EL0)
3785 .writes(1).user()
3786 .mapsTo(MISCREG_PMSWINC);
3787 InitReg(MISCREG_PMSELR_EL0)
3788 .allPrivileges()
3789 .mapsTo(MISCREG_PMSELR);
3790 InitReg(MISCREG_PMCEID0_EL0)
3791 .reads(1).user()
3792 .mapsTo(MISCREG_PMCEID0);
3793 InitReg(MISCREG_PMCEID1_EL0)
3794 .reads(1).user()
3795 .mapsTo(MISCREG_PMCEID1);
3796 InitReg(MISCREG_PMCCNTR_EL0)
3797 .allPrivileges()
3798 .mapsTo(MISCREG_PMCCNTR);
3799 InitReg(MISCREG_PMXEVTYPER_EL0)
3800 .allPrivileges()
3801 .mapsTo(MISCREG_PMXEVTYPER);
3802 InitReg(MISCREG_PMCCFILTR_EL0)
3803 .allPrivileges();
3804 InitReg(MISCREG_PMXEVCNTR_EL0)
3805 .allPrivileges()
3806 .mapsTo(MISCREG_PMXEVCNTR);
3807 InitReg(MISCREG_PMUSERENR_EL0)
3808 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3809 .mapsTo(MISCREG_PMUSERENR);
3810 InitReg(MISCREG_PMOVSSET_EL0)
3811 .allPrivileges()
3812 .mapsTo(MISCREG_PMOVSSET);
3813 InitReg(MISCREG_MAIR_EL1)
3814 .allPrivileges().exceptUserMode()
3815 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
3816 InitReg(MISCREG_AMAIR_EL1)
3817 .allPrivileges().exceptUserMode()
3818 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
3819 InitReg(MISCREG_MAIR_EL2)
3820 .hyp().mon()
3821 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
3822 InitReg(MISCREG_AMAIR_EL2)
3823 .hyp().mon()
3824 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
3825 InitReg(MISCREG_MAIR_EL3)
3826 .mon();
3827 InitReg(MISCREG_AMAIR_EL3)
3828 .mon();
3829 InitReg(MISCREG_L2CTLR_EL1)
3830 .allPrivileges().exceptUserMode();
3831 InitReg(MISCREG_L2ECTLR_EL1)
3832 .allPrivileges().exceptUserMode();
3833 InitReg(MISCREG_VBAR_EL1)
3834 .allPrivileges().exceptUserMode()
3835 .mapsTo(MISCREG_VBAR_NS);
3836 InitReg(MISCREG_RVBAR_EL1)
3837 .allPrivileges().exceptUserMode().writes(0);
3838 InitReg(MISCREG_ISR_EL1)
3839 .allPrivileges().exceptUserMode().writes(0);
3840 InitReg(MISCREG_VBAR_EL2)
3841 .hyp().mon()
3842 .mapsTo(MISCREG_HVBAR);
3843 InitReg(MISCREG_RVBAR_EL2)
3844 .mon().hyp().writes(0);
3845 InitReg(MISCREG_VBAR_EL3)
3846 .mon();
3847 InitReg(MISCREG_RVBAR_EL3)
3848 .mon().writes(0);
3849 InitReg(MISCREG_RMR_EL3)
3850 .mon();
3851 InitReg(MISCREG_CONTEXTIDR_EL1)
3852 .allPrivileges().exceptUserMode()
3853 .mapsTo(MISCREG_CONTEXTIDR_NS);
3854 InitReg(MISCREG_TPIDR_EL1)
3855 .allPrivileges().exceptUserMode()
3856 .mapsTo(MISCREG_TPIDRPRW_NS);
3857 InitReg(MISCREG_TPIDR_EL0)
3858 .allPrivileges()
3859 .mapsTo(MISCREG_TPIDRURW_NS);
3860 InitReg(MISCREG_TPIDRRO_EL0)
3861 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3862 .mapsTo(MISCREG_TPIDRURO_NS);
3863 InitReg(MISCREG_TPIDR_EL2)
3864 .hyp().mon()
3865 .mapsTo(MISCREG_HTPIDR);
3866 InitReg(MISCREG_TPIDR_EL3)
3867 .mon();
3868 InitReg(MISCREG_CNTKCTL_EL1)
3869 .allPrivileges().exceptUserMode()
3870 .mapsTo(MISCREG_CNTKCTL);
3871 InitReg(MISCREG_CNTFRQ_EL0)
3872 .reads(1).mon()
3873 .mapsTo(MISCREG_CNTFRQ);
3874 InitReg(MISCREG_CNTPCT_EL0)
3875 .reads(1)
3876 .mapsTo(MISCREG_CNTPCT); /* 64b */
3877 InitReg(MISCREG_CNTVCT_EL0)
3878 .unverifiable()
3879 .reads(1)
3880 .mapsTo(MISCREG_CNTVCT); /* 64b */
3881 InitReg(MISCREG_CNTP_TVAL_EL0)
3882 .allPrivileges()
3883 .mapsTo(MISCREG_CNTP_TVAL_NS);
3884 InitReg(MISCREG_CNTP_CTL_EL0)
3885 .allPrivileges()
3886 .mapsTo(MISCREG_CNTP_CTL_NS);
3887 InitReg(MISCREG_CNTP_CVAL_EL0)
3888 .allPrivileges()
3889 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
3890 InitReg(MISCREG_CNTV_TVAL_EL0)
3891 .allPrivileges()
3892 .mapsTo(MISCREG_CNTV_TVAL);
3893 InitReg(MISCREG_CNTV_CTL_EL0)
3894 .allPrivileges()
3895 .mapsTo(MISCREG_CNTV_CTL);
3896 InitReg(MISCREG_CNTV_CVAL_EL0)
3897 .allPrivileges()
3898 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
3899 InitReg(MISCREG_PMEVCNTR0_EL0)
3900 .allPrivileges();
3901// .mapsTo(MISCREG_PMEVCNTR0);
3902 InitReg(MISCREG_PMEVCNTR1_EL0)
3903 .allPrivileges();
3904// .mapsTo(MISCREG_PMEVCNTR1);
3905 InitReg(MISCREG_PMEVCNTR2_EL0)
3906 .allPrivileges();
3907// .mapsTo(MISCREG_PMEVCNTR2);
3908 InitReg(MISCREG_PMEVCNTR3_EL0)
3909 .allPrivileges();
3910// .mapsTo(MISCREG_PMEVCNTR3);
3911 InitReg(MISCREG_PMEVCNTR4_EL0)
3912 .allPrivileges();
3913// .mapsTo(MISCREG_PMEVCNTR4);
3914 InitReg(MISCREG_PMEVCNTR5_EL0)
3915 .allPrivileges();
3916// .mapsTo(MISCREG_PMEVCNTR5);
3917 InitReg(MISCREG_PMEVTYPER0_EL0)
3918 .allPrivileges();
3919// .mapsTo(MISCREG_PMEVTYPER0);
3920 InitReg(MISCREG_PMEVTYPER1_EL0)
3921 .allPrivileges();
3922// .mapsTo(MISCREG_PMEVTYPER1);
3923 InitReg(MISCREG_PMEVTYPER2_EL0)
3924 .allPrivileges();
3925// .mapsTo(MISCREG_PMEVTYPER2);
3926 InitReg(MISCREG_PMEVTYPER3_EL0)
3927 .allPrivileges();
3928// .mapsTo(MISCREG_PMEVTYPER3);
3929 InitReg(MISCREG_PMEVTYPER4_EL0)
3930 .allPrivileges();
3931// .mapsTo(MISCREG_PMEVTYPER4);
3932 InitReg(MISCREG_PMEVTYPER5_EL0)
3933 .allPrivileges();
3934// .mapsTo(MISCREG_PMEVTYPER5);
3935 InitReg(MISCREG_CNTVOFF_EL2)
3936 .hyp().mon()
3937 .mapsTo(MISCREG_CNTVOFF); /* 64b */
3938 InitReg(MISCREG_CNTHCTL_EL2)
3939 .unimplemented()
3940 .warnNotFail()
3941 .mon().monNonSecureWrite(0).hypWrite()
3942 .mapsTo(MISCREG_CNTHCTL);
3943 InitReg(MISCREG_CNTHP_TVAL_EL2)
3944 .unimplemented()
3945 .mon().monNonSecureWrite(0).hypWrite()
3946 .mapsTo(MISCREG_CNTHP_TVAL);
3947 InitReg(MISCREG_CNTHP_CTL_EL2)
3948 .unimplemented()
3949 .mon().monNonSecureWrite(0).hypWrite()
3950 .mapsTo(MISCREG_CNTHP_CTL);
3951 InitReg(MISCREG_CNTHP_CVAL_EL2)
3952 .unimplemented()
3953 .mon().monNonSecureWrite(0).hypWrite()
3954 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
3955 InitReg(MISCREG_CNTPS_TVAL_EL1)
3956 .unimplemented()
3957 .mon().monNonSecureWrite(0).hypWrite();
3958 InitReg(MISCREG_CNTPS_CTL_EL1)
3959 .unimplemented()
3960 .mon().monNonSecureWrite(0).hypWrite();
3961 InitReg(MISCREG_CNTPS_CVAL_EL1)
3962 .unimplemented()
3963 .mon().monNonSecureWrite(0).hypWrite();
3964 InitReg(MISCREG_IL1DATA0_EL1)
3965 .allPrivileges().exceptUserMode();
3966 InitReg(MISCREG_IL1DATA1_EL1)
3967 .allPrivileges().exceptUserMode();
3968 InitReg(MISCREG_IL1DATA2_EL1)
3969 .allPrivileges().exceptUserMode();
3970 InitReg(MISCREG_IL1DATA3_EL1)
3971 .allPrivileges().exceptUserMode();
3972 InitReg(MISCREG_DL1DATA0_EL1)
3973 .allPrivileges().exceptUserMode();
3974 InitReg(MISCREG_DL1DATA1_EL1)
3975 .allPrivileges().exceptUserMode();
3976 InitReg(MISCREG_DL1DATA2_EL1)
3977 .allPrivileges().exceptUserMode();
3978 InitReg(MISCREG_DL1DATA3_EL1)
3979 .allPrivileges().exceptUserMode();
3980 InitReg(MISCREG_DL1DATA4_EL1)
3981 .allPrivileges().exceptUserMode();
3982 InitReg(MISCREG_L2ACTLR_EL1)
3983 .allPrivileges().exceptUserMode();
3984 InitReg(MISCREG_CPUACTLR_EL1)
3985 .allPrivileges().exceptUserMode();
3986 InitReg(MISCREG_CPUECTLR_EL1)
3987 .allPrivileges().exceptUserMode();
3988 InitReg(MISCREG_CPUMERRSR_EL1)
3989 .allPrivileges().exceptUserMode();
3990 InitReg(MISCREG_L2MERRSR_EL1)
3991 .unimplemented()
3992 .warnNotFail()
3993 .allPrivileges().exceptUserMode();
3994 InitReg(MISCREG_CBAR_EL1)
3995 .allPrivileges().exceptUserMode().writes(0);
3996 InitReg(MISCREG_CONTEXTIDR_EL2)
3997 .mon().hyp();
3998
3999 // Dummy registers
4000 InitReg(MISCREG_NOP)
4001 .allPrivileges();
4002 InitReg(MISCREG_RAZ)
4003 .allPrivileges().exceptUserMode().writes(0);
4004 InitReg(MISCREG_CP14_UNIMPL)
4005 .unimplemented()
4006 .warnNotFail();
4007 InitReg(MISCREG_CP15_UNIMPL)
4008 .unimplemented()
4009 .warnNotFail();
4010 InitReg(MISCREG_UNKNOWN);
4011
4012 // Register mappings for some unimplemented registers:
4013 // ESR_EL1 -> DFSR
4014 // RMR_EL1 -> RMR
4015 // RMR_EL2 -> HRMR
4016 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
4017 // DBGDTRRX_EL0 -> DBGDTRRXint
4018 // DBGDTRTX_EL0 -> DBGDTRRXint
4019 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
4020
4021 completed = true;
4022}
4023
4024} // namespace ArmISA