1/*
2 * Copyright (c) 2010-2013, 2015-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 * Ali Saidi
39 * Giacomo Gabrielli
40 */
41
42#include "arch/arm/miscregs.hh"
43
44#include <tuple>
45
46#include "arch/arm/isa.hh"
47#include "base/logging.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51namespace ArmISA
52{
53
54MiscRegIndex
55decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
56{
57 switch(crn) {
58 case 0:
59 switch (opc1) {
60 case 0:
61 switch (opc2) {
62 case 0:
63 switch (crm) {
64 case 0:
65 return MISCREG_DBGDIDR;
66 case 1:
67 return MISCREG_DBGDSCRint;
68 }
69 break;
70 }
71 break;
72 case 7:
73 switch (opc2) {
74 case 0:
75 switch (crm) {
76 case 0:
77 return MISCREG_JIDR;
78 }
79 break;
80 }
81 break;
82 }
83 break;
84 case 1:
85 switch (opc1) {
86 case 6:
87 switch (crm) {
88 case 0:
89 switch (opc2) {
90 case 0:
91 return MISCREG_TEEHBR;
92 }
93 break;
94 }
95 break;
96 case 7:
97 switch (crm) {
98 case 0:
99 switch (opc2) {
100 case 0:
101 return MISCREG_JOSCR;
102 }
103 break;
104 }
105 break;
106 }
107 break;
108 case 2:
109 switch (opc1) {
110 case 7:
111 switch (crm) {
112 case 0:
113 switch (opc2) {
114 case 0:
115 return MISCREG_JMCR;
116 }
117 break;
118 }
119 break;
120 }
121 break;
122 }
123 // If we get here then it must be a register that we haven't implemented
124 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
125 crn, opc1, crm, opc2);
126 return MISCREG_CP14_UNIMPL;
127}
128
129using namespace std;
130
131MiscRegIndex
132decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
133{
134 switch (crn) {
135 case 0:
136 switch (opc1) {
137 case 0:
138 switch (crm) {
139 case 0:
140 switch (opc2) {
141 case 1:
142 return MISCREG_CTR;
143 case 2:
144 return MISCREG_TCMTR;
145 case 3:
146 return MISCREG_TLBTR;
147 case 5:
148 return MISCREG_MPIDR;
149 case 6:
150 return MISCREG_REVIDR;
151 default:
152 return MISCREG_MIDR;
153 }
154 break;
155 case 1:
156 switch (opc2) {
157 case 0:
158 return MISCREG_ID_PFR0;
159 case 1:
160 return MISCREG_ID_PFR1;
161 case 2:
162 return MISCREG_ID_DFR0;
163 case 3:
164 return MISCREG_ID_AFR0;
165 case 4:
166 return MISCREG_ID_MMFR0;
167 case 5:
168 return MISCREG_ID_MMFR1;
169 case 6:
170 return MISCREG_ID_MMFR2;
171 case 7:
172 return MISCREG_ID_MMFR3;
173 }
174 break;
175 case 2:
176 switch (opc2) {
177 case 0:
178 return MISCREG_ID_ISAR0;
179 case 1:
180 return MISCREG_ID_ISAR1;
181 case 2:
182 return MISCREG_ID_ISAR2;
183 case 3:
184 return MISCREG_ID_ISAR3;
185 case 4:
186 return MISCREG_ID_ISAR4;
187 case 5:
188 return MISCREG_ID_ISAR5;
189 case 6:
190 case 7:
191 return MISCREG_RAZ; // read as zero
192 }
193 break;
194 default:
195 return MISCREG_RAZ; // read as zero
196 }
197 break;
198 case 1:
199 if (crm == 0) {
200 switch (opc2) {
201 case 0:
202 return MISCREG_CCSIDR;
203 case 1:
204 return MISCREG_CLIDR;
205 case 7:
206 return MISCREG_AIDR;
207 }
208 }
209 break;
210 case 2:
211 if (crm == 0 && opc2 == 0) {
212 return MISCREG_CSSELR;
213 }
214 break;
215 case 4:
216 if (crm == 0) {
217 if (opc2 == 0)
218 return MISCREG_VPIDR;
219 else if (opc2 == 5)
220 return MISCREG_VMPIDR;
221 }
222 break;
223 }
224 break;
225 case 1:
226 if (opc1 == 0) {
227 if (crm == 0) {
228 switch (opc2) {
229 case 0:
230 return MISCREG_SCTLR;
231 case 1:
232 return MISCREG_ACTLR;
233 case 0x2:
234 return MISCREG_CPACR;
235 }
236 } else if (crm == 1) {
237 switch (opc2) {
238 case 0:
239 return MISCREG_SCR;
240 case 1:
241 return MISCREG_SDER;
242 case 2:
243 return MISCREG_NSACR;
244 }
245 }
246 } else if (opc1 == 4) {
247 if (crm == 0) {
248 if (opc2 == 0)
249 return MISCREG_HSCTLR;
250 else if (opc2 == 1)
251 return MISCREG_HACTLR;
252 } else if (crm == 1) {
253 switch (opc2) {
254 case 0:
255 return MISCREG_HCR;
256 case 1:
257 return MISCREG_HDCR;
258 case 2:
259 return MISCREG_HCPTR;
260 case 3:
261 return MISCREG_HSTR;
262 case 7:
263 return MISCREG_HACR;
264 }
265 }
266 }
267 break;
268 case 2:
269 if (opc1 == 0 && crm == 0) {
270 switch (opc2) {
271 case 0:
272 return MISCREG_TTBR0;
273 case 1:
274 return MISCREG_TTBR1;
275 case 2:
276 return MISCREG_TTBCR;
277 }
278 } else if (opc1 == 4) {
279 if (crm == 0 && opc2 == 2)
280 return MISCREG_HTCR;
281 else if (crm == 1 && opc2 == 2)
282 return MISCREG_VTCR;
283 }
284 break;
285 case 3:
286 if (opc1 == 0 && crm == 0 && opc2 == 0) {
287 return MISCREG_DACR;
288 }
289 break;
290 case 5:
291 if (opc1 == 0) {
292 if (crm == 0) {
293 if (opc2 == 0) {
294 return MISCREG_DFSR;
295 } else if (opc2 == 1) {
296 return MISCREG_IFSR;
297 }
298 } else if (crm == 1) {
299 if (opc2 == 0) {
300 return MISCREG_ADFSR;
301 } else if (opc2 == 1) {
302 return MISCREG_AIFSR;
303 }
304 }
305 } else if (opc1 == 4) {
306 if (crm == 1) {
307 if (opc2 == 0)
308 return MISCREG_HADFSR;
309 else if (opc2 == 1)
310 return MISCREG_HAIFSR;
311 } else if (crm == 2 && opc2 == 0) {
312 return MISCREG_HSR;
313 }
314 }
315 break;
316 case 6:
317 if (opc1 == 0 && crm == 0) {
318 switch (opc2) {
319 case 0:
320 return MISCREG_DFAR;
321 case 2:
322 return MISCREG_IFAR;
323 }
324 } else if (opc1 == 4 && crm == 0) {
325 switch (opc2) {
326 case 0:
327 return MISCREG_HDFAR;
328 case 2:
329 return MISCREG_HIFAR;
330 case 4:
331 return MISCREG_HPFAR;
332 }
333 }
334 break;
335 case 7:
336 if (opc1 == 0) {
337 switch (crm) {
338 case 0:
339 if (opc2 == 4) {
340 return MISCREG_NOP;
341 }
342 break;
343 case 1:
344 switch (opc2) {
345 case 0:
346 return MISCREG_ICIALLUIS;
347 case 6:
348 return MISCREG_BPIALLIS;
349 }
350 break;
351 case 4:
352 if (opc2 == 0) {
353 return MISCREG_PAR;
354 }
355 break;
356 case 5:
357 switch (opc2) {
358 case 0:
359 return MISCREG_ICIALLU;
360 case 1:
361 return MISCREG_ICIMVAU;
362 case 4:
363 return MISCREG_CP15ISB;
364 case 6:
365 return MISCREG_BPIALL;
366 case 7:
367 return MISCREG_BPIMVA;
368 }
369 break;
370 case 6:
371 if (opc2 == 1) {
372 return MISCREG_DCIMVAC;
373 } else if (opc2 == 2) {
374 return MISCREG_DCISW;
375 }
376 break;
377 case 8:
378 switch (opc2) {
379 case 0:
380 return MISCREG_ATS1CPR;
381 case 1:
382 return MISCREG_ATS1CPW;
383 case 2:
384 return MISCREG_ATS1CUR;
385 case 3:
386 return MISCREG_ATS1CUW;
387 case 4:
388 return MISCREG_ATS12NSOPR;
389 case 5:
390 return MISCREG_ATS12NSOPW;
391 case 6:
392 return MISCREG_ATS12NSOUR;
393 case 7:
394 return MISCREG_ATS12NSOUW;
395 }
396 break;
397 case 10:
398 switch (opc2) {
399 case 1:
400 return MISCREG_DCCMVAC;
401 case 2:
402 return MISCREG_DCCSW;
403 case 4:
404 return MISCREG_CP15DSB;
405 case 5:
406 return MISCREG_CP15DMB;
407 }
408 break;
409 case 11:
410 if (opc2 == 1) {
411 return MISCREG_DCCMVAU;
412 }
413 break;
414 case 13:
415 if (opc2 == 1) {
416 return MISCREG_NOP;
417 }
418 break;
419 case 14:
420 if (opc2 == 1) {
421 return MISCREG_DCCIMVAC;
422 } else if (opc2 == 2) {
423 return MISCREG_DCCISW;
424 }
425 break;
426 }
427 } else if (opc1 == 4 && crm == 8) {
428 if (opc2 == 0)
429 return MISCREG_ATS1HR;
430 else if (opc2 == 1)
431 return MISCREG_ATS1HW;
432 }
433 break;
434 case 8:
435 if (opc1 == 0) {
436 switch (crm) {
437 case 3:
438 switch (opc2) {
439 case 0:
440 return MISCREG_TLBIALLIS;
441 case 1:
442 return MISCREG_TLBIMVAIS;
443 case 2:
444 return MISCREG_TLBIASIDIS;
445 case 3:
446 return MISCREG_TLBIMVAAIS;
447 case 5:
448 return MISCREG_TLBIMVALIS;
449 case 7:
450 return MISCREG_TLBIMVAALIS;
451 }
452 break;
453 case 5:
454 switch (opc2) {
455 case 0:
456 return MISCREG_ITLBIALL;
457 case 1:
458 return MISCREG_ITLBIMVA;
459 case 2:
460 return MISCREG_ITLBIASID;
461 }
462 break;
463 case 6:
464 switch (opc2) {
465 case 0:
466 return MISCREG_DTLBIALL;
467 case 1:
468 return MISCREG_DTLBIMVA;
469 case 2:
470 return MISCREG_DTLBIASID;
471 }
472 break;
473 case 7:
474 switch (opc2) {
475 case 0:
476 return MISCREG_TLBIALL;
477 case 1:
478 return MISCREG_TLBIMVA;
479 case 2:
480 return MISCREG_TLBIASID;
481 case 3:
482 return MISCREG_TLBIMVAA;
483 case 5:
484 return MISCREG_TLBIMVAL;
485 case 7:
486 return MISCREG_TLBIMVAAL;
487 }
488 break;
489 }
490 } else if (opc1 == 4) {
491 if (crm == 0) {
492 switch (opc2) {
493 case 1:
494 return MISCREG_TLBIIPAS2IS;
495 case 5:
496 return MISCREG_TLBIIPAS2LIS;
497 }
498 } else if (crm == 3) {
499 switch (opc2) {
500 case 0:
501 return MISCREG_TLBIALLHIS;
502 case 1:
503 return MISCREG_TLBIMVAHIS;
504 case 4:
505 return MISCREG_TLBIALLNSNHIS;
506 case 5:
507 return MISCREG_TLBIMVALHIS;
508 }
509 } else if (crm == 4) {
510 switch (opc2) {
511 case 1:
512 return MISCREG_TLBIIPAS2;
513 case 5:
514 return MISCREG_TLBIIPAS2L;
515 }
516 } else if (crm == 7) {
517 switch (opc2) {
518 case 0:
519 return MISCREG_TLBIALLH;
520 case 1:
521 return MISCREG_TLBIMVAH;
522 case 4:
523 return MISCREG_TLBIALLNSNH;
524 case 5:
525 return MISCREG_TLBIMVALH;
526 }
527 }
528 }
529 break;
530 case 9:
531 // Every cop register with CRn = 9 and CRm in
532 // {0-2}, {5-8} is implementation defined regardless
533 // of opc1 and opc2.
534 switch (crm) {
535 case 0:
536 case 1:
537 case 2:
538 case 5:
539 case 6:
540 case 7:
541 case 8:
542 return MISCREG_IMPDEF_UNIMPL;
543 }
544 if (opc1 == 0) {
545 switch (crm) {
546 case 12:
547 switch (opc2) {
548 case 0:
549 return MISCREG_PMCR;
550 case 1:
551 return MISCREG_PMCNTENSET;
552 case 2:
553 return MISCREG_PMCNTENCLR;
554 case 3:
555 return MISCREG_PMOVSR;
556 case 4:
557 return MISCREG_PMSWINC;
558 case 5:
559 return MISCREG_PMSELR;
560 case 6:
561 return MISCREG_PMCEID0;
562 case 7:
563 return MISCREG_PMCEID1;
564 }
565 break;
566 case 13:
567 switch (opc2) {
568 case 0:
569 return MISCREG_PMCCNTR;
570 case 1:
571 // Selector is PMSELR.SEL
572 return MISCREG_PMXEVTYPER_PMCCFILTR;
573 case 2:
574 return MISCREG_PMXEVCNTR;
575 }
576 break;
577 case 14:
578 switch (opc2) {
579 case 0:
580 return MISCREG_PMUSERENR;
581 case 1:
582 return MISCREG_PMINTENSET;
583 case 2:
584 return MISCREG_PMINTENCLR;
585 case 3:
586 return MISCREG_PMOVSSET;
587 }
588 break;
589 }
590 } else if (opc1 == 1) {
591 switch (crm) {
592 case 0:
593 switch (opc2) {
594 case 2: // L2CTLR, L2 Control Register
595 return MISCREG_L2CTLR;
596 case 3:
597 return MISCREG_L2ECTLR;
598 }
599 break;
600 break;
601 }
602 }
603 break;
604 case 10:
605 if (opc1 == 0) {
606 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
607 if (crm < 2) {
608 return MISCREG_IMPDEF_UNIMPL;
609 } else if (crm == 2) { // TEX Remap Registers
610 if (opc2 == 0) {
611 // Selector is TTBCR.EAE
612 return MISCREG_PRRR_MAIR0;
613 } else if (opc2 == 1) {
614 // Selector is TTBCR.EAE
615 return MISCREG_NMRR_MAIR1;
616 }
617 } else if (crm == 3) {
618 if (opc2 == 0) {
619 return MISCREG_AMAIR0;
620 } else if (opc2 == 1) {
621 return MISCREG_AMAIR1;
622 }
623 }
624 } else if (opc1 == 4) {
625 // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
626 if (crm == 2) {
627 if (opc2 == 0)
628 return MISCREG_HMAIR0;
629 else if (opc2 == 1)
630 return MISCREG_HMAIR1;
631 } else if (crm == 3) {
632 if (opc2 == 0)
633 return MISCREG_HAMAIR0;
634 else if (opc2 == 1)
635 return MISCREG_HAMAIR1;
636 }
637 }
638 break;
639 case 11:
640 if (opc1 <=7) {
641 switch (crm) {
642 case 0:
643 case 1:
644 case 2:
645 case 3:
646 case 4:
647 case 5:
648 case 6:
649 case 7:
650 case 8:
651 case 15:
652 // Reserved for DMA operations for TCM access
653 return MISCREG_IMPDEF_UNIMPL;
654 default:
655 break;
656 }
657 }
658 break;
659 case 12:
660 if (opc1 == 0) {
661 if (crm == 0) {
662 if (opc2 == 0) {
663 return MISCREG_VBAR;
664 } else if (opc2 == 1) {
665 return MISCREG_MVBAR;
666 }
667 } else if (crm == 1) {
668 if (opc2 == 0) {
669 return MISCREG_ISR;
670 }
671 }
672 } else if (opc1 == 4) {
673 if (crm == 0 && opc2 == 0)
674 return MISCREG_HVBAR;
675 }
676 break;
677 case 13:
678 if (opc1 == 0) {
679 if (crm == 0) {
680 switch (opc2) {
681 case 0:
682 return MISCREG_FCSEIDR;
683 case 1:
684 return MISCREG_CONTEXTIDR;
685 case 2:
686 return MISCREG_TPIDRURW;
687 case 3:
688 return MISCREG_TPIDRURO;
689 case 4:
690 return MISCREG_TPIDRPRW;
691 }
692 }
693 } else if (opc1 == 4) {
694 if (crm == 0 && opc2 == 2)
695 return MISCREG_HTPIDR;
696 }
697 break;
698 case 14:
699 if (opc1 == 0) {
700 switch (crm) {
701 case 0:
702 if (opc2 == 0)
703 return MISCREG_CNTFRQ;
704 break;
705 case 1:
706 if (opc2 == 0)
707 return MISCREG_CNTKCTL;
708 break;
709 case 2:
710 if (opc2 == 0)
711 return MISCREG_CNTP_TVAL;
712 else if (opc2 == 1)
713 return MISCREG_CNTP_CTL;
714 break;
715 case 3:
716 if (opc2 == 0)
717 return MISCREG_CNTV_TVAL;
718 else if (opc2 == 1)
719 return MISCREG_CNTV_CTL;
720 break;
721 }
722 } else if (opc1 == 4) {
723 if (crm == 1 && opc2 == 0) {
724 return MISCREG_CNTHCTL;
725 } else if (crm == 2) {
726 if (opc2 == 0)
727 return MISCREG_CNTHP_TVAL;
728 else if (opc2 == 1)
729 return MISCREG_CNTHP_CTL;
730 }
731 }
732 break;
733 case 15:
734 // Implementation defined
735 return MISCREG_IMPDEF_UNIMPL;
736 }
737 // Unrecognized register
738 return MISCREG_CP15_UNIMPL;
739}
740
741MiscRegIndex
742decodeCP15Reg64(unsigned crm, unsigned opc1)
743{
744 switch (crm) {
745 case 2:
746 switch (opc1) {
747 case 0:
748 return MISCREG_TTBR0;
749 case 1:
750 return MISCREG_TTBR1;
751 case 4:
752 return MISCREG_HTTBR;
753 case 6:
754 return MISCREG_VTTBR;
755 }
756 break;
757 case 7:
758 if (opc1 == 0)
759 return MISCREG_PAR;
760 break;
761 case 14:
762 switch (opc1) {
763 case 0:
764 return MISCREG_CNTPCT;
765 case 1:
766 return MISCREG_CNTVCT;
767 case 2:
768 return MISCREG_CNTP_CVAL;
769 case 3:
770 return MISCREG_CNTV_CVAL;
771 case 4:
772 return MISCREG_CNTVOFF;
773 case 6:
774 return MISCREG_CNTHP_CVAL;
775 }
776 break;
777 case 15:
778 if (opc1 == 0)
779 return MISCREG_CPUMERRSR;
780 else if (opc1 == 1)
781 return MISCREG_L2MERRSR;
782 break;
783 }
784 // Unrecognized register
785 return MISCREG_CP15_UNIMPL;
786}
787
788std::tuple<bool, bool>
789canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
790{
791 bool secure = !scr.ns;
792 bool canRead = false;
793 bool undefined = false;
794
795 switch (cpsr.mode) {
796 case MODE_USER:
797 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
798 miscRegInfo[reg][MISCREG_USR_NS_RD];
799 break;
800 case MODE_FIQ:
801 case MODE_IRQ:
802 case MODE_SVC:
803 case MODE_ABORT:
804 case MODE_UNDEFINED:
805 case MODE_SYSTEM:
806 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
807 miscRegInfo[reg][MISCREG_PRI_NS_RD];
808 break;
809 case MODE_MON:
810 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
811 miscRegInfo[reg][MISCREG_MON_NS1_RD];
812 break;
813 case MODE_HYP:
814 canRead = miscRegInfo[reg][MISCREG_HYP_RD];
815 break;
816 default:
817 undefined = true;
818 }
819 // can't do permissions checkes on the root of a banked pair of regs
820 assert(!miscRegInfo[reg][MISCREG_BANKED]);
821 return std::make_tuple(canRead, undefined);
822}
823
824std::tuple<bool, bool>
825canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
826{
827 bool secure = !scr.ns;
828 bool canWrite = false;
829 bool undefined = false;
830
831 switch (cpsr.mode) {
832 case MODE_USER:
833 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
834 miscRegInfo[reg][MISCREG_USR_NS_WR];
835 break;
836 case MODE_FIQ:
837 case MODE_IRQ:
838 case MODE_SVC:
839 case MODE_ABORT:
840 case MODE_UNDEFINED:
841 case MODE_SYSTEM:
842 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
843 miscRegInfo[reg][MISCREG_PRI_NS_WR];
844 break;
845 case MODE_MON:
846 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
847 miscRegInfo[reg][MISCREG_MON_NS1_WR];
848 break;
849 case MODE_HYP:
850 canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
851 break;
852 default:
853 undefined = true;
854 }
855 // can't do permissions checkes on the root of a banked pair of regs
856 assert(!miscRegInfo[reg][MISCREG_BANKED]);
857 return std::make_tuple(canWrite, undefined);
858}
859
860int
861snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
862{
863 SCR scr = tc->readMiscReg(MISCREG_SCR);
864 return snsBankedIndex(reg, tc, scr.ns);
865}
866
867int
868snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
869{
870 int reg_as_int = static_cast<int>(reg);
871 if (miscRegInfo[reg][MISCREG_BANKED]) {
872 reg_as_int += (ArmSystem::haveSecurity(tc) &&
873 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
874 }
875 return reg_as_int;
876}
877
878
879/**
880 * If the reg is a child reg of a banked set, then the parent is the last
881 * banked one in the list. This is messy, and the wish is to eventually have
882 * the bitmap replaced with a better data structure. the preUnflatten function
883 * initializes a lookup table to speed up the search for these banked
884 * registers.
885 */
886
887int unflattenResultMiscReg[NUM_MISCREGS];
888
889void
890preUnflattenMiscReg()
891{
892 int reg = -1;
893 for (int i = 0 ; i < NUM_MISCREGS; i++){
894 if (miscRegInfo[i][MISCREG_BANKED])
895 reg = i;
896 if (miscRegInfo[i][MISCREG_BANKED_CHILD])
897 unflattenResultMiscReg[i] = reg;
898 else
899 unflattenResultMiscReg[i] = i;
900 // if this assert fails, no parent was found, and something is broken
901 assert(unflattenResultMiscReg[i] > -1);
902 }
903}
904
905int
906unflattenMiscReg(int reg)
907{
908 return unflattenResultMiscReg[reg];
909}
910
911bool
912canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
913{
914 // Check for SP_EL0 access while SPSEL == 0
915 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
916 return false;
917
918 // Check for RVBAR access
919 if (reg == MISCREG_RVBAR_EL1) {
920 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
921 if (highest_el == EL2 || highest_el == EL3)
922 return false;
923 }
924 if (reg == MISCREG_RVBAR_EL2) {
925 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
926 if (highest_el == EL3)
927 return false;
928 }
929
930 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
931
932 switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
933 case EL0:
934 return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
935 miscRegInfo[reg][MISCREG_USR_NS_RD];
936 case EL1:
937 return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
938 miscRegInfo[reg][MISCREG_PRI_NS_RD];
939 case EL2:
940 return miscRegInfo[reg][MISCREG_HYP_RD];
941 case EL3:
942 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
943 miscRegInfo[reg][MISCREG_MON_NS1_RD];
944 default:
945 panic("Invalid exception level");
946 }
947}
948
949bool
950canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
951{
952 // Check for SP_EL0 access while SPSEL == 0
953 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
954 return false;
955 ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
956 if (reg == MISCREG_DAIF) {
957 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
958 if (el == EL0 && !sctlr.uma)
959 return false;
960 }
961 if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
962 // In syscall-emulation mode, this test is skipped and DCZVA is always
963 // allowed at EL0
964 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
965 if (el == EL0 && !sctlr.dze)
966 return false;
967 }
968 if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
969 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
970 if (el == EL0 && !sctlr.uci)
971 return false;
972 }
973
974 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
975
976 switch (el) {
977 case EL0:
978 return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
979 miscRegInfo[reg][MISCREG_USR_NS_WR];
980 case EL1:
981 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
982 miscRegInfo[reg][MISCREG_PRI_NS_WR];
983 case EL2:
984 return miscRegInfo[reg][MISCREG_HYP_WR];
985 case EL3:
986 return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
987 miscRegInfo[reg][MISCREG_MON_NS1_WR];
988 default:
989 panic("Invalid exception level");
990 }
991}
992
993MiscRegIndex
994decodeAArch64SysReg(unsigned op0, unsigned op1,
995 unsigned crn, unsigned crm,
996 unsigned op2)
997{
998 switch (op0) {
999 case 1:
1000 switch (crn) {
1001 case 7:
1002 switch (op1) {
1003 case 0:
1004 switch (crm) {
1005 case 1:
1006 switch (op2) {
1007 case 0:
1008 return MISCREG_IC_IALLUIS;
1009 }
1010 break;
1011 case 5:
1012 switch (op2) {
1013 case 0:
1014 return MISCREG_IC_IALLU;
1015 }
1016 break;
1017 case 6:
1018 switch (op2) {
1019 case 1:
1020 return MISCREG_DC_IVAC_Xt;
1021 case 2:
1022 return MISCREG_DC_ISW_Xt;
1023 }
1024 break;
1025 case 8:
1026 switch (op2) {
1027 case 0:
1028 return MISCREG_AT_S1E1R_Xt;
1029 case 1:
1030 return MISCREG_AT_S1E1W_Xt;
1031 case 2:
1032 return MISCREG_AT_S1E0R_Xt;
1033 case 3:
1034 return MISCREG_AT_S1E0W_Xt;
1035 }
1036 break;
1037 case 10:
1038 switch (op2) {
1039 case 2:
1040 return MISCREG_DC_CSW_Xt;
1041 }
1042 break;
1043 case 14:
1044 switch (op2) {
1045 case 2:
1046 return MISCREG_DC_CISW_Xt;
1047 }
1048 break;
1049 }
1050 break;
1051 case 3:
1052 switch (crm) {
1053 case 4:
1054 switch (op2) {
1055 case 1:
1056 return MISCREG_DC_ZVA_Xt;
1057 }
1058 break;
1059 case 5:
1060 switch (op2) {
1061 case 1:
1062 return MISCREG_IC_IVAU_Xt;
1063 }
1064 break;
1065 case 10:
1066 switch (op2) {
1067 case 1:
1068 return MISCREG_DC_CVAC_Xt;
1069 }
1070 break;
1071 case 11:
1072 switch (op2) {
1073 case 1:
1074 return MISCREG_DC_CVAU_Xt;
1075 }
1076 break;
1077 case 14:
1078 switch (op2) {
1079 case 1:
1080 return MISCREG_DC_CIVAC_Xt;
1081 }
1082 break;
1083 }
1084 break;
1085 case 4:
1086 switch (crm) {
1087 case 8:
1088 switch (op2) {
1089 case 0:
1090 return MISCREG_AT_S1E2R_Xt;
1091 case 1:
1092 return MISCREG_AT_S1E2W_Xt;
1093 case 4:
1094 return MISCREG_AT_S12E1R_Xt;
1095 case 5:
1096 return MISCREG_AT_S12E1W_Xt;
1097 case 6:
1098 return MISCREG_AT_S12E0R_Xt;
1099 case 7:
1100 return MISCREG_AT_S12E0W_Xt;
1101 }
1102 break;
1103 }
1104 break;
1105 case 6:
1106 switch (crm) {
1107 case 8:
1108 switch (op2) {
1109 case 0:
1110 return MISCREG_AT_S1E3R_Xt;
1111 case 1:
1112 return MISCREG_AT_S1E3W_Xt;
1113 }
1114 break;
1115 }
1116 break;
1117 }
1118 break;
1119 case 8:
1120 switch (op1) {
1121 case 0:
1122 switch (crm) {
1123 case 3:
1124 switch (op2) {
1125 case 0:
1126 return MISCREG_TLBI_VMALLE1IS;
1127 case 1:
1128 return MISCREG_TLBI_VAE1IS_Xt;
1129 case 2:
1130 return MISCREG_TLBI_ASIDE1IS_Xt;
1131 case 3:
1132 return MISCREG_TLBI_VAAE1IS_Xt;
1133 case 5:
1134 return MISCREG_TLBI_VALE1IS_Xt;
1135 case 7:
1136 return MISCREG_TLBI_VAALE1IS_Xt;
1137 }
1138 break;
1139 case 7:
1140 switch (op2) {
1141 case 0:
1142 return MISCREG_TLBI_VMALLE1;
1143 case 1:
1144 return MISCREG_TLBI_VAE1_Xt;
1145 case 2:
1146 return MISCREG_TLBI_ASIDE1_Xt;
1147 case 3:
1148 return MISCREG_TLBI_VAAE1_Xt;
1149 case 5:
1150 return MISCREG_TLBI_VALE1_Xt;
1151 case 7:
1152 return MISCREG_TLBI_VAALE1_Xt;
1153 }
1154 break;
1155 }
1156 break;
1157 case 4:
1158 switch (crm) {
1159 case 0:
1160 switch (op2) {
1161 case 1:
1162 return MISCREG_TLBI_IPAS2E1IS_Xt;
1163 case 5:
1164 return MISCREG_TLBI_IPAS2LE1IS_Xt;
1165 }
1166 break;
1167 case 3:
1168 switch (op2) {
1169 case 0:
1170 return MISCREG_TLBI_ALLE2IS;
1171 case 1:
1172 return MISCREG_TLBI_VAE2IS_Xt;
1173 case 4:
1174 return MISCREG_TLBI_ALLE1IS;
1175 case 5:
1176 return MISCREG_TLBI_VALE2IS_Xt;
1177 case 6:
1178 return MISCREG_TLBI_VMALLS12E1IS;
1179 }
1180 break;
1181 case 4:
1182 switch (op2) {
1183 case 1:
1184 return MISCREG_TLBI_IPAS2E1_Xt;
1185 case 5:
1186 return MISCREG_TLBI_IPAS2LE1_Xt;
1187 }
1188 break;
1189 case 7:
1190 switch (op2) {
1191 case 0:
1192 return MISCREG_TLBI_ALLE2;
1193 case 1:
1194 return MISCREG_TLBI_VAE2_Xt;
1195 case 4:
1196 return MISCREG_TLBI_ALLE1;
1197 case 5:
1198 return MISCREG_TLBI_VALE2_Xt;
1199 case 6:
1200 return MISCREG_TLBI_VMALLS12E1;
1201 }
1202 break;
1203 }
1204 break;
1205 case 6:
1206 switch (crm) {
1207 case 3:
1208 switch (op2) {
1209 case 0:
1210 return MISCREG_TLBI_ALLE3IS;
1211 case 1:
1212 return MISCREG_TLBI_VAE3IS_Xt;
1213 case 5:
1214 return MISCREG_TLBI_VALE3IS_Xt;
1215 }
1216 break;
1217 case 7:
1218 switch (op2) {
1219 case 0:
1220 return MISCREG_TLBI_ALLE3;
1221 case 1:
1222 return MISCREG_TLBI_VAE3_Xt;
1223 case 5:
1224 return MISCREG_TLBI_VALE3_Xt;
1225 }
1226 break;
1227 }
1228 break;
1229 }
1230 break;
1231 }
1232 break;
1233 case 2:
1234 switch (crn) {
1235 case 0:
1236 switch (op1) {
1237 case 0:
1238 switch (crm) {
1239 case 0:
1240 switch (op2) {
1241 case 2:
1242 return MISCREG_OSDTRRX_EL1;
1243 case 4:
1244 return MISCREG_DBGBVR0_EL1;
1245 case 5:
1246 return MISCREG_DBGBCR0_EL1;
1247 case 6:
1248 return MISCREG_DBGWVR0_EL1;
1249 case 7:
1250 return MISCREG_DBGWCR0_EL1;
1251 }
1252 break;
1253 case 1:
1254 switch (op2) {
1255 case 4:
1256 return MISCREG_DBGBVR1_EL1;
1257 case 5:
1258 return MISCREG_DBGBCR1_EL1;
1259 case 6:
1260 return MISCREG_DBGWVR1_EL1;
1261 case 7:
1262 return MISCREG_DBGWCR1_EL1;
1263 }
1264 break;
1265 case 2:
1266 switch (op2) {
1267 case 0:
1268 return MISCREG_MDCCINT_EL1;
1269 case 2:
1270 return MISCREG_MDSCR_EL1;
1271 case 4:
1272 return MISCREG_DBGBVR2_EL1;
1273 case 5:
1274 return MISCREG_DBGBCR2_EL1;
1275 case 6:
1276 return MISCREG_DBGWVR2_EL1;
1277 case 7:
1278 return MISCREG_DBGWCR2_EL1;
1279 }
1280 break;
1281 case 3:
1282 switch (op2) {
1283 case 2:
1284 return MISCREG_OSDTRTX_EL1;
1285 case 4:
1286 return MISCREG_DBGBVR3_EL1;
1287 case 5:
1288 return MISCREG_DBGBCR3_EL1;
1289 case 6:
1290 return MISCREG_DBGWVR3_EL1;
1291 case 7:
1292 return MISCREG_DBGWCR3_EL1;
1293 }
1294 break;
1295 case 4:
1296 switch (op2) {
1297 case 4:
1298 return MISCREG_DBGBVR4_EL1;
1299 case 5:
1300 return MISCREG_DBGBCR4_EL1;
1301 }
1302 break;
1303 case 5:
1304 switch (op2) {
1305 case 4:
1306 return MISCREG_DBGBVR5_EL1;
1307 case 5:
1308 return MISCREG_DBGBCR5_EL1;
1309 }
1310 break;
1311 case 6:
1312 switch (op2) {
1313 case 2:
1314 return MISCREG_OSECCR_EL1;
1315 }
1316 break;
1317 }
1318 break;
1319 case 2:
1320 switch (crm) {
1321 case 0:
1322 switch (op2) {
1323 case 0:
1324 return MISCREG_TEECR32_EL1;
1325 }
1326 break;
1327 }
1328 break;
1329 case 3:
1330 switch (crm) {
1331 case 1:
1332 switch (op2) {
1333 case 0:
1334 return MISCREG_MDCCSR_EL0;
1335 }
1336 break;
1337 case 4:
1338 switch (op2) {
1339 case 0:
1340 return MISCREG_MDDTR_EL0;
1341 }
1342 break;
1343 case 5:
1344 switch (op2) {
1345 case 0:
1346 return MISCREG_MDDTRRX_EL0;
1347 }
1348 break;
1349 }
1350 break;
1351 case 4:
1352 switch (crm) {
1353 case 7:
1354 switch (op2) {
1355 case 0:
1356 return MISCREG_DBGVCR32_EL2;
1357 }
1358 break;
1359 }
1360 break;
1361 }
1362 break;
1363 case 1:
1364 switch (op1) {
1365 case 0:
1366 switch (crm) {
1367 case 0:
1368 switch (op2) {
1369 case 0:
1370 return MISCREG_MDRAR_EL1;
1371 case 4:
1372 return MISCREG_OSLAR_EL1;
1373 }
1374 break;
1375 case 1:
1376 switch (op2) {
1377 case 4:
1378 return MISCREG_OSLSR_EL1;
1379 }
1380 break;
1381 case 3:
1382 switch (op2) {
1383 case 4:
1384 return MISCREG_OSDLR_EL1;
1385 }
1386 break;
1387 case 4:
1388 switch (op2) {
1389 case 4:
1390 return MISCREG_DBGPRCR_EL1;
1391 }
1392 break;
1393 }
1394 break;
1395 case 2:
1396 switch (crm) {
1397 case 0:
1398 switch (op2) {
1399 case 0:
1400 return MISCREG_TEEHBR32_EL1;
1401 }
1402 break;
1403 }
1404 break;
1405 }
1406 break;
1407 case 7:
1408 switch (op1) {
1409 case 0:
1410 switch (crm) {
1411 case 8:
1412 switch (op2) {
1413 case 6:
1414 return MISCREG_DBGCLAIMSET_EL1;
1415 }
1416 break;
1417 case 9:
1418 switch (op2) {
1419 case 6:
1420 return MISCREG_DBGCLAIMCLR_EL1;
1421 }
1422 break;
1423 case 14:
1424 switch (op2) {
1425 case 6:
1426 return MISCREG_DBGAUTHSTATUS_EL1;
1427 }
1428 break;
1429 }
1430 break;
1431 }
1432 break;
1433 }
1434 break;
1435 case 3:
1436 switch (crn) {
1437 case 0:
1438 switch (op1) {
1439 case 0:
1440 switch (crm) {
1441 case 0:
1442 switch (op2) {
1443 case 0:
1444 return MISCREG_MIDR_EL1;
1445 case 5:
1446 return MISCREG_MPIDR_EL1;
1447 case 6:
1448 return MISCREG_REVIDR_EL1;
1449 }
1450 break;
1451 case 1:
1452 switch (op2) {
1453 case 0:
1454 return MISCREG_ID_PFR0_EL1;
1455 case 1:
1456 return MISCREG_ID_PFR1_EL1;
1457 case 2:
1458 return MISCREG_ID_DFR0_EL1;
1459 case 3:
1460 return MISCREG_ID_AFR0_EL1;
1461 case 4:
1462 return MISCREG_ID_MMFR0_EL1;
1463 case 5:
1464 return MISCREG_ID_MMFR1_EL1;
1465 case 6:
1466 return MISCREG_ID_MMFR2_EL1;
1467 case 7:
1468 return MISCREG_ID_MMFR3_EL1;
1469 }
1470 break;
1471 case 2:
1472 switch (op2) {
1473 case 0:
1474 return MISCREG_ID_ISAR0_EL1;
1475 case 1:
1476 return MISCREG_ID_ISAR1_EL1;
1477 case 2:
1478 return MISCREG_ID_ISAR2_EL1;
1479 case 3:
1480 return MISCREG_ID_ISAR3_EL1;
1481 case 4:
1482 return MISCREG_ID_ISAR4_EL1;
1483 case 5:
1484 return MISCREG_ID_ISAR5_EL1;
1485 }
1486 break;
1487 case 3:
1488 switch (op2) {
1489 case 0:
1490 return MISCREG_MVFR0_EL1;
1491 case 1:
1492 return MISCREG_MVFR1_EL1;
1493 case 2:
1494 return MISCREG_MVFR2_EL1;
1495 case 3 ... 7:
1496 return MISCREG_RAZ;
1497 }
1498 break;
1499 case 4:
1500 switch (op2) {
1501 case 0:
1502 return MISCREG_ID_AA64PFR0_EL1;
1503 case 1:
1504 return MISCREG_ID_AA64PFR1_EL1;
1505 case 2 ... 7:
1506 return MISCREG_RAZ;
1507 }
1508 break;
1509 case 5:
1510 switch (op2) {
1511 case 0:
1512 return MISCREG_ID_AA64DFR0_EL1;
1513 case 1:
1514 return MISCREG_ID_AA64DFR1_EL1;
1515 case 4:
1516 return MISCREG_ID_AA64AFR0_EL1;
1517 case 5:
1518 return MISCREG_ID_AA64AFR1_EL1;
1519 case 2:
1520 case 3:
1521 case 6:
1522 case 7:
1523 return MISCREG_RAZ;
1524 }
1525 break;
1526 case 6:
1527 switch (op2) {
1528 case 0:
1529 return MISCREG_ID_AA64ISAR0_EL1;
1530 case 1:
1531 return MISCREG_ID_AA64ISAR1_EL1;
1532 case 2 ... 7:
1533 return MISCREG_RAZ;
1534 }
1535 break;
1536 case 7:
1537 switch (op2) {
1538 case 0:
1539 return MISCREG_ID_AA64MMFR0_EL1;
1540 case 1:
1541 return MISCREG_ID_AA64MMFR1_EL1;
1542 case 2 ... 7:
1543 return MISCREG_RAZ;
1544 }
1545 break;
1546 }
1547 break;
1548 case 1:
1549 switch (crm) {
1550 case 0:
1551 switch (op2) {
1552 case 0:
1553 return MISCREG_CCSIDR_EL1;
1554 case 1:
1555 return MISCREG_CLIDR_EL1;
1556 case 7:
1557 return MISCREG_AIDR_EL1;
1558 }
1559 break;
1560 }
1561 break;
1562 case 2:
1563 switch (crm) {
1564 case 0:
1565 switch (op2) {
1566 case 0:
1567 return MISCREG_CSSELR_EL1;
1568 }
1569 break;
1570 }
1571 break;
1572 case 3:
1573 switch (crm) {
1574 case 0:
1575 switch (op2) {
1576 case 1:
1577 return MISCREG_CTR_EL0;
1578 case 7:
1579 return MISCREG_DCZID_EL0;
1580 }
1581 break;
1582 }
1583 break;
1584 case 4:
1585 switch (crm) {
1586 case 0:
1587 switch (op2) {
1588 case 0:
1589 return MISCREG_VPIDR_EL2;
1590 case 5:
1591 return MISCREG_VMPIDR_EL2;
1592 }
1593 break;
1594 }
1595 break;
1596 }
1597 break;
1598 case 1:
1599 switch (op1) {
1600 case 0:
1601 switch (crm) {
1602 case 0:
1603 switch (op2) {
1604 case 0:
1605 return MISCREG_SCTLR_EL1;
1606 case 1:
1607 return MISCREG_ACTLR_EL1;
1608 case 2:
1609 return MISCREG_CPACR_EL1;
1610 }
1611 break;
1612 }
1613 break;
1614 case 4:
1615 switch (crm) {
1616 case 0:
1617 switch (op2) {
1618 case 0:
1619 return MISCREG_SCTLR_EL2;
1620 case 1:
1621 return MISCREG_ACTLR_EL2;
1622 }
1623 break;
1624 case 1:
1625 switch (op2) {
1626 case 0:
1627 return MISCREG_HCR_EL2;
1628 case 1:
1629 return MISCREG_MDCR_EL2;
1630 case 2:
1631 return MISCREG_CPTR_EL2;
1632 case 3:
1633 return MISCREG_HSTR_EL2;
1634 case 7:
1635 return MISCREG_HACR_EL2;
1636 }
1637 break;
1638 }
1639 break;
1640 case 6:
1641 switch (crm) {
1642 case 0:
1643 switch (op2) {
1644 case 0:
1645 return MISCREG_SCTLR_EL3;
1646 case 1:
1647 return MISCREG_ACTLR_EL3;
1648 }
1649 break;
1650 case 1:
1651 switch (op2) {
1652 case 0:
1653 return MISCREG_SCR_EL3;
1654 case 1:
1655 return MISCREG_SDER32_EL3;
1656 case 2:
1657 return MISCREG_CPTR_EL3;
1658 }
1659 break;
1660 case 3:
1661 switch (op2) {
1662 case 1:
1663 return MISCREG_MDCR_EL3;
1664 }
1665 break;
1666 }
1667 break;
1668 }
1669 break;
1670 case 2:
1671 switch (op1) {
1672 case 0:
1673 switch (crm) {
1674 case 0:
1675 switch (op2) {
1676 case 0:
1677 return MISCREG_TTBR0_EL1;
1678 case 1:
1679 return MISCREG_TTBR1_EL1;
1680 case 2:
1681 return MISCREG_TCR_EL1;
1682 }
1683 break;
1684 }
1685 break;
1686 case 4:
1687 switch (crm) {
1688 case 0:
1689 switch (op2) {
1690 case 0:
1691 return MISCREG_TTBR0_EL2;
1692 case 1:
1693 return MISCREG_TTBR1_EL2;
1694 case 2:
1695 return MISCREG_TCR_EL2;
1696 }
1697 break;
1698 case 1:
1699 switch (op2) {
1700 case 0:
1701 return MISCREG_VTTBR_EL2;
1702 case 2:
1703 return MISCREG_VTCR_EL2;
1704 }
1705 break;
1706 }
1707 break;
1708 case 6:
1709 switch (crm) {
1710 case 0:
1711 switch (op2) {
1712 case 0:
1713 return MISCREG_TTBR0_EL3;
1714 case 2:
1715 return MISCREG_TCR_EL3;
1716 }
1717 break;
1718 }
1719 break;
1720 }
1721 break;
1722 case 3:
1723 switch (op1) {
1724 case 4:
1725 switch (crm) {
1726 case 0:
1727 switch (op2) {
1728 case 0:
1729 return MISCREG_DACR32_EL2;
1730 }
1731 break;
1732 }
1733 break;
1734 }
1735 break;
1736 case 4:
1737 switch (op1) {
1738 case 0:
1739 switch (crm) {
1740 case 0:
1741 switch (op2) {
1742 case 0:
1743 return MISCREG_SPSR_EL1;
1744 case 1:
1745 return MISCREG_ELR_EL1;
1746 }
1747 break;
1748 case 1:
1749 switch (op2) {
1750 case 0:
1751 return MISCREG_SP_EL0;
1752 }
1753 break;
1754 case 2:
1755 switch (op2) {
1756 case 0:
1757 return MISCREG_SPSEL;
1758 case 2:
1759 return MISCREG_CURRENTEL;
1760 }
1761 break;
1762 }
1763 break;
1764 case 3:
1765 switch (crm) {
1766 case 2:
1767 switch (op2) {
1768 case 0:
1769 return MISCREG_NZCV;
1770 case 1:
1771 return MISCREG_DAIF;
1772 }
1773 break;
1774 case 4:
1775 switch (op2) {
1776 case 0:
1777 return MISCREG_FPCR;
1778 case 1:
1779 return MISCREG_FPSR;
1780 }
1781 break;
1782 case 5:
1783 switch (op2) {
1784 case 0:
1785 return MISCREG_DSPSR_EL0;
1786 case 1:
1787 return MISCREG_DLR_EL0;
1788 }
1789 break;
1790 }
1791 break;
1792 case 4:
1793 switch (crm) {
1794 case 0:
1795 switch (op2) {
1796 case 0:
1797 return MISCREG_SPSR_EL2;
1798 case 1:
1799 return MISCREG_ELR_EL2;
1800 }
1801 break;
1802 case 1:
1803 switch (op2) {
1804 case 0:
1805 return MISCREG_SP_EL1;
1806 }
1807 break;
1808 case 3:
1809 switch (op2) {
1810 case 0:
1811 return MISCREG_SPSR_IRQ_AA64;
1812 case 1:
1813 return MISCREG_SPSR_ABT_AA64;
1814 case 2:
1815 return MISCREG_SPSR_UND_AA64;
1816 case 3:
1817 return MISCREG_SPSR_FIQ_AA64;
1818 }
1819 break;
1820 }
1821 break;
1822 case 6:
1823 switch (crm) {
1824 case 0:
1825 switch (op2) {
1826 case 0:
1827 return MISCREG_SPSR_EL3;
1828 case 1:
1829 return MISCREG_ELR_EL3;
1830 }
1831 break;
1832 case 1:
1833 switch (op2) {
1834 case 0:
1835 return MISCREG_SP_EL2;
1836 }
1837 break;
1838 }
1839 break;
1840 }
1841 break;
1842 case 5:
1843 switch (op1) {
1844 case 0:
1845 switch (crm) {
1846 case 1:
1847 switch (op2) {
1848 case 0:
1849 return MISCREG_AFSR0_EL1;
1850 case 1:
1851 return MISCREG_AFSR1_EL1;
1852 }
1853 break;
1854 case 2:
1855 switch (op2) {
1856 case 0:
1857 return MISCREG_ESR_EL1;
1858 }
1859 break;
1860 }
1861 break;
1862 case 4:
1863 switch (crm) {
1864 case 0:
1865 switch (op2) {
1866 case 1:
1867 return MISCREG_IFSR32_EL2;
1868 }
1869 break;
1870 case 1:
1871 switch (op2) {
1872 case 0:
1873 return MISCREG_AFSR0_EL2;
1874 case 1:
1875 return MISCREG_AFSR1_EL2;
1876 }
1877 break;
1878 case 2:
1879 switch (op2) {
1880 case 0:
1881 return MISCREG_ESR_EL2;
1882 }
1883 break;
1884 case 3:
1885 switch (op2) {
1886 case 0:
1887 return MISCREG_FPEXC32_EL2;
1888 }
1889 break;
1890 }
1891 break;
1892 case 6:
1893 switch (crm) {
1894 case 1:
1895 switch (op2) {
1896 case 0:
1897 return MISCREG_AFSR0_EL3;
1898 case 1:
1899 return MISCREG_AFSR1_EL3;
1900 }
1901 break;
1902 case 2:
1903 switch (op2) {
1904 case 0:
1905 return MISCREG_ESR_EL3;
1906 }
1907 break;
1908 }
1909 break;
1910 }
1911 break;
1912 case 6:
1913 switch (op1) {
1914 case 0:
1915 switch (crm) {
1916 case 0:
1917 switch (op2) {
1918 case 0:
1919 return MISCREG_FAR_EL1;
1920 }
1921 break;
1922 }
1923 break;
1924 case 4:
1925 switch (crm) {
1926 case 0:
1927 switch (op2) {
1928 case 0:
1929 return MISCREG_FAR_EL2;
1930 case 4:
1931 return MISCREG_HPFAR_EL2;
1932 }
1933 break;
1934 }
1935 break;
1936 case 6:
1937 switch (crm) {
1938 case 0:
1939 switch (op2) {
1940 case 0:
1941 return MISCREG_FAR_EL3;
1942 }
1943 break;
1944 }
1945 break;
1946 }
1947 break;
1948 case 7:
1949 switch (op1) {
1950 case 0:
1951 switch (crm) {
1952 case 4:
1953 switch (op2) {
1954 case 0:
1955 return MISCREG_PAR_EL1;
1956 }
1957 break;
1958 }
1959 break;
1960 }
1961 break;
1962 case 9:
1963 switch (op1) {
1964 case 0:
1965 switch (crm) {
1966 case 14:
1967 switch (op2) {
1968 case 1:
1969 return MISCREG_PMINTENSET_EL1;
1970 case 2:
1971 return MISCREG_PMINTENCLR_EL1;
1972 }
1973 break;
1974 }
1975 break;
1976 case 3:
1977 switch (crm) {
1978 case 12:
1979 switch (op2) {
1980 case 0:
1981 return MISCREG_PMCR_EL0;
1982 case 1:
1983 return MISCREG_PMCNTENSET_EL0;
1984 case 2:
1985 return MISCREG_PMCNTENCLR_EL0;
1986 case 3:
1987 return MISCREG_PMOVSCLR_EL0;
1988 case 4:
1989 return MISCREG_PMSWINC_EL0;
1990 case 5:
1991 return MISCREG_PMSELR_EL0;
1992 case 6:
1993 return MISCREG_PMCEID0_EL0;
1994 case 7:
1995 return MISCREG_PMCEID1_EL0;
1996 }
1997 break;
1998 case 13:
1999 switch (op2) {
2000 case 0:
2001 return MISCREG_PMCCNTR_EL0;
2002 case 1:
2003 return MISCREG_PMXEVTYPER_EL0;
2004 case 2:
2005 return MISCREG_PMXEVCNTR_EL0;
2006 }
2007 break;
2008 case 14:
2009 switch (op2) {
2010 case 0:
2011 return MISCREG_PMUSERENR_EL0;
2012 case 3:
2013 return MISCREG_PMOVSSET_EL0;
2014 }
2015 break;
2016 }
2017 break;
2018 }
2019 break;
2020 case 10:
2021 switch (op1) {
2022 case 0:
2023 switch (crm) {
2024 case 2:
2025 switch (op2) {
2026 case 0:
2027 return MISCREG_MAIR_EL1;
2028 }
2029 break;
2030 case 3:
2031 switch (op2) {
2032 case 0:
2033 return MISCREG_AMAIR_EL1;
2034 }
2035 break;
2036 }
2037 break;
2038 case 4:
2039 switch (crm) {
2040 case 2:
2041 switch (op2) {
2042 case 0:
2043 return MISCREG_MAIR_EL2;
2044 }
2045 break;
2046 case 3:
2047 switch (op2) {
2048 case 0:
2049 return MISCREG_AMAIR_EL2;
2050 }
2051 break;
2052 }
2053 break;
2054 case 6:
2055 switch (crm) {
2056 case 2:
2057 switch (op2) {
2058 case 0:
2059 return MISCREG_MAIR_EL3;
2060 }
2061 break;
2062 case 3:
2063 switch (op2) {
2064 case 0:
2065 return MISCREG_AMAIR_EL3;
2066 }
2067 break;
2068 }
2069 break;
2070 }
2071 break;
2072 case 11:
2073 switch (op1) {
2074 case 1:
2075 switch (crm) {
2076 case 0:
2077 switch (op2) {
2078 case 2:
2079 return MISCREG_L2CTLR_EL1;
2080 case 3:
2081 return MISCREG_L2ECTLR_EL1;
2082 }
2083 break;
2084 }
2085 break;
2086 }
2087 break;
2088 case 12:
2089 switch (op1) {
2090 case 0:
2091 switch (crm) {
2092 case 0:
2093 switch (op2) {
2094 case 0:
2095 return MISCREG_VBAR_EL1;
2096 case 1:
2097 return MISCREG_RVBAR_EL1;
2098 }
2099 break;
2100 case 1:
2101 switch (op2) {
2102 case 0:
2103 return MISCREG_ISR_EL1;
2104 }
2105 break;
2106 }
2107 break;
2108 case 4:
2109 switch (crm) {
2110 case 0:
2111 switch (op2) {
2112 case 0:
2113 return MISCREG_VBAR_EL2;
2114 case 1:
2115 return MISCREG_RVBAR_EL2;
2116 }
2117 break;
2118 }
2119 break;
2120 case 6:
2121 switch (crm) {
2122 case 0:
2123 switch (op2) {
2124 case 0:
2125 return MISCREG_VBAR_EL3;
2126 case 1:
2127 return MISCREG_RVBAR_EL3;
2128 case 2:
2129 return MISCREG_RMR_EL3;
2130 }
2131 break;
2132 }
2133 break;
2134 }
2135 break;
2136 case 13:
2137 switch (op1) {
2138 case 0:
2139 switch (crm) {
2140 case 0:
2141 switch (op2) {
2142 case 1:
2143 return MISCREG_CONTEXTIDR_EL1;
2144 case 4:
2145 return MISCREG_TPIDR_EL1;
2146 }
2147 break;
2148 }
2149 break;
2150 case 3:
2151 switch (crm) {
2152 case 0:
2153 switch (op2) {
2154 case 2:
2155 return MISCREG_TPIDR_EL0;
2156 case 3:
2157 return MISCREG_TPIDRRO_EL0;
2158 }
2159 break;
2160 }
2161 break;
2162 case 4:
2163 switch (crm) {
2164 case 0:
2165 switch (op2) {
2166 case 1:
2167 return MISCREG_CONTEXTIDR_EL2;
2168 case 2:
2169 return MISCREG_TPIDR_EL2;
2170 }
2171 break;
2172 }
2173 break;
2174 case 6:
2175 switch (crm) {
2176 case 0:
2177 switch (op2) {
2178 case 2:
2179 return MISCREG_TPIDR_EL3;
2180 }
2181 break;
2182 }
2183 break;
2184 }
2185 break;
2186 case 14:
2187 switch (op1) {
2188 case 0:
2189 switch (crm) {
2190 case 1:
2191 switch (op2) {
2192 case 0:
2193 return MISCREG_CNTKCTL_EL1;
2194 }
2195 break;
2196 }
2197 break;
2198 case 3:
2199 switch (crm) {
2200 case 0:
2201 switch (op2) {
2202 case 0:
2203 return MISCREG_CNTFRQ_EL0;
2204 case 1:
2205 return MISCREG_CNTPCT_EL0;
2206 case 2:
2207 return MISCREG_CNTVCT_EL0;
2208 }
2209 break;
2210 case 2:
2211 switch (op2) {
2212 case 0:
2213 return MISCREG_CNTP_TVAL_EL0;
2214 case 1:
2215 return MISCREG_CNTP_CTL_EL0;
2216 case 2:
2217 return MISCREG_CNTP_CVAL_EL0;
2218 }
2219 break;
2220 case 3:
2221 switch (op2) {
2222 case 0:
2223 return MISCREG_CNTV_TVAL_EL0;
2224 case 1:
2225 return MISCREG_CNTV_CTL_EL0;
2226 case 2:
2227 return MISCREG_CNTV_CVAL_EL0;
2228 }
2229 break;
2230 case 8:
2231 switch (op2) {
2232 case 0:
2233 return MISCREG_PMEVCNTR0_EL0;
2234 case 1:
2235 return MISCREG_PMEVCNTR1_EL0;
2236 case 2:
2237 return MISCREG_PMEVCNTR2_EL0;
2238 case 3:
2239 return MISCREG_PMEVCNTR3_EL0;
2240 case 4:
2241 return MISCREG_PMEVCNTR4_EL0;
2242 case 5:
2243 return MISCREG_PMEVCNTR5_EL0;
2244 }
2245 break;
2246 case 12:
2247 switch (op2) {
2248 case 0:
2249 return MISCREG_PMEVTYPER0_EL0;
2250 case 1:
2251 return MISCREG_PMEVTYPER1_EL0;
2252 case 2:
2253 return MISCREG_PMEVTYPER2_EL0;
2254 case 3:
2255 return MISCREG_PMEVTYPER3_EL0;
2256 case 4:
2257 return MISCREG_PMEVTYPER4_EL0;
2258 case 5:
2259 return MISCREG_PMEVTYPER5_EL0;
2260 }
2261 break;
2262 case 15:
2263 switch (op2) {
2264 case 7:
2265 return MISCREG_PMCCFILTR_EL0;
2266 }
2267 }
2268 break;
2269 case 4:
2270 switch (crm) {
2271 case 0:
2272 switch (op2) {
2273 case 3:
2274 return MISCREG_CNTVOFF_EL2;
2275 }
2276 break;
2277 case 1:
2278 switch (op2) {
2279 case 0:
2280 return MISCREG_CNTHCTL_EL2;
2281 }
2282 break;
2283 case 2:
2284 switch (op2) {
2285 case 0:
2286 return MISCREG_CNTHP_TVAL_EL2;
2287 case 1:
2288 return MISCREG_CNTHP_CTL_EL2;
2289 case 2:
2290 return MISCREG_CNTHP_CVAL_EL2;
2291 }
2292 break;
2293 }
2294 break;
2295 case 7:
2296 switch (crm) {
2297 case 2:
2298 switch (op2) {
2299 case 0:
2300 return MISCREG_CNTPS_TVAL_EL1;
2301 case 1:
2302 return MISCREG_CNTPS_CTL_EL1;
2303 case 2:
2304 return MISCREG_CNTPS_CVAL_EL1;
2305 }
2306 break;
2307 }
2308 break;
2309 }
2310 break;
2311 case 15:
2312 switch (op1) {
2313 case 0:
2314 switch (crm) {
2315 case 0:
2316 switch (op2) {
2317 case 0:
2318 return MISCREG_IL1DATA0_EL1;
2319 case 1:
2320 return MISCREG_IL1DATA1_EL1;
2321 case 2:
2322 return MISCREG_IL1DATA2_EL1;
2323 case 3:
2324 return MISCREG_IL1DATA3_EL1;
2325 }
2326 break;
2327 case 1:
2328 switch (op2) {
2329 case 0:
2330 return MISCREG_DL1DATA0_EL1;
2331 case 1:
2332 return MISCREG_DL1DATA1_EL1;
2333 case 2:
2334 return MISCREG_DL1DATA2_EL1;
2335 case 3:
2336 return MISCREG_DL1DATA3_EL1;
2337 case 4:
2338 return MISCREG_DL1DATA4_EL1;
2339 }
2340 break;
2341 }
2342 break;
2343 case 1:
2344 switch (crm) {
2345 case 0:
2346 switch (op2) {
2347 case 0:
2348 return MISCREG_L2ACTLR_EL1;
2349 }
2350 break;
2351 case 2:
2352 switch (op2) {
2353 case 0:
2354 return MISCREG_CPUACTLR_EL1;
2355 case 1:
2356 return MISCREG_CPUECTLR_EL1;
2357 case 2:
2358 return MISCREG_CPUMERRSR_EL1;
2359 case 3:
2360 return MISCREG_L2MERRSR_EL1;
2361 }
2362 break;
2363 case 3:
2364 switch (op2) {
2365 case 0:
2366 return MISCREG_CBAR_EL1;
2367
2368 }
2369 break;
2370 }
2371 break;
2372 }
2373 break;
2374 }
2375 break;
2376 }
2377
2378 return MISCREG_UNKNOWN;
2379}
2380
2381bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
2382
2383void
2384ISA::initializeMiscRegMetadata()
2385{
2386 // the MiscReg metadata tables are shared across all instances of the
2387 // ISA object, so there's no need to initialize them multiple times.
2388 static bool completed = false;
2389 if (completed)
2390 return;
2391
2392 // This boolean variable specifies if the system is running in aarch32 at
2393 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
2394 // is running in aarch64 (aarch32EL3 = false)
2395 bool aarch32EL3 = haveSecurity && !highestELIs64;
2396
2397 /**
2398 * Some registers alias with others, and therefore need to be translated.
2399 * When two mapping registers are given, they are the 32b lower and
2400 * upper halves, respectively, of the 64b register being mapped.
2401 * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543
2402 *
2403 * NAM = "not architecturally mandated",
2404 * from ARM DDI 0487A.i, template text
2405 * "AArch64 System register ___ can be mapped to
2406 * AArch32 System register ___, but this is not
2407 * architecturally mandated."
2408 */
2409
2410 InitReg(MISCREG_CPSR)
2411 .allPrivileges();
2412 InitReg(MISCREG_SPSR)
2413 .allPrivileges();
2414 InitReg(MISCREG_SPSR_FIQ)
2415 .allPrivileges();
2416 InitReg(MISCREG_SPSR_IRQ)
2417 .allPrivileges();
2418 InitReg(MISCREG_SPSR_SVC)
2419 .allPrivileges();
2420 InitReg(MISCREG_SPSR_MON)
2421 .allPrivileges();
2422 InitReg(MISCREG_SPSR_ABT)
2423 .allPrivileges();
2424 InitReg(MISCREG_SPSR_HYP)
2425 .allPrivileges();
2426 InitReg(MISCREG_SPSR_UND)
2427 .allPrivileges();
2428 InitReg(MISCREG_ELR_HYP)
2429 .allPrivileges();
2430 InitReg(MISCREG_FPSID)
2431 .allPrivileges();
2432 InitReg(MISCREG_FPSCR)
2433 .allPrivileges();
2434 InitReg(MISCREG_MVFR1)
2435 .allPrivileges();
2436 InitReg(MISCREG_MVFR0)
2437 .allPrivileges();
2438 InitReg(MISCREG_FPEXC)
2439 .allPrivileges();
2440
2441 // Helper registers
2442 InitReg(MISCREG_CPSR_MODE)
2443 .allPrivileges();
2444 InitReg(MISCREG_CPSR_Q)
2445 .allPrivileges();
2446 InitReg(MISCREG_FPSCR_EXC)
2447 .allPrivileges();
2448 InitReg(MISCREG_FPSCR_QC)
2449 .allPrivileges();
2450 InitReg(MISCREG_LOCKADDR)
2451 .allPrivileges();
2452 InitReg(MISCREG_LOCKFLAG)
2453 .allPrivileges();
2454 InitReg(MISCREG_PRRR_MAIR0)
2455 .mutex()
2456 .banked();
2457 InitReg(MISCREG_PRRR_MAIR0_NS)
2458 .mutex()
2459 .privSecure(!aarch32EL3)
2460 .bankedChild();
2461 InitReg(MISCREG_PRRR_MAIR0_S)
2462 .mutex()
2463 .bankedChild();
2464 InitReg(MISCREG_NMRR_MAIR1)
2465 .mutex()
2466 .banked();
2467 InitReg(MISCREG_NMRR_MAIR1_NS)
2468 .mutex()
2469 .privSecure(!aarch32EL3)
2470 .bankedChild();
2471 InitReg(MISCREG_NMRR_MAIR1_S)
2472 .mutex()
2473 .bankedChild();
2474 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
2475 .mutex();
2476 InitReg(MISCREG_SCTLR_RST)
2477 .allPrivileges();
2478 InitReg(MISCREG_SEV_MAILBOX)
2479 .allPrivileges();
2480
2481 // AArch32 CP14 registers
2482 InitReg(MISCREG_DBGDIDR)
2483 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2484 InitReg(MISCREG_DBGDSCRint)
2485 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2486 InitReg(MISCREG_DBGDCCINT)
2487 .unimplemented()
2488 .allPrivileges();
2489 InitReg(MISCREG_DBGDTRTXint)
2490 .unimplemented()
2491 .allPrivileges();
2492 InitReg(MISCREG_DBGDTRRXint)
2493 .unimplemented()
2494 .allPrivileges();
2495 InitReg(MISCREG_DBGWFAR)
2496 .unimplemented()
2497 .allPrivileges();
2498 InitReg(MISCREG_DBGVCR)
2499 .unimplemented()
2500 .allPrivileges();
2501 InitReg(MISCREG_DBGDTRRXext)
2502 .unimplemented()
2503 .allPrivileges();
2504 InitReg(MISCREG_DBGDSCRext)
2505 .unimplemented()
2506 .warnNotFail()
2507 .allPrivileges();
2508 InitReg(MISCREG_DBGDTRTXext)
2509 .unimplemented()
2510 .allPrivileges();
2511 InitReg(MISCREG_DBGOSECCR)
2512 .unimplemented()
2513 .allPrivileges();
2514 InitReg(MISCREG_DBGBVR0)
2515 .unimplemented()
2516 .allPrivileges();
2517 InitReg(MISCREG_DBGBVR1)
2518 .unimplemented()
2519 .allPrivileges();
2520 InitReg(MISCREG_DBGBVR2)
2521 .unimplemented()
2522 .allPrivileges();
2523 InitReg(MISCREG_DBGBVR3)
2524 .unimplemented()
2525 .allPrivileges();
2526 InitReg(MISCREG_DBGBVR4)
2527 .unimplemented()
2528 .allPrivileges();
2529 InitReg(MISCREG_DBGBVR5)
2530 .unimplemented()
2531 .allPrivileges();
2532 InitReg(MISCREG_DBGBCR0)
2533 .unimplemented()
2534 .allPrivileges();
2535 InitReg(MISCREG_DBGBCR1)
2536 .unimplemented()
2537 .allPrivileges();
2538 InitReg(MISCREG_DBGBCR2)
2539 .unimplemented()
2540 .allPrivileges();
2541 InitReg(MISCREG_DBGBCR3)
2542 .unimplemented()
2543 .allPrivileges();
2544 InitReg(MISCREG_DBGBCR4)
2545 .unimplemented()
2546 .allPrivileges();
2547 InitReg(MISCREG_DBGBCR5)
2548 .unimplemented()
2549 .allPrivileges();
2550 InitReg(MISCREG_DBGWVR0)
2551 .unimplemented()
2552 .allPrivileges();
2553 InitReg(MISCREG_DBGWVR1)
2554 .unimplemented()
2555 .allPrivileges();
2556 InitReg(MISCREG_DBGWVR2)
2557 .unimplemented()
2558 .allPrivileges();
2559 InitReg(MISCREG_DBGWVR3)
2560 .unimplemented()
2561 .allPrivileges();
2562 InitReg(MISCREG_DBGWCR0)
2563 .unimplemented()
2564 .allPrivileges();
2565 InitReg(MISCREG_DBGWCR1)
2566 .unimplemented()
2567 .allPrivileges();
2568 InitReg(MISCREG_DBGWCR2)
2569 .unimplemented()
2570 .allPrivileges();
2571 InitReg(MISCREG_DBGWCR3)
2572 .unimplemented()
2573 .allPrivileges();
2574 InitReg(MISCREG_DBGDRAR)
2575 .unimplemented()
2576 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2577 InitReg(MISCREG_DBGBXVR4)
2578 .unimplemented()
2579 .allPrivileges();
2580 InitReg(MISCREG_DBGBXVR5)
2581 .unimplemented()
2582 .allPrivileges();
2583 InitReg(MISCREG_DBGOSLAR)
2584 .unimplemented()
2585 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
2586 InitReg(MISCREG_DBGOSLSR)
2587 .unimplemented()
2588 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2589 InitReg(MISCREG_DBGOSDLR)
2590 .unimplemented()
2591 .allPrivileges();
2592 InitReg(MISCREG_DBGPRCR)
2593 .unimplemented()
2594 .allPrivileges();
2595 InitReg(MISCREG_DBGDSAR)
2596 .unimplemented()
2597 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2598 InitReg(MISCREG_DBGCLAIMSET)
2599 .unimplemented()
2600 .allPrivileges();
2601 InitReg(MISCREG_DBGCLAIMCLR)
2602 .unimplemented()
2603 .allPrivileges();
2604 InitReg(MISCREG_DBGAUTHSTATUS)
2605 .unimplemented()
2606 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2607 InitReg(MISCREG_DBGDEVID2)
2608 .unimplemented()
2609 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2610 InitReg(MISCREG_DBGDEVID1)
2611 .unimplemented()
2612 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2613 InitReg(MISCREG_DBGDEVID0)
2614 .unimplemented()
2615 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
2616 InitReg(MISCREG_TEECR)
2617 .unimplemented()
2618 .allPrivileges();
2619 InitReg(MISCREG_JIDR)
2620 .allPrivileges();
2621 InitReg(MISCREG_TEEHBR)
2622 .allPrivileges();
2623 InitReg(MISCREG_JOSCR)
2624 .allPrivileges();
2625 InitReg(MISCREG_JMCR)
2626 .allPrivileges();
2627
2628 // AArch32 CP15 registers
2629 InitReg(MISCREG_MIDR)
2630 .allPrivileges().exceptUserMode().writes(0);
2631 InitReg(MISCREG_CTR)
2632 .allPrivileges().exceptUserMode().writes(0);
2633 InitReg(MISCREG_TCMTR)
2634 .allPrivileges().exceptUserMode().writes(0);
2635 InitReg(MISCREG_TLBTR)
2636 .allPrivileges().exceptUserMode().writes(0);
2637 InitReg(MISCREG_MPIDR)
2638 .allPrivileges().exceptUserMode().writes(0);
2639 InitReg(MISCREG_REVIDR)
2640 .unimplemented()
2641 .warnNotFail()
2642 .allPrivileges().exceptUserMode().writes(0);
2643 InitReg(MISCREG_ID_PFR0)
2644 .allPrivileges().exceptUserMode().writes(0);
2645 InitReg(MISCREG_ID_PFR1)
2646 .allPrivileges().exceptUserMode().writes(0);
2647 InitReg(MISCREG_ID_DFR0)
2648 .allPrivileges().exceptUserMode().writes(0);
2649 InitReg(MISCREG_ID_AFR0)
2650 .allPrivileges().exceptUserMode().writes(0);
2651 InitReg(MISCREG_ID_MMFR0)
2652 .allPrivileges().exceptUserMode().writes(0);
2653 InitReg(MISCREG_ID_MMFR1)
2654 .allPrivileges().exceptUserMode().writes(0);
2655 InitReg(MISCREG_ID_MMFR2)
2656 .allPrivileges().exceptUserMode().writes(0);
2657 InitReg(MISCREG_ID_MMFR3)
2658 .allPrivileges().exceptUserMode().writes(0);
2659 InitReg(MISCREG_ID_ISAR0)
2660 .allPrivileges().exceptUserMode().writes(0);
2661 InitReg(MISCREG_ID_ISAR1)
2662 .allPrivileges().exceptUserMode().writes(0);
2663 InitReg(MISCREG_ID_ISAR2)
2664 .allPrivileges().exceptUserMode().writes(0);
2665 InitReg(MISCREG_ID_ISAR3)
2666 .allPrivileges().exceptUserMode().writes(0);
2667 InitReg(MISCREG_ID_ISAR4)
2668 .allPrivileges().exceptUserMode().writes(0);
2669 InitReg(MISCREG_ID_ISAR5)
2670 .allPrivileges().exceptUserMode().writes(0);
2671 InitReg(MISCREG_CCSIDR)
2672 .allPrivileges().exceptUserMode().writes(0);
2673 InitReg(MISCREG_CLIDR)
2674 .allPrivileges().exceptUserMode().writes(0);
2675 InitReg(MISCREG_AIDR)
2676 .allPrivileges().exceptUserMode().writes(0);
2677 InitReg(MISCREG_CSSELR)
2678 .banked();
2679 InitReg(MISCREG_CSSELR_NS)
2680 .bankedChild()
2681 .privSecure(!aarch32EL3)
2682 .nonSecure().exceptUserMode();
2683 InitReg(MISCREG_CSSELR_S)
2684 .bankedChild()
2685 .secure().exceptUserMode();
2686 InitReg(MISCREG_VPIDR)
2687 .hyp().monNonSecure();
2688 InitReg(MISCREG_VMPIDR)
2689 .hyp().monNonSecure();
2690 InitReg(MISCREG_SCTLR)
2691 .banked();
2692 InitReg(MISCREG_SCTLR_NS)
2693 .bankedChild()
2694 .privSecure(!aarch32EL3)
2695 .nonSecure().exceptUserMode();
2696 InitReg(MISCREG_SCTLR_S)
2697 .bankedChild()
2698 .secure().exceptUserMode();
2699 InitReg(MISCREG_ACTLR)
2700 .banked();
2701 InitReg(MISCREG_ACTLR_NS)
2702 .bankedChild()
2703 .privSecure(!aarch32EL3)
2704 .nonSecure().exceptUserMode();
2705 InitReg(MISCREG_ACTLR_S)
2706 .bankedChild()
2707 .secure().exceptUserMode();
2708 InitReg(MISCREG_CPACR)
2709 .allPrivileges().exceptUserMode();
2710 InitReg(MISCREG_SCR)
2711 .mon().secure().exceptUserMode()
2712 .res0(0xff40) // [31:16], [6]
2713 .res1(0x0030); // [5:4]
2714 InitReg(MISCREG_SDER)
2715 .mon();
2716 InitReg(MISCREG_NSACR)
2717 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
2718 InitReg(MISCREG_HSCTLR)
2719 .hyp().monNonSecure();
2720 InitReg(MISCREG_HACTLR)
2721 .hyp().monNonSecure();
2722 InitReg(MISCREG_HCR)
2723 .hyp().monNonSecure();
2724 InitReg(MISCREG_HDCR)
2725 .hyp().monNonSecure();
2726 InitReg(MISCREG_HCPTR)
2727 .hyp().monNonSecure();
2728 InitReg(MISCREG_HSTR)
2729 .hyp().monNonSecure();
2730 InitReg(MISCREG_HACR)
2731 .unimplemented()
2732 .warnNotFail()
2733 .hyp().monNonSecure();
2734 InitReg(MISCREG_TTBR0)
2735 .banked();
2736 InitReg(MISCREG_TTBR0_NS)
2737 .bankedChild()
2738 .privSecure(!aarch32EL3)
2739 .nonSecure().exceptUserMode();
2740 InitReg(MISCREG_TTBR0_S)
2741 .bankedChild()
2742 .secure().exceptUserMode();
2743 InitReg(MISCREG_TTBR1)
2744 .banked();
2745 InitReg(MISCREG_TTBR1_NS)
2746 .bankedChild()
2747 .privSecure(!aarch32EL3)
2748 .nonSecure().exceptUserMode();
2749 InitReg(MISCREG_TTBR1_S)
2750 .bankedChild()
2751 .secure().exceptUserMode();
2752 InitReg(MISCREG_TTBCR)
2753 .banked();
2754 InitReg(MISCREG_TTBCR_NS)
2755 .bankedChild()
2756 .privSecure(!aarch32EL3)
2757 .nonSecure().exceptUserMode();
2758 InitReg(MISCREG_TTBCR_S)
2759 .bankedChild()
2760 .secure().exceptUserMode();
2761 InitReg(MISCREG_HTCR)
2762 .hyp().monNonSecure();
2763 InitReg(MISCREG_VTCR)
2764 .hyp().monNonSecure();
2765 InitReg(MISCREG_DACR)
2766 .banked();
2767 InitReg(MISCREG_DACR_NS)
2768 .bankedChild()
2769 .privSecure(!aarch32EL3)
2770 .nonSecure().exceptUserMode();
2771 InitReg(MISCREG_DACR_S)
2772 .bankedChild()
2773 .secure().exceptUserMode();
2774 InitReg(MISCREG_DFSR)
2775 .banked();
2776 InitReg(MISCREG_DFSR_NS)
2777 .bankedChild()
2778 .privSecure(!aarch32EL3)
2779 .nonSecure().exceptUserMode();
2780 InitReg(MISCREG_DFSR_S)
2781 .bankedChild()
2782 .secure().exceptUserMode();
2783 InitReg(MISCREG_IFSR)
2784 .banked();
2785 InitReg(MISCREG_IFSR_NS)
2786 .bankedChild()
2787 .privSecure(!aarch32EL3)
2788 .nonSecure().exceptUserMode();
2789 InitReg(MISCREG_IFSR_S)
2790 .bankedChild()
2791 .secure().exceptUserMode();
2792 InitReg(MISCREG_ADFSR)
2793 .unimplemented()
2794 .warnNotFail()
2795 .banked();
2796 InitReg(MISCREG_ADFSR_NS)
2797 .unimplemented()
2798 .warnNotFail()
2799 .bankedChild()
2800 .privSecure(!aarch32EL3)
2801 .nonSecure().exceptUserMode();
2802 InitReg(MISCREG_ADFSR_S)
2803 .unimplemented()
2804 .warnNotFail()
2805 .bankedChild()
2806 .secure().exceptUserMode();
2807 InitReg(MISCREG_AIFSR)
2808 .unimplemented()
2809 .warnNotFail()
2810 .banked();
2811 InitReg(MISCREG_AIFSR_NS)
2812 .unimplemented()
2813 .warnNotFail()
2814 .bankedChild()
2815 .privSecure(!aarch32EL3)
2816 .nonSecure().exceptUserMode();
2817 InitReg(MISCREG_AIFSR_S)
2818 .unimplemented()
2819 .warnNotFail()
2820 .bankedChild()
2821 .secure().exceptUserMode();
2822 InitReg(MISCREG_HADFSR)
2823 .hyp().monNonSecure();
2824 InitReg(MISCREG_HAIFSR)
2825 .hyp().monNonSecure();
2826 InitReg(MISCREG_HSR)
2827 .hyp().monNonSecure();
2828 InitReg(MISCREG_DFAR)
2829 .banked();
2830 InitReg(MISCREG_DFAR_NS)
2831 .bankedChild()
2832 .privSecure(!aarch32EL3)
2833 .nonSecure().exceptUserMode();
2834 InitReg(MISCREG_DFAR_S)
2835 .bankedChild()
2836 .secure().exceptUserMode();
2837 InitReg(MISCREG_IFAR)
2838 .banked();
2839 InitReg(MISCREG_IFAR_NS)
2840 .bankedChild()
2841 .privSecure(!aarch32EL3)
2842 .nonSecure().exceptUserMode();
2843 InitReg(MISCREG_IFAR_S)
2844 .bankedChild()
2845 .secure().exceptUserMode();
2846 InitReg(MISCREG_HDFAR)
2847 .hyp().monNonSecure();
2848 InitReg(MISCREG_HIFAR)
2849 .hyp().monNonSecure();
2850 InitReg(MISCREG_HPFAR)
2851 .hyp().monNonSecure();
2852 InitReg(MISCREG_ICIALLUIS)
2853 .unimplemented()
2854 .warnNotFail()
2855 .writes(1).exceptUserMode();
2856 InitReg(MISCREG_BPIALLIS)
2857 .unimplemented()
2858 .warnNotFail()
2859 .writes(1).exceptUserMode();
2860 InitReg(MISCREG_PAR)
2861 .banked();
2862 InitReg(MISCREG_PAR_NS)
2863 .bankedChild()
2864 .privSecure(!aarch32EL3)
2865 .nonSecure().exceptUserMode();
2866 InitReg(MISCREG_PAR_S)
2867 .bankedChild()
2868 .secure().exceptUserMode();
2869 InitReg(MISCREG_ICIALLU)
2870 .writes(1).exceptUserMode();
2871 InitReg(MISCREG_ICIMVAU)
2872 .unimplemented()
2873 .warnNotFail()
2874 .writes(1).exceptUserMode();
2875 InitReg(MISCREG_CP15ISB)
2876 .writes(1);
2877 InitReg(MISCREG_BPIALL)
2878 .unimplemented()
2879 .warnNotFail()
2880 .writes(1).exceptUserMode();
2881 InitReg(MISCREG_BPIMVA)
2882 .unimplemented()
2883 .warnNotFail()
2884 .writes(1).exceptUserMode();
2885 InitReg(MISCREG_DCIMVAC)
2886 .unimplemented()
2887 .warnNotFail()
2888 .writes(1).exceptUserMode();
2889 InitReg(MISCREG_DCISW)
2890 .unimplemented()
2891 .warnNotFail()
2892 .writes(1).exceptUserMode();
2893 InitReg(MISCREG_ATS1CPR)
2894 .writes(1).exceptUserMode();
2895 InitReg(MISCREG_ATS1CPW)
2896 .writes(1).exceptUserMode();
2897 InitReg(MISCREG_ATS1CUR)
2898 .writes(1).exceptUserMode();
2899 InitReg(MISCREG_ATS1CUW)
2900 .writes(1).exceptUserMode();
2901 InitReg(MISCREG_ATS12NSOPR)
2902 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2903 InitReg(MISCREG_ATS12NSOPW)
2904 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2905 InitReg(MISCREG_ATS12NSOUR)
2906 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2907 InitReg(MISCREG_ATS12NSOUW)
2908 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
2909 InitReg(MISCREG_DCCMVAC)
2910 .writes(1).exceptUserMode();
2911 InitReg(MISCREG_DCCSW)
2912 .unimplemented()
2913 .warnNotFail()
2914 .writes(1).exceptUserMode();
2915 InitReg(MISCREG_CP15DSB)
2916 .writes(1);
2917 InitReg(MISCREG_CP15DMB)
2918 .writes(1);
2919 InitReg(MISCREG_DCCMVAU)
2920 .unimplemented()
2921 .warnNotFail()
2922 .writes(1).exceptUserMode();
2923 InitReg(MISCREG_DCCIMVAC)
2924 .unimplemented()
2925 .warnNotFail()
2926 .writes(1).exceptUserMode();
2927 InitReg(MISCREG_DCCISW)
2928 .unimplemented()
2929 .warnNotFail()
2930 .writes(1).exceptUserMode();
2931 InitReg(MISCREG_ATS1HR)
2932 .monNonSecureWrite().hypWrite();
2933 InitReg(MISCREG_ATS1HW)
2934 .monNonSecureWrite().hypWrite();
2935 InitReg(MISCREG_TLBIALLIS)
2936 .writes(1).exceptUserMode();
2937 InitReg(MISCREG_TLBIMVAIS)
2938 .writes(1).exceptUserMode();
2939 InitReg(MISCREG_TLBIASIDIS)
2940 .writes(1).exceptUserMode();
2941 InitReg(MISCREG_TLBIMVAAIS)
2942 .writes(1).exceptUserMode();
2943 InitReg(MISCREG_TLBIMVALIS)
2944 .writes(1).exceptUserMode();
2945 InitReg(MISCREG_TLBIMVAALIS)
2946 .writes(1).exceptUserMode();
2947 InitReg(MISCREG_ITLBIALL)
2948 .writes(1).exceptUserMode();
2949 InitReg(MISCREG_ITLBIMVA)
2950 .writes(1).exceptUserMode();
2951 InitReg(MISCREG_ITLBIASID)
2952 .writes(1).exceptUserMode();
2953 InitReg(MISCREG_DTLBIALL)
2954 .writes(1).exceptUserMode();
2955 InitReg(MISCREG_DTLBIMVA)
2956 .writes(1).exceptUserMode();
2957 InitReg(MISCREG_DTLBIASID)
2958 .writes(1).exceptUserMode();
2959 InitReg(MISCREG_TLBIALL)
2960 .writes(1).exceptUserMode();
2961 InitReg(MISCREG_TLBIMVA)
2962 .writes(1).exceptUserMode();
2963 InitReg(MISCREG_TLBIASID)
2964 .writes(1).exceptUserMode();
2965 InitReg(MISCREG_TLBIMVAA)
2966 .writes(1).exceptUserMode();
2967 InitReg(MISCREG_TLBIMVAL)
2968 .writes(1).exceptUserMode();
2969 InitReg(MISCREG_TLBIMVAAL)
2970 .writes(1).exceptUserMode();
2971 InitReg(MISCREG_TLBIIPAS2IS)
2972 .monNonSecureWrite().hypWrite();
2973 InitReg(MISCREG_TLBIIPAS2LIS)
2974 .monNonSecureWrite().hypWrite();
2975 InitReg(MISCREG_TLBIALLHIS)
2976 .monNonSecureWrite().hypWrite();
2977 InitReg(MISCREG_TLBIMVAHIS)
2978 .monNonSecureWrite().hypWrite();
2979 InitReg(MISCREG_TLBIALLNSNHIS)
2980 .monNonSecureWrite().hypWrite();
2981 InitReg(MISCREG_TLBIMVALHIS)
2982 .monNonSecureWrite().hypWrite();
2983 InitReg(MISCREG_TLBIIPAS2)
2984 .monNonSecureWrite().hypWrite();
2985 InitReg(MISCREG_TLBIIPAS2L)
2986 .monNonSecureWrite().hypWrite();
2987 InitReg(MISCREG_TLBIALLH)
2988 .monNonSecureWrite().hypWrite();
2989 InitReg(MISCREG_TLBIMVAH)
2990 .monNonSecureWrite().hypWrite();
2991 InitReg(MISCREG_TLBIALLNSNH)
2992 .monNonSecureWrite().hypWrite();
2993 InitReg(MISCREG_TLBIMVALH)
2994 .monNonSecureWrite().hypWrite();
2995 InitReg(MISCREG_PMCR)
2996 .allPrivileges();
2997 InitReg(MISCREG_PMCNTENSET)
2998 .allPrivileges();
2999 InitReg(MISCREG_PMCNTENCLR)
3000 .allPrivileges();
3001 InitReg(MISCREG_PMOVSR)
3002 .allPrivileges();
3003 InitReg(MISCREG_PMSWINC)
3004 .allPrivileges();
3005 InitReg(MISCREG_PMSELR)
3006 .allPrivileges();
3007 InitReg(MISCREG_PMCEID0)
3008 .allPrivileges();
3009 InitReg(MISCREG_PMCEID1)
3010 .allPrivileges();
3011 InitReg(MISCREG_PMCCNTR)
3012 .allPrivileges();
3013 InitReg(MISCREG_PMXEVTYPER)
3014 .allPrivileges();
3015 InitReg(MISCREG_PMCCFILTR)
3016 .allPrivileges();
3017 InitReg(MISCREG_PMXEVCNTR)
3018 .allPrivileges();
3019 InitReg(MISCREG_PMUSERENR)
3020 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
3021 InitReg(MISCREG_PMINTENSET)
3022 .allPrivileges().exceptUserMode();
3023 InitReg(MISCREG_PMINTENCLR)
3024 .allPrivileges().exceptUserMode();
3025 InitReg(MISCREG_PMOVSSET)
3026 .unimplemented()
3027 .allPrivileges();
3028 InitReg(MISCREG_L2CTLR)
3029 .allPrivileges().exceptUserMode();
3030 InitReg(MISCREG_L2ECTLR)
3031 .unimplemented()
3032 .allPrivileges().exceptUserMode();
3033 InitReg(MISCREG_PRRR)
3034 .banked();
3035 InitReg(MISCREG_PRRR_NS)
3036 .bankedChild()
3037 .privSecure(!aarch32EL3)
3038 .nonSecure().exceptUserMode();
3039 InitReg(MISCREG_PRRR_S)
3040 .bankedChild()
3041 .secure().exceptUserMode();
3042 InitReg(MISCREG_MAIR0)
3043 .banked();
3044 InitReg(MISCREG_MAIR0_NS)
3045 .bankedChild()
3046 .privSecure(!aarch32EL3)
3047 .nonSecure().exceptUserMode();
3048 InitReg(MISCREG_MAIR0_S)
3049 .bankedChild()
3050 .secure().exceptUserMode();
3051 InitReg(MISCREG_NMRR)
3052 .banked();
3053 InitReg(MISCREG_NMRR_NS)
3054 .bankedChild()
3055 .privSecure(!aarch32EL3)
3056 .nonSecure().exceptUserMode();
3057 InitReg(MISCREG_NMRR_S)
3058 .bankedChild()
3059 .secure().exceptUserMode();
3060 InitReg(MISCREG_MAIR1)
3061 .banked();
3062 InitReg(MISCREG_MAIR1_NS)
3063 .bankedChild()
3064 .privSecure(!aarch32EL3)
3065 .nonSecure().exceptUserMode();
3066 InitReg(MISCREG_MAIR1_S)
3067 .bankedChild()
3068 .secure().exceptUserMode();
3069 InitReg(MISCREG_AMAIR0)
3070 .banked();
3071 InitReg(MISCREG_AMAIR0_NS)
3072 .bankedChild()
3073 .privSecure(!aarch32EL3)
3074 .nonSecure().exceptUserMode();
3075 InitReg(MISCREG_AMAIR0_S)
3076 .bankedChild()
3077 .secure().exceptUserMode();
3078 InitReg(MISCREG_AMAIR1)
3079 .banked();
3080 InitReg(MISCREG_AMAIR1_NS)
3081 .bankedChild()
3082 .privSecure(!aarch32EL3)
3083 .nonSecure().exceptUserMode();
3084 InitReg(MISCREG_AMAIR1_S)
3085 .bankedChild()
3086 .secure().exceptUserMode();
3087 InitReg(MISCREG_HMAIR0)
3088 .hyp().monNonSecure();
3089 InitReg(MISCREG_HMAIR1)
3090 .hyp().monNonSecure();
3091 InitReg(MISCREG_HAMAIR0)
3092 .unimplemented()
3093 .warnNotFail()
3094 .hyp().monNonSecure();
3095 InitReg(MISCREG_HAMAIR1)
3096 .unimplemented()
3097 .warnNotFail()
3098 .hyp().monNonSecure();
3099 InitReg(MISCREG_VBAR)
3100 .banked();
3101 InitReg(MISCREG_VBAR_NS)
3102 .bankedChild()
3103 .privSecure(!aarch32EL3)
3104 .nonSecure().exceptUserMode();
3105 InitReg(MISCREG_VBAR_S)
3106 .bankedChild()
3107 .secure().exceptUserMode();
3108 InitReg(MISCREG_MVBAR)
3109 .mon().secure().exceptUserMode();
3110 InitReg(MISCREG_RMR)
3111 .unimplemented()
3112 .mon().secure().exceptUserMode();
3113 InitReg(MISCREG_ISR)
3114 .allPrivileges().exceptUserMode().writes(0);
3115 InitReg(MISCREG_HVBAR)
3116 .hyp().monNonSecure();
3117 InitReg(MISCREG_FCSEIDR)
3118 .unimplemented()
3119 .warnNotFail()
3120 .allPrivileges().exceptUserMode();
3121 InitReg(MISCREG_CONTEXTIDR)
3122 .banked();
3123 InitReg(MISCREG_CONTEXTIDR_NS)
3124 .bankedChild()
3125 .privSecure(!aarch32EL3)
3126 .nonSecure().exceptUserMode();
3127 InitReg(MISCREG_CONTEXTIDR_S)
3128 .bankedChild()
3129 .secure().exceptUserMode();
3130 InitReg(MISCREG_TPIDRURW)
3131 .banked();
3132 InitReg(MISCREG_TPIDRURW_NS)
3133 .bankedChild()
3134 .allPrivileges()
3135 .privSecure(!aarch32EL3)
3136 .monSecure(0);
3137 InitReg(MISCREG_TPIDRURW_S)
3138 .bankedChild()
3139 .secure();
3140 InitReg(MISCREG_TPIDRURO)
3141 .banked();
3142 InitReg(MISCREG_TPIDRURO_NS)
3143 .bankedChild()
3144 .allPrivileges()
3145 .userNonSecureWrite(0).userSecureRead(1)
3146 .privSecure(!aarch32EL3)
3147 .monSecure(0);
3148 InitReg(MISCREG_TPIDRURO_S)
3149 .bankedChild()
3150 .secure().userSecureWrite(0);
3151 InitReg(MISCREG_TPIDRPRW)
3152 .banked();
3153 InitReg(MISCREG_TPIDRPRW_NS)
3154 .bankedChild()
3155 .nonSecure().exceptUserMode()
3156 .privSecure(!aarch32EL3);
3157 InitReg(MISCREG_TPIDRPRW_S)
3158 .bankedChild()
3159 .secure().exceptUserMode();
3160 InitReg(MISCREG_HTPIDR)
3161 .hyp().monNonSecure();
3162 InitReg(MISCREG_CNTFRQ)
3163 .unverifiable()
3164 .reads(1).mon();
3165 InitReg(MISCREG_CNTKCTL)
3166 .allPrivileges().exceptUserMode();
3167 InitReg(MISCREG_CNTP_TVAL)
3168 .banked();
3169 InitReg(MISCREG_CNTP_TVAL_NS)
3170 .bankedChild()
3171 .allPrivileges()
3172 .privSecure(!aarch32EL3)
3173 .monSecure(0);
3174 InitReg(MISCREG_CNTP_TVAL_S)
3175 .unimplemented()
3176 .bankedChild()
3177 .secure().user(1);
3178 InitReg(MISCREG_CNTP_CTL)
3179 .banked();
3180 InitReg(MISCREG_CNTP_CTL_NS)
3181 .bankedChild()
3182 .allPrivileges()
3183 .privSecure(!aarch32EL3)
3184 .monSecure(0);
3185 InitReg(MISCREG_CNTP_CTL_S)
3186 .unimplemented()
3187 .bankedChild()
3188 .secure().user(1);
3189 InitReg(MISCREG_CNTV_TVAL)
3190 .allPrivileges();
3191 InitReg(MISCREG_CNTV_CTL)
3192 .allPrivileges();
3193 InitReg(MISCREG_CNTHCTL)
3194 .unimplemented()
3195 .hypWrite().monNonSecureRead();
3196 InitReg(MISCREG_CNTHP_TVAL)
3197 .unimplemented()
3198 .hypWrite().monNonSecureRead();
3199 InitReg(MISCREG_CNTHP_CTL)
3200 .unimplemented()
3201 .hypWrite().monNonSecureRead();
3202 InitReg(MISCREG_IL1DATA0)
3203 .unimplemented()
3204 .allPrivileges().exceptUserMode();
3205 InitReg(MISCREG_IL1DATA1)
3206 .unimplemented()
3207 .allPrivileges().exceptUserMode();
3208 InitReg(MISCREG_IL1DATA2)
3209 .unimplemented()
3210 .allPrivileges().exceptUserMode();
3211 InitReg(MISCREG_IL1DATA3)
3212 .unimplemented()
3213 .allPrivileges().exceptUserMode();
3214 InitReg(MISCREG_DL1DATA0)
3215 .unimplemented()
3216 .allPrivileges().exceptUserMode();
3217 InitReg(MISCREG_DL1DATA1)
3218 .unimplemented()
3219 .allPrivileges().exceptUserMode();
3220 InitReg(MISCREG_DL1DATA2)
3221 .unimplemented()
3222 .allPrivileges().exceptUserMode();
3223 InitReg(MISCREG_DL1DATA3)
3224 .unimplemented()
3225 .allPrivileges().exceptUserMode();
3226 InitReg(MISCREG_DL1DATA4)
3227 .unimplemented()
3228 .allPrivileges().exceptUserMode();
3229 InitReg(MISCREG_RAMINDEX)
3230 .unimplemented()
3231 .writes(1).exceptUserMode();
3232 InitReg(MISCREG_L2ACTLR)
3233 .unimplemented()
3234 .allPrivileges().exceptUserMode();
3235 InitReg(MISCREG_CBAR)
3236 .unimplemented()
3237 .allPrivileges().exceptUserMode().writes(0);
3238 InitReg(MISCREG_HTTBR)
3239 .hyp().monNonSecure();
3240 InitReg(MISCREG_VTTBR)
3241 .hyp().monNonSecure();
3242 InitReg(MISCREG_CNTPCT)
3243 .reads(1);
3244 InitReg(MISCREG_CNTVCT)
3245 .unverifiable()
3246 .reads(1);
3247 InitReg(MISCREG_CNTP_CVAL)
3248 .banked();
3249 InitReg(MISCREG_CNTP_CVAL_NS)
3250 .bankedChild()
3251 .allPrivileges()
3252 .privSecure(!aarch32EL3)
3253 .monSecure(0);
3254 InitReg(MISCREG_CNTP_CVAL_S)
3255 .unimplemented()
3256 .bankedChild()
3257 .secure().user(1);
3258 InitReg(MISCREG_CNTV_CVAL)
3259 .allPrivileges();
3260 InitReg(MISCREG_CNTVOFF)
3261 .hyp().monNonSecure();
3262 InitReg(MISCREG_CNTHP_CVAL)
3263 .unimplemented()
3264 .hypWrite().monNonSecureRead();
3265 InitReg(MISCREG_CPUMERRSR)
3266 .unimplemented()
3267 .allPrivileges().exceptUserMode();
3268 InitReg(MISCREG_L2MERRSR)
3269 .unimplemented()
3270 .warnNotFail()
3271 .allPrivileges().exceptUserMode();
3272
3273 // AArch64 registers (Op0=2);
3274 InitReg(MISCREG_MDCCINT_EL1)
3275 .allPrivileges();
3276 InitReg(MISCREG_OSDTRRX_EL1)
3277 .allPrivileges()
3278 .mapsTo(MISCREG_DBGDTRRXext);
3279 InitReg(MISCREG_MDSCR_EL1)
3280 .allPrivileges()
3281 .mapsTo(MISCREG_DBGDSCRext);
3282 InitReg(MISCREG_OSDTRTX_EL1)
3283 .allPrivileges()
3284 .mapsTo(MISCREG_DBGDTRTXext);
3285 InitReg(MISCREG_OSECCR_EL1)
3286 .allPrivileges()
3287 .mapsTo(MISCREG_DBGOSECCR);
3288 InitReg(MISCREG_DBGBVR0_EL1)
3289 .allPrivileges()
3290 .mapsTo(MISCREG_DBGBVR0 /*, MISCREG_DBGBXVR0 */);
3291 InitReg(MISCREG_DBGBVR1_EL1)
3292 .allPrivileges()
3293 .mapsTo(MISCREG_DBGBVR1 /*, MISCREG_DBGBXVR1 */);
3294 InitReg(MISCREG_DBGBVR2_EL1)
3295 .allPrivileges()
3296 .mapsTo(MISCREG_DBGBVR2 /*, MISCREG_DBGBXVR2 */);
3297 InitReg(MISCREG_DBGBVR3_EL1)
3298 .allPrivileges()
3299 .mapsTo(MISCREG_DBGBVR3 /*, MISCREG_DBGBXVR3 */);
3300 InitReg(MISCREG_DBGBVR4_EL1)
3301 .allPrivileges()
3302 .mapsTo(MISCREG_DBGBVR4 /*, MISCREG_DBGBXVR4 */);
3303 InitReg(MISCREG_DBGBVR5_EL1)
3304 .allPrivileges()
3305 .mapsTo(MISCREG_DBGBVR5 /*, MISCREG_DBGBXVR5 */);
3306 InitReg(MISCREG_DBGBCR0_EL1)
3307 .allPrivileges()
3308 .mapsTo(MISCREG_DBGBCR0);
3309 InitReg(MISCREG_DBGBCR1_EL1)
3310 .allPrivileges()
3311 .mapsTo(MISCREG_DBGBCR1);
3312 InitReg(MISCREG_DBGBCR2_EL1)
3313 .allPrivileges()
3314 .mapsTo(MISCREG_DBGBCR2);
3315 InitReg(MISCREG_DBGBCR3_EL1)
3316 .allPrivileges()
3317 .mapsTo(MISCREG_DBGBCR3);
3318 InitReg(MISCREG_DBGBCR4_EL1)
3319 .allPrivileges()
3320 .mapsTo(MISCREG_DBGBCR4);
3321 InitReg(MISCREG_DBGBCR5_EL1)
3322 .allPrivileges()
3323 .mapsTo(MISCREG_DBGBCR5);
3324 InitReg(MISCREG_DBGWVR0_EL1)
3325 .allPrivileges()
3326 .mapsTo(MISCREG_DBGWVR0);
3327 InitReg(MISCREG_DBGWVR1_EL1)
3328 .allPrivileges()
3329 .mapsTo(MISCREG_DBGWVR1);
3330 InitReg(MISCREG_DBGWVR2_EL1)
3331 .allPrivileges()
3332 .mapsTo(MISCREG_DBGWVR2);
3333 InitReg(MISCREG_DBGWVR3_EL1)
3334 .allPrivileges()
3335 .mapsTo(MISCREG_DBGWVR3);
3336 InitReg(MISCREG_DBGWCR0_EL1)
3337 .allPrivileges()
3338 .mapsTo(MISCREG_DBGWCR0);
3339 InitReg(MISCREG_DBGWCR1_EL1)
3340 .allPrivileges()
3341 .mapsTo(MISCREG_DBGWCR1);
3342 InitReg(MISCREG_DBGWCR2_EL1)
3343 .allPrivileges()
3344 .mapsTo(MISCREG_DBGWCR2);
3345 InitReg(MISCREG_DBGWCR3_EL1)
3346 .allPrivileges()
3347 .mapsTo(MISCREG_DBGWCR3);
3348 InitReg(MISCREG_MDCCSR_EL0)
3349 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3350 .mapsTo(MISCREG_DBGDSCRint);
3351 InitReg(MISCREG_MDDTR_EL0)
3352 .allPrivileges();
3353 InitReg(MISCREG_MDDTRTX_EL0)
3354 .allPrivileges();
3355 InitReg(MISCREG_MDDTRRX_EL0)
3356 .allPrivileges();
3357 InitReg(MISCREG_DBGVCR32_EL2)
3358 .allPrivileges()
3359 .mapsTo(MISCREG_DBGVCR);
3360 InitReg(MISCREG_MDRAR_EL1)
3361 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3362 .mapsTo(MISCREG_DBGDRAR);
3363 InitReg(MISCREG_OSLAR_EL1)
3364 .allPrivileges().monSecureRead(0).monNonSecureRead(0)
3365 .mapsTo(MISCREG_DBGOSLAR);
3366 InitReg(MISCREG_OSLSR_EL1)
3367 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3368 .mapsTo(MISCREG_DBGOSLSR);
3369 InitReg(MISCREG_OSDLR_EL1)
3370 .allPrivileges()
3371 .mapsTo(MISCREG_DBGOSDLR);
3372 InitReg(MISCREG_DBGPRCR_EL1)
3373 .allPrivileges()
3374 .mapsTo(MISCREG_DBGPRCR);
3375 InitReg(MISCREG_DBGCLAIMSET_EL1)
3376 .allPrivileges()
3377 .mapsTo(MISCREG_DBGCLAIMSET);
3378 InitReg(MISCREG_DBGCLAIMCLR_EL1)
3379 .allPrivileges()
3380 .mapsTo(MISCREG_DBGCLAIMCLR);
3381 InitReg(MISCREG_DBGAUTHSTATUS_EL1)
3382 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
3383 .mapsTo(MISCREG_DBGAUTHSTATUS);
3384 InitReg(MISCREG_TEECR32_EL1);
3385 InitReg(MISCREG_TEEHBR32_EL1);
3386
3387 // AArch64 registers (Op0=1,3);
3388 InitReg(MISCREG_MIDR_EL1)
3389 .allPrivileges().exceptUserMode().writes(0);
3390 InitReg(MISCREG_MPIDR_EL1)
3391 .allPrivileges().exceptUserMode().writes(0);
3392 InitReg(MISCREG_REVIDR_EL1)
3393 .allPrivileges().exceptUserMode().writes(0);
3394 InitReg(MISCREG_ID_PFR0_EL1)
3395 .allPrivileges().exceptUserMode().writes(0)
3396 .mapsTo(MISCREG_ID_PFR0);
3397 InitReg(MISCREG_ID_PFR1_EL1)
3398 .allPrivileges().exceptUserMode().writes(0)
3399 .mapsTo(MISCREG_ID_PFR1);
3400 InitReg(MISCREG_ID_DFR0_EL1)
3401 .allPrivileges().exceptUserMode().writes(0)
3402 .mapsTo(MISCREG_ID_DFR0);
3403 InitReg(MISCREG_ID_AFR0_EL1)
3404 .allPrivileges().exceptUserMode().writes(0)
3405 .mapsTo(MISCREG_ID_AFR0);
3406 InitReg(MISCREG_ID_MMFR0_EL1)
3407 .allPrivileges().exceptUserMode().writes(0)
3408 .mapsTo(MISCREG_ID_MMFR0);
3409 InitReg(MISCREG_ID_MMFR1_EL1)
3410 .allPrivileges().exceptUserMode().writes(0)
3411 .mapsTo(MISCREG_ID_MMFR1);
3412 InitReg(MISCREG_ID_MMFR2_EL1)
3413 .allPrivileges().exceptUserMode().writes(0)
3414 .mapsTo(MISCREG_ID_MMFR2);
3415 InitReg(MISCREG_ID_MMFR3_EL1)
3416 .allPrivileges().exceptUserMode().writes(0)
3417 .mapsTo(MISCREG_ID_MMFR3);
3418 InitReg(MISCREG_ID_ISAR0_EL1)
3419 .allPrivileges().exceptUserMode().writes(0)
3420 .mapsTo(MISCREG_ID_ISAR0);
3421 InitReg(MISCREG_ID_ISAR1_EL1)
3422 .allPrivileges().exceptUserMode().writes(0)
3423 .mapsTo(MISCREG_ID_ISAR1);
3424 InitReg(MISCREG_ID_ISAR2_EL1)
3425 .allPrivileges().exceptUserMode().writes(0)
3426 .mapsTo(MISCREG_ID_ISAR2);
3427 InitReg(MISCREG_ID_ISAR3_EL1)
3428 .allPrivileges().exceptUserMode().writes(0)
3429 .mapsTo(MISCREG_ID_ISAR3);
3430 InitReg(MISCREG_ID_ISAR4_EL1)
3431 .allPrivileges().exceptUserMode().writes(0)
3432 .mapsTo(MISCREG_ID_ISAR4);
3433 InitReg(MISCREG_ID_ISAR5_EL1)
3434 .allPrivileges().exceptUserMode().writes(0)
3435 .mapsTo(MISCREG_ID_ISAR5);
3436 InitReg(MISCREG_MVFR0_EL1)
3437 .allPrivileges().exceptUserMode().writes(0);
3438 InitReg(MISCREG_MVFR1_EL1)
3439 .allPrivileges().exceptUserMode().writes(0);
3440 InitReg(MISCREG_MVFR2_EL1)
3441 .allPrivileges().exceptUserMode().writes(0);
3442 InitReg(MISCREG_ID_AA64PFR0_EL1)
3443 .allPrivileges().exceptUserMode().writes(0);
3444 InitReg(MISCREG_ID_AA64PFR1_EL1)
3445 .allPrivileges().exceptUserMode().writes(0);
3446 InitReg(MISCREG_ID_AA64DFR0_EL1)
3447 .allPrivileges().exceptUserMode().writes(0);
3448 InitReg(MISCREG_ID_AA64DFR1_EL1)
3449 .allPrivileges().exceptUserMode().writes(0);
3450 InitReg(MISCREG_ID_AA64AFR0_EL1)
3451 .allPrivileges().exceptUserMode().writes(0);
3452 InitReg(MISCREG_ID_AA64AFR1_EL1)
3453 .allPrivileges().exceptUserMode().writes(0);
3454 InitReg(MISCREG_ID_AA64ISAR0_EL1)
3455 .allPrivileges().exceptUserMode().writes(0);
3456 InitReg(MISCREG_ID_AA64ISAR1_EL1)
3457 .allPrivileges().exceptUserMode().writes(0);
3458 InitReg(MISCREG_ID_AA64MMFR0_EL1)
3459 .allPrivileges().exceptUserMode().writes(0);
3460 InitReg(MISCREG_ID_AA64MMFR1_EL1)
3461 .allPrivileges().exceptUserMode().writes(0);
3462 InitReg(MISCREG_CCSIDR_EL1)
3463 .allPrivileges().exceptUserMode().writes(0);
3464 InitReg(MISCREG_CLIDR_EL1)
3465 .allPrivileges().exceptUserMode().writes(0);
3466 InitReg(MISCREG_AIDR_EL1)
3467 .allPrivileges().exceptUserMode().writes(0);
3468 InitReg(MISCREG_CSSELR_EL1)
3469 .allPrivileges().exceptUserMode()
3470 .mapsTo(MISCREG_CSSELR_NS);
3471 InitReg(MISCREG_CTR_EL0)
3472 .reads(1);
3473 InitReg(MISCREG_DCZID_EL0)
3474 .reads(1);
3475 InitReg(MISCREG_VPIDR_EL2)
3476 .hyp().mon()
3477 .mapsTo(MISCREG_VPIDR);
3478 InitReg(MISCREG_VMPIDR_EL2)
3479 .hyp().mon()
3480 .mapsTo(MISCREG_VMPIDR);
3481 InitReg(MISCREG_SCTLR_EL1)
3482 .allPrivileges().exceptUserMode()
3483 .mapsTo(MISCREG_SCTLR_NS);
3484 InitReg(MISCREG_ACTLR_EL1)
3485 .allPrivileges().exceptUserMode()
3486 .mapsTo(MISCREG_ACTLR_NS);
3487 InitReg(MISCREG_CPACR_EL1)
3488 .allPrivileges().exceptUserMode()
3489 .mapsTo(MISCREG_CPACR);
3490 InitReg(MISCREG_SCTLR_EL2)
3491 .hyp().mon()
3492 .mapsTo(MISCREG_HSCTLR);
3493 InitReg(MISCREG_ACTLR_EL2)
3494 .hyp().mon()
3495 .mapsTo(MISCREG_HACTLR);
3496 InitReg(MISCREG_HCR_EL2)
3497 .hyp().mon()
3498 .mapsTo(MISCREG_HCR /*, MISCREG_HCR2*/);
3499 InitReg(MISCREG_MDCR_EL2)
3500 .hyp().mon()
3501 .mapsTo(MISCREG_HDCR);
3502 InitReg(MISCREG_CPTR_EL2)
3503 .hyp().mon()
3504 .mapsTo(MISCREG_HCPTR);
3505 InitReg(MISCREG_HSTR_EL2)
3506 .hyp().mon()
3507 .mapsTo(MISCREG_HSTR);
3508 InitReg(MISCREG_HACR_EL2)
3509 .hyp().mon()
3510 .mapsTo(MISCREG_HACR);
3511 InitReg(MISCREG_SCTLR_EL3)
3512 .mon();
3513 InitReg(MISCREG_ACTLR_EL3)
3514 .mon();
3515 InitReg(MISCREG_SCR_EL3)
3516 .mon()
3517 .mapsTo(MISCREG_SCR); // NAM D7-2005
3518 InitReg(MISCREG_SDER32_EL3)
3519 .mon()
3520 .mapsTo(MISCREG_SDER);
3521 InitReg(MISCREG_CPTR_EL3)
3522 .mon();
3523 InitReg(MISCREG_MDCR_EL3)
3524 .mon();
3525 InitReg(MISCREG_TTBR0_EL1)
3526 .allPrivileges().exceptUserMode()
3527 .mapsTo(MISCREG_TTBR0_NS);
3528 InitReg(MISCREG_TTBR1_EL1)
3529 .allPrivileges().exceptUserMode()
3530 .mapsTo(MISCREG_TTBR1_NS);
3531 InitReg(MISCREG_TCR_EL1)
3532 .allPrivileges().exceptUserMode()
3533 .mapsTo(MISCREG_TTBCR_NS);
3534 InitReg(MISCREG_TTBR0_EL2)
3535 .hyp().mon()
3536 .mapsTo(MISCREG_HTTBR);
3537 InitReg(MISCREG_TTBR1_EL2)
3538 .hyp().mon();
3539 InitReg(MISCREG_TCR_EL2)
3540 .hyp().mon()
3541 .mapsTo(MISCREG_HTCR);
3542 InitReg(MISCREG_VTTBR_EL2)
3543 .hyp().mon()
3544 .mapsTo(MISCREG_VTTBR);
3545 InitReg(MISCREG_VTCR_EL2)
3546 .hyp().mon()
3547 .mapsTo(MISCREG_VTCR);
3548 InitReg(MISCREG_TTBR0_EL3)
3549 .mon();
3550 InitReg(MISCREG_TCR_EL3)
3551 .mon();
3552 InitReg(MISCREG_DACR32_EL2)
3553 .hyp().mon()
3554 .mapsTo(MISCREG_DACR_NS);
3555 InitReg(MISCREG_SPSR_EL1)
3556 .allPrivileges().exceptUserMode()
3557 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
3558 InitReg(MISCREG_ELR_EL1)
3559 .allPrivileges().exceptUserMode();
3560 InitReg(MISCREG_SP_EL0)
3561 .allPrivileges().exceptUserMode();
3562 InitReg(MISCREG_SPSEL)
3563 .allPrivileges().exceptUserMode();
3564 InitReg(MISCREG_CURRENTEL)
3565 .allPrivileges().exceptUserMode().writes(0);
3566 InitReg(MISCREG_NZCV)
3567 .allPrivileges();
3568 InitReg(MISCREG_DAIF)
3569 .allPrivileges();
3570 InitReg(MISCREG_FPCR)
3571 .allPrivileges();
3572 InitReg(MISCREG_FPSR)
3573 .allPrivileges();
3574 InitReg(MISCREG_DSPSR_EL0)
3575 .allPrivileges();
3576 InitReg(MISCREG_DLR_EL0)
3577 .allPrivileges();
3578 InitReg(MISCREG_SPSR_EL2)
3579 .hyp().mon()
3580 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
3581 InitReg(MISCREG_ELR_EL2)
3582 .hyp().mon();
3583 InitReg(MISCREG_SP_EL1)
3584 .hyp().mon();
3585 InitReg(MISCREG_SPSR_IRQ_AA64)
3586 .hyp().mon();
3587 InitReg(MISCREG_SPSR_ABT_AA64)
3588 .hyp().mon();
3589 InitReg(MISCREG_SPSR_UND_AA64)
3590 .hyp().mon();
3591 InitReg(MISCREG_SPSR_FIQ_AA64)
3592 .hyp().mon();
3593 InitReg(MISCREG_SPSR_EL3)
3594 .mon()
3595 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
3596 InitReg(MISCREG_ELR_EL3)
3597 .mon();
3598 InitReg(MISCREG_SP_EL2)
3599 .mon();
3600 InitReg(MISCREG_AFSR0_EL1)
3601 .allPrivileges().exceptUserMode()
3602 .mapsTo(MISCREG_ADFSR_NS);
3603 InitReg(MISCREG_AFSR1_EL1)
3604 .allPrivileges().exceptUserMode()
3605 .mapsTo(MISCREG_AIFSR_NS);
3606 InitReg(MISCREG_ESR_EL1)
3607 .allPrivileges().exceptUserMode();
3608 InitReg(MISCREG_IFSR32_EL2)
3609 .hyp().mon()
3610 .mapsTo(MISCREG_IFSR_NS);
3611 InitReg(MISCREG_AFSR0_EL2)
3612 .hyp().mon()
3613 .mapsTo(MISCREG_HADFSR);
3614 InitReg(MISCREG_AFSR1_EL2)
3615 .hyp().mon()
3616 .mapsTo(MISCREG_HAIFSR);
3617 InitReg(MISCREG_ESR_EL2)
3618 .hyp().mon()
3619 .mapsTo(MISCREG_HSR);
3620 InitReg(MISCREG_FPEXC32_EL2)
3621 .hyp().mon().mapsTo(MISCREG_FPEXC);
3622 InitReg(MISCREG_AFSR0_EL3)
3623 .mon();
3624 InitReg(MISCREG_AFSR1_EL3)
3625 .mon();
3626 InitReg(MISCREG_ESR_EL3)
3627 .mon();
3628 InitReg(MISCREG_FAR_EL1)
3629 .allPrivileges().exceptUserMode()
3630 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
3631 InitReg(MISCREG_FAR_EL2)
3632 .hyp().mon()
3633 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
3634 InitReg(MISCREG_HPFAR_EL2)
3635 .hyp().mon()
3636 .mapsTo(MISCREG_HPFAR);
3637 InitReg(MISCREG_FAR_EL3)
3638 .mon();
3639 InitReg(MISCREG_IC_IALLUIS)
3640 .warnNotFail()
3641 .writes(1).exceptUserMode();
3642 InitReg(MISCREG_PAR_EL1)
3643 .allPrivileges().exceptUserMode()
3644 .mapsTo(MISCREG_PAR_NS);
3645 InitReg(MISCREG_IC_IALLU)
3646 .warnNotFail()
3647 .writes(1).exceptUserMode();
3648 InitReg(MISCREG_DC_IVAC_Xt)
3649 .warnNotFail()
3650 .writes(1).exceptUserMode();
3651 InitReg(MISCREG_DC_ISW_Xt)
3652 .warnNotFail()
3653 .writes(1).exceptUserMode();
3654 InitReg(MISCREG_AT_S1E1R_Xt)
3655 .writes(1).exceptUserMode();
3656 InitReg(MISCREG_AT_S1E1W_Xt)
3657 .writes(1).exceptUserMode();
3658 InitReg(MISCREG_AT_S1E0R_Xt)
3659 .writes(1).exceptUserMode();
3660 InitReg(MISCREG_AT_S1E0W_Xt)
3661 .writes(1).exceptUserMode();
3662 InitReg(MISCREG_DC_CSW_Xt)
3663 .warnNotFail()
3664 .writes(1).exceptUserMode();
3665 InitReg(MISCREG_DC_CISW_Xt)
3666 .warnNotFail()
3667 .writes(1).exceptUserMode();
3668 InitReg(MISCREG_DC_ZVA_Xt)
3669 .warnNotFail()
3670 .writes(1).userSecureWrite(0);
3671 InitReg(MISCREG_IC_IVAU_Xt)
3672 .writes(1);
3673 InitReg(MISCREG_DC_CVAC_Xt)
3674 .warnNotFail()
3675 .writes(1);
3676 InitReg(MISCREG_DC_CVAU_Xt)
3677 .warnNotFail()
3678 .writes(1);
3679 InitReg(MISCREG_DC_CIVAC_Xt)
3680 .warnNotFail()
3681 .writes(1);
3682 InitReg(MISCREG_AT_S1E2R_Xt)
3683 .monNonSecureWrite().hypWrite();
3684 InitReg(MISCREG_AT_S1E2W_Xt)
3685 .monNonSecureWrite().hypWrite();
3686 InitReg(MISCREG_AT_S12E1R_Xt)
3687 .hypWrite().monSecureWrite().monNonSecureWrite();
3688 InitReg(MISCREG_AT_S12E1W_Xt)
3689 .hypWrite().monSecureWrite().monNonSecureWrite();
3690 InitReg(MISCREG_AT_S12E0R_Xt)
3691 .hypWrite().monSecureWrite().monNonSecureWrite();
3692 InitReg(MISCREG_AT_S12E0W_Xt)
3693 .hypWrite().monSecureWrite().monNonSecureWrite();
3694 InitReg(MISCREG_AT_S1E3R_Xt)
3695 .monSecureWrite().monNonSecureWrite();
3696 InitReg(MISCREG_AT_S1E3W_Xt)
3697 .monSecureWrite().monNonSecureWrite();
3698 InitReg(MISCREG_TLBI_VMALLE1IS)
3699 .writes(1).exceptUserMode();
3700 InitReg(MISCREG_TLBI_VAE1IS_Xt)
3701 .writes(1).exceptUserMode();
3702 InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
3703 .writes(1).exceptUserMode();
3704 InitReg(MISCREG_TLBI_VAAE1IS_Xt)
3705 .writes(1).exceptUserMode();
3706 InitReg(MISCREG_TLBI_VALE1IS_Xt)
3707 .writes(1).exceptUserMode();
3708 InitReg(MISCREG_TLBI_VAALE1IS_Xt)
3709 .writes(1).exceptUserMode();
3710 InitReg(MISCREG_TLBI_VMALLE1)
3711 .writes(1).exceptUserMode();
3712 InitReg(MISCREG_TLBI_VAE1_Xt)
3713 .writes(1).exceptUserMode();
3714 InitReg(MISCREG_TLBI_ASIDE1_Xt)
3715 .writes(1).exceptUserMode();
3716 InitReg(MISCREG_TLBI_VAAE1_Xt)
3717 .writes(1).exceptUserMode();
3718 InitReg(MISCREG_TLBI_VALE1_Xt)
3719 .writes(1).exceptUserMode();
3720 InitReg(MISCREG_TLBI_VAALE1_Xt)
3721 .writes(1).exceptUserMode();
3722 InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
3723 .hypWrite().monSecureWrite().monNonSecureWrite();
3724 InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
3725 .hypWrite().monSecureWrite().monNonSecureWrite();
3726 InitReg(MISCREG_TLBI_ALLE2IS)
3727 .monNonSecureWrite().hypWrite();
3728 InitReg(MISCREG_TLBI_VAE2IS_Xt)
3729 .monNonSecureWrite().hypWrite();
3730 InitReg(MISCREG_TLBI_ALLE1IS)
3731 .hypWrite().monSecureWrite().monNonSecureWrite();
3732 InitReg(MISCREG_TLBI_VALE2IS_Xt)
3733 .monNonSecureWrite().hypWrite();
3734 InitReg(MISCREG_TLBI_VMALLS12E1IS)
3735 .hypWrite().monSecureWrite().monNonSecureWrite();
3736 InitReg(MISCREG_TLBI_IPAS2E1_Xt)
3737 .hypWrite().monSecureWrite().monNonSecureWrite();
3738 InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
3739 .hypWrite().monSecureWrite().monNonSecureWrite();
3740 InitReg(MISCREG_TLBI_ALLE2)
3741 .monNonSecureWrite().hypWrite();
3742 InitReg(MISCREG_TLBI_VAE2_Xt)
3743 .monNonSecureWrite().hypWrite();
3744 InitReg(MISCREG_TLBI_ALLE1)
3745 .hypWrite().monSecureWrite().monNonSecureWrite();
3746 InitReg(MISCREG_TLBI_VALE2_Xt)
3747 .monNonSecureWrite().hypWrite();
3748 InitReg(MISCREG_TLBI_VMALLS12E1)
3749 .hypWrite().monSecureWrite().monNonSecureWrite();
3750 InitReg(MISCREG_TLBI_ALLE3IS)
3751 .monSecureWrite().monNonSecureWrite();
3752 InitReg(MISCREG_TLBI_VAE3IS_Xt)
3753 .monSecureWrite().monNonSecureWrite();
3754 InitReg(MISCREG_TLBI_VALE3IS_Xt)
3755 .monSecureWrite().monNonSecureWrite();
3756 InitReg(MISCREG_TLBI_ALLE3)
3757 .monSecureWrite().monNonSecureWrite();
3758 InitReg(MISCREG_TLBI_VAE3_Xt)
3759 .monSecureWrite().monNonSecureWrite();
3760 InitReg(MISCREG_TLBI_VALE3_Xt)
3761 .monSecureWrite().monNonSecureWrite();
3762 InitReg(MISCREG_PMINTENSET_EL1)
3763 .allPrivileges().exceptUserMode()
3764 .mapsTo(MISCREG_PMINTENSET);
3765 InitReg(MISCREG_PMINTENCLR_EL1)
3766 .allPrivileges().exceptUserMode()
3767 .mapsTo(MISCREG_PMINTENCLR);
3768 InitReg(MISCREG_PMCR_EL0)
3769 .allPrivileges()
3770 .mapsTo(MISCREG_PMCR);
3771 InitReg(MISCREG_PMCNTENSET_EL0)
3772 .allPrivileges()
3773 .mapsTo(MISCREG_PMCNTENSET);
3774 InitReg(MISCREG_PMCNTENCLR_EL0)
3775 .allPrivileges()
3776 .mapsTo(MISCREG_PMCNTENCLR);
3777 InitReg(MISCREG_PMOVSCLR_EL0)
3778 .allPrivileges();
3779// .mapsTo(MISCREG_PMOVSCLR);
3780 InitReg(MISCREG_PMSWINC_EL0)
3781 .writes(1).user()
3782 .mapsTo(MISCREG_PMSWINC);
3783 InitReg(MISCREG_PMSELR_EL0)
3784 .allPrivileges()
3785 .mapsTo(MISCREG_PMSELR);
3786 InitReg(MISCREG_PMCEID0_EL0)
3787 .reads(1).user()
3788 .mapsTo(MISCREG_PMCEID0);
3789 InitReg(MISCREG_PMCEID1_EL0)
3790 .reads(1).user()
3791 .mapsTo(MISCREG_PMCEID1);
3792 InitReg(MISCREG_PMCCNTR_EL0)
3793 .allPrivileges()
3794 .mapsTo(MISCREG_PMCCNTR);
3795 InitReg(MISCREG_PMXEVTYPER_EL0)
3796 .allPrivileges()
3797 .mapsTo(MISCREG_PMXEVTYPER);
3798 InitReg(MISCREG_PMCCFILTR_EL0)
3799 .allPrivileges();
3800 InitReg(MISCREG_PMXEVCNTR_EL0)
3801 .allPrivileges()
3802 .mapsTo(MISCREG_PMXEVCNTR);
3803 InitReg(MISCREG_PMUSERENR_EL0)
3804 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3805 .mapsTo(MISCREG_PMUSERENR);
3806 InitReg(MISCREG_PMOVSSET_EL0)
3807 .allPrivileges()
3808 .mapsTo(MISCREG_PMOVSSET);
3809 InitReg(MISCREG_MAIR_EL1)
3810 .allPrivileges().exceptUserMode()
3811 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
3812 InitReg(MISCREG_AMAIR_EL1)
3813 .allPrivileges().exceptUserMode()
3814 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
3815 InitReg(MISCREG_MAIR_EL2)
3816 .hyp().mon()
3817 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
3818 InitReg(MISCREG_AMAIR_EL2)
3819 .hyp().mon()
3820 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
3821 InitReg(MISCREG_MAIR_EL3)
3822 .mon();
3823 InitReg(MISCREG_AMAIR_EL3)
3824 .mon();
3825 InitReg(MISCREG_L2CTLR_EL1)
3826 .allPrivileges().exceptUserMode();
3827 InitReg(MISCREG_L2ECTLR_EL1)
3828 .allPrivileges().exceptUserMode();
3829 InitReg(MISCREG_VBAR_EL1)
3830 .allPrivileges().exceptUserMode()
3831 .mapsTo(MISCREG_VBAR_NS);
3832 InitReg(MISCREG_RVBAR_EL1)
3833 .allPrivileges().exceptUserMode().writes(0);
3834 InitReg(MISCREG_ISR_EL1)
3835 .allPrivileges().exceptUserMode().writes(0);
3836 InitReg(MISCREG_VBAR_EL2)
3837 .hyp().mon()
3838 .mapsTo(MISCREG_HVBAR);
3839 InitReg(MISCREG_RVBAR_EL2)
3840 .mon().hyp().writes(0);
3841 InitReg(MISCREG_VBAR_EL3)
3842 .mon();
3843 InitReg(MISCREG_RVBAR_EL3)
3844 .mon().writes(0);
3845 InitReg(MISCREG_RMR_EL3)
3846 .mon();
3847 InitReg(MISCREG_CONTEXTIDR_EL1)
3848 .allPrivileges().exceptUserMode()
3849 .mapsTo(MISCREG_CONTEXTIDR_NS);
3850 InitReg(MISCREG_TPIDR_EL1)
3851 .allPrivileges().exceptUserMode()
3852 .mapsTo(MISCREG_TPIDRPRW_NS);
3853 InitReg(MISCREG_TPIDR_EL0)
3854 .allPrivileges()
3855 .mapsTo(MISCREG_TPIDRURW_NS);
3856 InitReg(MISCREG_TPIDRRO_EL0)
3857 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
3858 .mapsTo(MISCREG_TPIDRURO_NS);
3859 InitReg(MISCREG_TPIDR_EL2)
3860 .hyp().mon()
3861 .mapsTo(MISCREG_HTPIDR);
3862 InitReg(MISCREG_TPIDR_EL3)
3863 .mon();
3864 InitReg(MISCREG_CNTKCTL_EL1)
3865 .allPrivileges().exceptUserMode()
3866 .mapsTo(MISCREG_CNTKCTL);
3867 InitReg(MISCREG_CNTFRQ_EL0)
3868 .reads(1).mon()
3869 .mapsTo(MISCREG_CNTFRQ);
3870 InitReg(MISCREG_CNTPCT_EL0)
3871 .reads(1)
3872 .mapsTo(MISCREG_CNTPCT); /* 64b */
3873 InitReg(MISCREG_CNTVCT_EL0)
3874 .unverifiable()
3875 .reads(1)
3876 .mapsTo(MISCREG_CNTVCT); /* 64b */
3877 InitReg(MISCREG_CNTP_TVAL_EL0)
3878 .allPrivileges()
3879 .mapsTo(MISCREG_CNTP_TVAL_NS);
3880 InitReg(MISCREG_CNTP_CTL_EL0)
3881 .allPrivileges()
3882 .mapsTo(MISCREG_CNTP_CTL_NS);
3883 InitReg(MISCREG_CNTP_CVAL_EL0)
3884 .allPrivileges()
3885 .mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */
3886 InitReg(MISCREG_CNTV_TVAL_EL0)
3887 .allPrivileges()
3888 .mapsTo(MISCREG_CNTV_TVAL);
3889 InitReg(MISCREG_CNTV_CTL_EL0)
3890 .allPrivileges()
3891 .mapsTo(MISCREG_CNTV_CTL);
3892 InitReg(MISCREG_CNTV_CVAL_EL0)
3893 .allPrivileges()
3894 .mapsTo(MISCREG_CNTV_CVAL); /* 64b */
3895 InitReg(MISCREG_PMEVCNTR0_EL0)
3896 .allPrivileges();
3897// .mapsTo(MISCREG_PMEVCNTR0);
3898 InitReg(MISCREG_PMEVCNTR1_EL0)
3899 .allPrivileges();
3900// .mapsTo(MISCREG_PMEVCNTR1);
3901 InitReg(MISCREG_PMEVCNTR2_EL0)
3902 .allPrivileges();
3903// .mapsTo(MISCREG_PMEVCNTR2);
3904 InitReg(MISCREG_PMEVCNTR3_EL0)
3905 .allPrivileges();
3906// .mapsTo(MISCREG_PMEVCNTR3);
3907 InitReg(MISCREG_PMEVCNTR4_EL0)
3908 .allPrivileges();
3909// .mapsTo(MISCREG_PMEVCNTR4);
3910 InitReg(MISCREG_PMEVCNTR5_EL0)
3911 .allPrivileges();
3912// .mapsTo(MISCREG_PMEVCNTR5);
3913 InitReg(MISCREG_PMEVTYPER0_EL0)
3914 .allPrivileges();
3915// .mapsTo(MISCREG_PMEVTYPER0);
3916 InitReg(MISCREG_PMEVTYPER1_EL0)
3917 .allPrivileges();
3918// .mapsTo(MISCREG_PMEVTYPER1);
3919 InitReg(MISCREG_PMEVTYPER2_EL0)
3920 .allPrivileges();
3921// .mapsTo(MISCREG_PMEVTYPER2);
3922 InitReg(MISCREG_PMEVTYPER3_EL0)
3923 .allPrivileges();
3924// .mapsTo(MISCREG_PMEVTYPER3);
3925 InitReg(MISCREG_PMEVTYPER4_EL0)
3926 .allPrivileges();
3927// .mapsTo(MISCREG_PMEVTYPER4);
3928 InitReg(MISCREG_PMEVTYPER5_EL0)
3929 .allPrivileges();
3930// .mapsTo(MISCREG_PMEVTYPER5);
3931 InitReg(MISCREG_CNTVOFF_EL2)
3932 .hyp().mon()
3933 .mapsTo(MISCREG_CNTVOFF); /* 64b */
3934 InitReg(MISCREG_CNTHCTL_EL2)
3935 .unimplemented()
3936 .warnNotFail()
3937 .mon().monNonSecureWrite(0).hypWrite()
3938 .mapsTo(MISCREG_CNTHCTL);
3939 InitReg(MISCREG_CNTHP_TVAL_EL2)
3940 .unimplemented()
3941 .mon().monNonSecureWrite(0).hypWrite()
3942 .mapsTo(MISCREG_CNTHP_TVAL);
3943 InitReg(MISCREG_CNTHP_CTL_EL2)
3944 .unimplemented()
3945 .mon().monNonSecureWrite(0).hypWrite()
3946 .mapsTo(MISCREG_CNTHP_CTL);
3947 InitReg(MISCREG_CNTHP_CVAL_EL2)
3948 .unimplemented()
3949 .mon().monNonSecureWrite(0).hypWrite()
3950 .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */
3951 InitReg(MISCREG_CNTPS_TVAL_EL1)
3952 .unimplemented()
3953 .mon().monNonSecureWrite(0).hypWrite();
3954 InitReg(MISCREG_CNTPS_CTL_EL1)
3955 .unimplemented()
3956 .mon().monNonSecureWrite(0).hypWrite();
3957 InitReg(MISCREG_CNTPS_CVAL_EL1)
3958 .unimplemented()
3959 .mon().monNonSecureWrite(0).hypWrite();
3960 InitReg(MISCREG_IL1DATA0_EL1)
3961 .allPrivileges().exceptUserMode();
3962 InitReg(MISCREG_IL1DATA1_EL1)
3963 .allPrivileges().exceptUserMode();
3964 InitReg(MISCREG_IL1DATA2_EL1)
3965 .allPrivileges().exceptUserMode();
3966 InitReg(MISCREG_IL1DATA3_EL1)
3967 .allPrivileges().exceptUserMode();
3968 InitReg(MISCREG_DL1DATA0_EL1)
3969 .allPrivileges().exceptUserMode();
3970 InitReg(MISCREG_DL1DATA1_EL1)
3971 .allPrivileges().exceptUserMode();
3972 InitReg(MISCREG_DL1DATA2_EL1)
3973 .allPrivileges().exceptUserMode();
3974 InitReg(MISCREG_DL1DATA3_EL1)
3975 .allPrivileges().exceptUserMode();
3976 InitReg(MISCREG_DL1DATA4_EL1)
3977 .allPrivileges().exceptUserMode();
3978 InitReg(MISCREG_L2ACTLR_EL1)
3979 .allPrivileges().exceptUserMode();
3980 InitReg(MISCREG_CPUACTLR_EL1)
3981 .allPrivileges().exceptUserMode();
3982 InitReg(MISCREG_CPUECTLR_EL1)
3983 .allPrivileges().exceptUserMode();
3984 InitReg(MISCREG_CPUMERRSR_EL1)
3985 .allPrivileges().exceptUserMode();
3986 InitReg(MISCREG_L2MERRSR_EL1)
3987 .unimplemented()
3988 .warnNotFail()
3989 .allPrivileges().exceptUserMode();
3990 InitReg(MISCREG_CBAR_EL1)
3991 .allPrivileges().exceptUserMode().writes(0);
3992 InitReg(MISCREG_CONTEXTIDR_EL2)
3993 .mon().hyp();
3994
3995 // Dummy registers
3996 InitReg(MISCREG_NOP)
3997 .allPrivileges();
3998 InitReg(MISCREG_RAZ)
3999 .allPrivileges().exceptUserMode().writes(0);
4000 InitReg(MISCREG_CP14_UNIMPL)
4001 .unimplemented()
4002 .warnNotFail();
4003 InitReg(MISCREG_CP15_UNIMPL)
4004 .unimplemented()
4005 .warnNotFail();
4006 InitReg(MISCREG_A64_UNIMPL)
4007 .unimplemented()
4008 .warnNotFail();
4009 InitReg(MISCREG_UNKNOWN);
4010
4011 // Register mappings for some unimplemented registers:
4012 // ESR_EL1 -> DFSR
4013 // RMR_EL1 -> RMR
4014 // RMR_EL2 -> HRMR
4015 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
4016 // DBGDTRRX_EL0 -> DBGDTRRXint
4017 // DBGDTRTX_EL0 -> DBGDTRRXint
4018 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
4019
4020 completed = true;
4021}
4022
4023} // namespace ArmISA