1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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387 return MISCREG_PMSWINC;
388 case 5:
389 return MISCREG_PMSELR;
390 case 6:
391 return MISCREG_PMCEID0;
392 case 7:
393 return MISCREG_PMCEID1;
394 }
395 case 13:
396 switch (opc2) {
397 case 0:
398 return MISCREG_PMCCNTR;
399 case 1:
400 return MISCREG_PMC_OTHER;
401 case 2:
402 return MISCREG_PMXEVCNTR;
403 }
404 case 14:
405 switch (opc2) {
406 case 0:
407 return MISCREG_PMUSERENR;
408 case 1:
409 return MISCREG_PMINTENSET;
410 case 2:
411 return MISCREG_PMINTENCLR;
412 }
413 }
414 } else if (opc1 == 1) {
415 switch (crm) {
416 case 0:
417 switch (opc2) {
418 case 2: // L2CTLR, L2 Control Register
419 return MISCREG_L2CTLR;
420 default:
421 warn("Uknown miscregs: crn:%d crm:%d opc1:%d opc2:%d\n",
422 crn,crm, opc1,opc2);
423 break;
424 }
425 default:
426 return MISCREG_L2LATENCY;
427 }
428 }
429 //Reserved for Branch Predictor, Cache and TCM operations
430 break;
431 case 10:
432 if (opc1 == 0) {

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